VIPER011LSTR_技术文档

VIPer01

Energy saving off-line high voltage converter

Datasheet - production data



Jittered switching frequency reduces the

EMI filter cost:



30 kHz ± 7% (type X)

60 kHz ± 7% (type L)

120 kHz ± 7% (type H)



Embedded E/A with 1.2 V reference

Protections with automatic restart:

overload/short-circuit (OLP), line or output

OVP, max. duty cycle counter, V_CCclamp

Pulse-skip protection to prevent

flux-runaway

Figure 1: Basic application schematic



Embedded thermal shutdown

Built-in soft-start for improved system

reliability

Applications



Low power SMPS for home appliances,

building and home control, small industrial,

consumers, lighting, motion control

Low power adapters



Description

The device is a high voltage converter smartly

integrating an 800 V avalanche-rugged power

MOSFET with PWM current mode control. The

power MOSFET with 800 V breakdown voltage

allows the extended input voltage range to be

applied, as well as the size of the DRAIN snubber

circuit to be reduced. This IC meets the most

stringent energy-saving standards as it has very

low consumption and operates in pulse frequency

modulation under light load. The design of

flyback, buck and buck boost converters is

supported. The integrated HV startup, sense-

FET, error amplifier and oscillator with jitter allow

a complete application to be designed with the

minimum number of components.

Features



800 V avalanche-rugged power MOSFET

allowing ultra wide V_ACinput range to be

covered



Embedded HV startup and sense-FET

Current mode PWM controller

Drain current limit protection (OCP)

Wide supply voltage range: 4.5 V to 30 V

Self-supply option allows the auxiliary

winding or bias components to be removed

Minimized system input power consumption:





Less than 10 mW @ 230 V_ACin no-load

condition



Less than 400 mW @ 230 V_ACwith

250 mW load

March 2016

DocID028751 Rev 1

1/36

www.st.com

This is information on a product in full production.

Contents

VIPer01

Contents

1

2

Pin setting........................................................................................5

Electrical and thermal ratings ........................................................6

2.1

Electrical characteristics....................................................................8

3

4

Typical electrical characteristics..................................................12

General description.......................................................................16

4.1

Block diagram .................................................................................16

Typical power capability..................................................................16

Primary MOSFET............................................................................17

High voltage startup ........................................................................17

Soft-start .........................................................................................19

Oscillator.........................................................................................19

Pulse-skipping.................................................................................19

Direct feedback ...............................................................................21

Secondary feedback .......................................................................21

Pulse frequency modulation............................................................21

Overload protection.........................................................................22

Max. duty cycle counter protection..................................................22

VCC clamp protection .....................................................................23

Disable function...............................................................................23

Thermal shutdown...........................................................................25

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

4.12

4.13

4.14

4.15

5

6

Application information ................................................................26

5.1

5.3

5.4

Typical schematics..........................................................................26

Energy saving performance ............................................................29

Layout guidelines and design recommendations ............................30

Package information .....................................................................32

6.1

SSOP10 package information.........................................................32

7

8

Ordering information.....................................................................34

Revision history ............................................................................35

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DocID028751 Rev 1

VIPer01

List of tables

Table 1: Pin description ..............................................................................................................................5

Table 2: Absolute maximum ratings ...........................................................................................................6

Table 3: Thermal data.................................................................................................................................6

Table 4: Avalanche characteristics.............................................................................................................7

Table 5: Power section ...............................................................................................................................8

Table 6: Supply section...............................................................................................................................8

Table 7: Controller section..........................................................................................................................9

Table 8: Typical power..............................................................................................................................16

Table 9: Power supply efficiency, V_OUT= 5 V ...........................................................................................29

Table 10: SSOP10 mechanical data.........................................................................................................33

Table 11: Order code................................................................................................................................34

Table 12: Document revision history ........................................................................................................35

DocID028751 Rev 1

3/36

List of figures

VIPer01

List of figures

Figure 1: Basic application schematic ........................................................................................................1

Figure 2: Connection diagram ....................................................................................................................5

Figure 3: R_thJA/(R_thJA@A=100 mm²) ............................................................................................................7

Figure 4: I_DLIMvs T_J...................................................................................................................................12

Figure 5: F_OSCvs T_J...................................................................................................................................12

Figure 6: V_{HV_START}vs T_J...........................................................................................................................12

Figure 7: V_{FB_REF}vs T_J..............................................................................................................................12

Figure 8: Quiescent current Iq vs T_J.........................................................................................................12

Figure 9: Operating current I_CCvs T_J........................................................................................................12

Figure 10: I_CH1vs T_J..................................................................................................................................13

Figure 11: I_CH1vs V_DRAIN............................................................................................................................13

Figure 12: I_CH2vs T_J..................................................................................................................................13

Figure 13: I_CH2vs V_DRAIN............................................................................................................................13

Figure 14: I_CH3vs T_J..................................................................................................................................13

Figure 15: I_CH3vs V_DRAIN............................................................................................................................13

Figure 16: G_Mvs T_J...................................................................................................................................14

Figure 17: I_COMPvs T_J................................................................................................................................14

Figure 18: R_DS(on)vs T_J..............................................................................................................................14

Figure 19: Static drain-source on-resistance............................................................................................14

Figure 20: V_BVDSSvs T_J.............................................................................................................................14

Figure 21: Output characteristic................................................................................................................14

Figure 22: SOA SSOP10 package ...........................................................................................................15

Figure 23: Maximum avalanche energy vs T_J...........................................................................................15

Figure 24: Block diagram..........................................................................................................................16

Figure 25: IC supply modes: self-supply and external supply ..................................................................17

Figure 26: Power-ON and power-OFF......................................................................................................18

Figure 27: Soft startup ..............................................................................................................................19

Figure 28: Pulse-skipping during startup ..................................................................................................20

Figure 29: Short-circuit condition..............................................................................................................22

Figure 30: Connection for input overvoltage protection (isolated or non-isolated topologies) .................23

Figure 31: Connection for output overvoltage protection (non-isolated topologies).................................24

Figure 32: Thermal shutdown timing diagram ..........................................................................................25

Figure 33: Flyback converter (non-isolated) .............................................................................................26

Figure 34: Flyback converter with line OVP (non-isolated) ......................................................................26

Figure 35: Flyback converter (isolated) ....................................................................................................27

Figure 36: Primary side regulation isolated flyback converter..................................................................27

Figure 37: Buck converter (positive output)..............................................................................................28

Figure 38: Buck-boost converter (negative output) ..................................................................................28

Figure 39: P_INversus V_INin no-load, V_OUT= 5 V.......................................................................................29

Figure 40: P_INversus V_INin light load, V_OUT= 5 V ....................................................................................29

Figure 41: Recommended routing for flyback converter...........................................................................31

Figure 42: Recommended routing for buck converter ..............................................................................31

Figure 43: SSOP10 package outline ........................................................................................................32

Figure 44: SSOP10 recommended footprint.............................................................................................33

4/36

DocID028751 Rev 1

VIPer01

Pin setting

1

Pin setting

Figure 2: Connection diagram

Table 1: Pin description

Function

SSOP10 Name

Ground and MOSFET source. Connection of source of the internal MOSFET

and the return of the bias current of the device. All groundings of bias

components must be tied to a trace going to this pin and kept separate from the

pulsed current return.

1

GND

Controller supply. An external storage capacitor has to be connected across

this pin and GND. The pin, internally connected to the high voltage current

source, provides the VCC capacitor charging current at startup and during

steady-state operation, if the self-supply mode is selected. A small bypass

capacitor (0.1 μF typ.) in parallel, placed as close as possible to the IC, is also

recommended, for noise filtering purpose.

2

VCC

Disable. If its voltage exceeds the internal threshold V_{DIS_th}(1.2 V typ.) for more

than t_DEBtime (1 ms, typ.), the PWM is disabled in auto-restart mode. An input

overvoltage protection can be built by connecting a voltage divider between DIS

pin and the rectified mains. In case of non-isolated topologies, with the same

principle an output overvoltage protection can be implemented. If the disable

function is not required, DIS pin must be soldered to GND, which excludes the

function.

3

DIS

FB

Direct feedback. It is the inverting input of the internal transconductance E/A,

which is internally referenced to 1.2 V with respect to GND. In case of non-

isolated converter, the output voltage information is directly fed into the pin

through a voltage divider. In case of primary regulation, the FB voltage divider is

connected to the VCC. The E/A is disabled soldering FB to GND.

4

5

Compensation. It is the output of the internal E/A. A compensation network is

placed between this pin and GND to achieve stability and good dynamic

COMP performance of the control loop. In case of secondary feedback, the internal E/A

must be disabled and the COMP directly driven by the optocoupler to control the

DRAIN peak current setpoint.

MOSFET drain. The internal high voltage current source sinks current from this

pin to charge the VCC capacitor at startup and during steady-state operation.

These pins are mechanically connected to the internal metal PAD of the

MOSFET in order to facilitate heat dissipation. On the PCB, copper area must

6 to 10

DRAIN

be placed under these pins in order to decrease the total junction-to-ambient

thermal resistance thus facilitating the power dissipation.

DocID028751 Rev 1

5/36

Electrical and thermal ratings

VIPer01

2

Electrical and thermal ratings

Table 2: Absolute maximum ratings

Symbol

Parameter ⁽¹⁾⁽²⁾

Min.

Max.

Unit

V_DS

6 to 10

Drain-to-source (ground) voltage

-0.3

800

V

Pulsed drain current (pulse-width limited by

SOA)

I_DRAIN

V_CC

6 to 10

2

A

Internally

limited

VCC voltage

-0.3

V

I_CC

V_DIS

V_FB

2

3

4

5

VCC internal Zener current (pulsed)

DIS voltage

45 ⁽³⁾

4.25 ⁽⁴⁾

5.25 ⁽⁴⁾

1 ⁽⁵⁾

mA

V

-0.3

FB voltage

V

V_COMP

P_TOT

T_J

COMP voltage

V

Power dissipation @ T_amb< 50 °C

Junction temperature operating range

Storage temperature

W

°C

-40

-55

150

T_STG

150

Notes:

⁽¹⁾Stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.

⁽²⁾Exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability.

⁽³⁾Pulse-width limited by maximum power dissipation, P_TOT

.

⁽⁴⁾The AMR value is intended when V_CC≥ 5 V, otherwise the value V_CC+ 0.3 V has to be considered.

⁽⁵⁾When mounted on a standard single side FR4 board with 100 mm² (0.1552 inch) of Cu (35 μm thick).

Table 3: Thermal data

Max. value

Symbol

Parameter

Unit

SSOP10

35

R_thJP

Thermal resistance junction-pin

Thermal resistance junction-ambient (dissipated power 1 W)

Thermal resistance junction-ambient (dissipated power 1 W) ⁽²⁾

145

°C/W

(1)

R_thJA

90

Notes:

⁽¹⁾Derived by characterization.

⁽²⁾When mounted on a standard single side FR4 board with 100 mm² (0.155²inch) of Cu (35 µm thick).

6/36

DocID028751 Rev 1

VIPer01

Electrical and thermal ratings

Figure 3: R_thJA/(R_thJA@A=100 mm²)

Table 4: Avalanche characteristics

Test conditions

Typ.

Symbol

Parameter

Min.

Max. Unit

Repetitive and non-repetitive

Pulse-width limited by T_Jmax

I_AR

Avalanche current

0.8

A

L = 1 mH

I_AS= 0.8 A

Single pulse avalanche

energy ⁽¹⁾

V_DS= 50 V

E_AS

1

mJ

R_G= 47 Ω

Starting T_J= 25 °C

Notes:

⁽¹⁾Parameter derived by characterization.

DocID028751 Rev 1

7/36

Electrical and thermal ratings

VIPer01

2.1

Electrical characteristics

T_j= -40 to 125 °C, V_CC= 9 V (unless otherwise specified).

Table 5: Power section

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

I_DRAIN= 1 mA

V_COMP= GND

T_J= 25 °C

V_BVDSS

Breakdown voltage

800

V

V_DS= 400 V

V_COMP= GND

T_J= 25 °C

Drain-source leakage

current

I_DSS

1

µA

V_DRAIN= max.

rating

OFF-state drain current

I_OFF

45

V_COMP= GND

T_J= 25 °C

I_DRAIN= 360 mA

T_J= 25 °C

30

60

Static drain-source

ON-resistance

R_DS(on)

Ω

I_DRAIN= 360 mA

T_J= 125 °C

V_GS= 0

Equivalent output

capacitance

C_{OSS EQ}

V_DS= 0 to 640 V

T_J= 25 °C

10

pF

Table 6: Supply section

Test conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

High voltage start-up current source

Breakdown voltage of

V_{BVDSS_SU}

T_J= 25 °C

800

V

start-up MOSFET

Drain-source start-up

V_{HV_START}

voltage

18

38

V

V_FB> V_{FB_REF}

R_G

I_CH1

I_CH2

Start-up resistor

22

30

MΩ

V_DRAIN= 400 V

V_DRAIN= 600 V

V_DRAIN= 100 V

V_CC= 0 V

VCC charging current at

startup

1.4

1.9

2.4

V_FB> V_{FB_REF}

V_DRAIN= 100 V

mA

VCC charging current at

startup

3.5

7.6

4.5

8.8

5.5

10

V_CC= 6 V

V_FB> V_{FB_REF}

V_DRAIN=100 V

Max. VCC charging

current in self-supply

(1)

I_CH3

V_CC= 6 V

8/36

DocID028751 Rev 1

VIPer01

Electrical and thermal ratings

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

IC supply and consumptions

V_CC

Operating voltage range

V_GND= 0 V

4.5

30

35

V

V_CCclamp

I_{clamp max}

Clamp voltage

I_CC= I_{clamp_max}

32.5

30

(2)

Clamp shutdown current

mA

Clamp time before

shutdown

t_{clamp max}

V_CCon

V_CSon

V_CCoff

I_q

325

7.5

4

500

8

675

8.5

µs

V

V_FB= 1.2 V

V_CCstart-up threshold

V_DRAIN= 400 V

HV current source

turn-on threshold

V_CCfalling

4.25

4

4.5

V

V_FB= 1.2 V

UVLO

3.75

4.25

0.45

V

V_DRAIN= 400 V

Not switching

V_FB> V_{FB_REF}

Quiescent current

0.3

mA

V_DS= 150 V

V_COMP= 1.2 V

F_OSC= 30 kHz

0.75

0.85

1

1.1

1.25

1.5

V_DS= 150 V

Operating supply

current, switching

I_CC

V_COMP= 1.2 V

F_OSC= 60 kHz

mA

V_DS= 150 V

V_COMP= 1.2 V

F_OSC= 120 kHz

Notes:

⁽¹⁾Current supplied during the main MOSFET OFF time only.

⁽²⁾Parameter assured by design and characterization.

Table 7: Controller section

Symbol

E/A

V_{FB_REF}

V_{FB_DIS}

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Reference voltage

E/A disable voltage

Pull-up current

1.175

150

1.2

180

1

1.225

210

V

mV

µA

I_{FB PULL UP}

0.9

1.1

V_COMP= 1.5 V

V_FB> V_{FB_REF}

G_M

Transconductance

Max. source current

Max. sink current

Dynamic resistance

350

65

500

100

105

58

650

135

140

66

µA/V

µA

V_COMP= 1.5 V

V_FB= 0.5 V

I_COMP1

V_FB= 2 V

I_COMP2

70

µA

V_COMP= 1.5 V

V_COMP= 2.7 V

V_FB= GND

R_COMP(DYN)

50

kΩ

Current limitation

threshold

V_COMPH

V_COMPL

3

V

PFM threshold

0.8

DocID028751 Rev 1

9/36

Electrical and thermal ratings

Symbol

VIPer01

Unit

Parameter

Test conditions

Min.

Typ.

Max.

OLP and timing

T_J= 25 °C

VIPer011*

114

228

120

240

360

I²f

126

252

378

T_J= 25 °C

VIPer012*

I_DLIM

Drain current limitation

Power coefficient

mA

T_J= 25 °C

VIPer013*

342

I_{DLIM_TYP}²x

F_{OSC_TYP}

I²f

0.9 ·I²f

1.1 ·I²f A²·kHz

T_J= 25 °C

(1)

V_COMP= V_COMPL

23

45

35

65

80

1.2

47

VIPer011*

T_J= 25 °C

Drain current limitation at

light load

(1)

I_{DLIM_PFM}

V_COMP= V_COMPL

85

mA

VIPer012*

T_J= 25 °C

(1)

V_COMP= V_COMPL

60

100

1.25

VIPer013*

V_CC= 9 V

V_COMP= 1 V

V_FB= V_{FB_REF}

V_DISth

Disable threshold voltage

1.15

V

Debounce time before

DIS protection tripping

t_DIS

0.65

325

1

1.35

675

ms

Restart time after DIS

protection tripping

t_{DIS_RESTART}

500

t_OVL

Overload delay time

45

50

55

ms

VIPer01*X

90

100

200

400

110

220

440

F_OSC= F_{OSC MIN}

VIPer01*L

t_{OVL_MAX}

Max. overload delay time

180

360

F_OSC= F_{OSC MIN}

VIPer01*H

F_OSC= F_{OSC MIN}

t_SS

Soft-start time

5

8

11

ms

ns

s

V_CC= 9 V

t_{ON_MIN}

Minimum turn-on time

Restart time after fault

V_COMP= 1 V

V_FB= V_{FB_REF}

250

0.65

360

1.35

t_RESTART

1

10/36

DocID028751 Rev 1

VIPer01

Electrical and thermal ratings

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Oscillator

T_J= 25 °C

VIPer01*X

27

54

30

60

33

66

T_J= 25 °C

VIPer01*L

F_OSC

Switching frequency

kHz

T_J= 25 °C

VIPer01*H

108

13.5

120

15

132

16.5

Minimum switching

frequency

F_{OSC_MIN}

F_D

T_J= 25 °C ⁽²⁾

kHz

%

±7

F_OSC

(3)

Modulation depth

(3)

F_M

Modulation frequency

Max. duty cycle

260

Hz

%

D_MAX

70

80

Thermal shutdown

temperature

(3)

T_SD

150

160

°C

Notes:

⁽¹⁾See Section 5.10: "Pulse frequency modulation".

⁽²⁾See Section 5.7: "Pulse-skipping".

⁽³⁾Parameter assured by design and characterization.

DocID028751 Rev 1

11/36

Typical electrical characteristics

VIPer01

3

Typical electrical characteristics

Figure 4: I_DLIMvs T_J

Figure 5: F_OSCvs T_J

Figure 6: V_{HV_START}vs T_J

Figure 7: V_{FB_REF}vs T_J

Figure 8: Quiescent current Iq vs T_J

Figure 9: Operating current I_CCvs T_J

12/36

DocID028751 Rev 1

VIPer01

Typical electrical characteristics

Figure 11: I_CH1vs V_DRAIN

Figure 10: I_CH1vs T_J

Figure 13: I_CH2vs V_DRAIN

Figure 12: I_CH2vs T_J

Figure 15: I_CH3vs V_DRAIN

Figure 14: I_CH3vs T_J

DocID028751 Rev 1

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Typical electrical characteristics

VIPer01

Figure 16: G_Mvs T_J

Figure 17: I_COMPvs T_J

Figure 18: R_DS(on)vs T_J

Figure 19: Static drain-source on-resistance

Figure 20: V_BVDSSvs T_J

Figure 21: Output characteristic

14/36

DocID028751 Rev 1

VIPer01

Typical electrical characteristics

Figure 23: Maximum avalanche energy vs T_J

Figure 22: SOA SSOP10 package

* When mounted on a standard single side FR4 board

with 50 mm²(0.077 sq in) of Cu (35 μm thick).

DocID028751 Rev 1

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General description

VIPer01

4

General description

4.1

Block diagram

Figure 24: Block diagram

4.2

Typical power capability

Table 8: Typical power

Vin: 230 V_AC

Open frame ⁽²⁾

8 W

Vin: 85-265 V_AC

Open frame ⁽²⁾

4.5 W

Adapter ⁽¹⁾

7 W

4 W

Notes:

⁽¹⁾Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.

⁽²⁾Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat-sinking.

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DocID028751 Rev 1

VIPer01

General description

4.3

Primary MOSFET

The primary switch is implemented with an avalanche-rugged N-channel MOSFET with

minimum breakdown voltage 800 V, V_BVDSS, and maximum on-resistance of 30 Ω, R_DS(on)

The sense-FET is embedded and it allows a virtually lossless current sensing. The

MOSFET is embedded and it allows the HV voltage start-up operation.

.

The MOSFET gate driver controls the gate current during both turn-on and turn-off in order

to minimize EMI. Under UVLO conditions the embedded pull-down circuit holds the gate

low in order to ensure that the MOSFET cannot be turned on accidentally.

4.4

High voltage startup

The embedded high voltage startup includes both the 800 V start-up FET, whose gate is

biased through the resistor R_G, and the switchable HV current source, delivering the current

I_HV. The major portion of I_HV, (I_CH), charges the capacitor connected to VCC. A minor

portion is sunk by the controller block.

At startup, as the voltage across the DRAIN pin exceeds the V_{HV_START}threshold, the HV

current source is turned on, charging linearly the C_Scapacitor. At the very beginning of the

startup, when Cs is fully discharged, the charging current is low, I_CH1, in order to avoid IC

damaging in case V_CCis accidentally shorted to GND. As V_CCexceeds 1 V, I_CHis increased

to I_CH2in order to speed up the charging of C_S.

As V_CCreaches the start-up threshold V_CCon(8 V typ.) the chip starts operating, the primary

MOSFET is enabled to switch, the HV current source is disabled and the device is powered

by the energy stored in the C_Scapacitor.

In steady-state the IC supports two different kind of supplies: self-supply and external

supply, as shown in Figure 25: "IC supply modes: self-supply and external supply".

Figure 25: IC supply modes: self-supply and external supply

External supply

Self-supply

V_Aux

V_OUT

I_CH

VCC

I_CH

C_S

from auxiliary winding

from the output

GIPD160720151024MT

In self-supply only one capacitor C_Sis connected to the VCC and the device is supplied by

the energy stored in C_S. After the IC startup, due to its internal consumption, the VCC

decays to V_CCson(4.25 V, typ.) and the HV current source is turned on delivering the current

I_CH3until V_CCis recharged to V_CCon. The HV current source is reactivated when V_CCdecays

to V_CCsonagain. The I_CH3is supplied during the switching OFF time only. In external supply

the HV current source is always kept off by maintaining the V_CCabove V_CSon. This can be

DocID028751 Rev 1

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General description

VIPer01

obtained through a transformer auxiliary winding or a connection from the output, the latter

in case of non-isolated topology only. In this case the residual consumption is given by the

power dissipated on R_G, calculated as follows:

At the nominal input voltage, 230 V_AC, the typical consumption (R_G= 30 MΩ) is 3.5 mW and

the worst-case consumption (R_G= 22 MΩ) is 4.8 mW.

When the IC is disconnected from the mains, or there is a mains interruption, for some time

the converter keeps on working, powered by the energy stored in the input bulk capacitor.

When it is discharged below a critical value, the converter is no longer able to keep the

output voltage regulated. During the power down, when the DRAIN voltage becomes too

low, the HV current source (I_HV) remains off and the IC is stopped as soon as the V_CCdrops

below the UVLO threshold, V_CCoff

.

Figure 26: Power-ON and power-OFF

18/36

DocID028751 Rev 1

VIPer01

General description

4.5

Soft-start

The internal soft-start function of the device progressively increases the cycle-by-cycle

current limitation set point from zero up to I_DLIMin 8 steps. The soft-start time, t_SS, is

internally set at 8 ms. This function is activated at any attempt of converter startup and at

any restart after a fault event. The feature protects the system at the startup when the

output load occurs like a short-circuit and the converter works at its maximum drain current

limitation.

Figure 27: Soft startup

4.6

4.7

Oscillator

The IC embeds a fixed frequency oscillator with jittering feature. The switching frequency is

modulated by approximately ± 7% kHz F_OSCat 260 Hz rate. The purpose of the jittering is

to get a spread-spectrum action that distributes the energy of each harmonic of the

switching frequency over a number of frequency bands, having the same energy on the

whole but smaller amplitudes. This helps to reduce the conducted emissions, especially

when measured with the average detection method or, which is the same, to pass the EMI

tests with an input filter of smaller size than that needed in absence of jittering feature.

Three options with different switching frequencies, F_OSC, are available: 30 (X type), 60 (L

type) and 120 kHz (H type).

Pulse-skipping

The IC embeds a pulse-skip circuit that operates in the following ways:



each time the DRAIN peak current exceeds I_DLIMlevel within t_{ON_MIN}, the switching

cycle is skipped. The cycles can be skipped until the minimum switching frequency is

reached, F_{OSC_MIN}(15 kHz).

each time the DRAIN peak current does not exceed I_DLIMwithin t_{ON_MIN}, a switching

cycle is restored. The cycles can be restored until the nominal switching frequency is

reached, F_OSC(30 or 60 or 120 kHz).

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General description

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If the converter is operated at F_{OSC_MIN}, the IC is turned off after the time t_{OVL_MAX}(100 ms or

200 ms or 400 ms typ., depending on F_OSC) and then automatically restarted with soft-start

phase, after the time t_RESTART(1 s, typ.).

The protection is intended to avoid the so called "flux-runaway" condition often present at

converter startup and due to the fact that the primary MOSFET, which is turned on by the

internal oscillator, cannot be turned off before than the minimum on-time.

During the on-time, the inductor is charged by the input voltage and if it cannot be

discharged by the same amount during the off-time, in every switching cycle there is an

increase of the average inductor current, that can reach dangerously high values until the

output capacitor is not charged enough to ensure the inductor discharge rate needed for

the volt-second balance. This condition may happen at converter startup, because of the

low output voltage.

In the following Figure 28: "Pulse-skipping during startup" the effect of pulse-skipping

feature on the DRAIN peak current shape is shown (solid line), compared with the DRAIN

peak current shape when pulse-skipping feature is not implemented (dashed line).

Providing more time for cycle-by-cycle inductor discharge when needed, this feature is

effective by keeping low the maximum DRAIN peak current avoiding the flux-runaway

condition.

Figure 28: Pulse-skipping during startup

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General description

4.8

Direct feedback

The IC embeds a transconductance type error amplifier (E/A) whose inverting input, ground

reference and output are FB and COMP, respectively. The internal reference voltage of the

E/A is V_{FB_REF}(1.2 V typical value referred to GND). In non-isolated topologies this tightly

regulates positive output voltages through a simple voltage divider applied to the output

voltage terminal, FB and GND.

The E/A output is scaled down and fed into the PWM comparator, where it is compared to

the voltage across the sense resistor in series to the sense-FET, thus setting the cycle-by-

cycle drain current limitation.

An R-C network connected on the output of the E/A (COMP) is usually used to stabilize the

overall control loop.

The FB is provided with an internal pull-up to prevent a wrong IC behavior when the pin is

accidentally left floating.

The E/A is disabled if the FB voltage is lower than V_{FB_DIS}(200 mV, typ.).

4.9

Secondary feedback

When a secondary feedback is required, the internal E/A has to be disabled shorting FB to

GND (V_FB< V_{FB_DIS}). With this setting, COMP is internally connected to a pre-regulated

voltage through the pull-up resistor R_COMP(DYN), (60 kΩ, typ.) and the voltage across COMP

is set by the current sunk.

This allows the output voltage value to be set through an external error amplifier (TL431 or

similar) placed on the secondary side, whose error signal is used to set the DRAIN peak

current setpoint corresponding to the output power demand. If isolation is required, the

error signal must be transferred through an optocoupler, with the phototransistor collector

connected across COMP and GND.

4.10

Pulse frequency modulation

If the output load is decreased, the feedback loop reacts lowering the V_COMPvoltage, which

reduces the DRAIN peak current setpoint, down to the minimum value of I_{DLIM_PFM}when the

V_COMPLthreshold is reached.

If the load is furtherly decreased, the DRAIN peak current value is maintained at I_{DLIM_PFM}

and some PWM cycles are skipped. This kind of operation is referred to as “pulse

frequency modulation” (PFM), the number of the skipped cycles depends on the balance

between the output power demand and the power transferred from the input. The result is

an equivalent switching frequency which can go down to some hundreds Hz, thus reducing

all the frequency-related losses.

This kind of operation, together with the extremely low IC quiescent current, allows very low

input power consumption in no-load and light load, while the low DRAIN peak current

value, I_{DLIM_PFM}, prevents any audible noise which could arise from low switching frequency

values. When the load is increased, V_COMPincreases and PFM is exited. V_COMPreaches its

maximum at V_COMPHand corresponding to that value, the DRAIN current limitation (I_DLIM) is

reached.

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General description

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4.11

Overload protection

To manage the overload condition, the IC embeds the following main blocks: the OCP

comparator to turn off the power MOSFET when the drain current reaches its limit (I_DLIM) ,

the up and down OCP counter to define the turn-off delay time in case of continuous

overload (t_OVL= 50 ms typ.) and the timer to define the restart time after protection tripping

(t_RESTART= 1 s typ.).

In case of short-circuit or overload, the control level on the inverting input of the PWM

comparator is greater than the reference level fed into the inverting input of the OCP

comparator. As a result, the cycle-by-cycle turn-off of the power switch is triggered by the

OCP comparator instead of PWM comparator. Every cycle where this condition is met, the

OCP counter is incremented and if the fault condition lasts longer than t_OVL(corresponding

to the counter end-of-count), the protection is tripped, the PWM is disabled for t_RESTART

,

then it resumes switching with soft-start and, if the fault is still present, it is disabled again

after t_OVL. The OLP management prevents IC from operating indefinitely at I_DLIMand the low

repetition rate of the restart attempts of the converter avoids IC overheating in case of

repeated fault events.

After the fault removal, the IC resumes working normally. If the fault is removed earlier than

the protection tripping (before t_OVL), the t_OVL-counter is decremented on a cycle-by-cycle

basis down to zero and the protection is not tripped. If the fault is removed during t_RESTART

,

the IC waits for the t_RESTARTperiod has elapsed before resuming switching.

In fault condition the V_CCranges between V_CSonand V_CConlevels, due to the periodical

activation of the HV current source recharging the V_CCcapacitor.

Figure 29: Short-circuit condition

4.12

Max. duty cycle counter protection

The IC embeds a max. duty cycle counter, which disables the PWM if the MOSFET is

turned off by max. duty cycle (70% min., 80% max.) for ten consecutive switching cycles.

After protection tripping, the PWM is stopped for t_RESTARTand then activated again with soft-

start phase until the fault condition is removed.

In some cases (i.e. breaking of the loop) even if V_COMPis saturated high, the OLP cannot be

triggered because at every switching cycle the PWM is turned off by maximum duty cycle

before than DRAIN peak current reaches the I_DLIMsetpoint. As a result, the output voltage

V_OUTcan increase without control by keeping a value much higher than the nominal one

with the risk for the output capacitor, the output diode and the IC itself. The max. duty cycle

counter protection avoids this kind of failures.

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General description

4.13

VCC clamp protection

This protection can occur when the IC is supplied by auxiliary winding or diode from the

output voltage, when an output overvoltage produces an increase of V_CC

.

If VCC reaches the clamp level V_CCclamp(30 V, min. referred to GND) the current injected

into the pin is monitored and if it exceeds the internal threshold I_{clamp_max}(30 mA, typ.) for

more than t_{clamp_max}(500 µs, typ.), the PWM is disabled for t_RESTART(1 s, typ.) and then

activated again in soft-start phase. The protection is disabled during the soft-start time.

4.14

Disable function

When the voltage across the pin is externally pulled above V_{DIS_th}(1.2 V typ.) for more than

t_DEB(for instance by a voltage divider connected to some higher voltages), the PWM is

disabled. If the voltage divider on the DIS pin is connected to the rectified mains, as shown

in Figure 30: "Connection for input overvoltage protection (isolated or non-isolated

topologies)", an input overvoltage protection can be built.

Figure 30: Connection for input overvoltage protection (isolated or non-isolated topologies)

In case of non-isolated topologies, by following the same principle an output overvoltage

protection can be built, as shown in Figure 31: "Connection for output overvoltage

protection (non-isolated topologies)".

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General description

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Figure 31: Connection for output overvoltage protection (non-isolated topologies)

If V_OVPis the desired input/output overvoltage threshold, the resistors R_Hand R_Lof the

voltage divider are to be selected according to the following formula:

The power dissipation associated to the DIS network is:

in case of connection for the input overvoltage detection and

in case of connection for the output overvoltage detection.

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General description

4.15

Thermal shutdown

If the junction temperature becomes higher than the internal threshold T_SD(160 °C, typ.),

the PWM is disabled. After t_RESTARTtime, a single switching cycle is performed, during

which the temperature sensor embedded in the power MOSFET section is checked. If a

junction temperature above T_SDis still measured, the PWM is maintained disabled for

t_RESTARTtime, otherwise it resumes switching with soft-start phase.

During t_RESTARTV_CCis maintained between V_CSonand V_CConlevels by the HV current source

periodical activation. Such a behavior is summarized in below figure:

Figure 32: Thermal shutdown timing diagram

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Application information

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5

Application information

5.1

Typical schematics

Figure 33: Flyback converter (non-isolated)

Figure 34: Flyback converter with line OVP (non-isolated)

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Application information

Figure 35: Flyback converter (isolated)

Figure 36: Primary side regulation isolated flyback converter

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Application information

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Figure 37: Buck converter (positive output)

Figure 38: Buck-boost converter (negative output)

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Application information

5.3

Energy saving performance

The device allows designing applications to be compliant with the most stringent energy

saving regulations. In order to show the typical performance is achievable, the active mode

average efficiency and the efficiency at 10% of the rated output power of a single output

flyback converter have been measured and are reported in Table 9: "Power supply

efficiency, V_OUT= 5 V". In addition, no-load and light load consumptions are shown in

Figure 39: "P_INversus V_INin no-load, V_OUT= 5 V" and Figure 40: "P_INversus V_INin light

load, V_OUT= 5 V".

Table 9: Power supply efficiency, V_OUT= 5 V

10 % output load

efficiency [%]

Active mode average

efficiency [%]

V_IN

Pin @ no-load [mW]

115 V_AC

230 V_AC

72.2

65.1

74.6

75.1

4.5

8.6

Figure 39: P_INversus V_INin no-load, V_OUT= 5 V

Figure 40: P_INversus V_INin light load, V_OUT= 5 V

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Application information

VIPer01

5.4

Layout guidelines and design recommendations

A proper printed circuit board layout ensures the correct operation of any switch-mode

converter and this is true for the VIPer as well. The main reasons to have a proper PCB

layout are:



Providing clean signals to the IC, ensuring good immunity against external and

switching noises.

Reducing the electromagnetic interferences, both radiated and conducted, to pass the

EMC tests more easily.

If the VIPer is used to design a SMPS, the following basic rules should be considered:



Separating signal from power tracks. Generally, traces carrying signal currents

should run far from others carrying pulsed currents or with fast swinging voltages.

Signal ground traces should be connected to the IC signal ground, GND, using a

single "star point", placed close to the IC. Power ground traces should be connected

to the IC power ground, GND. The compensation network should be connected to the

COMP, maintaining the trace to GND as short as possible. In case of two-layer PCB, it

is a good practice to route signal traces on one PCB side and power traces on the

other side.



Filtering sensitive pins. Some crucial points of the circuit need or may need filtering.

A small high-frequency bypass capacitor to GND might be useful to get a clean bias

voltage for the signal part of the IC and protect the IC itself during EFT/ESD tests. A

low ESL ceramic capacitor (a few hundreds pF up to 0.1 μF) should be connected

across VCC and GND, placed as close as possible to the IC. With flyback topologies,

when the auxiliary winding is used, it is suggested to connect the VCC capacitor on

the auxiliary return and then to the main GND using a single track.

Keeping power loops as confined as possible. The area circumscribed by current

loops where high pulsed current flow should be minimized to reduce its parasitic self-

inductance and the radiated electromagnetic field. As a consequence, the

electromagnetic interferences produced by the power supply during the switching are

highly reduced. In a flyback converter the most critical loops are: the one including the

input bulk capacitor, the power switch, the power transformer, the one including the

snubber, the one including the secondary winding, the output rectifier and the output

capacitor. In a buck converter the most critical loop is the one including the input bulk

capacitor, the power switch, the power inductor, the output capacitor and the free-

wheeling diode.



Reducing line lengths. Any wire acts as an antenna. With the very short rise times

exhibited by EFT pulses, any antenna can receive high voltage spikes. By reducing

line lengths, the level of received radiated energy is reduced, and the resulting spikes

from electrostatic discharges are lower. This also keeps both resistive and inductive

effects to a minimum. In particular, all traces carrying high currents, especially if

pulsed (tracks of the power loops) should be as short and wide as possible.

Optimizing track routing. As levels of pickup from static discharges are likely greater

near the edges of the board, it is wise to keep any sensitive lines away from these

areas. Input and output lines often need to reach the PCB edge at some stage, but

they can be routed away from the edge as soon as possible where applicable. Since

vias are to be considered inductive elements, it is recommended to minimize their

number in the signal path and avoid them in the power path.

Improving thermal dissipation. An adequate copper area has to be provided under

the DRAIN pins as heatsink, while it is not recommended to place large copper areas

on the GND.

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Application information

Figure 41: Recommended routing for flyback converter

Figure 42: Recommended routing for buck converter

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Package information

VIPer01

6

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK^®packages, depending on their level of environmental compliance. ECOPACK^®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK^®is an ST trademark.

6.1

SSOP10 package information

Figure 43: SSOP10 package outline

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Package information

Table 10: SSOP10 mechanical data

mm

Dim.

Min.

Typ.

Max.

1.75

0.25

A

A1

A2

b

0.10

1.25

0.31

0.17

4.80

5.80

3.80

0.51

0.25

5

c

D

E

4.90

6

6.20

4

E1

e

3.90

1

h

0.25

0.40

0°

0.50

0.90

8°

L

K

Figure 44: SSOP10 recommended footprint

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Ordering information

VIPer01

7

Ordering information

Table 11: Order code

Package

Order code

I_DLIM(OCP)

120 mA

240 mA

360 mA

120 mA

240 mA

360 mA

240 mA

360 mA

F_OSC± jitter

VIPer011XS(TR)

VIPer012XS(TR)

VIPer013XS(TR)

VIPer011LS(TR)

VIPer012LS(TR)

VIPer013LS(TR)

VIPer012HS(TR)

VIPer013HS(TR)

30 kHz ± 7%

SSOP10 tube (tape and reel)

60 kHz ± 7%

120 kHz ± 7%

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Revision history

8

Revision history

Table 12: Document revision history

Revision

Date

Changes

Initial release

09-Mar-2016

1

DocID028751 Rev 1

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VIPer01

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and

improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST

products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order

acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the

design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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DocID028751 Rev 1


型号：	VIPER011LSTR
厂家：	ST
描述：	Energy saving off-line high voltage converter
文件：	总36页 (文件大小：1677K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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