VIPER06LS [STMICROELECTRONICS]
Fixed-frequency VIPer plus family; 固定频率蝰蛇加上家庭
| 型号： | VIPER06LS |
| 厂家： | 
ST |
| 描述： | Fixed-frequency VIPer plus family |
| 文件： | 总28页 (文件大小：999K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VIPER06
Fixed-frequency VIPer™ plus family
Datasheet — production data
Features
■ 800 V avalanche rugged power section
■ PWM operation with frequency jittering for low
EMI
SSO10
DIP-7
■ Operating frequency:
– 30 kHz for VIPER06Xx
– 60 kHz for VIPER06Lx
– 115 kHz for VIPER06Hx
Figure 1.
Typical application
$# INPUT VOLTAGE
$# OUTPUT VOLTAGE
ꢆ
■ No need for an auxiliary winding in low-power
ꢅ
applications
■ Standby power < 30 mW at 265 VAC
■ Limiting current with adjustable set point
■ On-board soft-start
$2 !).
#/-0
6)0%2ꢀꢁ
'.$
6$$
,)-
&"
■ Safe auto-restart after a fault condition
■ Hysteretic thermal shutdown
!-ꢂꢂꢃꢃꢄVꢂ
Applications
■ Replacement of capacitive power supplies
■ Home appliances
■ Power metering
■ LED drivers
Description
The VIPER06 is an offline converter with an 800 V
avalanche rugged power section, a PWM
controller, a user-defined overcurrent limit, open-
loop failure protection, hysteretic thermal
protection, soft startup and safe auto-restart after
any fault condition. The device is able to power
itself directly from the rectified mains, eliminating
the need for an auxiliary bias winding. Advanced
frequency jittering reduces EMI filter cost. Burst
mode operation and the device’s very low power
consumption both help to meet the standards set
by energy-saving regulations.
March 2012
Doc ID 022794 Rev 1
1/28
This is information on a product in full production.
www.st.com
28
Contents
VIPER06
Contents
1
2
3
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
4.2
4.3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
High voltage current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Soft startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Adjustable current limit set point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FB pin and COMP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Automatic auto-restart after overload or short-circuit . . . . . . . . . . . . 19
Open-loop failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
7
8
9
10
11
12
13
14
15
16
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VIPER06
17
Contents
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
18
Doc ID 022794 Rev 1
3/28
Block diagram
VIPER06
1
Block diagram
Figure 2.
Block diagram
VDD
DRAIN
SUPPLY
&
UVLO
HV_ON
Internal Supply BUS &
REFERENCE VOLTAGES
IDDch
UVLO
THERMAL
SHUTDOWN
IDLIM
LIM
set-up
Oscillator
OTP
-
TURN-ON
LOGIC
S
VCOMPL
+
BURST-MODE
Logic
BURST
Q
OCP
Burst
LEB
R
-
+
PWM
-
FB
E/A
+
OTP
VREF_FB
RSENSE
COMP
GND
2
Typical power
Table 1.
Typical power
230 VAC
85-265 VAC
Part number
Adapter(1)
Open frame(2)
Adapter(1)
Open frame(2)
VIPER06
6 W
8 W
4 W
5 W
1. Typical continuous power in non-ventilated enclosed adapter measured at 50 ° C ambient.
2. Maximum practical continuous power in an open-frame design at 50 °C ambient, with adequate heat
sinking.
4/28
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VIPER06
Pin settings
3
Pin settings
Figure 3.
Connection diagram (top view)
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
GND
VDD
LIM
FB
COMP
AM11339v1
Note:
The copper area for heat dissipation has to be designed under the DRAIN pins.
Table 2.
Pin
Pin description
Name
Function
DIP-7
SSO10
Connected to the source of the internal power MOSFET and controller
ground reference.
1
1
GND
VDD
Supply voltage of the control section. This pin provides the charging
current of the external capacitor.
2
3
2
3
This pin allows setting the drain current limitation. The limit can be
reduced by connecting an external resistor between this pin and GND.
Pin left open if default drain current limitation is used.
LIM
FB
Inverting input of the internal transconductance error amplifier.
Connecting the converter output to this pin through a single resistor
results in an output voltage equal to the error amplifier reference
voltage (see VFB_REF in Table 6). An external resistor divider is
required for higher output voltages.
4
4
Output of the internal transconductance error amplifier. The
compensation network has to be placed between this pin and GND to
achieve stability and good dynamic performance of the voltage control
loop. The pin is used also to directly control the PWM with an
optocoupler. The linear voltage range extends from VCOMPL to
5
5
COMP
DRAIN
VCOMPH (Table 6).
High-voltage drain pins. The built-in high-voltage switched startup bias
current is drawn from these pins too.
7, 8
6-10
Pins connected to the metal frame to facilitate heat dissipation.
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Electrical data
VIPER06
4
Electrical data
4.1
Maximum ratings
Table 3.
Symbol
Absolute maximum ratings
Value
Pin
Parameter
Unit
(DIP-7)
Min
Max
VDRAIN
EAV
7, 8
7, 8
7, 8
7, 8
5
Drain-to-source (ground) voltage
Repetitive avalanche energy (limited by TJ = 150 °C)
Repetitive avalanche current (limited by TJ = 150 °C)
Pulse drain current (limited by TJ = 150 °C)
Input pin voltage
800
2
V
mJ
A
IAR
1
IDRAIN
VCOMP
VFB
2.5
3.5
4.8
2.4
Self-
A
-0.3
-0.3
-0.3
V
4
Input pin voltage
V
VLIM
3
Input pin voltage
V
VDD
IDD
2
2
Supply voltage
-0.3
V
limited
Input current
20
mA
W
Power dissipation at TA < 40 °C (DIP-7)
Power dissipation at TA < 50 °C (SSO10)
Operating junction temperature range
Storage temperature
1
PTOT
1
W
TJ
-40
-55
150
150
°C
°C
TSTG
4.2
Thermal data
Table 4.
Symbol
Thermal data
Max value
SSO10
Max value
DIP-7
Parameter
Unit
Thermal resistance junction pin
(dissipated power = 1 W)
RthJP
RthJA
RthJA
35
100
80
40
110
90
°C/W
°C/W
°C/W
Thermal resistance junction ambient
(dissipated power = 1 W)
Thermal resistance junction ambient (1)
(dissipated power = 1 W)
2
1. When mounted on a standard single side FR4 board with 100 mm (0.155 sq in) of Cu (35 μm thick).
6/28
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VIPER06
Electrical data
4.3
Electrical characteristics
(TJ = -25 to 125 °C, VDD = 14 V (a) unless otherwise specified).
Table 5.
Symbol
Power section
Parameter
Test condition
DRAIN = 1 mA,
Min Typ Max Unit
I
VBVDSS
IOFF
Breakdown voltage
800
V
VCOMP = GND, TJ = 25 °C
VDRAIN = max rating,
VCOMP = GND
OFF state drain current
60
μA
I
I
DRAIN = 0.2 A, TJ = 25 °C
DRAIN = 0.2 A, TJ = 125 °C
32
67
Ω
Ω
RDS(on)
COSS
Drain-source on-state resistance
Effective (energy related) output capacitance VDRAIN = 0 to 640 V
10
pF
Table 6.
Symbol
Supply section
Parameter
Test condition
Min Typ Max Unit
Voltage
V
Drain-source startup voltage
Startup charging current
25
45
V
_START
DRAIN
VDRAIN = 100 V to 640 V,
VDD = 4 V
IDDch1
-0.6
-1.8 mA
-14 mA
VDRAIN = 100 V to 640 V,
VDD = 9 V falling edge
IDDch2
Charging current during operation
-7
VDD
Operating voltage range
VDD clamp voltage
11.5
23.5
12
23.5
14
V
V
V
VDDclamp
VDDon
IDD = 15 mA
VDD startup threshold
13
VDD on internal high-voltage current
generator threshold
VDDCSon
9.5 10.5 11.5
7
V
V
VDDoff
Current
IDD0
VDD undervoltage shutdown threshold
8
9
Operating supply current, not switching
FOSC = 0 kHz, VCOMP = GND
VDRAIN = 120 V,
0.6 mA
1.3 mA
F
OSC = 30 kHz
VDRAIN = 120 V,
OSC = 60 kHz
VDRAIN = 120 V,
OSC = 115 kHz
IDD1
Operating supply current, switching
1.45 mA
F
1.6 mA
0.35 mA
mA
F
IDDoff
IDDol
Operating supply current with VDD < VDDoff
Open-loop failure current threshold
VDD < VDDoff
VDD = VDDclamp
VCOMP = 3.3 V,
4
a. Adjust V above V
startup threshold before setting to 14 V.
Doc ID 022794 Rev 1
DD
DDon
7/28
Electrical data
VIPER06
Table 7.
Symbol
Controller section
Parameter
Test condition
Min Typ Max Unit
Error amplifier
VREF_FB
FB reference voltage
3.2 3.3 3.4
V
IFB_PULL UP Current pull-up
-1
2
μA
GM
Transconductance
mA/V
Current setting (LIM) pin
VLIM_LOW Low-level clamp voltage
ILIM = -100 μA
0.5
3
V
Compensation (COMP) pin
VCOMPH
VCOMPL
Upper saturation limit
Burst mode threshold
TJ = 25 °C
TJ = 25 °C
TJ = 25 °C
V
V
1
4
1.1 1.2
VCOMPL_HYS Burst mode hysteresis
HCOMP ΔVCOMP / ΔIDRAIN
40
mV
V/A
kΩ
μA
μA
9
RCOMP(DYN) Dynamic resistance
VFB = GND
15
Source / sink current
ICOMP
VFB > 100 mV
150
220
Max source current
VCOMP = GND, VFB = GND
Current limitation
ILIM = -10 μA, VCOMP = 3.3 V,
TJ = 25 °C
IDlim
Drain current limitation
0.32 0.35 0.38
A
tSS
Soft-start time
8.5
450
85
ms
ns
TON_MIN
IDlim_bm
Minimum turn-on time
Burst mode current limitation
VCOMP = VCOMPL
mA
Overload
tOVL
Overload time
50
1
ms
s
tRESTART
Restart time after fault
Oscillator section
VIPER06Xx
VIPER06Lx
VIPER06Hx
FOSC = 30 kHz
27
54
30
60
33 kHz
66 kHz
FOSC
Switching frequency
103 115 127 kHz
3
4
kHz
kHz
kHz
Hz
FD
Modulation depth
F
OSC = 60 kHz
FOSC = 115 kHz
8
FM
Modulation frequency
Maximum duty cycle
230
DMAX
70
80
%
8/28
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VIPER06
Electrical data
Table 7.
Symbol
Controller section (continued)
Parameter
Test condition
Min Typ Max Unit
Thermal shutdown
TSD
Thermal shutdown temperature
Thermal shutdown hysteresis
150 160
30
°C
°C
THYST
Doc ID 022794 Rev 1
9/28
Typical electrical characteristics
VIPER06
5
Typical electrical characteristics
Figure 4.
IDlim vs. TJ
Figure 5.
FOSC vs. TJ
IDlim/ IDlim@2 5°C
1.04
1.02
1.00
0.98
0.96
0.94
FOSC
/
FOSC@2 5°C
1.04
1.02
1.00
0.98
0.96
0.94
0.92
-50
0
50
100
150
-50
0
50
100
150
TJ [°C]
TJ [°C]
AM01145v1
AM01144v1
Figure 6.
VDRAIN_START vs. TJ
Figure 7.
HCOMP vs. TJ
V DRAIN_ START
/
V DRAIN_ START@2 5°C
1.30
1.020
1.010
1.000
0.990
0.980
0.970
0.960
1.20
1.10
1.00
0.90
0.80
-50
0
50
TJ [°C]
100
150
-50
0
50
100
150
TJ [°C]
AM01147v1
AM01146v1
Figure 8.
GM vs. TJ
Figure 9.
VREF_FB vs. TJ
V REF_ FB
/ V REF_ FB@2 5°C
GM
/
GM @2 5°C
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.08
1.04
1.00
0.96
0.92
0.88
0.84
0.80
-50
0
50
100
150
-50
0
50
100
150
TJ [°C]
TJ [°C]
AM01148v1
AM01149v1
10/28
Doc ID 022794 Rev 1
VIPER06
Typical electrical characteristics
Figure 10. ICOMP vs. TJ
Figure 11. Operating supply current
(no switching) vs. TJ
ICOM P
/ ICOM P@2 5°C
IDD0
/
IDD0 @2 5°C
1.08
1.04
1.00
0.96
0.92
0.88
0.84
0.80
1.08
1.04
1.00
0.96
0.92
0.88
0.84
0.80
-50
0
50
100
150
-50
0
50
100
150
TJ [°C]
TJ [°C]
AM01150v1
AM01151v1
Figure 12. Operating supply current
(switching) vs. TJ
Figure 13. IDlim vs. RLIM
IDlim
/ IDlim@10 0 KOhm
IDD1 / IDD1@2 5°C
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
-50
0
50
100
150
0
20
40
60
80
100
TJ [°C]
Rlim [k Ohm ]
AM01152v1
AM01153v1
Figure 14. Power MOSFET on-resistance
vs. TJ
Figure 15. Power MOSFET breakdown voltage
vs. TJ
Doc ID 022794 Rev 1
11/28
Typical electrical characteristics
Figure 16. Thermal shutdown
VIPER06
VDD
VDDon
VDDCSon
VDDoff
time
time
IDRAIN
TJ
TSD
TSD - THYST
time
Normal operation
Normal operation
Shut down after over temperature
12/28
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VIPER06
Typical circuit
6
Typical circuit
Figure 17. Flyback converter (non-isolated output)
Rin
L1
AC IN
6
Din
-
+
2
4
C2
+
C3
+
Rcl
Ccl
VOUT
Dout
12
10
AC IN
D1
4
+
Cout
Daux
VIPer16
Rfb1
VDD
DRAIN
GND
FB
CONTROL
LIM
COMP
Rfb2 C1
Rcomp1
Ccomp1
Ccomp2
RLIM
(optional)
AM01197v1
Figure 18. Flyback converter (isolated output)
R1
D1
T2
L1
AC IN
R2
C5
D3
VOUT
D2
+
C7
VIPER06
-
C3
VDD
DRAIN
GND
FB
C1
+
C2
+
C6
R3
CONTROL
COMP
LIM
R5
IC3
R4
C8
C4
IC2
R6
AC IN
AM01195v1
Doc ID 022794 Rev 1
13/28
Typical circuit
Figure 19. Flyback converter (isolated output without optocoupler)
VIPER06
FUSE
AC IN
TRANSF
L1
-
+
D0
2
4
6
BRIDGE
C1
C2
AC IN
+
+
Rcl
Ccl
D2
Vout
12
10
D1
+
Raux
Daux
Cout
4
3
.
VIPer06
1
DRAIN
GND
Rfbh
VDD
FB
CONTROL
CVDD
+
COMP
LIM
Rfbl
Cfb
Rc
Cc
Cp
RLIM
(optional)
AM01196v1
Figure 20. Buck converter
Rfb1
Rfb2
AC IN
L1
VIPer06
C2
C3
DRAIN
VDD
C4
GND
FB
CONTROL
LIM
C1
COMP
D2
Cfb
GND
Rcomp
Ccomp
RLIM
(optional)
Lout
Vout
Cout
Dout
AM01194v1
14/28
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VIPER06
Power section
7
Power section
The power section is implemented with an N-channel power MOSFET with a breakdown
voltage of 800 V min. and a typical RDS(on) of 32 Ω. It includes a SenseFET structure to allow
virtually lossless current sensing and the thermal sensor.
The gate driver of the power MOSFET is designed to supply a controlled gate current during
both turn-ON and turn-OFF in order to minimize common-mode EMI. During UVLO
conditions, an internal pull-down circuit holds the gate low in order to ensure that the power
MOSFET cannot be turned ON accidentally.
8
High voltage current generator
The high-voltage current generator is supplied by the DRAIN pin. At the first startup of the
converter it is enabled when the voltage across the input bulk capacitor reaches the
V
DRAIN_START threshold, sourcing a IDDch1 current (see Table 6 on page 7). As the VDD
voltage reaches the VDDon threshold, the power section starts switching and the high-
voltage current generator is turned OFF. The VIPER06 is powered by the energy stored in
the VDD capacitor.
In a steady-state condition, if the self-biasing function is used, the high-voltage current
generator is activated between VDDCSon and VDDon (see Table 6 on page 7), delivering
IDDch2, see Table 6 on page 7 to the VDD capacitor during the MOSFET off-time (see
Figure 21).
The device can also be supplied through the auxiliary winding in which case the high-
voltage current source is disabled during steady-state operation, provided that VDD is
above VDDCSon
.
At converter power-down, the VDD voltage drops and the converter activity stops as it falls
below the VDDoff threshold (see Table 6 on page 7).
Figure 21. Power-on and power-off
VIN < VDRAIN_START
VIN
HV startup is no more activated
VDRAIN_START
With internal self-supply
VDD
VDDon
t
t
regulation is lost here
Without internal self-supply
VDDCSon
VDDoff
VDRAIN
IDD
IDDch2
t
t
IDDch1
Normal operation
Power-off
Power-on
Doc ID 022794 Rev 1
15/28
Oscillator
VIPER06
9
Oscillator
The switching frequency is internally fixed at 30 kHz or 60 kHz or 115 kHz (respectively part
numbers VIPER06Xx, VIPER06Lx and VIPER06Hx).
The switching frequency is modulated by approximately 3 kHz (30 kHz version) or 4 kHz
(60 kHz version) or 8 kHz (115 kHz version) at 230 Hz (typical) rate, so that the resulting
spread spectrum action distributes the energy of each harmonic of the switching frequency
over a number of sideband harmonics having the same energy on the whole, but smaller
amplitudes.
10
11
Soft startup
During the converter’s startup phase, the soft-start function progressively increases the
cycle-by-cycle drain current limit, up to the default value IDlim. In this way the drain current is
further limited and the output voltage is progressively increased, reducing the stress on the
secondary diode. The soft-start time is internally fixed to tSS, see typical value
in Table 7 on page 8, and the function is activated for any attempt of converter startup and
after a fault event.
This function helps prevent saturation of the transformer during startup and short-circuit.
Adjustable current limit set point
The VIPER06 includes a current-mode PWM controller. The drain current is sensed cycle-
by-cycle through the integrated resistor RSENSE and the voltage is applied to the non-
inverting input of the PWM comparator, see Figure 2 on page 4. As soon as the sensed
voltage is equal to the voltage derived from the COMP pin, the power MOSFET is switched
OFF.
In parallel with the PWM operations, the comparator OCP, see Figure 2 on page 4, checks
the level of the drain current and switches OFF the power MOSFET in case the current is
higher than the threshold IDlim, see Table 7 on page 8.
The level of the drain current limit IDlim can be reduced using a resistor RLIM connected
between the LIM and GND pins. Current is sunk from the LIM pin through the resistor RLIM
and the setup of IDlim depends on the level of this current. The relation between IDlim and
R
LIM is shown in Figure 13 on page 11.
When the LIM pin is left open or if RLIM has a high value (i.e. > 80 kΩ), the current limit is
fixed to its default value, IDlim, as given in Table 7 on page 8.
16/28
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VIPER06
FB pin and COMP pin
12
FB pin and COMP pin
The device can be used both in non-isolated and isolated topology. In non-isolated topology,
the feedback signal from the output voltage is applied directly to the FB pin as the inverting
input of the internal error amplifier having the reference voltage, VREF_FB, see Table 7 on
page 8.
The output of the error amplifier sources and sinks the current, ICOMP, respectively to and
from the compensation network connected on the COMP pin. This signal is then compared
in the PWM comparator with the signal coming from the SenseFET in order to switch off the
power MOSFET on a cycle-by-cycle basis. See the Figure 2 on page 4 and the Figure 22.
When the power supply output voltage is equal to the error amplifier reference voltage,
V
REF_FB, a single resistor has to be connected from the output to the FB pin. For higher
output voltages the external resistor divider is needed. If the voltage on the FB pin is
accidentally left floating, an internal pull-up protects the controller.
The output of the error amplifier is externally accessible through the COMP pin and it’s used
for the loop compensation, usually an RC network.
As shown in Figure 22, in case of an isolated power supply, the internal error amplifier has to
be disabled (FB pin shorted to GND). In this case an internal resistor is connected between
an internal reference voltage and the COMP pin, see Figure 22. The current loop has to be
closed on the COMP pin through the opto-transistor in parallel with the compensation
network. The VCOMP dynamic range is between VCOMPL and VCOMPH shown in Figure 23 on
page 18.
When the voltage VCOMP drops below the voltage threshold VCOMPL, the converter enters
burst mode, see Section 13 on page 18.
When the voltage VCOMP rises above the VCOMPH threshold, the peak drain current, as well
as the deliverable output power, will reach its limit.
Figure 22. Feedback circuit
Without Isolation:
VREF
switch open & E/A enabled
RCOMP
VCOMPL
With Isolation:
switch closed & E/A disabled
PWM stop
+
-
VOUT
SW
BUS
FB
-
from RSENSE
E/A
+
RH
VREF_FB
to PWM
+
-
nR
Isolation
No
Isolation
RL
R
COMP
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Burst mode
VIPER06
Figure 23. COMP pin voltage versus IDRAIN
DRAIN
I
IDlim
IDlim_bm
COMP
V
VCOMPL
VCOMPH
AM01095v1
13
Burst mode
When the voltage VCOMP drops below the threshold, VCOMPL, the power MOSFET is kept in
the OFF state and the consumption is reduced to the IDD0 current, as reported on Table 6 on
page 7. In reaction to the loss of energy, the VCOMP voltage increases and as soon as it
exceeds the threshold VCOMPL + VCOMPL_HYS, the converter starts switching again with a
level of consumption equal to the IDD1 current. This ON-OFF operation mode, referred to as
“burst mode” and shown in Figure 24 on page 18, reduces the average frequency, which can
go down even to a few hundreds hertz, thus minimizing all frequency-related losses and
making it easier to comply with energy-saving regulations. During burst mode, the drain
current limit is reduced to the value IDlim_bm (given inTable 7 on page 8) in order to avoid the
audible noise issue.
Figure 24. Load-dependent operating modes: timing waveforms
VCOMP
VCOMPL +VCOMPL_HYS
VCOMPL
time
IDD
IDD1
IDD0
time
IDRAIN
IDlim_bm
time
Burst Mode
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VIPER06
Automatic auto-restart after overload or short-circuit
14
Automatic auto-restart after overload or short-circuit
The overload protection is implemented automatically using the integrated up-down counter.
Every cycle, it is incremented or decremented depending upon the current logic detection of
the limit condition or not. The limit condition is the peak drain current, IDlim , given in Table 7
on page 8 or the one set by the user through the RLIM resistor, shown in Figure 13 on
page 11. After the reset of the counter, if the peak drain current is continuously equal to the
level IDlim, the counter will be incremented until the fixed time, tOVL, at which point the power
MOSFET switch ON will be disabled. It will be activated again through the soft-start after the
tRESTART time (see Figure 25 and Figure 26 on page 19) and the time values mentioned in
Table 7 on page 8.
For overload or short-circuit events, the power MOSFET switching will be stopped after a
period of time dependent upon the counter with a maximum equal to tOVL. The protection
sequence continues until the overload condition is removed, see Figure 25 and Figure 26.
This protection ensures a low repetition rate of restart attempts of the converter, so that it
works safely with extremely low power throughput and avoids overheating the IC in case of
repeated overload events. If the overload is removed before the protection tripping, the
counter will be decremented cycle-by-cycle down to zero and the IC will not be stopped.
Figure 25. Timing diagram: OLP sequence (IC externally biased)
SHORT CIRCUIT
REMOVED HERE
SHORT CIRCUIT
OCCURS HERE
VDD
VDDon
VDDCSon
time
time
IDRAIN
IDlim_bm
tOVL
tOVL
*
tRESTART
t1
tRESTART
tRESTART
tSS
* The time t1 can be lower or equal to the time tOVL
tSS
tSS
Figure 26. Timing diagram: OLP sequence (IC internally biased)
SHORT CIRCUIT
REMOVED HERE
SHORT CIRCUIT
OCCURS HERE
VDD
VDDon
VDDCSon
time
time
IDRAIN
IDlim_bm
tOVL
tOVL
*
tRESTART
t1
tRESTART
tRESTART
tSS
tSS
tSS
*
The time t1 can be lower than or equal to the time tOVL
Doc ID 022794 Rev 1
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Open-loop failure protection
VIPER06
15
Open-loop failure protection
If the power supply has been designed using flyback topology and the VIPER06 is supplied
by an auxiliary winding, as shown in Figure 27 and Figure 28 on page 21, the converter is
protected against feedback loop failure or accidental disconnections of the winding.
The following description is applicable for the schematics of Figure 27 and Figure 28 on
page 21, respectively the non-isolated flyback and the isolated flyback.
If RH is open or RL is shorted, the VIPER06 works at its drain current limitation. The output
voltage, VOUT, will increase as does the auxiliary voltage, VAUX, which is coupled with the
output through the secondary-to-auxiliary turns ratio.
As the auxiliary voltage increases up to the internal VDD active clamp, VDDclamp (the value is
given in Table 7 on page 8) and the clamp current injected on the VDD pin exceeds the latch
threshold, IDDol (the value is given in Table 7 on page 8), a fault signal is internally
generated.
In order to distinguish an actual malfunction from a bad auxiliary winding design, both the
above conditions (drain current equal to the drain current limitation and current higher than
IDDol through the VDD clamp) have to be verified to reveal the fault.
If RL is open or RH is shorted, the output voltage, VOUT, will be clamped to the reference
voltage VREF_FB (for non-isolated flyback) or to the external TL voltage reference (for
isolated flyback).
Figure 27. FB pin connection for non-isolated flyback
DAUX
RAUX
VAUX
CVDD
VDD
VOUT
VCOMPL
PWM stop
+
-
RH
RL
BUS
FB
-
from RSENSE
E/A
+
VREF_FB
+
-
to PWM
nR
R
COMP
RS
CS
CP
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VIPER06
Open-loop failure protection
Figure 28. FB pin connection for isolated flyback
RAUX
DAUX
VAUX
CVDD
VREF
RCOMP
SW
VCOMPL
+
-
PWM stop
BUS
Disabled
FB
VOUT
from RSENSE
-
E/A
+
VREF_FB
+
-
nR
to PWM
R
ROPTO
RH
COMP
R3
U5
RC
CC
CCOMP
TL
RL
-
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Package mechanical data
VIPER06
16
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 8.
DIP-7 mechanical data
mm
Min
Dim.
Typ
Max
A
A1
A2
b
5.33
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
10.16
8.26
7.11
b2
c
D
E
E1
e
eA
eB
L
10.92
3.81
3.30
2.508
0.50
2.92
0.40
M(1)(2)
N
0.60
0.60
N1
O(2)(3)
0.548
1. Creepage distance > 800 V.
2. Creepage distance as given in the 664-1 CEI / IEC standard.
3. Creepage distance 250 V.
Note:
1
2
3
4
The lead size includes the thickness of the lead finishing material.
Dimensions do not include mold protrusion, not to exceed 0.25 mm in total (both sides).
Package outline exclusive of metal burr dimensions.
Datum plane “H” coincident with the bottom of lead, where lead exits body (refer to
Figure 29 on page 23).
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VIPER06
Package mechanical data
Figure 29. DIP-7 package dimensions
Doc ID 022794 Rev 1
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Package mechanical data
Table 9. SSO10 mechanical data
VIPER06
Databook (mm.)
Min.
Dim.
Typ
Max
A
A1
A2
b
1.75
0.25
0.10
1.25
0.31
0.17
4.80
5.80
3.80
0.51
0.25
5
c
D
E
4.90
6
6.20
4
E1
e
3.90
1
h
0.25
0.40
0°
0.50
0.90
8°
L
K
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Doc ID 022794 Rev 1
VIPER06
Package mechanical data
Figure 30. SSO10 package dimensions
8140761 rev. A
Doc ID 022794 Rev 1
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Order codes
VIPER06
17
Order codes
Table 10. Ordering information
Order code
Package
Packaging
VIPER06XN
VIPER06LN
DIP-7
Tube
VIPER06HN
VIPER06XS
VIPER06XSTR
VIPER06LS
Tube
Tape and reel
Tube
SSO10
VIPER06LSTR
VIPER06HS
VIPER06HSTR
Tape and reel
Tube
Tape and reel
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Doc ID 022794 Rev 1
VIPER06
Revision history
18
Revision history
s
Table 11. Document revision history
Date
Revision
Changes
08-Mar-2012
1
Initial release.
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VIPER06
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