VIPER319HDTR_技术文档

VIPER31

Datasheet

Energy saving offline high voltage converter

Features

•

800 V avalanche-rugged power MOSFET to cover ultra-wide VAC input range

Embedded HV startup and sense FET

Current mode PWM controller

Drain current limit protection (OCP):

–

710 mA (VIPER317)

850 mA (VIPER318)

990 mA (VIPER319)

~

AC

D_IN

R_IN

VCC

DRAIN

GND

OVP

FB

VIPER31

CONTROL

COMP

•

Wide supply voltage range: 4.5 V to 30 V

UVP

C_IN

D_AUX

–

< 20 mW @ 230 V_ACin no-load;

R1

< 430 mW @ 230 V_AC, 25 0mW output load

C1

C2

D1

D2

R2

C3

L_OUT

V_OUT

GND

Jittered switching frequency reduces the EMI filter cost:

C_OUT

–

30 kHz ± 7% (type X)

60 kHz ± 7% (type L)

132 kHz ±7% (type H)

GND

•

Embedded E/A with 1.2 V reference

Built-in soft-start for improved system reliability

Protections with automatic restart:

–

overload/short-circuit (OLP)

thermal shutdown

overvoltage

Product status link

•

Protections without automatic restart:

VIPER31

–

pulse-skip protection to avoid flux runaway

undervoltage/disable

Product label

max. duty cycle

Application

•

Low power SMPS for home appliances, home automation, industrial,

consumers, lighting

•

Low power adapters

Description

The VIPER31 device is a high-voltage converter that smartly integrates an 800

V avalanche rugged power MOSFET with PWM current-mode control. The 800 V

breakdown allows extended input voltage range to be applied, as well as to reduce

the size of the DRAIN snubber circuit. The IC can meet the most stringent energy-

saving standards as it has very low consumption and operates in pulse frequency

modulation at light load. Overvoltage and undervoltage protections with separate and

settable intervention thresholds are available at OVP and UVP pins respectively. UVP

can also be used as a disabling input for the entire SMPS, with ultra-low residual

input power consumption. Integrated HV startup, sense FET, error amplifier and

oscillator with frequency jitter allow a complete application to be designed with a

minimum component count. Flyback, buck and buck boost topologies are supported.

DS13285 - Rev 3 - November 2020

For further information contact your local STMicroelectronics sales office.

www.st.com

VIPER31

Pin setting

1

Pin setting

Figure 1. Connection diagram

DRAIN

GND

N.C.

DRAIN

VCC

N. A.

N. C.

UVP

OVP

FB

COMP

Table 1. Pin description

Function

number

Name

Ground and MOSFET source. Connection of both the source of the internal MOSFET and the return of

the bias current of the device. All of the groundings of bias components must be tied to a trace going to

this pin and kept separate from the pulsed current return.

1

2

GND

N. C.

Not connected. When designing the PCB, this pin can be soldered to GND.

Controller Supply. An external storage capacitor has to be connected across this pin and GND. The

pin, internally connected to the high-voltage current source, provides the VCC capacitor charging current

at startup. A small bypass capacitor (0.1 μF typ.) in parallel, placed as close as possible to the IC, is also

recommended, for noise filtering purposes.

3

4

VCC

N.A.

Not available for user. This pin is mechanically connected to the controller die pad of the frame. In order

to improve noise immunity, it is highly recommended to connect it to GND.

Undervoltage Protection. If V

falls below the internal threshold V

(0.4 V typ.) for more than

UVP_th

UVP

t

time (30 ms, typ.), the IC is disabled, and its consumption reduced to ultra-low values. When

UVP_DEB

V

rises above V

the device waits for a t

time interval (30 ms, typ.) then resumes

UVP_REST

UVP

UVP_th,

5

UVP

switching. The pin can be used to realize an input undervoltage protection or as a disabling input for the

entire SMPS, with ultra-low residual input power consumption. If the feature is not required, the pin must

be left open, which excludes the function.

Overvoltage protection. If VOVP exceeds the internal threshold V

(4 V typ.) for more than

OVP_th

t

time (250 μsec, typ.), the PWM is disabled in auto-restart for t

(500 msec, typ.) until

OVP_REST

OVP_DEB

the OVP condition is removed, after that it restarts switching with soft-start phase. OVP pin can be

used to realize an input overvoltage protection (or, in non-isolated topologies, an output overvoltage

protection).

6

7

OVP

FB

If the feature is not required, the pin must be connected to GND, which excludes the function.

Direct feedback. It is the inverting input of the internal transconductance E/A, internally referenced to

1.2 V with respect to GND. In non-isolated converter, the output voltage information is directly fed into the

pin through a voltage divider. In primary regulation, the FB voltage divider is connected to the VCC. The

E/A is disabled if FB is connected to GND pin.

DS13285 - Rev 3

page 2/40

VIPER31

Pin setting

number

Name

Function

Compensation. This is the output of the internal E/A. A compensation network is placed between

this pin and GND to achieve stability and good dynamic performance of the control loop. In case of

secondary feedback, the internal E/A must be disabled and the COMP directly driven by the optocoupler

to control the DRAIN peak current setpoint.

8

COMP

N.C.

9 to 12

Not connected. These pins must be left floating in order to get a safe clearance distance.

MOSFET drain. The internal high-voltage current source sources current from these pins to charge

the VCC capacitor at startup. The pins are mechanically connected to the internal metal PAD of the

MOSFET in order to facilitate heat dissipation. On the PCB, some copper areas under these pins

decreases the total junction-to-ambient thermal resistance thus facilitating the power dissipation.

13 to 16 DRAIN

DS13285 - Rev 3

page 3/40

VIPER31

Electrical and thermal ratings

2

Electrical and thermal ratings

Table 2. Absolute maximum ratings

Parameter ⁽¹⁾⁽²⁾

Drain-to- source (ground) voltage

Symbol

Min.

Max.

800

Unit

V

I

V

A

V

DS

Pulsed drain current (pulse-width limited by SOA)

VCC voltage

3

DRAIN

V

-0.3

30.5V

CC

Internally

limited⁽³⁾

V

OVP voltage

-0.3

V

OVP

Internally

limited ⁽³⁾

V

UVP voltage

FB voltage

-0.3

V

UVP

FB

5 ⁽⁴⁾

Internally

limited ⁽³⁾

COMP voltage

COMP

1⁽⁵⁾

P

T

Power Dissipation @ Tamb < 50°C

Junction Temperature operating range

Storage Temperature

W

TOT

-40

-55

150

°C

J

T

STG

1. stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.

2. exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability

3. by internal clamp between 4.75 V and 5.25 V or Vcc + 0.6 V, whichever is lower

4. the AMR value is intended when VCC ≥ 5 V, otherwise the value VCC + 0.3 V has to be considered.

5. when mounted on a standard single side FR4 board with 100 mm² (0.155² inch) of Cu (35 μm thick)

Table 3. Thermal data

Max. value

Symbol

Parameter

Unit

SO16N

Thermal resistance junction to case⁽¹⁾

R

10

120

5

°C/W

TH-JC

(dissipated power = 1W)

Thermal resistance junction to ambient⁽¹⁾

(dissipated power = 1W)

TH-JA

TH-JC

TH-JA

Thermal resistance junction to case⁽²⁾

(dissipated power = 1W)

Thermal resistance junction to ambient⁽²⁾

(dissipated power = 1W)

85

1. when mounted on a standard single side FR4 board with minimum copper area

2. when mounted on a standard single side FR4 board with 100mm² (0.155² inch) of Cu (35 μm thick)

DS13285 - Rev 3

page 4/40

VIPER31

Electrical characteristics

Figure 2. R_{th_JA}versus copper area

R

_thJA/(R_thJA@ A = 100mm²)

1.500

1.375

1.250

1.125

1.000

0.875

0.750

0

25

50

75

100

125

150

175

200

225

A (mm²)

Table 4. Avalanche characteristics

Symbol

Parameter

Avalanche current

Condition

Min.

Typ.

Max.

1.15

Unit

Repetitive and non-repetitive.

I

A

AR

Pulse-width limited by T

Jmax

I

= I

AR

,

AS

Single pulse avalanche energy⁽¹⁾

V

= 100 V,

EAS

3

mJ

DS

Starting T = 25°C

J

1. Parameter derived by characterization

2.1

Electrical characteristics

Tj = -40 to 125°C, V_CC= 9 V (unless otherwise specified)

Table 5. Power section

Test condition

Parameter

Symbol

Min.

Typ.

Max.

Unit

I

= 1 mA, V

= V

,

GND

DRAIN

COMP

V

I

Breakdown voltage

800

V

BVDSS

T = 25°C

J

V

= 400 V, V

= V

,

GND

DS

COMP

Drain-source leakage current

OFF state drain current

1

µA

DSS

OFF

T = 25°C

J

V

= max. rating,

DRAIN

COMP

I

60

= V

, T = 25°C

GND J

I

= 400 mA, T = 25°C

J

3.5

7

Ω

DRAIN

Static drain-source

ON‑resistance

R

DS(on)

I

= 400 mA, T = 125°C

J

DS13285 - Rev 3

page 5/40

VIPER31

Electrical characteristics

Table 6. Supply section

Test condition

Symbol

Parameter

Min.

Typ.

Max.

Unit

High-voltage startup current source

Breakdown voltage of startup

MOSFET

V

T = 25°C

800

V

BVDSS_SU

J

V

Drain-source startup voltage

Startup resistor

24

54

HV_START

V

> V

,

FB_REF

FB

R

I

= 400 V,

= 600 V

36

45

MΩ

mA

G

DRAIN

V

charging current at startup

charging current

V

= 100V, V ≤ 1V

0.5

7.6

1

1.5

10

CH1

CC

DRAIN

CC

> V

, V

DRAIN

= 100V

FB

FB_REF

I

8.8

CH2

1V < V <V

CC

CCon

IC supply and consumptions

V

Operating voltage range

VCC startup threshold

4.5

7.5

30

V

CC

V

8

4.25

4

8.5

Ccon

HV current source turn-on

threshold

V

falling

CC

4

4.5

V

Cson

Ccoff

UVLO

3.75

4.25

0.35

0.48

Not switching,

X, L versions

H version

= 1.2 V,

I

Quiescent current

mA

q

V

FB

> V

FB_REF

V

DS

= 150 V, V

= 30 kHz

COMP

1.25

1.5

1.7

2

F

OSC

V

= 150 V, V

= 60 kHz

= 1.2 V,

Operating supply current,

switching

DS

I

mA

CC

F

OSC

V

= 150 V, V

= 132 kHz

DS

2.25

2.8

F

OSC

Note:

1.

2.

Current supplied only during the main MOSFET OFF time.

Parameter assured by design and characterization.

DS13285 - Rev 3

page 6/40

VIPER31

Electrical characteristics

Table 7. Controller section

Test condition

Symbol

E/A

Parameter

Min.

Typ.

Max.

Unit

V

I

Reference voltage

1.175

150

1.2

180

1

1.225

210

V

FB_REF

E/A disable voltage

Pull-up current

mV

µA

FB_DIS

0.9

1.1

FB_PULL UP

V

=1.5 V,

COMP

G

Trans conductance

Max. source current

Max. sink current

400

75

550

100

700

125

µA/V

µA

M

FB >VFBREF

V

=1.5 V,

COMP

I

COMP1

COMP2

=0.5 V

FB

V

=2 V,

FB

75

µA

=1.5 V

=2.7 V,

COMP

V

COMP

R

V

Dynamic resistance

13

15

17

kΩ

COMP(DYN)

=G

FB

ND

Current limitation threshold

PFM threshold

2.75

3.1

3.45

V

COMPH

COMPL

V

0.6

3.8

3.2

2.9

0.8

4.2

3.5

3.2

1

VIPER317*

VIPER318*

VIPER319*

4,6

3.8

3.5

H

ΔV

/ΔI

COMP

COMP DRAIN

V/A

OLP and timing

T = 25°C , VIPER317*

675

810

940

639

765

891

710

850

745

890

J

T = 25°C , VIPER318*

J

T = 25°C , VIPER319*

J

990

710

1040

781

I

Drain current limitation

mA

DLIM

VIPER317*⁽¹⁾

VIPER318*⁽¹⁾

VIPER319*⁽¹⁾

VIPER317L

VIPER317H

VIPER318X

VIPER318L

VIPER318H

VIPER319X

VIPER319L

VIPER319H

850

935

990

1089

30.2

66.5

21.7

43.4

95.4

29.4

58.8

129.4

Power coefficient

2

-10%

+10%

I f

A ·kHz

2

I

x F

OSC_TYP

DLIM_TYP

(2)

T =25°C, V

=V

J

COMP

COMPL

80

110

130

150

140

160

180

VIPER317* ⁽¹⁾

T =25°C, V

J

COMP

I

Drain current limitation at light load

100

120

mA

Dlim_PFM

VIPER318*⁽¹⁾

T =25°C, V

J

COMP

VIPER319*⁽¹⁾

DS13285 - Rev 3

page 7/40

VIPER31

Electrical characteristics

Symbol

Parameter

Overload delay time

Test condition

Min.

Typ.

Max.

55

Unit

ms

t

45

50

OVL

Max. overload delay time

Soft-start time

When in pulse skipping

100

11

ms

OVL_max

SS

5

8

300

1

ms

V

=9 V,

CC

t

=1 V,

Minimum turn-on time

Restart time after fault

250

350

ns

s

ON_MIN

COMP

=V

FB

FB_REF

0.625

1.375

RESTART

UVP

V

=9 V,

CC

V

=1 V,

UVP threshold

0.38

0.4

0.42

V

UVP_th

COMP

FB=VFB_REF

I

t

UVP pull-up current

-1

µA

ms

UVP_pull- up

Debounce time before UVP tripping

18.75

30

41.25

0.35

UVP_DEB

Debounce time for restoring normal

operation from UVP

t

I

30

ms

UVP_REST

Not switching, V >V

Quiescient current during UVP

0.25

mA

q_DIS

FB

FB_REF

OVP

V

=9 V,

CC

V

=1 V,

Overvoltage protection threshold

Debounce time before OVP tripping

3.85

4

4.15

V

OVP_th

COMP

=V

FB

FB_REF

t

156

312

250

500

344

688

µs

OVP_DEB

Restart time after overvoltage

protection tripping

ms

OVP_REST

Oscillator

T =25ºC VIPER31*X

27

54

30

60

33

66

J

F

T = 25ºC, VIPER31*L

J

Switching frequency

kHz

OSC

T = 25ºC, VIPER31*H

119

13.5

132

15

145

16.5

J

T = 25ºC ⁽³⁾

F

Min. switching frequency

Modulation depth

kHz

%

OSC MIN

J

(4)

F

±7·F

OSC

D

F

Modulation frequency

Max. duty cycle

200

Hz

%

M

D

70

80

MAX

Thermal shutdown protection

Thermal shutdown temperature

threshold

(4)

T

150

160

°C

SD

1. Measured at Vin = 100 Vdc in Flyback topology, with 1.5 mH transformer primary inductance

2. See Section 4.10 Pulse frequency modulation

3. See Section 4.7 Pulse skipping

4. Parameter assured by design and characterization.

DS13285 - Rev 3

page 8/40

VIPER31

Typical electrical characteristics

3

Typical electrical characteristics

Figure 3. I_DLIMvs. T_J

Figure 4. F_OSCvs. T_J

I_DLIM/(I_DLIM@25°C)

F_OSC/(F_OSC@25°C)

1.2

1.1

1

1.1

1.05

1

0.9

0.8

0.95

0.9

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

T_j[°C]

Figure 5. V_{HV_START}vs. T_J

Figure 6. VF_{B_REF}vs. T_J

V_{HV_START}/(V_{HV_START}@25°C)

V_{FB_REF}/(V_{FB_REF}@25°C)

1.2

1.1

1

1.05

1.025

1

0.9

0.8

0.975

0.95

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

T_j[°C]

Figure 7. Quiescent Current I_qvs. T_J

Figure 8. Operating current I_CCvs. T_J

I_q/(I_q@25°C)

I_CC/(I_CC@25°C)

1.1

1.2

1.05

1.1

1

0.95

0.9

0.8

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

T_j[°C]

DS13285 - Rev 3

page 9/40

VIPER31

Typical electrical characteristics

Figure 9. I_CH1vs. T_J

Figure 10. I_CH2vs. T_J

I_CH2/(I_CH2@25°C)

I_CH1/(I_CH1@25°C)

1.5

1.3

1.1

0.9

0.7

0.5

1.2

1.1

1

0.9

0.8

-50

-25

0

25

50

75

100

125

700

125

150

800

150

-50

-25

0

25

50

75

100

125

700

125

150

800

150

T_j[°C]

Figure 11. I_CH1vs. V_DRAIN

Figure 12. I_CH2vs. V_DRAIN

I_CH1/(I_CH1@V_DRAIN= 100V)

I_CH2/(I_CH2@V_DRAIN=100V)

1.1

1.05

1

1.1

1.05

1

0.95

0.9

0.95

0.9

0

100

200

300

400

500

600

0

100

200

300

400

V_DRAIN[V]

500

600

V_DRAIN[V]

Figure 13. G_Mvs. T_J

Figure 14. I_COMPvs. T_J

I_COMP/(I_COMP@25°C)

G_M/(G_M@25°C)

1.2

1.1

1

1.1

1.05

1

0.9

0.8

0.95

0.9

-50

-25

0

25

50

T_j[°C]

75

100

-50

-25

0

25

50

T_j[°C]

75

100

DS13285 - Rev 3

page 10/40

VIPER31

Typical electrical characteristics

Figure 16. R_DSONvs. I_DRAIN

Figure 15. R_DSONvs. T_J

R_DS(on)/(R_DS(on)@I_DRAIN= 360mA)

1.5

R_DS(on)/(R_DS(on)@25°C)

2.50

2.00

1.50

1.00

0.50

0.00

1

0.5

T = 25°C

-50

-25

0

25

50

75

100

125

150

T_j[°C]

0

50

100

150

200

I_DRAIN[mA]

250

300

350

400

Figure 18. Power MOSFET C_OSSvs. V_DS@ V_GS=0, f=1MHz

C_OSS[pF]

Figure 17. Static drain-source on resistance

10000

1000

100

10

1

0

1

10

100

1000

V_DS[V]

Figure 19. V_BVDSSvs. T_J

Figure 20. Output characteristic

V_(BR)DSS/ (V_(BR)DSS@ 25⁰C)

1.12

I_DRAIN[A]

4.8

4.4

4.0

3.6

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0.0

-40°C

1.08

1.04

1

25°C

I_D= 1 mA

125°C

0.96

0.92

0.88

-50

0

50

T_J[°C]

100

150

0.0

4.0

8.0

12.0

16.0

20.0

V_DS[V]

DS13285 - Rev 3

page 11/40

VIPER31

Typical electrical characteristics

Figure 22. Maximum avalanche energy vs. Tj

Figure 21. SOA SO16N package

E_AS[mJ]

I_D[A]

4

3

2

1

0

10

Single pulse,

I_D= 1A, V_DD= 50 V

1

t_p= 1 ms

R_DS(on)limit

t_p= 10 ms

0.1

t_p= 100 ms

t_p= 1 ms

0.01

0.1

1

10

100

1000

V100[0V0]

DS

-50

0

50

100

150

T_j[°C]

DS13285 - Rev 3

page 12/40

VIPER31

General description

4

General description

4.1

Block diagram

Figure 23. Block diagram

VCC

DRAIN

IC_DIS

HV

Start up

I_HV

I_CH*

REGULATOR

Q

IC DISABLE

LOGIC

4V

S

R

HV DISABLE

LOGIC

R_G

V_z

Internal Supply bus

LIGHT LOAD PFM

COMP

JITTERED

OSCILLATOR

THERMAL

DIODE

(OTP)

SOFT START

TURN ON

LOGIC

I_DLIMref

LEB

+

S

OCP

E/A

-

Q

-

FB

+

R

+

-

PWM

-

OCP

t_OVLfilter

PROTECTION

LOGIC

t_RESTART

V_{FB_REF}

IC_DIS_SET

IC_DIS_RESET

+

UVLO VCC

VCC_clamp

t_{UVP_DEB}filter

OVP LOGIC

t_{OVP_REST}

t_{OVP_DEB}filter

T_SDLOGIC

t_RESTART

t_{UVP_REST}filter

OTP

IC_DIS

+

-

+

-

V_{UVP_th}

V_{OVP_th}

RSENSE

UVP

OVP

GND

4.2

Typical power capability

Table 8. Typical power

Vin: 230 V

Vin: 85-265 V

AC

Adapter ⁽¹⁾

27 W

Open Frame ⁽²⁾

31 W

Adapter ⁽¹⁾

16 W

Open Frame ⁽²⁾

19 W

1. Typical continuous power in non-ventilated enclosed adapter measured at 50°C ambient.

2. Maximum practical continuous power in an open frame design at 50°C ambient, with adequate heat sinking.

DS13285 - Rev 3

page 13/40

VIPER31

Primary MOSFET

Figure 24. Typical deliverable output power vs. T_AMB(Vin: 85-265V_AC

)

4.3

4.4

Primary MOSFET

The primary switch is implemented with an avalanche rugged N-channel MOSFET with 800 V minimum

breakdown voltage, V_BVDSS, and 3.5 Ω maximum on-resistance, R_DS(on)

.

The sense-FET is embedded and allows a virtually lossless current sensing.

The MOSFET gate driver controls the gate current during both turn-on and turn-off in order to minimize common

mode EMI. Under UVLO conditions the embedded pull-down circuit holds the gate low in order to ensure that the

MOSFET cannot be turned on accidentally.

High-voltage startup

The embedded high-voltage startup includes both the 800 V startup FET, whose gate is biased through the

resistor R_G, and the switchable HV current source, delivering the current I_HV. The major portion of I_HV, (I_CH),

charges the capacitor connected to VCC pin. A minor portion is sunk by the controller block.

Power on: at startup, as the voltage across the DRAIN pin exceeds the V_{HV_START}threshold, the HV current

source is turned on, charging linearly the VCC capacitor with the current I_CH2(8.8 mA typ.). This charging current

is reduced to I_CH1(1 mA typ.) in case V_CCis lower than 1 V (typical value), in order to limit IC power dissipation in

case the pin is accidentally shorted to GND.

As V_CCreaches the startup threshold, V_CCon, the chip starts operating, the primary MOSFET is enabled to switch,

the HV current source is disabled and the device is powered by the energy stored in the VCC capacitor. The IC

can be supplied through a transformer auxiliary winding or, in case of not isolated topologies with V_OUT≥ 5 V,

directly from the converter’s output.

The supply operating range is from 4.5 V to 30.5 V. If VCC pin voltage exceeds 30.5 V (referred to V_GND), the

internal clamp could be reached, which causes the VIPER31 to stop switching.

This condition is potentially dangerous for the VIPER31 and must be avoided, by means of proper transformer

design and/or external protection (zener diode between VCC and GND pins).

In normal operation the HV current source is always kept off by maintaining V_CCabove V_Cson, so its residual

consumption is given by the power dissipated on R_Gonly, calculated as follows:

Equation 1

(1)

P_HV(V_IN) = V_IN²/R_G

DS13285 - Rev 3

page 14/40

VIPER31

Soft startup

At nominal input voltage (230 V_AC), typical and worst-case consumptions are 2.4 mW and 3.0 mW respectively

(corresponding to R_G_typ = 45 Mohm and R_G_min = 36 Mohm). This means that, with a careful design, the

overall no-load input power consumption of the application can be maintained very low (typically, below 10 mW

@230 V_AC

)

Power-off: when the IC is disconnected from the mains, or there is a mains interruption, for some time the

converter keeps on working, powered by the energy stored in the input bulk capacitor. When it is discharged

below a critical value, the converter is no longer able to keep the output voltage regulated. During the power

down, when the DRAIN voltage becomes too low, the HV current source remains off and the IC is stopped as

soon as V_CCdrops below the UVLO threshold, V_Ccoff

.

Figure 25. Power ON and power OFF

V_{IN_DC}

Power-off:

V_INdecreases

V_{HV_START}

Power-on:

HV current source enabled

t

V_DRAIN

t

HV current source is

disabled here

V_CC

HV current source is no

more activated because

of too low V_DRAIN

V_CCon

V_CSon

V_CCoff

UVLO

I_CH2

1V

I_CH1

t

V_OUT

Output regulation is lost here

Power-off

t

Power-on

Steady-state

4.5

Soft startup

The internal soft-start function of the VIPer31 progressively increases the cycle-by-cycle current limitation set

point from zero up to I_DLIM

.

The soft-start time, t_SS, which is internally set at 8 ms, is activated at any attempt of converter power-on and at

any restart after a fault event.

The feature is used to reduce the stress of the power components and increase the reliability of the system.

DS13285 - Rev 3

page 15/40

VIPER31

Oscillator

Figure 26. Soft startup

I_DRAIN

Soft start phase

t_SS

Steady state

I_DLIM

time

V_COMP

V_COMPH

time

V_OUT

time

4.6

4.7

Oscillator

The IC embeds a fixed frequency oscillator with jittering feature. The switching frequency is modulated by

approximately ±7%·F_OSCat 200 Hz rate. The purpose of the jittering is to get a spread-spectrum action that

distributes the energy of each harmonic of the switching frequency over a number of frequency bands, having

the same energy on the whole but smaller amplitudes. This helps to reduce the conducted emissions, especially

when measured with the average detection method or, which is the same, to pass the EMI tests with an input

filter of smaller size with respect to the one that should be needed in absence of jittering feature. Three switching

frequency options, F_OSC, are available: 30 kHz (X type), 60 kHz (L type) and 132 kHz (H type).

Pulse skipping

The IC embeds a pulse skip circuit that operates in the following way:

•

Each time the DRAIN peak current exceeds I_DLIMlevel within t_{ON_MIN}, the next switching cycle is skipped.

The cycles can be skipped until the minimum switching frequency F_{OSC_MIN}(15 kHz) is reached.

•

Each time the DRAIN peak current does not exceed I_DLIMwithin t_{ON_MIN}, the next switching cycle is

restored. The cycles can be restored until the nominal switching frequency FOSC is reached.

The protection is intended in order to avoid the so called “flux runaway” condition often present at converter

startup and due to the fact that the primary MOSFET, which is turned on by the internal oscillator, cannot be

turned off before the minimum on-time.

During the on-time, the inductor is charged through the input voltage and, if it cannot be discharged by the

same amount during the off-time, in every switching cycle there is a net increase of the average inductor current,

that can reach dangerously high values until the output capacitor is not charged enough to ensure the inductor

discharge rate needed for the volt-second balance. This condition is common at converter startup, because of the

low output voltage.

In the following Figure 27. Pulse skipping during startup the effect of pulse skipping feature on the DRAIN peak

current shape is shown (solid line), compared with the DRAIN peak current shape when pulse skipping feature

is not implemented (dashed line). Providing more time for cycle-by-cycle inductor discharge when needed, this

feature is effective in keeping low the maximum DRAIN peak current avoiding the flux runaway condition.

DS13285 - Rev 3

page 16/40

VIPER31

Direct feedback

Figure 27. Pulse skipping during startup

V_OUT

V_{OUT_nom}

time

I_DRAIN

without pulse skipping

with pulse skipping

I_DLIM

time

skipped cycles

4.8

Direct feedback

The IC embeds a transconductance type error amplifier (E/A) whose inverting input and output are FB and

COMP, respectively. The internal reference voltage of the E/A is V_{FB_REF}(1.2 V typical value referred to GND).

In non-isolated topologies, a positive output voltage can be tightly set through a simple voltage divider applied

among the output voltage terminal, FB and GND.

The E/A output is scaled down and fed into the PWM comparator, where it is compared to the voltage across the

sense resistor in series to the sense-FET, thus setting the cycle-by-cycle drain current limitation.

An R-C network connected on the output of the error amplifier (COMP) is usually used to stabilize the overall

control loop.

The FB is provided with an internal pull-up to prevent a wrong IC behavior when the pin is accidentally left

floating.

The E/A is disabled if the FB voltage is lower than V_{FB_DIS}(200 mV, typ).

4.9

Secondary feedback

When a secondary feedback is required, the internal E/A has to be disabled shorting FB to GND (V_FB< V_{FB_}D_IS).

With this setting, COMP is internally connected to the parallel of a 100 uA current generator and the 15 kΩ (typ.)

R_COMP(DYN)resistor, and the voltage across COMP is set by the current sunk.

This allows to set the output voltage value through an external error amplifier (TS431 or similar) placed on the

secondary side, whose error signal is used to set the DRAIN peak current setpoint corresponding to the output

power demand. If isolation is required, the error signal must be transferred through an optocoupler, with the

phototransistor collector connected across COMP and GND.

4.10

Pulse frequency modulation

If the output load is decreased, the feedback loop reacts by lowering V_COMP,which reduces the DRAIN peak

current setpoint. The minimum value is I_{DLIM_PFM}, corresponding to the V_COMPLthreshold.

If the load is further decreased, the DRAIN peak current value is maintained at I_{DLIM_PFM}and some PWM cycles

are skipped. This kind of operation is referred to as “pulse frequency modulation” (PFM), the number of the

skipped cycles depending on the balance between the output power demand and the power transferred from the

input. The result is an equivalent switching frequency which can go down to some hundreds Hz, thus reducing all

the frequency-related losses.

DS13285 - Rev 3

page 17/40

VIPER31

Overload protection

This kind of operation, together with the extremely low IC quiescent current, allows very low input power

consumption in no-load and light load, while the low DRAIN peak current value, I_{DLIM_PFM}, prevents any

audible noise which could arise from low switching frequency values. When the output load is increased, V_COMP

increases and PFM is exited. V_COMPreaches its maximum at V_COMPH, corresponding to the DRAIN current

limitation (IDLIM).

4.11

Overload protection

In order to manage the overload condition the IC embeds the following main blocks: the OCP comparator to turn

off the power MOSFET when the drain current reaches its limit (I_DLIM), the up and down OCP counter to define

the turn-off delay time in case of continuous overload (t_OVL= 50 ms typ.) and the timer to define the restart time

after protection tripping (t_RESTART= 1 sec, typ.).

In case of short-circuit or overload, the control level on the inverting input of the PWM comparator is greater than

the reference level fed into the inverting input of the OCP comparator. As a result, the cycle-by-cycle turn off of the

power switch is triggered by the OCP comparator instead of by the PWM comparator. Every cycle this condition is

met, the OCP counter is incremented. If the fault condition persists for a time greater than t_OVL(corresponding to

the counter end-of-count), the protection is tripped, the PWM is disabled for t_RESTART, then it resumes switching

with soft-start and, if the fault is still present, it is disabled again after t_OVL. The OLP management prevents the IC

from being indefinitely operated at I_DLIMand the low repetition rate of the restart attempts of the converter avoids

overheating the IC in case of repeated fault events.

After the fault removal, the IC resumes working normally. If the fault is removed before the protection tripping

(before t_OVL), the t_OVLcounter is decremented on a cycle-by-cycle basis down to zero and the protection is not

tripped. If the fault is removed during t_RESTART, the IC waits for the t_RESTARTperiod ot have elapsed before

resuming switching.

In fault condition, V_CCis kept between V_CSonand V_CConby the periodical activation of the HV current source,

which recharges the VCC capacitor to V_Cconany time the IC internal consumption discharges it to V_Cson

.

Figure 28. Overload protection

Overload removed

Overload applied

V_CC

V_CCon

V_CSon

I_DRAIN

time

I_DLIM

t_OVL

time

t_RESTART

t_SS

4.12

Undervoltage protection

If the voltage across the UVP pin (V_UVP) falls below the internal threshold V_{UVP_th}(0.4 V typ.) for a time greater

than t_{UVP_DEB}(30 ms, typ.), the IC is disabled and its consumption is reduced to ultra-low values (I_{q_DIS}).

When V_UVPrises above V_{UVP_th}, the IC must wait t_{UVP_REST}(30 ms, typ.) before resuming switching.

Both t_{UVP_DEB}and t_{UVP_REST}are intended to filter out possible noises/disturbances of the line, which could affect

the correct operation of the function. They are obtained through two separate up/down counters:

DEB (REST) up/down counter has a deb_eoc (rest_eoc) end-of-count. The operation is illustrated in

Figure 29. UVP timing.

If the counter starts from zero and counts always up, end-of-count is reached in a time interval t_{UVP_DEB}

(t_{UVP_REST}).

DS13285 - Rev 3

page 18/40

VIPER31

Undervoltage protection

If V_UVPfalls below V_{UVP_th}, the DEB counter is incremented. If V_UVPincreases above V_UVP_th before uvp_eoc

is reached, the counter is decremented. If the count goes back down to zero, a disturbance on the UVP pin is

assumed and there is no consequence on the IC behavior.

If V_UVPstays below V_{UVP_th}until the counter reaches deb_eoc: the device is disabled; most of the internal blocks

are turned off and the internal consumption is reduced to I_{q_DIS}; V_CCis maintained between V_Csonand V_Ccon

by the periodical activation of the internal HV-current source; the DEB counter is reset. Of course, if during the

count-up V_UVPexceeds V_{UVP_th}for some time, the DEB counter is decremented during that time and the IC

disable is delayed accordingly.

With IC disabled: if V_UVPrises above V_{UVP_th}, the REST counter is incremented, and when it reaches rest_eoc

(corresponding to t_{UVP_REST}), the IC resumes switching. Of course, if during the count-up, V_UVPfalls below

V_{UVP_th}for some time, the REST counter is decremented during that time and the IC re-enabling is delayed

accordingly.

Figure 29. UVP timing

V_UVP

V_UVP_th

V_DD

V_CCon

V_CSon

DEB counter

deb_eoc

REST counter

t_{UVP_DEB}

< t_{UVP_DEB}

rest_eoc

t_{UVP_REST}

I_DRAIN

IC re-enabled

IC disabled

Restart

delay

normal operation

disabled with ultra-low consumption (I_{q_DIS})

An input undervoltage protection can be easily realized connecting the rectified mains to UVP pin through a

voltage divider, as shown in Figure 30. Connection for input undervoltage protection/disable (isolated or non-

isolated topologies).

DS13285 - Rev 3

page 19/40

VIPER31

Undervoltage protection

Figure 30. Connection for input undervoltage protection/disable (isolated or non-isolated topologies)

D_IN

~ AC

from V_AUXor V_OUT

RH

VIPER31

VCC

OVP

DRAIN

C_IN

CONTROL

Cs

FB

GND

COMP

UVP

R2

C2

RL

C1

GND

If UVP function is not required, the UVP pin must be left floating. In this case, noise immunity of the pin is

guaranteed by the internal pull-up I_{UVP_pull-up}(1 uA, typ.) present in the UVP block.

If UVP function is required, RH value can be set arbitrarily, but some Mohms at least are recommended in order to

minimize the power consumption of the UVP network. Then, if V_{in_UVP}is the desired input undervoltage threshold,

the value of RL can be found from the following formula:

Equation 2

(2)

V

UVP_th

RL =

V

− V

in_UVP

UVP_th

+ I

UVP_pull − up

RH

Equation 3

(3)

2

Vin

RH + RL

PUVP Vin =

Thanks to the ultra-low consumption, the UVP pin can be used as an input to disable the SMPS from external,

reaching the lowest input power consumption while the SMPS is still connected to the AC mains but not delivering

power to its output.

The purpose of the UVP debounce time t_{UVP_DEB}is also to guarantee some hold-up in case of a missing cycle of

the input line, as illustrated in Figure 31. Hold-up in case of input line missing cycles.

DS13285 - Rev 3

page 20/40

VIPER31

Overvoltage protection

Figure 31. Hold-up in case of input line missing cycles

V_BULK

1 missing cycle

2 missing cycles

V_UVP

V_{UVP_th}

t_{UVP_DEB}

IC disabled

here

I_DRAIN

4.13

Overvoltage protection

If the voltage across OVP pin (V_OVP) exceeds the internal threshold V_{OVP_th}(4 V typ.) for a time greater than

t_{OVP_DEB}(250 us, typ.), the PWM is disabled in autorestart for t_{OVP_REST}time (500 ms, typ.), until V_OVPfalls

below V_{OVP_th}

.

The time interval t_{OVP_DEB}is intended to filter out possible noises/disturbances of the line, which could affect the

correct operation of the function, and is obtained through an up/down counter, where t_{OVP_DEB}is the time the

counter needs to reach its end-of-count (ovp_eoc) starting from zero and counting always up.

The operation is shown in Figure 32. OVP timing. When V_OVPexceeds V_{OVP_th}, the up/down OVP counter is

incremented.

If V_OVPfalls below V_{OVP_th}before the OVP counter reaches ovp_eoc, the counter is decremented. If the count

goes down to zero, a disturbance on the OVP pin is assumed and there is no consequence on the IC behavior.

If V_OVPstays above V_{OVP_th}until the OVP counter reaches ovp_eoc: the PWM is disabled in autorestart for a

t_{OVP_REST}time interval; the OVP counter is reset; V_CCis maintained between V_Csonand V_Cconby the periodical

activation of the internal HV-current source. Of course, if during the count-up V_OVPfalls below V_{OVP_th}for some

time, during that time the counter is decremented and the PWM disable is delayed accordingly.

When V_OVPdrops below V_{OVP_th}, the IC waits for the end of t_{OVP_REST}, then restarts with soft-start phase.

DS13285 - Rev 3

page 21/40

VIPER31

Overvoltage protection

Figure 32. OVP timing

V_OVP

V_OVP_th

V_DD

V_CCon

V_CSon

OVP count

ovp_eoc

< t_{OVP_DEB}

t_{OVP_DEB}

t_{OVP_REST}

t_{OVP_DEB}

OVP check and

IC re-enabled

GD

OVP triggered

and IC disabled

OVP check and

IC disabled

An input overvoltage protection can be easily realized connecting the rectified mains to OVP pin through a voltage

divider, as shown in Figure 33. Connection for input overvoltage protection (iso/non-iso topologies).

In case of non-isolated topologies, with the same principle an output overvoltage protection can be implemented,

as shown in Figure 34. Connection for output overvoltage protection (non-iso topologies).

If the OVP feature is not required, OVP pin must be connected to GND, which excludes the function.

If the OVP feature is required, RH value can be set arbitrarily, but some Mohms at least are recommended in

order to minimize the power consumption of the OVP network. Then, if V_{in/out_OVP}is the desired input/output

overvoltage threshold, the value of RL can be calculated from the following formula:

Equation 4

(4)

RH

RL =

V

in/out_OVP

− 1

V

OVP_tℎ

The power consumption of the OVP network at given Vin is expressed as:

Equation 5

(5)

2

Vin

POVP Vin =

RH + RL

in case of connection for input overvoltage protection and

Equation 6

(6)

2

VOUT

POVP VOUT =

RH + RL

in case of connection for output overvoltage protection.

DS13285 - Rev 3

page 22/40

VIPER31

Undervoltage and overvoltage protection

Figure 33. Connection for input overvoltage protection (iso/non-iso topologies)

D_IN

~ AC

from V_AUXor V_OUT

RH

VIPER31

VCC

OVP

DRAIN

C_IN

CONTROL

Cs

FB

GND

COMP

UVP

R2

C2

RL

C1

GND

Figure 34. Connection for output overvoltage protection (non-iso topologies)

V_OUT

D_OUT

C_OUT

from V_AUXor V_OUT

VIPER31

GND

VCC

DRAIN

OVP

FB

Rfb1

RH

CONTROL

COMP

Cs

GND

UVP

R2

C2

C1

Rfb2

RL

4.14

Undervoltage and overvoltage protection

If both undervoltage and overvoltage protections are required, they can be set independently from each other

through a single voltage divider, as illustrated in the figure below.

DS13285 - Rev 3

page 23/40

VIPER31

Undervoltage and overvoltage protection

Figure 35. Connection for input and output overvoltage protections (iso/non-iso topologies)

~ AC

D_IN

from V_AUXor V_OUT

RH

VIPER31

VCC

DRAIN

OVP

FB

C_IN

CONTROL

COMP

Cs

RM

GND

UVP

R2

C2

RL

C1

GND

The voltage divider equations are:

Equation 7

(7)

(8)

V

UVP

tℎ

RL

V

=

− I

· RH + RM + RL + RL · I

in_UVP

UVP_pull − up UVP_pull − up

Equation 8

RH

RH + RM + RL

V

= V

−

· RL · I

UVP_pull − up

·

in_OVP

OVP

RH + RM + RL

RM + RL

tℎ

Considering that the value of RH is much higher than the values of RM and RL (Mohms vs. kohms), equations 7

and 8 can be approximated into Eq. 7.a) and Eq. 8.a) respectively:

Equation 7.a

(7.a)

V

UVP

RL

tℎ

V

− I

· RH + RL · I

UVP_pull − up

in_UVP

UVP_pull − up

Equation 8.a

(8.a)

RH

V

− RL · I

·

UVP_pull − up

RM + RL

in_OVP

OVP

tℎ

Selecting arbitrarily the RH value, Equation 7.a) can be solved for RL:

Equation 9

(9)

2

V

+ I

UVP_pull − up

· RH −

V

+ I

UVP_pull − up

· RH − 4 · V

· I · RH

UVP_pull − up

in_UVP

2 · I

UVP

tℎ

RL =

UVP_pull − up

and Equation 8.a) for RM:

Equation 10

DS13285 - Rev 3

page 24/40

VIPER31

Thermal shutdown

(10)

(11)

RH

RM = V

− RL · I

·

− RL

OVP

UVP_pull − up

V

tℎ

in_OVP

The power consumption of the UVP-OVP network at given Vin is expressed as:

Equation 11

2

in

V

P

V

=

UVP_OVP in

RH + RM + RL

As an example, if V_{in_UVP}and V_{in_OVP}design values are 50 Vdc and 450 Vdc respectively, and RH is set to 6

Mohm: from Equations 9 and 10 we have RL = 43 kohm, and RM = 60 kohm respectively, while from Equation 11

the power consumption of the network at 230 Vac is about 17 mW.

4.15

Thermal shutdown

The power MOSFET junction temperature is sensed during the on-time through a diode integrated into the HV

section of the chip. If a junction temperature higher than the internal threshold TSD (160°C, typ.) is measured, the

PWM is disabled for t_RESTART. In order to increase robustness against electromagnetic noises, the protection is

triggered only if the condition is met for nth = 3 consecutive switching cycles.

After t_RESTART, the IC resumes switching with soft-start phase: if a junction temperature above TSD is still

measured for nth consecutive switching cycles, the protection is triggered and PWM is disabled again for

t_RESTART; otherwise normal operation is restored.

During t_RESTART, V_CCis maintained between V_Csonand V_Cconby the HV current source periodical activation.

Such a behavior is summarized in Figure 36. Thermal shutdown timing diagram.

Figure 36. Thermal shutdown timing diagram

T_J

T_SD

t

V_CC

V_CCon

V_CSon

t

GD

n < n_th

n = n_th

t

t_RESTART

DS13285 - Rev 3

page 25/40

VIPER31

Application information

5

Application information

5.1

Typical schematics

Figure 37. Flyback converter (non-isolated)

Daux

~ AC

Din

Rin

Dout

Vout

T

Ccl

Cout

Cin

Rcl

GND

VIPER31

DRAIN

VCC

OVP

CONTROL

RH

FB

COMP

UVP

Cs

GND

R2

C2

RL

C1

Figure 38. Flyback converter (isolated)

~ AC

Din

Rin

T

Dout

Vout

Cin

Ccl

Cout

Rcl

Raux

Daux

GND2

R3

VIPER31

VCC

DRAIN

RH

OVP

FB

OPTO

CONTROL

COMP

R4

C2

Cs

GND

UVP

OPTO

C1

RL

GND1

DS13285 - Rev 3

page 26/40

VIPER31

Typical schematics

Figure 39. Flyback converter (primary regulation)

Dout

Din

Rin

Vout

T

~ AC

Cout

Ccl

Rcl

GND2

Daux

VIPER31

VCC

DRAIN

RH

Cin

OVP

FB

Cs

CONTROL

COMP

GND

UVP

RL

C2

C1

R2

GND1

Figure 40. Buck converter

Din

Rin

~ AC

Daux

VIPER31

VCC

DRAIN

GND

RH

RL

OVP

FB

Cs

C3

CONTROL

COMP

UVP

C1

D2

Cin

R2

C2

Lout

Vout

D1

Cout

GND

Figure 41. Buck-boost converter

Din

Rin

~ AC

Daux

VIPER31

VCC

DRAIN

GND

RH

OVP

FB

Cs

CONTROL

COMP

C3

UVP

C1

Cin

RL

D2

D1

Vout

GND

R2

C2

Cout

Lout

GND

DS13285 - Rev 3

page 27/40

VIPER31

Energy saving performances

5.2

Energy saving performances

The VIPer31 allows the design of applications compliant with the most stringent energy saving regulations. In

order to show the typical performances achievable, the active mode average efficiency and the efficiency at

10% of the rated output power of a single output flyback converter using VIPer31 have been measured and are

reported in Table 9. In addition, Figures 52 and 53 show no-load and light load consumptions.

Table 9. Power supply efficiency, VOUT = 15 V

10% output load

efficiency [%]

Active mode average

efficiency [%]

Pin @ no-load

[mW]

V

Parameter

IN

115 V

230 V

83.2

77.4

85.9

86.6

26.0

29.7

AC

Flyback iso, 15V/1.2A

AC

Figure 42. PIN versus VIN in no-load, VOUT = 15V

40

30

20

10

50

100

150

200

V_IN[V_AC]

250

300

DS13285 - Rev 3

page 28/40

VIPER31

Energy saving performances

Figure 43. PIN versus VIN in light-load, VOUT = 15V

450

400

350

300

250

200

150

100

50

P_OUT= 250mW

P_OUT= 50mW

P_OUT= 25mW

0

50

100

150

200

V_IN[V_AC

250

300

]

DS13285 - Rev 3

page 29/40

VIPER31

Layout guidelines and design recommendations

5.3

Layout guidelines and design recommendations

A proper printed circuit board layout is essential for correct operation of any switch-mode converter and this is

true for the VIPer as well. The main reasons to have a proper PCB layout are to:

•

Provide clean signals to the IC, ensuring good immunity against external noises and switching noises

Reduce the electromagnetic interferences, both radiated and conducted, to pass more easily the EMC

When designing an SMPS using VIPer, the following basic rules should be considered:

•

Separating signal from power tracks: generally, traces carrying signal currents should run far from those

carrying pulsed currents or with quickly swinging voltages. Signal ground traces should be connected to the

IC signal ground, GND, using a single “star point”, placed close to the IC. Power ground traces should be

connected to the IC power ground, GND. The compensation network should be connected to the COMP,

maintaining the trace to GND as short as possible. In case of two layer PCB, it is a good practice to route

signal traces on one PCB side and power traces on the other side.

Filtering sensitive pins: some crucial points of the circuit need or may need filtering. A small high-

frequency bypass capacitor to GND might be useful to get a clean bias voltage for the signal part of the

IC and protect the IC itself during EFT/ESD tests. A low ESL ceramic capacitor (a few hundreds pF up to

0.1 μF) should be connected across VCC and GND, placed as close as possible to the IC. With flyback

topologies, when the auxiliary winding is used, it is suggested to connect the VCC capacitor on the auxiliary

return and then to the main GND using a single track.

Keep power loops as confined as possible: minimize the area circumscribed by current loops where high

pulsed currents flow, in order to reduce its parasitic self-inductance and the radiated electromagnetic field:

this greatly reduces the electromagnetic interferences produced by the power supply during the switching. In

a flyback converter the most critical loops are: the one including the input bulk capacitor, the power switch,

the power transformer, the one including the snubber, the one including the secondary winding, the output

rectifier and the output capacitor. In a buck converter the most critical loop is the one including the input bulk

capacitor, the power switch, the power inductor, the output capacitor and the free-wheeling diode.

•

Reduce line lengths: any wire acts as an antenna. With the very short rise times exhibited by EFT pulses,

any antenna has the capability of receiving high-voltage spikes. By reducing line lengths, the level of

radiated energy that is received is reduced, and the resulting spikes from electrostatic discharges are lower.

This also keeps both resistive and inductive effects to a minimum. In particular, all of the traces carrying high

currents, especially if pulsed (tracks of the power loops) should be as short and fat as possible.

Optimize track routing: as levels of pickup from static discharges are likely to be greater closer to the

extremities of the board, it is wise to keep any sensitive lines away from these areas. Input and output lines

often need to reach the PCB edge at some stage, but they can be routed away from the edge as soon

as possible where applicable. Since vias are to be considered inductive elements, it is recommended to

minimize their number in the signal path and avoid them when designing the power path.

Improve thermal dissipation: an adequate copper area has to be provided under the DRAIN pins as heat

sink, while it is not recommended to place large copper areas on the GND.

DS13285 - Rev 3

page 30/40

VIPER31

Layout guidelines and design recommendations

Figure 44. Recommended routing for flyback converter

D_IN

R_IN

D_OUT

V_OUT

~ AC

TR

C_IN

C_CL

R_CL

C_OUT

D_AUX

GROUND

Cs

R_OPTO

OPTO

RH

C_C

R_C

DR. DR. DR. DR. N.C. N.C. N.C. N.C.

VIPER31

CONTROL

GND N.C. VCC N.A. UVP OVP FB COMP

OPTO

RL

C1

Figure 45. Recommended routing for buck converter

D_IN

R_IN

~ AC

C_IN

DR. DR. DR. DR. N.C. N.C. N.C. N.C.

VIPER31

CONTROL

GND N.C. VCC N.A. UVP OVP FB COMP

Cc

D_AUX

Cs

RH

RL

C1

D1

L_OUT

V_OUT

C_OUT

D_OUT

GROUND

DS13285 - Rev 3

page 31/40

VIPER31

Package information

6

Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,

depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product

status are available at: www.st.com. ECOPACK is an ST trademark.

6.1

SO16N package information

Figure 46. SO16N package outline

DS13285 - Rev 3

page 32/40

VIPER31

SO16N package information

Table 10. SO16N mechanical data

mm

Dim.

Min.

Typ.

Max.

1.75

0.25

A

A1

A2

b

0.1

1.25

0.31

0.17

9.8

0.51

0.25

10

c

D

9.9

6

E

5.8

6.2

4

E1

e

3.8

3.9

1.27

h

0.25

0.4

0

0.5

1.27

8

L

k

ccc

0.1

DS13285 - Rev 3

page 33/40

VIPER31

Order code

7

Order code

Table 11. Order code

I

(OCP) typ

Order code

FOSC ± jitter

Package

DLIM

VIPER318XDTR

VIPER319XDTR

VIPER317LDTR

VIPER318LDTR

VIPER319LDTR

VIPER317HDTR

VIPER318HDTR

VIPER319HDTR

850 mA

990 mA

710 mA

850 mA

990 mA

710 mA

850 mA

990 mA

30 kHz ± 7%

60 kHz ± 7%

132 kHz ± 7%

SO16N tape and reel

DS13285 - Rev 3

page 34/40

VIPER31

Revision history

Table 12. Document revision history

Date

Version

Changes

31-Mar-2020

8-Jun-2020

1

2

Initial release.

Updated Section Features; updated Table 6, Table 7, Table 11; updated

figures in Section 5.1 Typical schematics; minor text update.

Added data for VIPER317/318/319 in Section Features, in Table 7 and

Table 11

17-Nov-2020

3

DS13285 - Rev 3

page 35/40

VIPER31

Contents

1

2

Pin setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Electrical and thermal ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.1

Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

4

Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Typical power capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Primary MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

High-voltage startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Soft startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Pulse skipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Direct feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Secondary feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.10 Pulse frequency modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.11 Overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.12 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.13 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.14 Undervoltage and overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.15 Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

5

5.1

5.2

5.3

Typical schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Energy saving performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Layout guidelines and design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6

7

Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

6.1

[Package name] package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

DS13285 - Rev 3

page 36/40

VIPER31

Contents

List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

DS13285 - Rev 3

page 37/40

VIPER31

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Avalanche characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Supply section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Controller section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power supply efficiency, VOUT = 15 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 10. SO16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 11. Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 12. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

DS13285 - Rev 3

page 38/40

VIPER31

List of figures

Figure 1.

Figure 2.

Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

R_{th_JA}versus copper area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

I_DLIMvs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

F_OSCvs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V_{HV_START}vs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

VF_{B_REF}vs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Quiescent Current I_qvs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Operating current I_CCvs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

I_CH1vs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

I_CH2vs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

I_CH1vs. V_DRAIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

I_CH2vs. V_DRAIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

G_Mvs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

I_COMPvs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

R_DSONvs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

R_DSONvs. I_DRAIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Static drain-source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power MOSFET C_OSSvs. V_DS@ V_GS=0, f=1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V_BVDSSvs. T_J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SOA SO16N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Maximum avalanche energy vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Typical deliverable output power vs. T_AMB(Vin: 85-265V_AC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power ON and power OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Soft startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pulse skipping during startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Overload protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

UVP timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Connection for input undervoltage protection/disable (isolated or non-isolated topologies) . . . . . . . . . . . . . . . 20

Hold-up in case of input line missing cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

OVP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Connection for input overvoltage protection (iso/non-iso topologies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Connection for output overvoltage protection (non-iso topologies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Connection for input and output overvoltage protections (iso/non-iso topologies). . . . . . . . . . . . . . . . . . . . . . 24

Thermal shutdown timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Flyback converter (non-isolated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Flyback converter (isolated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Flyback converter (primary regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Buck-boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PIN versus VIN in no-load, VOUT = 15V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

PIN versus VIN in light-load, VOUT = 15V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Recommended routing for flyback converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Recommended routing for buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SO16N package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

Figure 31.

Figure 32.

Figure 33.

Figure 34.

Figure 35.

Figure 36.

Figure 37.

Figure 38.

Figure 39.

Figure 40.

Figure 41.

Figure 42.

Figure 43.

Figure 44.

Figure 45.

Figure 46.

DS13285 - Rev 3

page 39/40

VIPER31

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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DS13285 - Rev 3

page 40/40


型号：	VIPER319HDTR
厂家：	ST
描述：	Energy saving offline high voltage converter
文件：	总40页 (文件大小：1107K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VIPER319HDTR [STMICROELECTRONICS]

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