VN7040AJTR-E [STMICROELECTRONICS]
BUF OR INV BASED PRPHL DRVR, PDSO16, ROHS COMPLIANT, SSOP-16;
| 型号： | VN7040AJTR-E |
| 厂家： | 
ST |
| 描述： | BUF OR INV BASED PRPHL DRVR, PDSO16, ROHS COMPLIANT, SSOP-16 驱动 光电二极管 接口集成电路 |
| 文件： | 总54页 (文件大小：1994K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
62ꢀꢂ
VN7040AS-E
VN7040AJ-E
High-side driver with MultiSense analog feedback
for automotive application
Datasheet
-
production data
– Configurable latch-off on overtemperature
or power limitation with dedicated fault
reset pin
– Loss of ground and loss of VCC
1PXFS440ꢅꢆꢂ
("1($'5ꢀꢀꢁꢀꢂ
– Reverse battery with external components
– Electrostatic discharge protection
("1($'5ꢀꢀꢁꢃꢄ
Features
Applications
Max transient supply voltage
Operating voltage range
VCC
VCC
40 V
4 to 28 V
40 mΩ
34 A
• All types of automotive resistive, inductive and
capacitive loads
Typ. on-state resistance (per Ch) RON
• Specially intended for Automotive Turn
Indicators (up to P27W or SAE1156 and R5W
paralleled or LED Rear Combinations)
Current limitation (typ)
Stand-by current (max)
ILIMH
ISTBY
0.5 µA
Description
• General
The VN7040AS-E and VN7040AJ-E are single
channel high-side drivers manufactured using ST
proprietary VIPower® technology and housed in
PowerSSO-16 and SO-8 packages. The devices
are designed to drive 12 V automotive grounded
loads through a 3 V and 5 V CMOS compatible
interface, and to provide protection and
diagnostics.
– Single channel smart high-side driver with
MultiSense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS
outputs
• MultiSense diagnostic functions
– Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
The devices integrate advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off. A FaultRST pin unlatches the output in
case of fault or disables the latch-off functionality.
T
CHIP device temperature
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
– Sense enable/ disable
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load.
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
May 2014
DocID022406 Rev 7
1/54
This is information on a product in full production.
www.st.com
1
Contents
VN7040AS-E, VN7040AJ-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3
4
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1
3.2
3.3
3.4
Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 30
4.1.1 Diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2
4.3
4.4
Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 31
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Multisense - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4.1
4.4.2
4.4.3
Principle of Multisense signal generation . . . . . . . . . . . . . . . . . . . . . . . 34
CASE and VCC monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . 37
T
4.5
Maximum demagnetization energy (V = 13.5 V) . . . . . . . . . . . . . . . . . 38
CC
5
6
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1
5.2
PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
®
6.1
6.2
ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2/54
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Contents
6.3
6.4
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7
8
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DocID022406 Rev 7
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List of tables
VN7040AS-E, VN7040AJ-E
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified). . . . . . . . . . . . . . 12
Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MultiSense multiplexer addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . 31
Multisense pin levels in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4/54
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I
OUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current sense accuracy versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Switching times and Pulse skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MultiSense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Multisense timings (chip temperature and VCC sense mode) (VN7040AJ-E only) . . . . . . 20
T
DSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) . . . . . . . . . . . 22
Figure 11. Latch functionality - behavior in hard short circuit condition . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) 23
Figure 13. Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16. Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17.
IGND(ON) vs. Iout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 18. Logic Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. Logic Input low level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 22. Logic Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 23. FaultRST Input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 24. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 25. On-state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 26. On-state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 27. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 28. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 29. Won vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 30. Woff vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 31.
ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 32. OFF-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 33.
Figure 34.
V
V
sense clamp vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
senseh vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 35. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 36. Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 37. Multisense and diagnostic – block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 38. Multisense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 39. Analogue HSD – open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 40. Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 41. GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 42. Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . 39
Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . 39
Figure 45. PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . 40
Figure 46. PowerSSO-16 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 40
Figure 47. Thermal fitting model for PowerSSO-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 48. SO-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DocID022406 Rev 7
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List of figures
VN7040AS-E, VN7040AJ-E
Figure 49. SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 50. SO-8 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . 43
Figure 51. SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 52. Thermal fitting model for SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 53. PowerSSO-16 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 54. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 55. SO-8 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 56. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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VN7040AS-E, VN7040AJ-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
VCC
Internal supply
VCC – GND
Clamp
Undervoltage
shut-down
Control & Diagnostic
VCC – OUT
Clamp
FaultRST
Gate Driver
INPUT
SEL1
T
VCC
VON
Limitation
SEL0
Current
Limitation
SEn
Power Limitation
Overtemperature
T
Multisense
Short to VCC
Open-Load in OFF
Current
Sense
Fault
VSENSEH
GND
OUTPUT
Table 1. Pin functions
Name
VCC
Function
Battery connection.
Power output.
OUTPUT
GND
Ground connection. Must be reverse battery protected by an external
diode/resistor network.
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V
CMOS outputs. It controls output switch state.
INPUT
MultiSense
SEn
Multiplexed analog sense output pin; it delivers a current proportional to the
selected diagnostic: load current, supply voltage or chip temperature
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the
MultiSense diagnostic pin.
Active high compatible with 3 V and 5 V CMOS outputs pin; they address the
MultiSense multiplexer.
SEL0,1
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the
output in case of fault; If kept low, sets the outputs in auto-restart mode.
FaultRST
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Block diagram and pin description
VN7040AS-E, VN7040AJ-E
Figure 2. Configuration diagram (top view)
PowerSSO-16
1
16
15
14
13
12
11
10
9
OUTPUT
OUTPUT
OUTPUT
OUTPUT
N.C.
N.C.
N.C.
N.C.
INPUT
FaultRST
SEn
2
3
4
5
6
7
8
GND
SEL0
SEL1
MultiSense
N.C.
TAB = VCC
SO-8
VCC
1
2
3
4
8
7
6
5
INPUT
SEn
OUTPUT
OUTPUT
VCC
GND
MultiSense
Table 2. Suggested connections for unused and not connected pins
SEn, SELx,
FaultRST
Connection/pin MultiSense
N.C.
Output
Input
Floating
To ground
Not allowed
X(1)
X
X
X
X
Through 1 kΩ
Through 15 kΩ Through 15 kΩ
resistor resistor
Not allowed
resistor
1. X: do not care.
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Electrical specification
2
Electrical specification
Figure 3. Current and voltage conventions
,
6
9&&
9&&
9)Q
,
,
)5
,
287
)DXOW567
6(Q
287387
6(Q
9287
,
6(16(
,
6(/
0XOWL6HQVH
6(/ꢃꢄꢅ
96(16(
,
,1
,1387
,
*1'
*$3*&)7ꢃꢃꢆꢆꢃ
Note: VF = VOUT - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions in table below for extended periods may affect device reliability.
Table 3. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
38
-VCC
Reverse DC supply voltage
0.3
Maximum transient supply voltage (ISO 16750-2:2010 Test B
clamped to 40 V; RL = 4 Ω)
V
VCCPK
VCCJS
40
28
Maximum jump start voltage for single pulse short circuit
protection
-IGND
IOUT
-IOUT
IIN
DC reverse ground pin current
OUTPUT DC output current
Reverse DC output current
INPUT DC input current
SEn DC input current
200
Internally limited
11
mA
A
ISEn
ISEL
IFR
-1 to 10
mA
V
SEL0,1 DC input current
FaultRST DC input current
FaultRST DC input voltage
-1 to 10
7.5
VFR
DocID022406 Rev 7
9/54
Electrical specification
VN7040AS-E, VN7040AJ-E
Table 3. Absolute maximum ratings (continued)
Symbol
Parameter
Value
Unit
MultiSense pin DC output current (VGND = VCC and
VSENSE < 0 V)
10
-20
36
ISENSE
mA
MultiSense pin DC output current in reverse (VCC < 0V)
Maximum switching energy (single pulse)
TDEMAG = 0.4 ms; Tjstart = 150 °C
EMAX
mJ
Electrostatic discharge (JEDEC 22A-114F)
– INPUT
4000
2000
4000
4000
4000
V
V
V
V
V
– MultiSense
– SEn, SEL0,1, FaultRST
– OUTPUT
VESD
– VCC
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
750
V
-40 to 150
-55 to 150
°C
Tstg
2.2
Thermal data
Table 4. Thermal data
Parameter
Typ. value
Symbol
Unit
SO-8 PSSO-16
Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5/51-8) (1) 29
6.2
57
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5) (2)
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7) (1)
1. Device mounted on four-layers 2s2p PCB.
67
45
°C/W
23.5
2
2. Device mounted on two-layers 2s0p PCB with 2 cm heatsink copper trace.
10/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Electrical specification
2.3
Main electrical characteristics
7 V < VCC < 28 V; -40 °C < Tj < 150 °C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5. Power section
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
Undervoltage shutdown
4
13
28
4
VUSD
Undervoltage shutdown
reset
V
VUSDReset
5
Undervoltage shutdown
hysteresis
VUSDhyst
0.3
40
IOUT = 2.5 A; Tj = 25 °C
IOUT = 2.5 A; Tj = 150 °C
RON
On-state resistance
Clamp voltage
80
60
mΩ
I
OUT = 2.5 A; VCC = 4 V; Tj = 25 °C
IS = 20 mA; Tj = -40 °C
38
41
Vclamp
V
IS = 20 mA; 25°C < Tj < 150°C
46
52
VCC = 13 V;
VIN = VOUT = VSEn 0 V;
0.5
V
FR = VSEL0,1 = 0 V; Tj = 25 °C
Supply current in
standby at
V
CC = 13 V;
ISTBY
VIN = VOUT = VSEn 0 V;
V
FR = VSEL0,1 = 0 V; Tj = 85 °C (2)
0.5
3
µA
VCC = 13 V (1)
VCC = 13 V;
VIN = VOUT = VSEn 0 V;
V
FR = VSEL0,1 = 0 V; Tj = 125 °C;
VCC = 13 V;
VIN = VOUT = VFR = VSEL0,1 = 0V;
Standby mode blanking
time
tD_STBY
60 300 550 µs
V
SEn = 5 V to 0 V
V
CC = 13 V; VSEn = 0 V;
IS(ON)
Supply current
VSEL0,1 = VFR = 0V;
IN = 5 V; IOUT = 0 A
3
5
6
mA
mA
V
Control stage current
consumption in ON
state. All channels
active.
VCC = 13 V; VSEn = 5 V;
VFR = VSEL0,1 = 0 V; VIN = 5 V;
IGND(ON)
I
OUT = 2.5 A
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25 °C
0
0
0.01 0.5
Off-state output current
at VCC = 13 V
IL(off)
µA
V
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C
3
Output - VCC diode
voltage
VF
IOUT = -2.5 A; Tj = 150 °C
0.7
1. PowerMOS leakage included.
2. Parameter specified by design; not subject to production test.
DocID022406 Rev 7
11/54
Electrical specification
VN7040AS-E, VN7040AJ-E
Table 6. Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified(1)
)
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
Turn-on delay time at
Tj = 25°C
td(on)
10
40
120
100
0.7
RL = 5.2 Ω
µs
Turn-off delay time at
Tj = 25°C
td(off)
(dVOUT/dt)on
(dVOUT/dt)off
WON
10
0.1
0.1
—
35
Turn-on voltage slope at
Tj = 25°C
0.24
0.28
0.32
0.33
10
RL = 5.2 Ω
V/µs
Turn-off voltage slope at
Tj = 25°C
0.7
Switching energy losses at
RL = 5.2 Ω
RL = 5.2 Ω
RL = 5.2 Ω
0.4(2)
0.4(2)
60
mJ
mJ
µs
turn-on (twon
)
Switching energy losses at
WOFF
—
turn-off (twoff
)
Differential Pulse skew
(tPHL - tPLH) see Figure 6
tSKEW
-40
1. See Figure 6: Switching times and Pulse skew.
2. Parameter guaranteed by design and characterization; not subject to production test.
Table 7. Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
INPUT characteristics
VIL
IIL
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
0.9
V
µA
V
VIN = 0.9 V
VIN = 2.1 V
IIN = 1 mA
1
VIH
2.1
IIH
10
µA
V
VI(hyst)
0.2
5.3
7.2
VICL
Input clamp voltage
V
I
IN = -1 mA
-0.7
FaultRST characteristics (VN7040AJ-E only)
VFRL
IFRL
VFRH
IFRH
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
0.9
V
µA
V
VIN = 0.9 V
VIN = 2.1 V
1
2.1
10
µA
V
VFR(hyst)
0.2
5.3
I
IN = 1 mA
7.5
VFRCL
Input clamp voltage
V
IIN = -1 mA
-0.3
SEL0,1 characteristics (7 V < VCC < 18 V) (VN7040AJ-E only)
VSELL Input low level voltage
0.9
V
12/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Electrical specification
Table 7. Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
ISELL
VSELH
ISELH
Low level input current
Input high level voltage
High level input current
VIN = 0.9 V
1
µA
V
2.1
VIN = 2.1 V
10
µA
V
VSEL(hyst) Input hysteresis voltage
VSELCL Input clamp voltage
SEn characteristics (7 V < VCC < 18 V)
0.2
5.3
IIN = 1 mA
IIN = -1 mA
7.2
V
-0.7
VSEnL
ISEnL
VSEnH
ISEnH
Input low level voltage
Low level input current
Input high level voltage
High level input current
0.9
V
µA
V
VIN = 0.9 V
VIN = 2.1 V
1
2.1
10
µA
V
VSEn(hyst) Input hysteresis voltage
0.2
5.3
I
IN = 1 mA
7.2
VSEnCL
Input clamp voltage
V
IIN = -1 mA
-0.7
Table 8. Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V
CC = 13 V
24
34
48
48
ILIMH
DC short circuit current
4 V < VCC < 18 V(1)
A
Short circuit current
during thermal cycling
VCC = 13 V;
TR < Tj < TTSD
ILIML
13
TTSD
TR
Shutdown temperature
Reset temperature(1)
150
175
200
TRS + 1 TRS + 7
135
Thermal reset of fault
diagnostic indication
VFR = 0 V;
°C
TRS
VSEn = 5 V;
Thermal hysteresis
(TTSD - TR)(1)
THYST
ΔTJ_SD
7
Tj = -40 °C;
VCC = 13 V
Dynamic temperature
60
K
Fault reset time for output VFR = 5 V to 0 V;
tLATCH_RST unlatch(1) (VN7040AJ-E
only)
V
SEn = 5 V;VIN = 5 V;
3
10
20
µs
VSEL0,1 = 0 V
DocID022406 Rev 7
13/54
Electrical specification
VN7040AS-E, VN7040AJ-E
Table 8. Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
IOUT = 2 A; L = 6 mH;
Tj = -40 °C
VCC - 38
Turn-off output voltage
clamp
VDEMAG
V
IOUT = 2 A; L = 6 mH;
Tj = 25 °C to +150 °C
VCC - 41 VCC - 46 VCC - 52
20
Output voltage drop
limitation
VON
IOUT = 0.25 A
mV
1. Parameter guaranteed by design and characterization; not subject to production test.
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VSEn = 0 V; ISENSE = 1 mA
-17
-12
V
MultiSense clamp
voltage
VSENSE_CL
VSEn = 0 V; ISENSE = -1 mA
7
Current Sense characteristics
IOUT = 0.01 A;
VSENSE = 0.5 V; VSEn = 5 V
KOL
dKcal/Kcal
KLED
IOUT/ISENSE
530
-30
Current sense ratio
drift at calibration
point
IOUT = 0.01 A to 0.05 A;
(1)(2)
I
cal = 30 mA;
30
%
VSENSE = 0.5 V; VSEn = 5 V
IOUT = 0.05 A;
IOUT/ISENSE
900 1800 2650
V
SENSE = 0.5 V; VSEn = 5 V
Current sense ratio
drift
IOUT = 0.05 A; VSENSE = 0.5
V; VSEn = 5 V
(1)(2)
dKLED/KLED
-25
940 1550 2200
-20 20
25
%
%
%
%
%
IOUT = 0.25 A; VSENSE = 0.5
V; VSEn = 5 V
K0
IOUT/ISENSE
Current sense ratio
drift
IOUT = 0.25 A; VSENSE = 0.5
V; VSEn = 5 V
(1)(2)
dK0/K0
IOUT = 0.5 A; VSENSE = 4 V;
VSEn = 5 V
K1
IOUT/ISENSE
1000 1400 1920
-15 15
1140 1350 1710
Current sense ratio
drift
IOUT = 0.5 A; VSENSE = 4 V;
VSEn = 5 V
(1)(2)
dK1/K1
IOUT = 1.5 A; VSENSE = 4 V;
K2
IOUT/ISENSE
VSEn = 5 V
Current sense ratio
drift
IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V
(1)(2)
dK2/K2
K3
-10
10
IOUT = 4.5 A; VSENSE = 4 V;
VSEn = 5 V
IOUT/ISENSE
1200 1340 1470
Current sense ratio
drift
IOUT = 4.5 A; VSENSE = 4 V;
(1)(2)
dK3/K3
-5
5
VSEn = 5 V
14/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Electrical specification
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
MultiSense disabled:
VSEn = 0 V;
0
0.5
0.5
MultiSense disabled:
-1 V < VSENSE < 5 V(1)
-0.5
MultiSense enabled:
VSEn = 5 V
Channel ON; IOUT = 0 A;
Diagnostic selected;
0
0
2
2
MultiSense leakage
current
ISENSE
µA
0
V
IN = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT = 0 A;
MultiSense enabled:
VSEn = 5 V
Channel OFF;
Diagnostic selected:
VIN = 0 V;
VSEL0 = 0 V; VSEL1 = 0 V;
VSEn = 5 V;
Output Voltage for
MultiSense shutdown VSEL0 = 0 V; VSEL1 = 0 V;
RSENSE = 2.7 kΩ; VIN = 5 V;
(1)
VOUT_MSD
5
V
V
I
OUT = 2.5 A
VCC = 7 V;
RSENSE = 2.7 kΩ;
Multisense saturation
voltage
VSENSE_SAT
V
SEn = 5 V; VIN = 5 V;
5
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT = 4.5 A; Tj = 150°C
VCC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
(1)
ISENSE_SAT
CS saturation current
4
6
mA
A
V
CC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V;
SEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
Output saturation
current
(1)
IOUT_SAT
V
OFF-state diagnostic
OFF-state open-load VIN = 0 V;
VOL
voltage detection
threshold
V
SEn = 5 V;
2
3
4
V
VSEL0 = 0 V; VSEL1 = 0 V;
OFF-state output sink VIN = 0 V; VOUT = VOL
;
IL(off2)
-100
-15
µA
current
Tj = -40°C to 125°C
OFF-state diagnostic
delay time from falling
edge of INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
tDSTKON
100
350
700
µs
I
OUT = 0 A; VOUT = 4 V
(see Figure 9)
DocID022406 Rev 7
15/54
Electrical specification
VN7040AS-E, VN7040AJ-E
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Settling time for valid
OFF-state open load
diagnostic indication
from rising edge of
SEn
VIN = 0 V; VFR = 0 V;
V
SEL0 = 0 V; VSEL1 = 0 V;
tD_OL_V
60
30
µs
µs
VOUT = 4 V; VSEn = 0 V to
5 V
OFF-state diagnostic VIN = 0 V; VSEn = 5 V;
delay time from rising VSEL0 = 0 V; VSEL1 = 0 V;
tD_VOL
5
edge of VOUT
Chip temperature analog feedback (VN7040AJ-E only)
VSEn = 5 V; VSEL0 = 0 V;
VOUT = 0 V to 4 V
VSEL1 = 5 V; VIN = 0 V;
RSENSE = 1 KΩ; Tj = -40 °C
2.325 2.41 2.495
1.985 2.07 2.155
V
V
MultiSense output
voltage proportional
to chip temperature
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN = 0 V;
RSENSE = 1 KΩ; Tj = 25 °C
VSENSE_TC
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN = 0 V;
RSENSE = 1 KΩ; Tj = 125 °C
1.435 1.52 1.605
-5.5
V
Temperature
coefficient
dVSENSE_TC/dT
Transfer function
Tj = -40 °C to 150 °C
mV/K
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T -
T0)
VCC supply voltage analog feedback (VN7040AJ-E only)
MultiSense output
voltage proportional
VCC = 13 V; VSEn = 5 V;
VSEL0 = 5 V; VSEL1 = 5 V;
VSENSE_VCC
3.16 3.23
3.3
V
to VCC supply voltage VIN = 0 V; RSENSE = 1 KΩ
Transfer function(3)
VSENSE_VCC = VCC / 4
Fault diagnostic feedback (see Table 10)
VCC = 13 V; RSENSE = 1 kΩ;
SEn = 5 V; VIN = 0 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT = 0 A; VOUT = 4 V
MultiSense output
voltage in fault
condition
V
VSENSEH
5
6.6
30
V
MultiSense output
current in fault
condition
ISENSEH
VCC = 13 V; VSENSE = 5 V
7
20
mA
MultiSense timings (current sense mode - see Figure 7)
Current sense settling
time from rising edge
of SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 5.2 Ω
tDSENSE1H
60
20
µs
µs
Current sense disable
delay time from falling
edge of SEn
VIN = 5 V; VSEn = 5 V to 0 V;
RSENSE = 1 kΩ; RL = 5.2 Ω
tDSENSE1L
5
16/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Electrical specification
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Current sense settling
time from rising edge
of INPUT
V
R
IN = 0 V to 5 V; VSEn = 5 V;
SENSE = 1 kΩ; RL = 5.2 Ω
tDSENSE2H
100
250
100
250
µs
µs
µs
Current sense settling
time from rising edge
of IOUT (dynamic
VIN = 5 V; VSEn = 5 V;
R
ISENSE = 90 % of
ISENSEMAX; RL = 5.2 Ω
SENSE = 1 kΩ;
ΔtDSENSE2H
response to a step
change of IOUT
)
Current sense turn-off
delay time from falling
edge of INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 5.2 Ω
tDSENSE2L
50
MultiSense timings (chip temperature sense mode - see Figure 8) (VN7040AJ-E only)
VSENSE_TC settling VSEn = 0 V to 5 V;
tDSENSE3H
time from rising edge VSEL0 = 0 V; VSEL1 = 5 V;
60
20
µs
µs
of SEn
RSENSE = 1 kΩ
VSENSE_TC disable
VSEn = 5 V to 0 V;
tDSENSE3L
delay time from falling VSEL0 = 0 V; VSEL1 = 5 V;
edge of SEn RSENSE = 1 kΩ
MultiSense timings (VCC voltage sense mode - see Figure 8) (VN7040AJ-E only)
VSENSE_VCC settling VSEn = 0 V to 5 V;
tDSENSE4H
time from rising edge VSEL0 = 5 V; VSEL1 = 5 V;
of SEn RSENSE = 1 kΩ
60
20
µs
µs
VSENSE_VCC disable VSEn = 5 V to 0 V;
delay time from falling VSEL0 = 5 V; VSEL1 = 5 V;
tDSENSE4L
edge of SEn
MultiSense timings (Multiplexer transition times)(4) (VN7040AJ-E only)
IN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ
V
MultiSense transition VSEL0 = 0 V;
tD_CStoTC
tD_TCtoCS
tD_CStoVCC
delay from current
sense to TC sense
VSEL1 = 0 V to 5 V;
OUT = 1.25 A;
RSENSE = 1 kΩ
60
20
60
µs
µs
µs
I
VIN = 5 V; VSEn = 5 V;
VSEL0 = 0 V;
MultiSense transition
delay from TC sense VSEL1 = 5 V to 0 V;
to current sense IOUT = 1.25 A;
SENSE = 1 kΩ
R
V
IN = 5 V; VSEn = 5 V;
MultiSense transition VSEL0 = 5 V;
delay from current
sense to VCC sense
VSEL1 = 0 V to 5 V;
IOUT = 1.25 A;
RSENSE = 1 kΩ
DocID022406 Rev 7
17/54
Electrical specification
VN7040AS-E, VN7040AJ-E
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VIN = 5 V; VSEn = 5 V;
MultiSense transition VSEL0 = 5 V;
tD_VCCtoCS
delay from VCC sense VSEL1 = 5 V to 0 V;
20
µs
to current sense
IOUT = 1.25 A;
RSENSE = 1 kΩ
VCC = 13 V; Tj = 125 °C;
VSEn = 5 V; VSEL1 = 5 V;
VSEL0 = 0 V to 5 V;
MultiSense transition
delay from TC sense
to VCC sense
tD_TCtoVCC
20
20
µs
µs
RSENSE = 1 kΩ
VCC = 13 V; Tj = 125 °C;
VSEn = 5 V; VSEL1 = 5 V;
MultiSense transition
delay from VCC sense
to TC sense
tD_VCCtoTC
V
SEL0 = 5 V to 0 V;
RSENSE = 1 kΩ
1. Parameter specified by design; not subject to production test.
2. All values refer to V = 13 V; T = 25°C, unless otherwise specified.
CC
j
3.
V
sensing and T are referred to GND potential.
CC C
4. Transition delay are measured up to +/- 10% of final conditions.
Figure 4. IOUT SENSE
/I
versus IOUT
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18/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Electrical specification
Figure 5. Current sense accuracy versus IOUT
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DocID022406 Rev 7
19/54
Electrical specification
VN7040AS-E, VN7040AJ-E
Figure 7. MultiSense timings (current sense mode)
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Figure 8. Multisense timings (chip temperature and VCC sense mode) (VN7040AJ-E
only)
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20/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Electrical specification
Figure 9. TDSTKON
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Table 10. Truth table
FR
SELX
Mode
Conditions INX
SEn
OUTX MultiSense
Comments
(1)
(1)
All logic
L
Low quiescent current
consumption
Standby
L
X
L
L
L
L
L
Hi-Z
inputs low
L
Nominal load
connected;
Outputs configured for
auto-restart
H
Refer to
Table 11
H
Refer to
Table 11
Normal
Tj < 150°C
H
Outputs configured for
Latch-off(1)
H
X
L
H
L
Overload or
short to GND
causing:
L
H
H
Output cycles with
temperature hysteresis
Refer to
Table 11
Refer to
Table 11
H
L
Overload
Tj > TTSD or
ΔTj > ΔTj_SD
H
Output latches-off(1)
Re-start when
VCC > VUSD +
VUSDhyst (rising)
VCC < VUSD
(falling)
L
L
Hi-Z
Hi-Z
Undervoltage
X
X
X
X
Short to VCC
Open-load
Inductive
L
L
X
X
H
H
OFF-state
diagnostics
Refer to
Table 11
Refer to
Table 11
External pull-up
Negative
Refer to
Table 11
Refer to
Table 11
L
X
< 0 V
output voltage loads turn-off
1. VN7040AJ only
DocID022406 Rev 7
21/54
Electrical specification
VN7040AS-E, VN7040AJ-E
Table 11. MultiSense multiplexer addressing
MultiSense output
MUX
channel
SEn SEL1 SEL0
OFF-state
diag.(1)
Negative
output
Nomal mode
SO-8
Overload
L
n.a. n.a. n.a.
Channel
Hi-Z
ISENSE
1/K * IOUT
=
VSENSE
VSENSEH
=
VSENSE =
VSENSEH
H
n.a. n.a.
Hi-Z
diagnostic
PowerSSO-16
ISENSE VSENSE
Channel
diagnostic
=
=
VSENSE
VSENSEH
=
H
H
L
L
L
Hi-Z
Hi-Z
1/K * IOUT VSENSEH
Channel
diagnostic
ISENSE
=
VSENSE
=
VSENSE
VSENSEH
=
H
1/K * IOUT VSENSEH
H
H
H
H
L
TCHIP Sense
VCC Sense
VSENSE = VSENSE_TC
VSENSE = VSENSE_VCC
H
1. In case the output channel corresponding to the selected MUX channel is latched off while the relevant
input is low, Multisense pin delivers feedback according to OFF-State diagnostic.
Example 1: FR = 1; IN = 0; OUT = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0
0
0
0
0
Example 2: FR = 1; IN = 0; OUT = latched, V
> V ; MUX channel = channel 0 diagnostic;
OUT0
OL
Mutisense = V
SENSEH
2.4
Waveforms
Figure 10. Latch functionality - behavior in hard short circuit condition (TAMB << TTSD
)
22/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Electrical specification
Figure 11. Latch functionality - behavior in hard short circuit condition
Figure 12. Latch functionality - behavior in hard short circuit condition (autorestart mode + latch
off)
DocID022406 Rev 7
23/54
Electrical specification
VN7040AS-E, VN7040AJ-E
Figure 13. Standby mode activation
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24/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Electrical specification
2.5
Electrical characteristics curves
Figure 15. OFF-state output current
Figure 16. Standby current
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Figure 20. High level logic input current
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DocID022406 Rev 7
25/54
Electrical specification
VN7040AS-E, VN7040AJ-E
Figure 21. Low level logic input current
Figure 22. Logic Input hysteresis voltage
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Figure 23. FaultRST Input clamp voltage
Figure 24. Undervoltage shutdown
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Figure 25. On-state resistance vs. Tcase
Figure 26. On-state resistance vs. VCC
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26/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Electrical specification
Figure 27. Turn-on voltage slope
Figure 28. Turn-off voltage slope
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Figure 29. Won vs. Tcase
Figure 30. Woff vs. Tcase
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Figure 31. ILIMH vs. Tcase
Figure 32. OFF-state open-load voltage
detection threshold
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DocID022406 Rev 7
27/54
Electrical specification
VN7040AS-E, VN7040AJ-E
Figure 33. Vsense clamp vs. Tcase
Figure 34. Vsenseh vs. Tcase
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28/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Protections
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as soon
as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the FaultRST
pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the
maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently,
reduces thermo-mechanical fatigue.
3.2
3.3
3.4
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon as
its junction temperature drops to TR (see Table 8, FaultRST = Low) or remains off (FaultRST
= High).
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as
the other components of the system (e.g. bonding wires, wiring harness, connectors, loads,
etc.) from excessive current flow. Consequently, in case of short circuit, overload or during
load power-up, the output current is clamped to a safety level, ILIMH, by operating the output
power MOSFET in the active region.
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain
value, VDEMAG (see Table 8), allowing the inductor energy to be dissipated without
damaging the device.
DocID022406 Rev 7
29/54
Application information
VN7040AS-E, VN7040AJ-E
4
Application information
Figure 35. Application diagram
+5V
VDD
OUT
OUT
OUT
OUT
ADC in
OUT
VCC
Rprot
Rprot
FaultRST
INPUT
Logic
Dld
Rprot
Rprot
SEn
SEL
OUTPUT
Rprot
Multisense
Currentmirror
GND
Cext
Rsense
R GND
D GND
GND
GND
GND
GND
GND
GND
4.1
GND protection network against reverse battery
Figure 36. Simplified internal structure
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30/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Application information
4.1.1
Diode (D
) in the ground line
GND
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device
only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns automatically
to normal operation after the test”.
Table 12. ISO 7637-2 - electrical transient conduction along supply line
Test pulse severity
Test
Pulse
Minimum
number of
pulses or test
time
level with Status II
functionalperformance
status
Burst cycle / pulse
repetition time
Pulse duration and
pulse generator
internal impedance
2011(E)
(1)
Level
US
min
max
1
III
III
IV
IV
IV
-112V
+55V
-220V
+150V
-7V
500 pulses
500 pulses
1h
0,5 s
0,2 s
2ms, 10Ω
50μs, 2Ω
2a
3a
3b
4(2)
5 s
90 ms
90 ms
100 ms
100 ms
0.1μs, 50Ω
0.1μs, 50Ω
100ms, 0.01Ω
1h
1 pulse
Load dump according to ISO 16750-2:2010
Test B(3)
40V
5 pulse
1 min
400ms, 2Ω
1.
U is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
S
2. Test pulse from ISO 7637-2:2004(E).
3. With 40 V external suppressor referred to ground (-40°C < T < 150°C).
j
DocID022406 Rev 7
31/54
Application information
VN7040AS-E, VN7040AJ-E
4.3
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
Equation 1
V
CCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20mA; VOHμC ≥ 4.5V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(Multisense) delivering the following signals:
•
•
•
Current monitor: current mirror of channel output current
CC monitor: voltage propotional to VCC
TCASE: voltage propotional to chip temperature
V
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in Table 11.
32/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Application information
Figure 37. Multisense and diagnostic – block diagram
Internal Supply
VCC – GND
Clamp
Undervoltage
shut-down
Control & Diagnostic
VCC – OUT
Clamp
FaultRST
INPUT
Gate Driver
VCC
T
SEL1
SEL0
SEn
VON
Limitation
VCC
Current
Limitation
MONITOR
ISENSE
Power Limitation
Overtemperature
Fault
Diagnostic
RPROT
MultiSense
TEMP
Temp
MONITOR
Short to VCC
To uC ADC
Open-Load in OFF
K factor
RSENSE
Current
Sense
CURRENT
IOUT
OUT
MONITOR
Fault
VSENSEH
GND
DocID022406 Rev 7
33/54
Application information
VN7040AS-E, VN7040AJ-E
4.4.1
Principle of Multisense signal generation
Figure 38. Multisense block diagram
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Current monitor
When current mode is selected in the Multisense, this output is capable to provide:
•
Current mirror proportional to the load current in normal operation, delivering
current proportional to the load according to known ratio named K
•
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation
can be done using simple equations
Current provided by Multisense output: ISENSE = IOUT/K
.
.
Voltage on RSENSE: VSENSE = RSENSE ISENSE = RSENSE IOUT/K
34/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Application information
Where :
•
•
•
•
VSENSE is voltage measurable on RSENSE resistor
I
SENSE is current provided from Multisense pin in current output mode
OUT is current flowing through output
I
K factor represent the ratio between PowerMOS cells and SenseMOS cells; its spread
includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between IOUT and ISENSE
.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the Multisense pin
which is switched to a “current limited” voltage source, VSENSEH (see Table 9).
In any case, the current sourced by the Multisense in this condition is limited to ISENSEH (see
Table 9).
The typical behavior in case of overload or hard short circuit is shown in Table 8, Table 9
and Table 10.
Figure 39. Analogue HSD – open-load detection in off-state
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DocID022406 Rev 7
35/54
Application information
VN7040AS-E, VN7040AJ-E
Figure 40. Open-load / short to VCC condition
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Table 13. Multisense pin levels in off-state
Condition
Output
Multisense
SEn
Hi-Z
VSENSEH
Hi-Z
L
H
L
VOUT > VOL
Open-load
VOUT < VOL
VOUT > VOL
VOUT < VOL
0
H
L
Hi-Z
Short to VCC
Nominal
VSENSEH
Hi-Z
H
L
0
H
4.4.2
T
and V monitor
CASE CC
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because of a
voltage shift is generated between device GND and the microcontroller input GND
reference.
Figure 41 shows link between VMEASURED and real VSENSE signal.
36/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Application information
Figure 41. GND voltage shift
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V
monitor
CC
Battery monitoring channel provides VSENSE = VCC / 4.
Case temperature monitor
Case temperature monitor is capable to provide information about actual device
temperature. Since diode is used for temperature sensing, following equation describe link
between temperature and output VSENSE level:
V
SENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40oC to +150oC).
4.4.3
Short to V and OFF-state open-load detection
CC
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
V
SENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU
.
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
R
PU must be selected in order to ensure VOUT > VOLmax in accordance with to following
equation:
Equation 2
V
– 4
PU
R
< -----------------------------------------
PU
I
L(off2)min @ 4V
DocID022406 Rev 7
37/54
Application information
VN7040AS-E, VN7040AJ-E
4.5
Maximum demagnetization energy (V = 13.5 V)
CC
Figure 42. Maximum turn off current versus inductance
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A: Tjstart = 150 °C single pulse
B
: Tjstart = 100 °C repetitive pulse
: Tjstart = 125 °C repetitive pulse
C
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
1. Values are generated with R = 0 Ω.
L
jstart
In case of repetitive pulses, T
(at the beginning of each demagnetization) of every pulse must not
exceed the temperature specified above for curves A and B.
38/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Package and PCB thermal data
5
Package and PCB thermal data
5.1
PowerSSO-16 thermal data
Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
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Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
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Table 14. PCB properties
Dimension
Value
Board finish thickness
Board dimension
Board Material
1.6 mm +/- 10%
77 mm x 86 mm
FR4
Copper thickness (top and bottom layers)
Copper thickness (inner layers)
Thermal vias separation
0.070 mm
0.035 mm
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
0.025 mm
Copper thickness on vias
Footprint dimension (top layer)
Heatsink copper area dimension (bottom layer)
2.2 mm x 3.9 mm
Footprint, 2 cm2 or 8 cm2
DocID022406 Rev 7
39/54
Package and PCB thermal data
VN7040AS-E, VN7040AJ-E
Figure 45. PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition
57+MDPE
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Equation 3: pulse calculation formula
Z
= R
⋅ δ + Z
(1 – δ)
THtp
THδ
TH
where δ = tP/T
40/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Package and PCB thermal data
Figure 47. Thermal fitting model for PowerSSO-16
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1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 15. Thermal parameters
Area/island (cm2)
R1 (°C/W)
Footprint
2
8
4L
2.3
1.8
7
R2 (°C/W)
R3 (°C/W)
7
6
7
6
5
4
3
7
R4 (°C/W)
14
R5 (°C/W)
30
20
20
10
18
R6 (°C/W)
26
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.00045
0.03
0.1
0.2
0.4
3
0.3
1
0.3
1
0.4
4
5
7
18
DocID022406 Rev 7
41/54
Package and PCB thermal data
VN7040AS-E, VN7040AJ-E
5.2
SO-8 thermal data
Figure 48. SO-8 on two-layers PCB (2s0p to JEDEC JESD 51-5)
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Figure 49. SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7)
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Table 16. PCB properties
Dimension
Value
Board finish thickness
Board dimension
Board Material
1.6 mm +/- 10%
77 mm x 86 mm
FR4
Copper thickness (top and bottom layers)
Copper thickness (inner layers)
Thermal vias separation
0.070 mm
0.035 mm
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
0.025 mm
Copper thickness on vias
Footprint dimension (top layer)
Heatsink copper area dimension (bottom layer)
2.2 mm x 3.9 mm
Footprint, 2 + 2 cm2 or 8 + 8 cm2
42/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Package and PCB thermal data
Figure 50. SO-8 Rthj-amb vs PCB copper area in open box free air condition
57+MDPE
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Equation 4: pulse calculation formula
Z
= R
⋅ δ + Z
(1 – δ)
THtp
THδ
TH
where δ = tP/T
DocID022406 Rev 7
43/54
Package and PCB thermal data
VN7040AS-E, VN7040AJ-E
Figure 52. Thermal fitting model for SO-8
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1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 17. Thermal parameters
Area/island (cm2)
R1 (°C/W)
Footprint
2.3
2
8
4L
R2 (°C/W)
2.5
R3 (°C/W)
10
R4 (°C/W)
28
17
12
23
17
9
17
4
R5 (°C/W)
24
R6 (°C/W)
30
19
9
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.0006
0.03
0.05
0.1
0.4
0.8
7
0.8
11
0.8
22
3
44/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Package information
6
Package information
®
6.1
ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.2
PowerSSO-16 package information
Figure 53. PowerSSO-16 package dimensions
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Table 18. PowerSSO-16 mechanical data
Millimeters
Typ.
Symbol
Min.
Max.
Θ
0°
0°
8°
Θ1
DocID022406 Rev 7
45/54
Package information
VN7040AS-E, VN7040AJ-E
Table 18. PowerSSO-16 mechanical data (continued)
Millimeters
Typ.
Symbol
Min.
Max.
Θ2
Θ3
A
5°
5°
15°
15°
1.70
0.10
1.65
0.30
0.30
0.25
0.23
A1
A2
b
0.00
1.10
0.20
0.20
0.19
0.19
b1
c
0.25
c1
D
0.20
4.9
D1
e
2.20
2.80
0.50
6.00
3.90
E
E1
E2
h
2.90
0.25
0.40
3.50
0.50
0.85
L
0.60
1.00
16
L1
N
R
0.7
0.7
R1
S
0.20
46/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Package information
6.3
SO-8 package information
Figure 54. SO-8 package dimensions
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DocID022406 Rev 7
47/54
Package information
VN7040AS-E, VN7040AJ-E
Table 19. SO-8 mechanical data
mm.
Dim.
Min.
Typ.
Max.
A
A1
A2
b
1.75
0.25
0.10
1.25
0.28
0.17
4.80
5.80
3.80
0.48
0.23
5.00
6.20
4.00
c
D
4.90
6.00
3.90
1.27
E
E1
e
h
0.25
0.40
0.50
1.27
L
L1
k
1.04
0°
8°
ccc
0.10
48/54
DocID022406 Rev 7
VN7040AS-E, VN7040AJ-E
Package information
6.4
Packing information
Figure 55. SO-8 tube shipment (no suffix)
Base q.ty
100
2000
532
3.2
%
&
$
Bulk q.ty
Tube length (± 0.5)
A
B
6
C (± 0.1)
0.6
All dimensions are in mm
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Figure 56. SO-8 tape and reel shipment (suffix “TR”)
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DocID022406 Rev 7
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Order codes
VN7040AS-E, VN7040AJ-E
7
Order codes
Table 20. Device summary
Order codes
Package
Tube
Tape and reel
VN7040AJTR-E
VN7040ASTR-E
PowerSSO-16
SO-8
VN7040AJ-E
VN7040AS-E
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Revision history
8
Revision history
Table 21. Document revision history
Changes
Date
Revision
26-Oct-2011
1
Initial release
Updated Features list
Updated Table 1: Pin functions
Table 3: Absolute maximum ratings:
– VCCPK, -IOUT, ISENSE, VESD: updated values
– VCCJS: added row
– VSENSE: removed row
Table 5: Power section:
– VUSDReset, IGND(ON): added row
– Vclamp: updated test conditions and values
Table 8: Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– ILIM, TR: added note
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– VSENSE_CL, KOL, KLED, dKLED/KLED, K0, dK0/K0, K1, dK1/K1, K2,
dK2/K2, K3, dK3/K3, ISENSE0, IL(off2), VSENSE_TC, VSENSE_VCC
VSENSEH, ISENSEH,: updated test condiions and values;
,
03-Oct-2012
2
– tDSENSE1H, tDSENSE1L, tDSENSE2H, tDSENSE2L, ΔtDSENSE2H
tDSENSE3L, tDSENSE3H, tDSENSE3L, tDSENSE4H, tDSENSE4L, tD_CStoTC
tD_TCtoCS, tD_CStoVCC, tD_VCCtoCS, tD_TCtoVCC, tD_VCCtoTC: updated
test condiions
,
,
– VOUT_MSD, VSENSE_SAT, ISENSE_SAT, IOUT_SAT, tD_OL_V: added rows
Updated Figure 6: Switching times and Pulse skew
Removed Figure: Pulse skew
Figure 9: TDSTKON
Uploaded Table 10: Truth table:
– Overload conditions updated
Table 11: MultiSense multiplexer addressing:
– Added note
Updated Section 2.4: Waveforms
Added Chapter 3: Protections and Chapter 4: Application information
Figure 39: Analogue HSD – open-load detection in off-state:
– X, Y: updated min and max values
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Revision history
VN7040AS-E, VN7040AJ-E
Table 21. Document revision history (continued)
Date
Revision
Changes
Updated Table 2: Suggested connections for unused and not
connected pins
Table 3: Absolute maximum ratings:
– ISENSE: updated value
Updated Table 4: Thermal data
Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless
otherwise specified):
– td(on): updated min value
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– dKcal/Kcal: added row
– VSENSE_CL, VSENSE_VCC: updated test conditions
– KLED, K0, K1, K2, K3, VSENSE_H: updated values
– tDSTKON: updated parameter
– VSENSE_TC, VSENSE_VCC: updated test conditions and values
Updated Table 11: MultiSense multiplexer addressing
Removed following tables:
06-Feb-2013
3
Table: Electrical transient requirements (part 1/3)
Table: Electrical transient requirements (part 2/3)
Table: Electrical transient requirements (part 3/3)
Updated Section 3.2: Thermal shutdown, Section 3.4: Negative
voltage clamp and Section 4.1.1: Diode (DGND) in the ground line
Removed Section: Load dump protection
Added Section 4.2: Immunity against transient electrical disturbances
and Section 4.5: Maximum demagnetization energy (VCC = 13.5 V)
Updated Figure 39: Analogue HSD – open-load detection in off-state
and Figure 41: GND voltage shift
Updated Table 13: Multisense pin levels in off-state
Updated Chapter 5: Package and PCB thermal data
Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless
otherwise specified):
15-Feb-2013
4
– WON, WOFF: updated typical and maximum value
Table 3: Absolute maximum ratings:
– VCCPK: updated parameter
– -IOUT: updated value
– EMAX: updated parameter and value
Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless
otherwise specified):
– WON, WOFF: updated typical and maximum values
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– KOL, KLED, K1, K2, K3: updated value
15-Mar-2013
5
Added Figure 4: IOUT/ISENSE versus IOUT and Figure 5: Current
sense accuracy versus IOUT
Added Section 2.5: Electrical characteristics curves
Updated Figure 42: Maximum turn off current versus inductance
Updated Section 6.2: PowerSSO-16 package information
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Revision history
Table 21. Document revision history (continued)
Revision Changes
Date
18-Sep-2013
6
7
Updated disclaimer.
Updated Section 6.2: PowerSSO-16 package information and
Section 6.3: SO-8 package information
26-May-2014
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VN7040AS-E, VN7040AJ-E
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