VND5T100LASTR-E [STMICROELECTRONICS]
Double channel high-side driver with analog current sense for 24 V automotive applications;
| 型号： | VND5T100LASTR-E |
| 厂家： | 
ST |
| 描述： | Double channel high-side driver with analog current sense for 24 V automotive applications |
| 文件： | 总38页 (文件大小：790K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND5T100LAJ-E
VND5T100LAS-E
Double channel high-side driver with analog current sense
for 24 V automotive applications
Datasheet - production data
Protection
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
SO-16N
PowerSSO-12
– Protection against loss of ground and loss
of V
CC
– Thermal shutdown
Features
– Electrostatic discharge protection
Max transient supply voltage
Operating voltage range
VCC
58 V
Application
VCC 8 to 36 V
All types of resistive, inductive and capacitive
loads
Typ on-state resistance (per ch.)
Current limitation (typ)
RON 100 m
ILIM
IS
22 A
2 µA(1)
Off-state supply current
Description
1. Typical value with all loads connected.
The VND5T100LAJ-E and VND5T100LAS-E are
monolithic devices made using
STMicroelectronics VIPower technology,
intended for driving resistive or inductive loads
AEC-Q100 qualified
®
®
General
with one side connected to ground. Active V
– Very low standby current
CC
pin voltage clamp protects the devices against
low energy spikes.
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
These devices integrate an analog current sense
which delivers a current proportional to the load
current.
– Compliant with European directive
2002/95/EC
– Fault reset standby pin (FR_Stby)
– Optimized for LED application
Fault conditions such as overload,
overtemperature or short to V are reported via
CC
the current sense pin.
Diagnostic functions
Output current limitation protects the devices in
overload condition. The devices latch off in case
of overload or thermal shutdown.
– Proportional load current sense
– High current sense precision for wide range
currents
– Off-state open-load detection
The devices are reset by a low level pass on the
fault reset standby pin.
– Output short to V detection
CC
– Overload and short to ground latch-off
– Thermal shutdown latch-off
A permanent low level on the inputs and fault
reset standby pin disables all outputs and sets the
devices in standby mode.
– Very low current sense leakage
August 2016
DocID023364 Rev 5
1/38
This is information on a product in full production.
www.st.com
Contents
VND5T100LAJ-E, VND5T100LAS-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1
3.1.2
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21
Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22
3.2
3.3
3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum demagnetization energy (VCC = 24 V) . . . . . . . . . . . . . . . . . . . 23
4
5
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
4.2
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SO-16N thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1
5.2
5.3
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SO-16N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1
6.2
PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SO-16N packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
8
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/38
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VND5T100LAJ-E, VND5T100LAS-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (V = 24 V; T = 25 °C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
j
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current sense (8 V < V < 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CC
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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3
List of figures
VND5T100LAJ-E, VND5T100LAS-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram PowerSSO-12 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagram SO-16N (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
T
T
definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
standby
reset
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Open-load off-state delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Output stuck to V detection delay time at FR
activation . . . . . . . . . . . . . . . . . . . . . 15
CC
STBY
Figure 11. Delay response time between rising edge of output current and rising
edge of current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. On-state resistance vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
case
Figure 21. On-state resistance vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CC
Figure 22.
I
vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LIMH
case
Figure 23. Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 26. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 27. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 28. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 24
Figure 29. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 25
Figure 30. Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 25
Figure 31. SO-16N PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 32.
R
vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . . 27
thj-amb
Figure 33. SO-16N thermal impedance junction ambient single pulse (one channel on) . . . . . . . . . . 28
Figure 34. Thermal fitting model of a double channel HSD in SO-16N . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 35. PowerSSO-12 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 36. SO-16N package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 37. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 38. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 39. SO-16N tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 40. SO-16N tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
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Table 1. Pin function
Function
Name
VCC
OUTn
GND
Battery connection
Power output
Ground connection
Voltage controlled input pin with hysteresis, CMOS compatible. It controls output
switch state
INn
CSn
Analog current sense pin, it delivers a current proportional to the load current
In case of latch-off for overtemperature/overcurrent condition, a low pulse on the
FR_Stby pin is needed to reset the channel.
FR_Stby
The device enters in standby mode if all inputs and the FR_Stby pin are low.
DocID023364 Rev 5
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37
Block diagram and pin description
VND5T100LAJ-E, VND5T100LAS-E
Figure 2. Configuration diagram PowerSSO-12 (top view)
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Figure 3. Configuration diagram SO-16N (top view)
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Table 2. Suggested connections for unused and not connected pins
Connection / pin Current sense
N.C.
Output
Input
FR_Stby
Floating
To ground
Not allowed
X(1)
X
X
X
Through10 K
Through
10 Kresistor 10 Kresistor
Through
X
Not allowed
resistor
1. X: do not care.
6/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Electrical specifications
2
Electrical specifications
Figure 4. Current and voltage conventions
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2.1
Absolute maximum ratings
Stressing the device above the ratings listed in Table 3 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions reported in this section for extended periods may affect device
reliability.
Table 3. Absolute maximum ratings
Symbol
VCC
Parameter
Value
Unit
V
DC supply voltage
58
0.3
-VCC
-IGND
IOUT
Reverse DC supply voltage
DC reverse ground pin current
DC output current
V
200
mA
A
Internally limited
20
-IOUT
IIN
Reverse DC output current
DC input current
A
-1 to 10
-1 to 1.5
200
mA
mA
mA
IFR_Stby Fault reset standby DC input current
-ICSENSE DC reverse CS pin current
VCC - 58 to
+VCC
VCSENSE Current sense maximum voltage
V
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37
Electrical specifications
Symbol
VND5T100LAJ-E, VND5T100LAS-E
Table 3. Absolute maximum ratings (continued)
Parameter
Value
Unit
Maximum switching energy
(L = 1.9 mH; Vbat = 32 V; Tjstart = 150°C; IOUT = IlimL (Typ))
EMAX
70
mJ
Electrostatic discharge
(Human Body Model: R = 1.5 K C = 100 pF)
– INPUT
4000
2000
4000
5000
5000
V
V
V
V
V
VESD
– CURRENT SENSE
– FR_STBY
– OUTPUT
– VCC
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
750
V
-40 to 150
-55 to 150
°C
°C
Tstg
Maximum stray inductance in short circuit
LSmax
40
µH
RL = 300 m, Vbat = 32 V, Tjstart = 150°C, IOUT = IlimHmax
2.2
Thermal data
Table 4. Thermal data
Parameter
Maximum value
Symbol
Unit
PowerSSO-12
SO-16N
Thermal resistance junction-case (with one
channel ON)
Rthj-case
Rthj-pin
6
—
°C/W
°C/W
Thermal resistance junction-pin (with one
channel ON)
—
26
Rthj-amb Thermal resistance junction-ambient
See Figure 28
See Figure 32 °C/W
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DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Electrical specifications
2.3
Electrical characteristics
8 V < V < 36 V; -40°C < T < 150°C, unless otherwise specified.
CC
j
.
Table 5. Power section
Test conditions
Symbol
Parameter
Operating supply voltage
Min. Typ. Max. Unit
VCC
8
24
36
5
V
V
VUSD Undervoltage shutdown
3.5
Undervoltage shutdown
hysteresis
VUSDhyst
0.5
V
IOUT = 1.5 A; Tj = 25°C
IOUT = 1.5 A; Tj = 150°C
IS = 20 mA
100
RON
On-state resistance(1)
m
200
70
Vclamp Clamp voltage
58
64
V
Off-state: VCC = 24 V; Tj = 25°C;
VIN = VOUT = VSENSE = 0 V
2(2)
5(2)
µA
IS
Supply current
On-state: VCC = 24 V; VIN = 5 V;
IOUT = 0 A
4.2
6
mA
V
IN = VOUT = 0 V; VCC = 24 V;
0
0
0.01
3
Tj = 25°C
IL(off)
Off-state output current
µA
V
VIN = VOUT = 0 V; VCC = 24 V;
Tj = 125°C
5
VF
Output - VCC diode voltage -IOUT = 1.5 A; Tj = 150°C
0.7
1. For each channel.
2. PowerMos leakage included
Table 6. Switching (V = 24 V; T = 25 °C)
CC
j
Symbol
Parameter
Test conditions
RL = 16
Min. Typ. Max. Unit
td(on)
td(off)
Turn-on delay time
Turn-off delay time
27
38
µs
µs
RL = 16
RL = 16
RL = 16
dVOUT/dt(on) Turn-on voltage slope
dVOUT/dt(off) Turn-off voltage slope
1
Vµs
Vµs
0.65
Switching energy losses
during twon
WON
RL = 16
RL = 16
0.23
0.26
mJ
mJ
Switching energy losses
during twoff
WOFF
Table 7. Logic inputs
Test conditions
Symbol
Parameter
Min. Typ. Max. Unit
VIL
IIL
Input low level voltage
Low level input current
Input high level voltage
0.9
V
µA
V
VIN = 0.9 V
1
VIH
2.1
DocID023364 Rev 5
9/38
37
Electrical specifications
Symbol
VND5T100LAJ-E, VND5T100LAS-E
Table 7. Logic inputs (continued)
Parameter
Test conditions
VIN = 2.1 V
Min. Typ. Max. Unit
IIH
High level input current
Input hysteresis voltage
10
µA
V
VI(hyst)
0.25
5.5
I
IN = 1 mA
7
V
VICL
Input clamp voltage
IIN = -1 mA
-0.7
V
Fault_reset_standby low level
voltage
VFR_Stby_L
IFR_Stby_L
VFR_Stby_H
IFR_Stby_H
0.9
V
µA
V
Low level fault_reset_standby
current
VFR_Stby = 0.9 V
1
Fault_reset_standby high
level voltage
2.1
High level fault_reset_standby
current
VFR_Stby = 2.1 V
10
µA
V
Fault_reset_standby
hysteresis voltage
VFR_Stby (hyst)
0.25
11
IFR_Stby = 15 mA
15
24
V
Fault_reset_standby clamp
voltage
(t < 10 ms)
VFR_Stby_CL
IFR_Stby = -1 mA
See Figure 5
See Figure 6
-0.7
V
treset
tstby
Overload latch-off reset time
Standby delay
2
µs
120
1200 µs
Figure 5. T
definition
standby
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10/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Electrical specifications
Figure 6. T
definition
reset
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Table 8. Protections and diagnostics
Symbol
Parameter
Test conditions
CC = 24 V
Min.
Typ.
Max.
Unit
V
16
22
30
30
A
A
IlimH
DC short circuit current
5 V < VCC < 36 V
Short circuit current
during thermal cycling
VCC = 24 V;
TR < Tj < TTSD
IlimL
6
A
TTSD
TR
Shutdown temperature
Reset temperature
150
175
200
°C
°C
°C
TRS + 1 TRS + 5
135
TRS
Thermal reset of status
Thermal hysteresis
(TTSD - TR)
THYST
VDEMAG
VON
7
°C
V
Turn-off output voltage
clamp
IOUT = 1.5 A; VIN = 0;
L = 6 mH
V
CC - 58 VCC - 64 VCC - 70
Output voltage drop
limitation
IOUT = 50 mA;
Tj = -40°C to 150°C
25
mV
DocID023364 Rev 5
11/38
37
Electrical specifications
VND5T100LAJ-E, VND5T100LAS-E
Table 9. Current sense (8 V < V < 36 V)
CC
Symbol
Parameter
IOUT/ISENSE
IOUT/ISENSE
Test conditions
Min. Typ. Max. Unit
IOUT = 12 mA; VSENSE = 0.5 V;
Tj = -40°C to 150°C
KOL
833
IOUT = 50 mA; VSENSE = 0.5 V;
Tj = -40°C to 150°C
KLED
dKLED/KLED(TOT)
K0
1328 2190 3332
IOUT = 12 mA to 25 mA;
ICAL = 18 mA; VSENSE = 0.5 V; -30
Tj = -40°C to 150°C
Current sense ratio
drift
(1)
30
%
IOUT = 100 mA; VSENSE = 0.5 V;
Tj = -40°C to 150°C
IOUT SENSE
/I
1170 1950 2730
Current sense ratio IOUT = 100 mA; VSENSE = 0.5 V;
(1)
dK0/K0
-18
1259 1740 2191
-15 15
1372 1730 2058
-12 12
1509 1720 1921
-8
1646 1720 1784
18
%
%
%
%
drift
IOUT SENSE
Tj = -40°C to 150°C
IOUT = 0.4 A; VSENSE = 1 V;
Tj = -40°C to 150°C
K1
/I
Current sense ratio IOUT = 0.4 A; VSENSE = 1 V;
(1)
dK1/K1
drift
Tj = -40°C to 150°C
IOUT = 0.8 A; VSENSE = 2 V;
Tj = -40°C to 150°C
K2
IOUT SENSE
/I
Current sense ratio IOUT = 0.8 A; VSENSE = 2 V;
(1)
dK2/K2
drift
Tj = -40°C to 150°C
IOUT = 1.6 A; VSENSE = 2 V;
Tj = -40°C to 150°C
K3
IOUT SENSE
/I
Current sense ratio IOUT = 1.6 A; VSENSE = 2 V;
(1)
dK3/K3
8
drift
Tj = -40°C to 150°C
IOUT = 6 A; VSENSE = 4 V;
Tj = -40°C to 150°C
K4
IOUT SENSE
/I
Current sense ratio IOUT = 6 A; VSENSE = 4 V;
(1)
dK4/K4
-4
0
4
1
2
%
µA
µA
V
drift
Tj = -40°C to 150°C
IOUT = 0 A; VSENSE = 0 V;
VIN = 0 V; Tj = -40 °C to 150 °C
Analog sense
ISENSE0
leakage current
I
V
OUT = 0 A; VSENSE = 0 V;
IN = 5 V; Tj = -40 °C to 150 °C
0
Max analog sense
output voltage
VSENSE
IOUT = 6 A; RSENSE = 3.9 K
VCC = 24 V; RSENSE = 3.9 K
5
Analog sense
VSENSEH
output voltage in
7.5
4.9
8.5 9.5
V
fault condition(2)
Analog sense
ISENSEH
output current in
VCC = 24 V; VSENSE = 5 V
9
12 mA
fault condition(2)
VSENSE < 4 V;
0.07 A < IOUT < 6 A;
ISENSE = 90 % of ISENSE max
Delay response
time from rising
edge of INPUT pin
tDSENSE2H
100 200 µs
(see Figure 7)
12/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Electrical specifications
Table 9. Current sense (8 V < V < 36 V) (continued)
CC
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Delay response
time between
rising edge of
VSENSE < 4 V;
ISENSE = 90 % of ISENSEMAX
;
tDSEN
150 µs
SE2H
output current and IOUT = 90 % of IOUTMAX
;
rising edge of
current sense
IOUTMAX = 1.5 A (see Figure 12)
V
SENSE < 4 V;
Delay response
time from falling
edge of INPUT pin
0.07 A < IOUT < 6 A;
ISENSE = 10 % of ISENSE max
tDSENSE2L
5
20
µs
(see Figure 7)
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, overtemperature and open-load in OFF-state condition.
Table 10. Open-load detection
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
Open-load off-state
voltage detection
threshold
VIN = 0 V; 8 V < VCC < 36 V;
FR_STBY = 5 V
VOL
2
—
4
1800
50
V
Output short circuit to
tDSTKON VCC detection delay at
turn off
See Figure 7;
FR_STBY = 5 V
180
—
—
—
µs
µs
µA
Output short circuit to
tDFRSTK_ON VCC detection delay at
FRSTBY activation
See Figure 10;
Input1,2 = low
VIN = 0 V; VSENSE = 0 V;
VOUT rising from 0 V to 4 V;
FR_STBY = 5 V
Off-state output current
at VOUT = 4V
IL(off2)
-120
0
Delay response from
VOUT = 4 V; VIN = 0 V;
output rising edge to
VSENSE rising edge in
VSENSE = 90 % of VSENSEH;
RSENSE = 3.9 K
td_vol
—
20
µs
open-load
FR_STBY = 5 V
Figure 7. Current sense delay characteristics
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DocID023364 Rev 5
13/38
37
Electrical specifications
VND5T100LAJ-E, VND5T100LAS-E
Figure 8. Open-load off-state delay timing
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14/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Electrical specifications
Figure 10. Output stuck to V detection delay time at FR
activation
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DocID023364 Rev 5
15/38
37
Electrical specifications
VND5T100LAJ-E, VND5T100LAS-E
Figure 12. Output voltage drop limitation
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16/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Electrical specifications
Table 11. Truth table
Fault reset standby
Conditions
Input
Output
Sense
Standby
L
L
L
0
X
X
L
L
0
Normal operation
Overload
H
H
Nominal
X
X
L
L
0
H
H
> Nominal
X
L
L
H
H
L
0
Overtemperature / short to ground
Undervoltage
Cycling
Latched
VSENSEH
VSENSEH
H
X
X
L
0
L
H
X
L
L
H
H
H
0
Short to VBAT
VSENSEH
< Nominal
H
L
H
X
L
L
H
H
H
0
VSENSEH
0
Open-load off-state (with pull-up)
Negative output voltage clamp
H
X
L
Negative
0
DocID023364 Rev 5
17/38
37
Electrical specifications
VND5T100LAJ-E, VND5T100LAS-E
Table 12. Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
Test levels (1)
Number of
pulses or test
times
Burst cycle/pulse
repetition time
Delays and
impedance
III
IV
Test pulse
1
2a
- 450 V
+ 37 V
- 150 V
+ 150 V
- 12 V
- 600 V
+ 50 V
- 200 V
+ 200 V
- 16 V
5000 pulses
5000 pulses
1h
0.5 s
0.2 s
5 s
1 ms, 50
50 µs, 2
5 s
3a
90 ms
90 ms
100 ms
100 ms
0.1 µs, 50
0.1 µs, 50
100 ms, 0.01
350 ms, 1
3b
1h
4
1 pulse
1 pulse
5b (2)
+ 123 V
+ 174 V
Table 13. Electrical transient requirements (part 2)
Test level results
ISO 7637-2:
2004(E)
III
IV
Test pulse
1
2a
C
C
C
E
C
C
C
C
C
C
E
C
C
C
3a
3b(1)
3b(2)
4
5b (3)
1. Without capacitor between VCC and GND.
2. With 10 nF between VCC and GND.
3. External load dump clamp, 58 V maximum, referred to ground.
Table 14. Electrical transient requirements (part 3)
Contents
Class
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure
to disturbance and cannot be returned to proper operation without replacing the
E
18/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Electrical specifications
2.4
Electrical characteristics curves
Figure 14. Off-state output current
Figure 15. High level input current
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Figure 17. Input high level voltage
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Figure 19. Input hysteresis voltage
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DocID023364 Rev 5
19/38
37
Electrical specifications
VND5T100LAJ-E, VND5T100LAS-E
Figure 20. On-state resistance vs T
Figure 21. On-state resistance vs V
CC
case
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Figure 23. Turn-on voltage slope
LIMH
case
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Figure 24. Turn-off voltage slope
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20/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Application information
3
Application information
Figure 25. Application schematic
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3.1
GND protection network against reverse battery
3.1.1
Solution 1: resistor in the ground line (R
only)
GND
This solution can be used with any type of load.
The following is an indication on how to select the R
resistor.
GND
1.
2.
R
R
600 mV / (I
).
S(on)max
GND
GND
V ) / (-I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power dissipation in R
(when V < 0: during reverse battery situations) is:
CC
GND
2
P = (-V ) / R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
Please note that if the microprocessor ground is not shared by the device ground then the
produces a shift (I * R ) in the input thresholds and the status output
R
GND
S(on)max
GND
values. This shift varies depending on how many devices are ON in case of several high
side drivers sharing the same R
.
GND
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests Solution 2 is used (see below).
DocID023364 Rev 5
21/38
37
Application information
VND5T100LAJ-E, VND5T100LAS-E
3.1.2
Solution 2: diode (D
) in the ground line
GND
A resistor (R
= 4.7 kshould be inserted in parallel to D if the device drives an
GND
GND
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (600 mV) in the input threshold
and in the status output values, if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
3.2
3.3
Load dump protection
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to
ld
V
max DC rating. The same applies if the device is subject to transients on the V line
CC
CC
that are greater than the ones shown in the ISO T/R 7637/2 table.
MCUI/Os protection
If a ground protection network is used and negative transient are present on the V line,
CC
the control pins are pulled negative. ST suggests that a resistor (R ) be inserted in line to
prot
prevent the microcontroller I/O pins from latching-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-V
/I
R
(V
-V -V
) / I
CCpeak latchup
prot
OHC IH GND IHmax
Calculation example:
For V = -600 V and I
20 mA; V 4.5 V
OHC
CCpeak
latchup
30 k R
180 k.
prot
Recommended R
value is 60 k
prot
22/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Application information
3.4
Maximum demagnetization energy (VCC = 24 V)
Figure 26. Maximum turn-off current versus inductance
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A
B
C
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/ĆꢌP+ꢎ
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A: T
= 150°C single pulse
jstart
B: T
C: T
= 100°C repetitive pulse
= 125°C repetitive pulse
jstart
jstart
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
1. Values are generated with RL =0 .
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not
exceed the temperature specified above for curves A and B.
DocID023364 Rev 5
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37
Package and PCB thermal data
VND5T100LAJ-E, VND5T100LAS-E
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 27. PowerSSO-12 PC board
*$3*&)7ꢆꢆꢆꢃꢂꢆ
.
1. Layout condition of Rth and Zth measurements (Board finish thickness 1.6 mm +/- 10 %; Board double
layer; Board dimension 77 mm x 86 mm; Board Material FR4; Cu thickness 0.070 mm (front and back
side); Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias
0.025 mm; Footprint dimension 4.1 mm x 6.5 mm)
Figure 28.
R
vs PCB copper area in open box free air condition (one channel ON)
thj-amb
RTHjamb
65
60
55
50
45
40
35
30
RTHjamb
0
2
4
6
8
10
GAPGCFT000124
24/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Package and PCB thermal data
Figure 29. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel ON)
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Figure 30. Thermal fitting model of a double channel HSD in PowerSSO-12
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1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Equation 1: pulse calculation formula
ZTH = RTH + ZTHtp1 –
= tp T
where
DocID023364 Rev 5
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37
Package and PCB thermal data
VND5T100LAJ-E, VND5T100LAS-E
Table 15. Thermal parameters
Area/island (cm2)
Footprint
0.8
2
8
R1 = R7 (°C/W)
R2 = R8 (°C/W)
R3 (°C/W)
1.5
3
R4 (°C/W)
8
8
7
R5 (°C/W)
22
15
20
10
15
R6 (°C/W)
26
C1 = C7 (W.s/°C)
C2 = C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.0008
0.005
0.05
0.2
0.1
0.8
6
0.1
1
0.27
3
9
26/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Package and PCB thermal data
4.2
SO-16N thermal data
Figure 31. SO-16N PC board
("1(ꢉꢈꢉꢃꢀꢃꢀꢁꢉꢉ$'5
1. Layout condition of Rth and Zth measurements (Board finish thickness 1.6 mm +/- 10%; Board double
layer; Board dimension 129 x 60; Board Material FR4; Cu thickness 0.070mm (front and back side),
Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025
mm).
Figure 32. R
vs PCB copper area in open box free air condition (one channel
ON)
thj-amb
57+MDPE
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DocID023364 Rev 5
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37
Package and PCB thermal data
VND5T100LAJ-E, VND5T100LAS-E
Figure 33. SO-16N thermal impedance junction ambient single pulse (one channel on)
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Figure 34. Thermal fitting model of a double channel HSD in SO-16N
("1(ꢉꢈꢉꢃꢀꢃꢀꢁꢀꢇ$'5
Equation 2: pulse calculation formula
ZTH = RTH + ZTHtp1 –
= tp T
where
28/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Package and PCB thermal data
Table 16. Thermal parameters
Area/island (cm2)
R1 = R7 (°C/W)
R2 = R8(°C/W)
R3 (°C/W)
Footprint
0.8
2
8
3
6
R4 (°C/W)
10
R5 (°C/W)
20
14
23
12
14
R6 (°C/W)
27
C1 = C7(W.s/°C)
C2 = C8 (W.s/°C)
C3 (W.s/°C)
0.0005
0.005
0.015
0.1
C4 (W.s/°C)
C5 (W.s/°C)
0.3
0.5
5
0.5
7
C6 (W.s/°C)
2.5
DocID023364 Rev 5
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37
Package and packing information
VND5T100LAJ-E, VND5T100LAS-E
5
Package and packing information
5.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
5.2
PowerSSO-12 mechanical data
Figure 35. PowerSSO-12 package dimensions
("1(ꢉꢄꢉꢀꢀꢅꢀꢉꢂꢁ$'5
30/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Package and packing information
Table 17. PowerSSO-12 mechanical data
Millimeters
Typ.
Symbol
Min.
Max.
A
A1
A2
B
1.250
0.000
1.100
0.230
0.190
4.800
3.800
1.700
0.100
1.600
0.410
0.250
5.000
4.000
C
D
E
e
0.800
H
5.800
0.250
0.400
0°
6.200
0.550
1.270
8°
h
L
k
X
1.900
3.600
2.500
4.200
0.100
Y
ddd
DocID023364 Rev 5
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37
Package and packing information
VND5T100LAJ-E, VND5T100LAS-E
5.3
SO-16N package information
Figure 36. SO-16N package dimensions
("1(ꢉꢈꢉꢃꢀꢃꢀꢁꢁꢂ$'5
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DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Package and packing information
Table 18. SO-16N mechanical data
Millimeters
Typ.
Symbol
Min.
Max.
1.75
0.25
A
A1
A2
b
0.10
1.25
0.31
017
0.51
0.25
10.00
6.20
4.00
c
D
9.80
5.80
3.80
9.90
6.00
3.90
1.27
E
E1
e
h
0.25
0.40
0°
0.50
1.27
8°
L
k
ccc
0.10
DocID023364 Rev 5
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37
Packing information
VND5T100LAJ-E, VND5T100LAS-E
6
Packing information
6.1
PowerSSO-12 packing information
Figure 37. PowerSSO-12 tube shipment (no suffix)
All dimensions are in mm.
B
C
Base q.ty
100
2000
532
Bulk q.ty
Tube length (± 0.5)
A
B
1.85
6.75
0.6
A
C (± 0.1)
GA P GCFT000123
Figure 38. PowerSSO-12 tape and reel shipment (suffix “TR”)
Reel dimensions
Base q.ty
Bulk q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
12
4
8
1.5
1.5
5.5
4.5
2
Tape hole spacing
Component spacing
Hole diameter
Hole diameter
Hole position
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
Compartment depth
Hole spacing
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
34/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Packing information
6.2
SO-16N packing information
Figure 39. SO-16N tube shipment (no suffix)
Base q.ty
50
1000
532
3.2
6
Bulk q.ty
B
C
Tube length (± 0.5)
A
B
A
C (± 0.1)
0.6
All dimensions are in mm.
Figure 40. SO-16N tape and reel shipment (suffix “TR”)
.REEL DIMENSIONS
Base q.ty
Bulk q.ty
A (max)
B (min)
C (± 0.2)
F
1000
1000
330
1.5
13
20.2
16.4
60
G (+ 2 / -0)
N (min)
T (max)
22.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
W
P0 (± 0.1)
P
16
4
Tape hole spacing
Component spacing
Hole diameter
8
D (± 0.1/-0) 1.5
Hole diameter
D1 (min)
F (± 0.05)
K (max)
1.5
7.5
6.5
2
Hole position
Compartment depth
Hole spacing
P1 (± 0.1)
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
cover
tape
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
DocID023364 Rev 5
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37
Order code
VND5T100LAJ-E, VND5T100LAS-E
7
Order code
Table 19. Device summary
Order codes
Package
Tube
Tape and reel
PowerSSO-12
SO-16N
VND5T100LAJ-E
VND5T100LAS-E
VND5T100LAJTR-E
VND5T100LASTR-E
36/38
DocID023364 Rev 5
VND5T100LAJ-E, VND5T100LAS-E
Revision history
8
Revision history
Table 20. Document revision history
Changes
Date
Revision
25-Jun-2012
18-Sep-2013
30-Apr-2014
1
2
3
Initial release.
Updated disclaimer.
Added SO-16N package and related details.
Table 4: Thermal data:
– Rthj-case: updated values
– Rthj-pin: added row
08-Feb-2016
23-Aug-2016
4
5
Updated Section 5.2: PowerSSO-12 mechanical data and
Section 5.3: SO-16N package information
Added indication of AEC-Q100 qualification in Features.
Updated Figure 3: Configuration diagram SO-16N (top view).
DocID023364 Rev 5
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37
VND5T100LAJ-E, VND5T100LAS-E
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
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