VND7140AJ [STMICROELECTRONICS]
Double channel high-side driver with MultiSense analog feedback for automotive applications;型号: | VND7140AJ |
厂家: | ST |
描述: | Double channel high-side driver with MultiSense analog feedback for automotive applications |
文件: | 总47页 (文件大小:2389K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
VND7140AJ
Double channel high-side driver with MultiSense analog
feedback for automotive applications
Datasheet - production data
Loss of ground and loss of VCC
Reverse battery with external
components
Electrostatic discharge protection
Applications
All types of automotive resistive, inductive
and capacitive loads
Features
Max transient supply voltage
Operating voltage range
Typ. on-state resistance (per Ch)
Current limitation (typ)
VCC
VCC
40 V
4 to 28 V
140 mΩ
12 A
Specially intended for automotive signal
lamps (up to R10W or LED Rear
Combinations)
RON
ILIMH
ISTBY
Description
Standby current (max)
0.5 µA
The device is a double channel high-side driver
manufactured using ST proprietary VIPower®
M0-7 technology and housed in PowerSSO-16
package. The device is designed to drive 12 V
automotive grounded loads through a 3 V and
5 V CMOS-compatible interface, providing
protection and diagnostics.
AEC-Q100 qualified
General
Double channel smart high-side driver
with MultiSense analog feedback
Very low standby current
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
Compatible with 3 V and 5 V CMOS
outputs
MultiSense diagnostic functions
Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
TCHIP device temperature
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
Overload and short to ground (power
limitation) indication
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load.
Thermal shutdown indication
OFF-state open-load detection
Output short to VCC detection
Sense enable/disable
Protections
Undervoltage shutdown
Overvoltage clamp
Load current limitation
Self limiting of fast thermal transients
Configurable latch-off on
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
overtemperature or power limitation
with dedicated fault reset pin
October 2016
DocID027398 Rev 2
1/47
www.st.com
This is information on a product in full production.
Contents
VND7140AJ
Contents
1
2
Block diagram and pin description................................................5
Electrical specification....................................................................7
2.1
2.2
2.3
2.4
2.5
Absolute maximum ratings................................................................7
Thermal data.....................................................................................8
Main electrical characteristics ...........................................................8
Waveforms......................................................................................20
Electrical characteristics curves ......................................................23
3
4
Protections.....................................................................................27
3.1
3.2
3.3
3.4
Power limitation...............................................................................27
Thermal shutdown...........................................................................27
Current limitation.............................................................................27
Negative voltage clamp...................................................................27
Application information ................................................................28
4.1
GND protection network against reverse battery.............................28
4.1.1
Diode (DGND) in the ground line ..................................................... 29
4.2
4.3
4.4
Immunity against transient electrical disturbances..........................29
MCU I/Os protection........................................................................30
Multisense - analog current sense ..................................................30
4.4.1
4.4.2
4.4.3
Principle of Multisense signal generation......................................... 32
TCASE and VCC monitor................................................................. 34
Short to VCC and OFF-state open-load detection ........................... 35
5
6
Maximum demagnetization energy (VCC = 16 V)........................36
Package and PCB thermal data....................................................37
6.1
PowerSSO-16 thermal data ............................................................37
7
Package information .....................................................................40
7.1
7.2
7.3
PowerSSO-16 package information................................................40
PowerSSO-16 packing information .................................................42
PowerSSO-16 marking information.................................................44
8
9
Order codes ...................................................................................45
Revision history ............................................................................46
2/47
DocID027398 Rev 2
VND7140AJ
List of tables
List of tables
Table 1: Pin functions .................................................................................................................................5
Table 2: Suggested connections for unused and not connected pins........................................................6
Table 3: Absolute maximum ratings ...........................................................................................................7
Table 4: Thermal data.................................................................................................................................8
Table 5: Power section ...............................................................................................................................9
Table 6: Switching.....................................................................................................................................10
Table 7: Logic inputs.................................................................................................................................10
Table 8: Protections..................................................................................................................................11
Table 9: MultiSense ..................................................................................................................................12
Table 10: Truth table.................................................................................................................................19
Table 11: MultiSense multiplexer addressing...........................................................................................20
Table 12: ISO 7637-2 - electrical transient conduction along supply line.................................................29
Table 13: MultiSense pin levels in off-state ..............................................................................................34
Table 14: PCB properties .........................................................................................................................37
Table 15: Thermal parameters .................................................................................................................39
Table 16: PowerSSO-16 mechanical data................................................................................................40
Table 17: Reel dimensions .......................................................................................................................42
Table 18: PowerSSO-16 carrier tape dimensions ....................................................................................43
Table 19: Device summary.......................................................................................................................45
Table 20: Document revision history ........................................................................................................46
DocID027398 Rev 2
3/47
List of figures
VND7140AJ
List of figures
Figure 1: Block diagram..............................................................................................................................5
Figure 2: Configuration diagram (top view).................................................................................................6
Figure 3: Current and voltage conventions.................................................................................................7
Figure 4: IOUT/ISENSE versus IOUT.......................................................................................................16
Figure 5: Current sense accuracy versus IOUT .......................................................................................17
Figure 6: Switching time and Pulse skew .................................................................................................17
Figure 7: MultiSense timings (current sense mode).................................................................................18
Figure 8: Multisense timings (chip temperature and VCC sense mode) ..................................................18
Figure 9: TDSTKON..................................................................................................................................19
Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ......................20
Figure 11: Latch functionality - behavior in hard short circuit condition....................................................21
Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off)....21
Figure 13: Standby mode activation .........................................................................................................22
Figure 14: Standby state diagram.............................................................................................................22
Figure 15: OFF-state output current .........................................................................................................23
Figure 16: Standby current .......................................................................................................................23
Figure 17: IGND(ON) vs. Iout ...................................................................................................................23
Figure 18: Logic Input high level voltage ..................................................................................................23
Figure 19: Logic Input low level voltage....................................................................................................23
Figure 20: High level logic input current ...................................................................................................23
Figure 21: Low level logic input current ....................................................................................................24
Figure 22: Logic Input hysteresis voltage .................................................................................................24
Figure 23: FaultRST Input clamp voltage .................................................................................................24
Figure 24: Undervoltage shutdown...........................................................................................................24
Figure 25: On-state resistance vs. Tcase.................................................................................................24
Figure 26: On-state resistance vs. VCC ...................................................................................................24
Figure 27: Turn-on voltage slope..............................................................................................................25
Figure 28: Turn-off voltage slope..............................................................................................................25
Figure 29: Won vs. Tcase.........................................................................................................................25
Figure 30: Woff vs. Tcase.........................................................................................................................25
Figure 31: ILIMH vs. Tcase.......................................................................................................................25
Figure 32: OFF-state open-load voltage detection threshold ...................................................................25
Figure 33: Vsense clamp vs. Tcase..........................................................................................................26
Figure 34: Vsenseh vs. Tcase ..................................................................................................................26
Figure 35: Application diagram.................................................................................................................28
Figure 36: Simplified internal structure .....................................................................................................28
Figure 37: MultiSense and diagnostic – block diagram............................................................................31
Figure 38: MultiSense block diagram .......................................................................................................32
Figure 39: Analogue HSD – open-load detection in off-state ...................................................................33
Figure 40: Open-load / short to VCC condition.........................................................................................34
Figure 41: GND voltage shift ....................................................................................................................35
Figure 42: Maximum turn off current versus inductance ..........................................................................36
Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)............................................37
Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ...........................................37
Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on) .....................38
Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) ..............38
Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16..........................................39
Figure 48: PowerSSO-16 package outline ...............................................................................................40
Figure 49: PowerSSO-16 reel 13" ............................................................................................................42
Figure 50: PowerSSO-16 carrier tape ......................................................................................................43
Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape ..................................................43
Figure 52: PowerSSO-16 marking information.........................................................................................44
4/47
DocID027398 Rev 2
VND7140AJ
Block diagram and pin description
1
Block diagram and pin description
Figure 1: Block diagram
Table 1: Pin functions
Function
Name
VCC
Battery connection.
OUTPUT0,1 Power output.
Ground connection. Must be reverse battery protected by an external diode / resistor
network.
GND
INPUT0,1
MultiSense
SEn
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS
outputs. It controls output switch state.
Multiplexed analog sense output pin; it delivers a current proportional to the selected
diagnostic: load current, supply voltage or chip temperature.
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense
diagnostic pin.
Active high compatible with 3 V and 5 V CMOS outputs pin; they address the
MultiSense multiplexer.
SEL0,1
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in
case of fault; If kept low, sets the outputs in auto-restart. mode
FaultRST
DocID027398 Rev 2
5/47
Block diagram and pin description
VND7140AJ
Figure 2: Configuration diagram (top view)
Table 2: Suggested connections for unused and not connected pins
SEn, SELx,
FaultRST
Connection /
pin
MultiSense
N.C.
Output
Input
Floating
Not allowed
X (1)
X
X
X
X
Through 1 kΩ
Not
allowed
Through 15 kΩ
Through 15 kΩ
To ground
resistor
resistor
resistor
Notes:
(1)X: do not care.
6/47
DocID027398 Rev 2
VND7140AJ
Electrical specification
2
Electrical specification
Figure 3: Current and voltage conventions
IS
VCC
VCC
VFn
IFR
IOUT
FaultRST
SEn
OUTPUT0,1
MultiSense
ISEn
VOUT
ISENSE
ISEL
SEL0,1
VSENSE
IIN
INPUT0,1
IGND
GAPGCFT00315
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Table 3: Absolute maximum ratings
Symbol
VCC
Parameter
Value
38
Unit
DC supply voltage
V
-VCC
Reverse DC supply voltage
0.3
Maximum transient supply voltage (ISO 16750-2:2010 Test B
clamped to 40V; RL = 4 Ω)
VCCPK
40
V
Maximum jump start voltage for single pulse short circuit
protection
VCCJS
-IGND
IOUT
28
V
DC reverse ground pin current
200
mA
Internally
limited
OUTPUT0,1 DC output current
A
-IOUT
IIN
Reverse DC output current
INPUT0,1 DC input current
SEn DC input current
4
ISEn
ISEL
IFR
-1 to 10
mA
SEL0,1 DC input current
FaultRST DC input current
DocID027398 Rev 2
7/47
Electrical specification
VND7140AJ
Symbol
Parameter
Value
Unit
VFR
FaultRST DC input voltage
7.5
10
V
MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V)
MultiSense pin DC output current in reverse (VCC < 0 V)
ISENSE
mA
mJ
-20
Maximum switching energy (single pulse) (TDEMAG = 0.4 ms;
Tjstart = 150 °C)
EMAX
10
Electrostatic discharge (JEDEC 22A-114F)
4000
2000
4000
4000
4000
V
V
V
V
V
INPUT0,1
MultiSense
SEn, SEL0,1, FaultRST
OUTPUT0,1
VCC
VESD
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
750
V
-40 to 150
-55 to 150
°C
Tstg
2.2
Thermal data
Table 4: Thermal data
Parameter
Symbol
Typ. value
7.7
Unit
Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) (1)(2)
Rthj-amb
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-5)(1)(3)
Thermal resistance junction-ambient (JEDEC JESD 51-7)(1)(2)
61
°C/W
26.5
Notes:
(1)One channel ON.
(2)Device mounted on four-layers 2s2p PCB
(3)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
2.3
Main electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
8/47
DocID027398 Rev 2
VND7140AJ
Electrical specification
Table 5: Power section
Test conditions
Symbol
Parameter
Min. Typ. Max. Unit
Operating supply
voltage
VCC
4
13
28
4
V
V
V
Undervoltage
shutdown
VUSD
Undervoltage
shutdown reset
VUSDReset
5
Undervoltage
VUSDhyst shutdown
hysteresis
0.3
V
IOUT = 1 A; Tj = 25°C
140
On-state
RON
IOUT = 1 A; Tj = 150°C
280
210
52
mΩ
resistance (1)
IOUT = 1 A; VCC = 4 V; Tj = 25°C
IS = 20 mA; 25°C < Tj < 150°C
IS = 20 mA; Tj = -40°C
41
38
46
V
V
Vclamp
Clamp voltage
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 25°C
0.5
0.5
3
Supply current in
standby at
VCC = 13 V (2)
VCC = 13 V;
ISTBY
VIN = VOUT = VFR = VSEn = 0 V;
µA
(3)
VSEL0,1 = 0 V; Tj = 85°C
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1 = 0 V; Tj = 125°C
VCC = 13 V;
VIN = VOUT = VFR = VSEL0,1 = 0 V;
VSEn = 5 V to 0 V
Standby mode
blanking time
tD_STBY
60
300
5
550
8
µs
VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V;
VIN0 = 5 V; VIN1 = 5 V;
IS(ON)
Supply current
mA
IOUT0 = 0 A; IOUT1 = 0 A
Control stage
current
VCC = 13 V; VSEn = 5 V;
IGND(ON)
consumption in ON VFR = VSEL0,1 = 0 V; VIN0 = 5 V;
12
mA
state. All channels
active.
VIN1 = 5 V; IOUT0 = 1 A; IOUT1 = 1 A
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25°C
0
0
0.01
0.5
3
Off-state output
current at
IL(off)
µA
V
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C
VCC = 13 V (1)
Output - VCC diode
voltage (1)
VF
IOUT = -1 A; Tj = 150°C
0.7
Notes:
(1)For each channel
(2)PowerMOS leakage included.
(3)Parameter specified by design; not subject to production test.
DocID027398 Rev 2
9/47
Electrical specification
VND7140AJ
Table 6: Switching
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Test
conditions
Symbol
Parameter
Min. Typ. Max. Unit
(1)
td(on)
Turn-on delay time at Tj = 25 °C
Turn-off delay time at Tj = 25 °C
Turn-on voltage slope at Tj = 25 °C
Turn-off voltage slope at Tj = 25 °C
Switching energy losses at turn-on
10
10
70
40
120
100
0.7
RL = 13 Ω
µs
(1)
td(off)
(1)
(1)
(dVOUT/dt)on
(dVOUT/dt)off
0.1
0.1
0.27
0.35
RL = 13 Ω
RL = 13 Ω
V/µs
mJ
0.7
WON
—
0.15 0.18(2)
(twon
Switching energy losses at turn-off
(twoff
Differential Pulse skew (tPHL - tPLH
)
WOFF
RL = 13 Ω
RL = 13 Ω
—
0.1
-50
0.18(2)
0
mJ
µs
)
(1)
tSKEW
)
-100
Notes:
(1)See Figure 6: "Switching time and Pulse skew".
(2)Parameter guaranteed by design and characterization; not subject to production test.
Table 7: Logic inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
INPUT0,1 characteristics
VIL
IIL
Input low level voltage
0.9
V
µA
V
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
VIN = 0.9 V
VIN = 2.1 V
1
VIH
2.1
IIH
10
µA
V
VI(hyst)
0.2
5.3
IIN = 1 mA
IIN = -1 mA
7.2
VICL
Input clamp voltage
V
-0.7
FaultRST characteristics
VFRL Input low level voltage
IFRL
VFRH
IFRH
0.9
V
µA
V
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
VIN = 0.9 V
VIN = 2.1 V
1
2.1
10
µA
V
VFR(hyst)
0.2
5.3
IIN = 1 mA
IIN = -1 mA
7.5
VFRCL
Input clamp voltage
V
-0.7
SEL0,1 characteristics (7 V < VCC < 18 V)
VSELL
ISELL
VSELH
ISELH
Input low level voltage
Low level input current
Input high level voltage
High level input current
0.9
10
V
µA
V
VIN = 0.9 V
VIN = 2.1 V
1
2.1
µA
10/47
DocID027398 Rev 2
VND7140AJ
Electrical specification
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min.
0.2
Typ.
Max.
Unit
VSEL(hyst)
Input hysteresis voltage
V
IIN = 1 mA
IIN = -1 mA
5.3
7.2
VSELCL
Input clamp voltage
V
-0.7
SEn characteristics (7 V < VCC < 18 V)
VSEnL
ISEnL
VSEnH
ISEnH
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
0.9
V
µA
V
VIN = 0.9 V
VIN = 2.1 V
1
2.1
10
µA
V
VSEn(hyst)
0.2
5.3
IIN = 1 mA
IIN = -1 mA
7.2
VSEnCL
Input clamp voltage
V
-0.7
Table 8: Protections
Test conditions
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Min.
Typ.
Max. Unit
VCC = 13 V
8
12
ILIMH
DC short circuit current
16
4 V < VCC < 18 V (1)
A
VCC = 13 V;
Short circuit current
during thermal cycling
ILIML
4
TR < Tj < TTSD
TTSD
TR
Shutdown temperature
Reset temperature (1)
150
175
200
TRS + 1 TRS + 7
Thermal reset of fault
diagnostic indication
°C
TRS
VFR = 0 V; VSEn = 5 V
Tj = -40°C; VCC = 13 V
135
Thermal hysteresis
(TTSD - TR)(1)
THYST
7
ΔTJ_SD
Dynamic temperature
60
K
VFR = 5 V to 0 V;
VSEn = 5 V;
Fault reset time for
output unlatch (1)
E.g. Ch0:
tLATCH_RST
3
10
20
µs
VIN0 = 5 V;
VSEL0 = 0 V;
VSEL1 = 0 V
IOUT = 1 A; L = 6 mH;
Tj = -40°C
VCC
38
-
-
V
V
Turn-off output voltage
clamp
VDEMAG
IOUT = 1 A; L = 6 mH;
Tj = 25°C to 150°C
VCC
41
VCC
46
-
VCC
52
-
Output voltage drop
limitation
VON
IOUT = 0.07 A
20
mV
Notes:
(1)Parameter guaranteed by design and characterization; not subject to production test.
DocID027398 Rev 2
11/47
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
VND7140AJ
Table 9: MultiSense
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VSEn = 0 V; ISENSE = 1 mA
-17
-12
MultiSense clamp
voltage
VSENSE_CL
V
VSEn = 0 V; ISENSE = -1 mA
7
Current sense characteristics
IOUT = 0.01 A; VSENSE = 0.5 V;
VSEn = 5 V
KOL
dKcal/Kcal
KLED
IOUT/ISENSE
295
-30
Current sense ratio
drift at calibration
point
IOUT = 0.01 A to 0.025 A;
Ical = 17.5 mA; VSENSE = 0.5 V;
VSEn = 5 V
(1)(2)
30
%
IOUT = 0.025 A;
VSENSE = 0.5 V; VSEn = 5 V
IOUT/ISENSE
330
-25
580
550
820
25
Current sense ratio
drift
IOUT = 0.025 A;
VSENSE = 0.5 V; VSEn = 5 V
(1)(2)
dKLED/KLED
K0
%
%
%
%
%
IOUT = 0.07 A; VSENSE = 0.5 V;
VSEn = 5 V
IOUT/ISENSE
375
720
IOUT = 0.07 A; VSENSE = 0.5 V;
VSEn = 5 V
Current sense ratio
drift
(1)(2)
dK0/K0
K1
-20
360
-15
380
-10
20
670
15
IOUT = 0.15 A; VSENSE = 4 V;
VSEn = 5 V
IOUT/ISENSE
500
475
470
IOUT = 0.15 A; VSENSE = 4 V;
VSEn = 5 V
Current sense ratio
drift
(1)(2)
dK1/K1
K2
IOUT = 0.7 A; VSENSE = 4 V;
VSEn = 5 V
IOUT/ISENSE
570
10
IOUT = 0.7 A; VSENSE = 4 V;
VSEn = 5 V
Current sense ratio
drift
(1)(2)
(1)(2)
dK2/K2
K3
IOUT = 2 A; VSENSE = 4 V;
VSEn = 5 V
IOUT/ISENSE
430
-5
520
5
Current sense ratio
drift
IOUT = 2 A; VSENSE = 4 V;
VSEn = 5 V
dK3/K3
MultiSense disabled:
VSEn = 0 V
0
0.5
0.5
MultiSense disabled:
-1 V < VSENSE < 5 V(1)
-0.5
MultiSense enabled:
VSEn = 5 V; All channels ON;
IOUTX = 0 A; ChX diagnostic
selected;
MultiSense leakage
current
ISENSE0
µA
0
2
E.g. Ch0:
VIN0 = 5 V; VIN1 = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT0 = 0 A; IOUT1 = 1 A
12/47
DocID027398 Rev 2
VND7140AJ
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
MultiSense enabled:
VSEn = 5 V; ChX OFF; ChX
diagnostic selected:
0
2
E.g. Ch0:
VIN0 = 0 V; VIN1 = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT1 = 1 A
VSEn = 5 V; RSENSE = 2.7 kΩ;
Output Voltage for
MultiSense
shutdown
E.g. Ch0:
(1)
VOUT_MSD
5
V
V
VIN0 = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; IOUT0 = 1 A
VCC = 7 V; RSENSE = 2.7 kΩ;
VSEn = 5 V; VIN0 = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT0 = 2 A; Tj = 150°C
Multisense
saturation voltage
VSENSE_SAT
5
4
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
CS saturation
current
(1)
ISENSE_SAT
mA
A
Tj = 150°C
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
Output saturation
current
(1)
IOUT_SAT
2.2
Tj = 150°C
OFF-state diagnostic
VSEn = 5 V; ChX OFF;
OFF-state open-load ChX diagnostic selected
voltage detection
VOL
2
3
4
V
E.g: Ch0
threshold
VIN0 = 0 V; VSEL0 = 0 V;
VSEL1 = 0 V
OFF-state output
sink current
IL(off2)
VIN = 0 V; VOUT = VOL
-100
-15
µA
VSEn = 5 V; ChX ON to OFF
transition;
OFF-state
diagnostic delay
time from falling
edge of INPUT (see
Figure 9:
ChX diagnostic selected
tDSTKON
100
350
700
60
µs
µs
E.g: Ch0
VIN0 = 5 V to 0 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT0 = 0 A; VOUT = 4 V
"TDSTKON")
Settling time for
valid OFF-state
open load diagnostic
indication from rising
edge of SEn
VIN0 = 0 V; VIN1 = 0 V;
VFR = 0 V; VSEL0 = 0 V;
VSEL1 = 0 V; VOUT0 = 4 V;
VSEn = 0 V to 5 V
tD_OL_V
DocID027398 Rev 2
13/47
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
VND7140AJ
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VSEn = 5 V; ChX OFF;
OFF-state
ChX diagnostic selected
diagnostic delay
time from rising
edge of VOUT
E.g: Ch0
tD_VOL
5
30
µs
VIN0 = 0 V; VSEL0 = 0 V;
VSEL1 = 0 V; VOUT = 0 V
to 4 V
Chip temperature analog feedback
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN0,1 = 0 V;
RSENSE = 1 kΩ; Tj = -40°C
2.325 2.41 2.495
1.985 2.07 2.155
V
V
MultiSense output
VSEn = 5 V; VSEL0 = 0 V;
voltage proportional VSEL1 = 5 V; VIN0,1 = 0 V;
VSENSE_TC
to chip temperature
RSENSE = 1 kΩ; Tj = 25°C
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN0,1 = 0 V;
RSENSE = 1 kΩ; Tj = 125°C
1.435 1.52 1.605
-5.5
V
Temperature
coefficient
dVSENSE_TC/dT(1)
Transfer function
Tj = -40°C to 150°C
mV/K
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
VCC supply voltage analog feedback
MultiSense output
voltage proportional
to VCC supply
voltage
VCC = 13 V; VSEn = 5 V;
VSEL0 = 5 V; VSEL1 = 5 V; VIN0,1 3.16 3.23
= 0 V; RSENSE = 1 kΩ
VSENSE_VCC
3.3
V
Transfer function (3)
VSENSE_VCC = VCC / 4
Fault diagnostic feedback (see Table 10: "Truth table")
VCC = 13 V; RSENSE = 1 kΩ;
MultiSense output
voltage in fault
condition
E.g: Ch0 in open load
VIN0 = 0 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT0 = 0 A; VOUT = 4 V
VSENSEH
5
7
6.6
30
V
MultiSense output
current in fault
condition (2)
ISENSEH
VCC = 13 V; VSENSE = 5 V
20
mA
MultiSense timings (current sense mode - see Figure 7: "MultiSense timings (current sense
mode)")(4)
Current sense
settling time from
rising edge of SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 13 Ω
tDSENSE1H
60
20
µs
µs
Current sense
disable delay time
from falling edge of
SEn
VIN = 5 V; VSEn = 5 V to 0 V;
RSENSE = 1 kΩ; RL = 13 Ω
tDSENSE1L
5
Current sense
settling time from
rising edge of
INPUT
VIN = 0 V to 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 13 Ω
tDSENSE2H
100
250
µs
14/47
DocID027398 Rev 2
VND7140AJ
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Current sense
settling time from
rising edge of IOUT
(dynamic response
to a step change of
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; ISENSE = 90 %
of ISENSEMAX; RL = 13 Ω
ΔtDSENSE2H
100
µs
IOUT
)
Current sense turn-
off delay time from
falling edge of
INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 13 Ω
tDSENSE2L
50
250
µs
MultiSense timings (chip temperature sense mode - see Figure 8: "Multisense timings (chip
temperature and VCC sense mode)")(4)
VSENSE_TC settling
time from rising
edge of SEn
VSEn = 0 V to 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
tDSENSE3H
60
20
µs
µs
VSENSE_TC disable
delay time from
falling edge of SEn
VSEn = 5 V to 0 V; VSEL0 = 0 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
tDSENSE3L
MultiSense timings (VCC voltage sense mode - see Figure 8: "Multisense timings (chip
temperature and VCC sense mode)")(4)
VSENSE_VCC settling
time from rising
edge of SEn
VSEn = 0 V to 5 V; VSEL0 = 5 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
tDSENSE4H
60
20
µs
µs
VSENSE_VCC disable
delay time from
falling edge of SEn
VSEn = 5 V to 0 V; VSEL0 = 5 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
tDSENSE4L
MultiSense timings (Multiplexer transition times)(4)
VIN0 = 5 V; VIN1 = 5 V;
VSEn = 5 V; VSEL1 = 0 V;
VSEL0 = 0 V to 5 V; IOUT0 = 0 A;
IOUT1 = 1 A; RSENSE = 1 kΩ
MultiSense
transition delay from
ChX to ChY
tD_XtoY
20
60
20
60
20
µs
µs
µs
µs
µs
MultiSense
VIN0 = 5 V; VSEn = 5 V;
transition delay from VSEL0 = 0 V; VSEL1 = 0 V to
current sense to TC
sense
tD_CStoTC
tD_TCtoCS
tD_CStoVCC
tD_VCCtoCS
5 V; IOUT0 = 0.5 A;
RSENSE = 1 kΩ
MultiSense
VIN0 = 5 V; VSEn = 5 V;
transition delay from VSEL0 = 0 V; VSEL1 = 5 V to
TC sense to current
sense
0 V; IOUT0 = 0.5 A;
RSENSE = 1 kΩ
MultiSense
VIN1 = 5 V; VSEn = 5 V;
transition delay from VSEL0 = 5 V; VSEL1 = 0 V to
current sense to VCC 5 V; IOUT1 = 0.5 A;
sense
RSENSE = 1 kΩ
MultiSense
VIN1 = 5 V; VSEn = 5 V;
transition delay from VSEL0 = 5 V; VSEL1 = 5 V to
VCC sense to current 0 V; IOUT1 = 0.5 A;
sense
RSENSE = 1 kΩ
DocID027398 Rev 2
15/47
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
VND7140AJ
Symbol
Parameter
MultiSense
transition delay from
TC sense to VCC
sense
Test conditions
Min. Typ. Max. Unit
VCC = 13 V; Tj = 125°C;
VSEn = 5 V; VSEL0 = 0 V to 5 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
tD_TCtoVCC
20
20
µs
µs
MultiSense
VCC = 13 V; Tj = 125°C;
VSEn = 5 V; VSEL0 = 5 V to 0 V;
VSEL1 = 5 V; RSENSE = 1 kΩ
transition delay from
VCC sense to TC
sense
tD_VCCtoTC
MultiSense
VIN0 = 5 V; VIN1 = 0 V;
transition delay from
stable current sense
on ChX to VSENSEH on
ChY
VSEn = 5 V; VSEL1 = 0 V;
VSEL0 = 0 V to 5 V; IOUT0 = 1 A;
VOUT1 = 4 V; RSENSE = 1 kΩ
tD_CStoVSENSEH
60
µs
Notes:
(1)Parameter specified by design; not subject to production test.
(2)All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
(3)
V
sensing and TC sensing are referred to GND potential.
CC
(4)Transition delays are measured up to +/- 10% of final conditions.
Figure 4: IOUT/ISENSE versus IOUT
1000
800
600
400
200
0
Max
Min
Typ
0
1
2
3
IOUT[A]
16/47
DocID027398 Rev 2
VND7140AJ
Electrical specification
Figure 5: Current sense accuracy versus IOUT
65
60
55
50
45
40
35
30
25
20
15
10
5
Current sense uncalibrated precision
Current sense calibrated precision
%
0
0
1
2
3
IOUT[A]
GAPGCFT01218
Figure 6: Switching time and Pulse skew
DocID027398 Rev 2
17/47
Electrical specification
VND7140AJ
Figure 7: MultiSense timings (current sense mode)
Figure 8: Multisense timings (chip temperature and VCC sense mode)
18/47
DocID027398 Rev 2
VND7140AJ
Electrical specification
Figure 9: TDSTKON
Table 10: Truth table
INX FR SEn SELX OUTX MultiSense
Mode
Standby
Conditions
Comments
Low quiescent
current
consumption
All logic inputs
low
L
L
L
X
L
L
L
L
L
Hi-Z
See (1)
See (1)
Outputs
configured for
auto-restart
Nominal load
connected;
H
H
Normal
See (1)
Tj < 150 °C
Outputs
configured for
Latch-off
H
L
H
X
H
L
See (1)
See (1)
Overload or
short to GND
causing:
Output cycles
with
temperature
hysteresis
H
L
H
L
See (1)
See (1)
Overload
See (1)
Tj > TTSD or
ΔTj > ΔTj_SD
Output latches-
off
H
X
H
X
Re-start when
L
L
Hi-Z
Hi-Z
VCC < VUSD
(falling)
VCC > VUSD
+
Undervoltage
X
X
VUSDhyst (rising)
Short to VCC
Open-load
Inductive
L
L
X
X
H
H
See (1)
See (1)
OFF-state
diagnostics
See (1)
See (1)
External pull-up
Negative
L
X
< 0 V
See (1)
output voltage loads turn-off
Notes:
(1)Refer to Table 11: "MultiSense multiplexer addressing"
DocID027398 Rev 2
19/47
Electrical specification
VND7140AJ
Table 11: MultiSense multiplexer addressing
MultiSense output
SEn SEL1 SEL0 MUX channel
Normal
mode
OFF-state
diag. (1)
Negative
output
Overload
L
X
L
X
L
Hi-Z
Channel 0
diagnostic
ISENSE
1/K * IOUT0
=
VSENSE
VSENSEH
=
VSENSE
VSENSEH
=
H
Hi-Z
Hi-Z
Channel 1
diagnostic
ISENSE
1/K * IOUT1
=
VSENSE
VSENSEH
=
VSENSE
VSENSEH
=
H
L
H
H
H
H
H
L
TCHIP Sense
VCC Sense
VSENSE = VSENSE_TC
VSENSE = VSENSE_VCC
H
Notes:
(1)In case the output channel corresponding to the selected MUX channel is latched off while the
relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic.
Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0.
Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic;
Mutisense = VSENSEH
2.4
Waveforms
Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)
20/47
DocID027398 Rev 2
VND7140AJ
Electrical specification
Figure 11: Latch functionality - behavior in hard short circuit condition
Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode +
latch off)
DocID027398 Rev 2
21/47
Electrical specification
VND7140AJ
Figure 13: Standby mode activation
Figure 14: Standby state diagram
22/47
DocID027398 Rev 2
VND7140AJ
Electrical specification
2.5
Electrical characteristics curves
Figure 16: Standby current
Figure 15: OFF-state output current
ISTBY [µA]
1
Iloff [nA]
160
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
140
120
Vcc = 13V
Off State
100
Vcc = 13V
Vin = Vout = 0
80
60
40
20
0
-50
-25
0
25
50
T [°C]
75
100
125
150
175
-50
-25
0
25
50
T [°C]
75
100
125
150
175
GAPGCFT01222
GAPGCFT01221
Figure 17: IGND(ON) vs. Iout
Figure 18: Logic Input high level voltage
ViH, VFRH, VSELH, VSEnH [V]
IGND(ON) [mA]
3.5
2
1.8
1.6
1.4
1.2
1
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Vcc = 13V
Iout0 = Iout1 = 1A
0.8
0.6
0.4
0.2
0
-50
-25
0
25
50
T [°C]
75
100
125
150
175
-50
-25
0
25
50
T [°C]
75
100
125
150
175
GAPGCFT01224
GAPGCFT01223
Figure 19: Logic Input low level voltage
Figure 20: High level logic input current
IiH, IFRH, ISELH, ISEnH [ µA]
VilL VFRL, VSELL, VSEnL [V]
4
2
1.8
1.6
1.4
1.2
1
3.5
3
2.5
2
0.8
0.6
0.4
0.2
0
1.5
1
0.5
0
-50
-25
0
25
50
T [°C]
75
100
125
150
175
-50
-25
0
25
50
T [°C]
75
100
125
150
175
GAPGCFT01225
GAPGCFT01226
DocID027398 Rev 2
23/47
Electrical specification
Figure 21: Low level logic input current
VND7140AJ
Figure 22: Logic Input hysteresis voltage
Vi(hyst), VFR(hyst), VSEL(hyst), VSEn(hyst) [V]
IiL, IFRL, ISELL, ISEnL [µA]
4
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
T [°C]
75
100
125
150
175
-50
-25
0
25
50
T [°C]
75
100
125
150
175
GAPGCFT01227
GAPGCFT01228
Figure 23: FaultRST Input clamp voltage
Figure 24: Undervoltage shutdown
VFRCL [V]
8
VUSD [V]
8
7
7
6
5
4
3
2
1
Iin = 1mA
6
5
4
3
2
1
Iin = -1mA
0
-1
0
-50
-25
0
25
50
T [°C]
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
T [°C]
GAPGCFT01229
GAPGCFT01230
Figure 25: On-state resistance vs. Tcase
Figure 26: On-state resistance vs. VCC
Ron [mOhm]
Ron [mOhm]
280
260
240
220
200
180
160
140
120
100
80
280
260
240
220
200
T = 150 °C
T = 125 °C
180
Iout = 1A
Vcc = 13V
160
140
120
100
80
T = 25 °C
T = -40 °C
60
60
40
40
20
20
0
0
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
T [°C]
75
100
125
150
175
Vcc [V]
GAPGCFT01231
GAPGCFT01232
24/47
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VND7140AJ
Electrical specification
Figure 28: Turn-off voltage slope
Figure 27: Turn-on voltage slope
(dVout/dt)Off [V/ µs]
(dVout/dt)On [V/µs]
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Vcc = 13V
Rl = 13Ω
Vcc = 13V
Rl = 13Ω
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
T [°C]
T [°C]
GAPGCFT01233
GAPGCFT01234
Figure 29: Won vs. Tcase
Figure 30: Woff vs. Tcase
Woff [mJ]
1
Won [mJ]
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
T [°C]
T [°C]
GAPGCFT01235
GAPGCFT01236
Figure 32: OFF-state open-load voltage
detection threshold
Figure 31: ILIMH vs. Tcase
Ilimh [A]
20
VOL [V]
4
3.5
3
15
10
5
2.5
2
Vcc = 13V
1.5
1
0.5
0
0
-50
-25
0
25
50
T [°C]
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
T [°C]
GAPGCFT01237
GAPGCFT01238
DocID027398 Rev 2
25/47
Electrical specification
Figure 33: Vsense clamp vs. Tcase
VND7140AJ
Figure 34: Vsenseh vs. Tcase
VSENSEH [V]
10
VSENSE_CL [V]
10
9
8
7
6
5
4
3
2
1
0
9
8
7
Iin = 1mA
6
5
4
3
2
1
Iin = -1mA
0
-1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
T [°C]
T [°C]
GAPGCFT01239
GAPGCFT01240
26/47
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VND7140AJ
Protections
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as
soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the
FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low)
or remains off (FaultRST = High). The protection prevents fast thermal transient effects
and, consequently, reduces thermo-mechanical fatigue.
3.2
3.3
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon
as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High).
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well
as the other components of the system (e.g. bonding wires, wiring harness, connectors,
loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or
during load power-up, the output current is clamped to a safety level, ILIMH, by operating the
output power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a
certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the
device.
DocID027398 Rev 2
27/47
Application information
VND7140AJ
4
Application information
Figure 35: Application diagram
4.1
GND protection network against reverse battery
Figure 36: Simplified internal structure
28/47
DocID027398 Rev 2
VND7140AJ
Application information
4.1.1
Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12: "ISO 7637-2 -
electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 12: ISO 7637-2 - electrical transient conduction along supply line
Test pulse severity
Test
Pulse
2011(E)
Burst cycle /
pulse
Minimum
number of
pulses or test
time
level with Status II
functional performance
status
Pulse duration and
pulse generator
internal impedance
repetition time
(1)
Level
III
US
min
0.5 s
0.2 s
max
1
-112 V
+55 V
500 pulses
500 pulses
2 ms, 10 Ω
50 µs, 2 Ω
2a
III
5 s
100
ms
3a
IV
-220 V
1h
90 ms
90 ms
0.1 µs, 50 Ω
100
ms
3b
IV
IV
+150 V
-7 V
1h
0.1 µs, 50 Ω
4 (2)
1 pulse
100 ms, 0.01 Ω
Load dump according to ISO 16750-2:2010
Test B (3)
40 V
5 pulse
1 min
400 ms, 2 Ω
Notes:
(1)US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test pulse from ISO 7637-2:2004(E).
(3)With 40 V external suppressor referred to ground (-40°C < Tj < 150 °C).
DocID027398 Rev 2
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Application information
VND7140AJ
4.3
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with
the latch-up limit of microcontroller I/Os.
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(MultiSense) delivering the following signals:
Current monitor: current mirror of channel output current
VCC monitor: voltage propotional to VCC
TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in MultiSense multiplexer
addressing Table.
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Application information
Figure 37: MultiSense and diagnostic – block diagram
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4.4.1
Principle of Multisense signal generation
Figure 38: MultiSense block diagram
Current monitor
When current mode is selected in the MultiSense, this output is capable to provide:
Current mirror proportional to the load current in normal operation, delivering current
proportional to the load according to known ratio named K
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can
be done using simple equations
Current provided by MultiSense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
Where:
VSENSE is voltage measurable on RSENSE resistor
ISENSE is current provided from MultiSense pin in current output mode
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Application information
IOUT is current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its
spread includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between IOUT and ISENSE
.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin
which is switched to a “current limited” voltage source, VSENSEH
.
In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH
.
The typical behavior in case of overload or hard short circuit is shown in Waveforms
section.
Figure 39: Analogue HSD – open-load detection in off-state
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Application information
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Figure 40: Open-load / short to VCC condition
Table 13: MultiSense pin levels in off-state
Condition
Output
MultiSense
SEn
L
Hi-Z
VSENSEH
Hi-Z
0
VOUT > VOL
H
L
Open-load
VOUT < VOL
VOUT > VOL
VOUT < VOL
H
L
Hi-Z
VSENSEH
Hi-Z
0
Short to VCC
Nominal
H
L
H
4.4.2
TCASE and VCC monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because a
voltage shift is generated between the device GND and the microcontroller input GND
reference.
Figure 41: "GND voltage shift" shows the link between VMEASURED and the real VSENSE
signal.
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Application information
Figure 41: GND voltage shift
VCC monitor
Battery monitoring channel provides VSENSE = VCC / 8.
Case temperature monitor
Case temperature monitor is capable of providing information about the actual device
temperature. Since a diode is used for temperature sensing, the following equation
describes the link between temperature and output VSENSE level:
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C)).
4.4.3
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable that VPU is switched off during the module standby mode in order to avoid
the overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
Equation
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Maximum demagnetization energy (VCC = 16 V)
VND7140AJ
5
Maximum demagnetization energy (VCC = 16 V)
Figure 42: Maximum turn off current versus inductance
VND7140Ax- Maximum turn off current versus inductance
10
1
VND7140AJ - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
0.1
0.1
1
10
100
1000
L (mH)
VND7140Ax- Maximum turn off Energy versus Tdemag
100
VND7140AJ - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
10
1
0.01
0.1
1
10
Tdemag [ms]
Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of
every pulse must not exceed the temperature specified above for curves A and B.
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Package and PCB thermal data
6
Package and PCB thermal data
6.1
PowerSSO-16 thermal data
Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 14: PCB properties
Dimension
Value
1.6 mm +/- 10%
77 mm x 86 mm
FR4
Board finish thickness
Board dimension
Board Material
Copper thickness (top and bottom layers)
Copper thickness (inner layers)
Thermal vias separation
0.070 mm
0.035 mm
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
0.025 mm
Copper thickness on vias
Footprint dimension (top layer)
Heatsink copper area dimension (bottom layer)
2.2 mm x 3.9 mm
Footprint, 2 cm2 or 8 cm2
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Package and PCB thermal data
VND7140AJ
Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on)
RTHjamb
100
90
80
70
60
50
40
30
RTHjamb
0
2
4
6
8
10
Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
ZTH (°C/W)
100
10
1
Cu=foot print
Cu=2 cm2
Cu=8 cm2
4 Layer
0.1
0.0001
0.001
0.01
0.1
Time (s)
1
10
100
1000
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
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Package and PCB thermal data
Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16
The fitting model is a simplified thermal tool and is valid for transient evolutions
where the embedded protections (power limitation or thermal cycling during
thermal shutdown) are not triggered.
Table 15: Thermal parameters
Area/island (cm2)
R1 = R7 (°C/W)
R2 = R8 (°C/W)
R3 (°C/W)
Footprint
2.8
2
8
4L
2.5
10
10
6
10
6
7
4
3
7
R4 (°C/W)
16
R5 (°C/W)
30
20
20
10
18
R6 (°C/W)
26
C1 = C7 (W.s/°C)
C2 = C8 (W.s/°C)
C3 (W.s/°C)
0.00012
0.005
0.07
0.2
C4 (W.s/°C)
0.3
1
0.3
1
0.4
4
C5 (W.s/°C)
0.4
C6 (W.s/°C)
3
5
7
18
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Package information
VND7140AJ
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
PowerSSO-16 package information
Figure 48: PowerSSO-16 package outline
Table 16: PowerSSO-16 mechanical data
Dimensions
Ref.
Millimeters
Typ.
Min.
0°
Max.
Θ
Θ1
Θ2
Θ3
A
8°
0°
5°
15°
15°
5°
1.70
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Package information
Dimensions
Millimeters
Typ.
Ref.
Min.
0.00
1.10
0.20
0.20
0.19
0.19
Max.
0.10
1.60
0.30
0.28
0.25
0.23
A1
A2
b
b1
c
0.25
c1
D
0.20
4.9 BSC
D1
e
2.90
3.50
0.50 BSC
6.00 BSC
3.90 BSC
E
E1
E2
h
2.20
0.25
0.40
2.80
0.50
0.85
L
0.60
1.00 REF
16
L1
N
R
0.07
0.07
0.20
R1
S
Tolerance of form and position
aaa
bbb
ccc
ddd
eee
fff
0.10
0.10
0.08
0.08
0.10
0.10
0.15
ggg
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Package information
VND7140AJ
7.2
PowerSSO-16 packing information
Figure 49: PowerSSO-16 reel 13"
Table 17: Reel dimensions
Description
Value(1)
2500
2500
330
Base quantity
Bulk quantity
A (max)
B (min)
1.5
C (+0.5, -0.2)
D (min)
13
20.2
100
N
W1 (+2 /-0)
W2 (max)
12.4
18.4
Notes:
(1)All dimensions are in mm.
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Package information
Figure 50: PowerSSO-16 carrier tape
Table 18: PowerSSO-16 carrier tape dimensions
Description
Value(1)
A0
B0
K0
K1
F
6.50 ± 0.1
5.25 ± 0.1
2.10 ± 0.1
1.80 ± 0.1
5.50 ± 0.1
8.00 ± 0.1
12.00 ± 0.3
P1
W
Notes:
(1)All dimensions are in mm.
Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape
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Package information
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7.3
PowerSSO-16 marking information
Figure 52: PowerSSO-16 marking information
Engineering Samples: these samples can be clearly identified by a dedicated
special symbol in the marking of each unit. These samples are intended to be
used for electrical compatibility evaluation only; usage for any other purpose may
be agreed only upon written authorization by ST. ST is not liable for any customer
usage in production and/or in reliability qualification trials.
Commercial Samples: fully qualified parts from ST standard production with no
usage restrictions.
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Order codes
8
Order codes
Table 19: Device summary
Order codes
Tape and reel
VND7140AJTR
Package
PowerSSO-16
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Revision history
VND7140AJ
9
Revision history
Table 20: Document revision history
Changes
Date
Revision
25-May-2015
1
Initial release.
Added AEC Q100 qualified in Features section
Updated Figure 52: "PowerSSO-16 marking information"
13-Oct-2016
2
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© 2016 STMicroelectronics – All rights reserved
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相关型号:
VND7140AJTR
Double channel high-side driver with MultiSense analog feedback for automotive applications
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