VNH7100AS_技术文档

VNH7100AS

Automotive fully integrated H-bridge motor driver

Datasheet

-

production data

Description

The device is a full bridge motor driver intended

for a wide range of automotive applications. The

device incorporates a dual monolithic high-side

driver and two low-side switches.

SO-16N

GAPGCFT00648

Both switches are designed using

Features

STMicroelectronics’ well known and proven

proprietary VIPower^®M0 technology that allows

to efficiently integrate on the same die a true

Power MOSFET with an intelligent

Type

R_DS(on)

I_outV_CCmax

signal/protection circuitry. The three dies are

assembled in SO-16N package on electrically

isolated leadframes.

100 mΩ typ

(per leg)

VNH7100AS

12 A

41 V

Moreover, its fully symmetrical mechanical design

allows superior manufacturability at board level.

The input signals IN_Aand IN_Bcan directly

interface the microcontroller to select the motor

direction and the brake condition. A SEL0 pin is

available to address the information available on

the MultiSense to the microcontroller. The

MultiSense pin allows to monitor the motor

current by delivering a current proportional to the

motor current value.

• Automotive qualified

• Output current: 15 A

• 3 V CMOS-compatible inputs

• Undervoltage shutdown

• Overvoltage clamp

• Thermal shutdown

• Cross-conduction protection

• Current and power limitation

The PWM, up to 20 kHz, allows to control the

speed of the motor in all possible conditions. In all

cases, a low level state on the PWM pin turns off

both the LS_Aand LS_Bswitches.

• Very low standby power consumption

• Protection against loss of ground and loss of

V_CC

• PWM operation up to 20 kHz

Table 1. Device summary

• MultiSense diagnostic functions

– Analog motor current feedback

– Output short to ground detection

– Thermal shutdown indication

– OFF-state open-load detection

– Output short to V_CCdetection

Order codes

Package

Tube

Tape and reel

SO-16N

—

VNH7100ASTR

• Output protected against short to ground and

short to V_CC

• Standby Mode

• Half Bridge Operation

• Package: ECOPACK^®

October 2015

DocID028092 Rev 4

1/38

This is information on a product in full production.

www.st.com

Contents

VNH7100AS

Contents

1

2

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

2.2

2.3

2.4

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3

4

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1

3.2

3.3

3.4

Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

OFF-state open-load detection – External circuitry dimensioning . . . . . . 23

Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 24

Device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1

4.2

SO16-N thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Package thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.1

4.2.2

Thermal characterization in steady state conditions . . . . . . . . . . . . . . . 28

Thermal characterization during transients . . . . . . . . . . . . . . . . . . . . . . 29

5

6

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1

5.2

5.3

SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SO-16N packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SO-16N marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2/38

DocID028092 Rev 4

VNH7100AS

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin definitions and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic inputs (IN_A, IN_B, PWM) (V_CC= 7 V up to 28 V; -40°C < T_j< 150°C) . . . . . . . . . . . . 10

Switching (V_CC= 13 V; R_LOAD= 5.2 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Protections and diagnostics (V_CC= 7 V up to 18 V; -40°C < T_j< 150°C). . . . . . . . . . . . . . 11

CS (7 V < V_CC< 18 V; -40 °C < T_j< 150 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Operative condition - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

On-state fault conditions - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Off-state - truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . . 24

Thermal model for junction temperature calculation in steady-state conditions\ . . . . . . . . 29

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SO-16N carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DocID028092 Rev 4

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3

List of figures

VNH7100AS

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

T

_DSTKON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Low-side turn-on delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Time to shutdown for the low-side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Input reset time for HSD - fault unlatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. Input reset time for LSD - fault unlatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11. OFF-state diagnostic delay time from rising edge of V_OUT(t_{D_VOL}). . . . . . . . . . . . . . . . . . 17

Figure 12. Normal operative conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 13. OUT shorted to ground and short clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 14. OUT shorted to Vcc and short clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15. Application schematic with reverse battery protection connected to Vbatt. . . . . . . . . . . . . 22

Figure 16. Application schematic with reverse battery protection connected to GND . . . . . . . . . . . . . 22

Figure 17. Suggested PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 18. Half-bridge configuration (case a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 19. Half-bridge configuration (case b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 20. Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 21. PCB layout (top and bottom): footprint, 2+2+2 cm², 8+8+8 cm². . . . . . . . . . . . . . . . . . . . 27

Figure 22. PCB 4 layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 23. Chipset configuration configuration in steady state conditions . . . . . . . . . . . . . . . . . . . . . . 28

Figure 24. Auto and mutual R_thj-ambvs. PCB heat-sink area in open box free air condition . . . . . . . . 29

Figure 25. HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 26. LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 27. Electrical equivalent model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 28. SO-16N package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 29. SO-16N reel 13” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 30. SO-16N carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 31. SO-16N schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 32. SO-16N marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4/38

DocID028092 Rev 4

VNH7100AS

Block diagram and pin description

1

Block diagram and pin description

Figure 1. Block diagram

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Table 2. Block description

Description

Name

Allows the turn-on and the turn-off of the high-side and the

low-side switches according to the truth table.

Logic control

Undervoltage

Shuts down the device for battery voltage lower than 4 V.

Protect the high-side and the low-side switches from the

high voltage on the battery line.

High-side and low-side clamp voltage

Drive the gate of the concerned switch to allow a proper

R_onfor the leg of the bridge.

High-side and low-side driver

Current limitation

Limits the motor current in case of short circuit.

In case of short-circuit with the increase of the junction

temperature, it shuts down the concerned driver to prevent

degradation and to protect the die.

High-side and low-side overtemperature

protection

Detects when low side current exceeds shutdown current

and latches off the concerned Low side.

Low-side overload detector

DocID028092 Rev 4

5/38

37

Block diagram and pin description

VNH7100AS

Table 2. Block description (continued)

Description

Name

Signalizes the abnormal behavior of the switch through

MultiSense pin.

Fault detection

Limits the power dissipation of the high-side driver inside

safe range in case of short to ground condition.

Power limitation

Figure 2. Configuration diagram (top view)

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Table 3. Pin definitions and functions

Function

Pin N°

Symbol

1, 16

2, 15

3

GND_A

OUT_A

IN_A

Source of low-side switch A

Source of high-side switch A / drain of low-side switch A

Clockwise input

4, 5, 12

6

V_CC

Power supply voltage

IN_B

Counter clockwise input

7, 10

8, 9

OUT_B

GND_B

Source of high-side switch B / drain of low-side switch B

Source of low-side switch B

Voltage controlled input pin with hysteresis, CMOS compatible. Gates

of low-side FETS get modulated by the PWM signal during their on

phase allowing speed control of the motor. Active high.

11

13

14

PWM

CS

Multiplexed analog sense output pin; it delivers a current proportional

to the motor current.

Active high compatible with 3 V and 5 V CMOS outputs pin; in

combination with IN_A, IN_B, it addresses the CurrentSense information

delivered to the micro according to the operative truth table.

SEL₀

6/38

DocID028092 Rev 4

VNH7100AS

Electrical specifications

2

Electrical specifications

Figure 3. Current and voltage conventions

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2.1

Absolute maximum ratings

Stressing the device above the rating listed in Table 4: Absolute maximum ratings may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability.

Table 4. Absolute maximum ratings

Symbol

Parameter

Value

Unit

V_CC

-V_CC

I_max

I_R

Supply voltage

38

V

A

Reverse DC Supply Voltage

0.3

Internally limited

-15

Maximum output current (continuous)

Reverse output current (continuous)

Maximum transient supply voltage (ISO 16750-2:2010

Test B clamped to 40 V; R_L= 4 Ω)

V_CCPK

V_CCJS

40

28

V

Maximum jump start voltage for single pulse short circuit

protection

I_IN

Input current (IN_Aand IN_Bpins)

-1 to 10

10

mA

I_SEL0

I_PWM

SEL₀DC input current

PWM input current

CS pin DC output current (V_GND= V_CCand V_SENSE< 0 V)

CS pin DC output current in reverse (V_CC< 0 V)

I_SENSE

mA

-20

DocID028092 Rev 4

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37

Electrical specifications

Symbol

VNH7100AS

Unit

Table 4. Absolute maximum ratings (continued)

Parameter

Value

Electrostatic discharge

(Human body model: R = 1.5 kΩ; C = 100 pF)

– IN_A,IN_B, PWM

2

4

V_ESD

– SEL₀

kV

– CS

– V_CC

– Output

V_ESD

T_c

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

750

V

-40 to 150

-55 to 150

°C

T_STG

2.2

Thermal data

Table 5. Thermal data

Parameter

Symbol

Max. value

Unit

HSD

LSD

32

45

°C/W

R_thj-pinThermal resistance junction-pin

R_thj-ambThermal resistance junction-ambient (JEDEC JESD 51-2)⁽¹⁾

R_thj-ambThermal resistance junction-ambient (JEDEC JESD 51-2)⁽²⁾

See Figure 24 °C/W

HSD

LSD

40.7

55.4

°C/W

1. Device mounted on two-layers 2s0p PCB.

2. Device mounted on four-layers 2s2p PCB.

8/38

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VNH7100AS

Electrical specifications

2.3

Electrical characteristics

Values specified in this section are for V_CC= 7 V up to 28 V; -40°C < T_j< 150°C, unless

otherwise specified.

Table 6. Power section

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

Operating supply

voltage

V_CC

4

28

1

V

Off-state (standby)

µA

IN_A= IN_B= 0; SEL₀= 0;

PWM = 0; T_j= 25 °C; V_CC= 13 V;

Off-state (standby)

IN_A= IN_B= 0; SEL₀= 0;

PWM = 0; V_CC= 13 V; T_j= 85°C

1

3

µA

Off-state (standby)

IN_A= IN_B= 0; SEL₀= 0;

PWM = 0; V_CC= 13 V; T_j= 125 °C

I_S

Supply current

Off-state (no standby)

2

4

6

mA

IN_A= IN_B= 0; SEL₀= 5 V;

PWM= 0

On-state: IN_Aor IN_B= 5 V;

PWM = 0 or PWM = 5; SEL₀= X

3.5

V

_CC= 13 V;

Standby mode blanking

time

(1)

t_{D_STBY}

IN_A= IN_B= PMW = 0 V;

V_SEL0from 5 V to 0 V

0.2

1

1.8

ms

I

_OUT= 2.5 A; T_j= 25°C

60

mΩ

Static high-side

resistance

R_ONHS

I_OUT= 2.5 A; T_j= -40 to 150°C

I_OUT= 2.5 A; T_j= 25°C

120 mΩ

mΩ

40

Static low-side

resistance

R_ONLS

I

_OUT= 2.5 A; T_j= -40°C to 150°C

80

mΩ

Free-wheeling diode

forward voltage

V_f

I_OUT= -2.5 A; T_j= 150°C

0.7

0.9

V

IN_A= IN_B= 0; PWM = 0;

0

0.5

3

µA

V

_CC= 13 V; T_j= 25 °C

Off-state output current

of one leg

I_L(off)

IN_A= IN_B= 0; PWM = 0;

V_CC= 13 V; T_j= 125 °C

Off-state output current

I_{L(off_h)}of one leg with other

HSD on

IN_A= 0; IN_B= 5 V; PWM = 0;

V_CC= 13 V

20

60

µA

1. To power on the device from the standby, it is recommended to:

— toggle INA or INB from 0 to 1 first to come out from STBY mode

— toggle PWM from 0 to 1 with a delay of 20 µs

this avoids any over-stress on the device in case of existing short-to-battery.

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37

Electrical specifications

VNH7100AS

Table 7. Logic inputs (IN_A, IN_B, PWM) (V_CC= 7 V up to 28 V; -40°C < T_j< 150°C)

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

V_IL

V_IH

Input low level voltage

Input high level voltage

Input hysteresis voltage

0.9

V

2.1

0.2

5.3

V_IHYST

V

I_IN= 1 mA

7.2

V

V_ICL

Input clamp voltage

I_IN= -1 mA

V_IN= 0.9 V

V_IN= 2.1 V

-0.7

V

I_INL

I_INH

Input current

1

µA

10

SEL₀(V_CC= 7 V up to 18 V; -40°C < T_j< 150°C)

V_SELL

I_SELL

V_SELH

I_SELH

Input low level voltage

Low level input current

Input high level voltage

High level input current

0.9

V

µA

V

V_SEL= 0.9 V

V_SEL= 2.1 V

1

2.1

10

µA

V

V_SEL(hyst)Input hysteresis voltage

0.2

5.3

I

_SEL= 1 mA

I_SEL= -1 mA

PWM (V_CC= 7 V up to 28 V; -40°C < T_j< 150°C)

7.5

V

V_SELCL

Input clamp voltage

-0.8

V

V_PWM

I_PWM

V_PWM

I_PWMH

Input low level voltage

Low level input current

Input high level voltage

High level input current

0.9

V

µA

V

V_PWM= 0.9 V

V_PWM= 2.1 V

1

2.1

10

µA

V

V_PWM(hyst)Input hysteresis voltage

0.2

5.3

I

_PWM= 1 mA

_PWM= -1 mA

7.2

V

V_PMWCLInput clamp voltage

I

-0.7

V

Table 8. Switching (V_CC= 13 V; R_LOAD= 5.2 Ω)

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

f⁽¹⁾

t_d(on)

t_d(off)

t_r

PWM frequency

Turn-on delay time

Turn-off delay time

Rise time

0

20

kHz

µs

Input rise time < 1µs (see Figure 6)

See Figure 5

20

13

1

µs

2

µs

t_f

Fall time

See Figure 5

1

µs

Low-side turn-on delay

time

t_cross

Input rise time < 1 µs (see Figure 7) 40 150 350

µs

1. Parameter guaranteed by design and characterization; not subjected to production test.

10/38

DocID028092 Rev 4

VNH7100AS

Electrical specifications

Table 9. Protections and diagnostics (V_CC= 7 V up to 18 V; -40°C < T_j< 150°C)

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

V_USD

Undervoltage shutdown

4

5

V

Undervoltage shutdown

reset

V_USDreset

V_USDHyst

Undervolatge shutdown

Hysteresis

0.4

V

High-side current

limitation

I_{LIM_H}

I_{SD_LS}

t_{SD_LS}

12

14

18

22

5

24

30

A

Shutdown LS current

Time to shutdown for the V_INA= V_INB= 0 V;

low-side

µs

PWM = 5 V (see Figure 8)

High-side clamp voltage

(V_CCto OUT_A= 0 or

OUT_B= 0)

I_OUT= 100 mA;

t_CLAMP= 1 ms

V_{CL_HSD}

38

46

V

Low-side clamp voltage

(OUT_A= V_CCor

OUT_B= V_CCto GND)

I_OUT= 100 mA;

t_CLAMP= 1 ms

V_{CL_LSD}

High-side thermal

shutdown temperature

T_{TSD_HS}

T_{TR_HS}

IN_x= 2.1 V

150 175 200 °C

High-side thermal reset

temperature

135

°C

High-side thermal

T_{HYST_HS}

hysteresis (T_{SD_HS}

T_{R_HS}

-

7

)

Low-side thermal

shutdown temperature

T_{TSD_LS}

V_CL

IN_x= 0 V

_OUT= 100 mA;

150 175 200 °C

Total clamp voltage

(V_CCto GND)

I

38

2

46

3

52

4

V

t_CLAMP= 1 ms

IN_A= IN_B= 0; PWM = 0;

OFF-state open-load

voltage detection

threshold

V

_SEL0= 5 V for CHA;

V_OL

V_SEL0= 0 V and within

t_{D_STBY}for CHB

IN_A= IN_B= 0; V_OUTx= V_OL

;

OFF-state output sink

current

PWM = 0 V; V_SEL0= 5 V for

CHA; V_SEL0= 0 V and within

I_L(off2)

-100

40

-15

µA

t_{D_STBY}for CHB

OFF-state diagnostic

delay time from falling

edge of INPUT (see

Figure 4)

IN_A= 5 V to 0 V; IN_B= 0 V;

V_SEL0= 5 V; I_OUT= 0 A;

t_DSTKON

150 350 µs

V_OUTA= 4 V; PWM = 0 V

IN_A= IN_B= 0 V; PWM = 0 V;

_OUTx= 0 V to 4 V;

V_SEL0= 5 V for CHA;

V_SEL0= 0 V and within

OFF-state diagnostic

delay time from rising

edge of V_OUT(see

Figure 11)

V

(1)

t_{D_VOL}

5

30

µs

t_{D_STBY}for CHB

DocID028092 Rev 4

11/38

37

Electrical specifications

VNH7100AS

Table 9. Protections and diagnostics (V_CC= 7 V up to 18 V; -40°C < T_j< 150°C)

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

Input reset time for high-

side fault unlatch (see

Figure 9)

V

_INx= 5 V to 0 V; HSDx

(1)

t_{Latch_RST_HD}

3

10

20

µs

faulting

Input reset time for low-

side fault unlatch (see

Figure 10)

V

_INx= 0 V to 5 V; LSDx

(1)

t_{Latch_RST_LS}

faulting

1. Parameter guaranteed by design and characterization; not subjected to production test.

Table 10. CS (7 V < V_CC< 18 V; -40 °C < T_j< 150 °C)

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

V_CC= 18 V; I_SENSE= -5 mA

11

V

MultiSense clamp

voltage

V_{SENSE_CL}

V_CC= 18 V; I_SENSE= 5 mA

-13

-9

I_OUT= 0.05 A; V_SENSE= 0.5 V;

T_j= -40°C to 150°C

K₀

K₁

K₂

K₃

I_{OUT SENSE}

I_OUT/I_SENSE

/I

420

I_OUT= 0.2 A; V_SENSE= 0.5 V;

T_j= -40°C to 150°C

710 1190 1670

980 1120 1247

990 1120 1235

I_OUT= 2.5 A; V_SENSE= 4 V;

T_j= -40°C to 150°C

I_OUT= 4 A; V_SENSE= 4 V;

T_j= -40°C to 150°C

Analog sense current I_OUT= 0.05 A; V_SENSE= 0.5 V;

drift T_j= -40°C to 150°C

(1)(2)

dK₀/K₀

-25

-21

-5

25

21

5

%

Analog sense current I_OUT= 0.2 A; V_SENSE= 0.5 V;

drift T_j= -40°C to 150°C

(1)(2)

dK₁/K₁

Analog sense current I_OUT= 2.5 A; V_SENSE= 4 V;

drift T_j= -40°C to 150°C

(1)(2)

dK₂/K₂

Analog sense current I_OUT= 4 A; V_SENSE= 4 V;

(1)(2)

dK₃/K₃

-4

4

drift

T_j= -40°C to 150°C

V

_CC= 7 V; R_SENSE= 10 kΩ;

Max analog sense

output voltage

V_{SENSE_SAT}

V_SEL0= 5 V; I_OUTA= 4 A;

_INA= 5 V; PWM = 0; T_j= 150 °C

5

0

V

I_OUT= 0 A; V_SENSE= 0 V;

IN_x= 0 V; SEL₀= 0;

T_j= -40°C to 150°C (standby)

0.5 µA

MultiSense leakage I_OUT= 0 A; V_SENSE= 0 V;

I_SENSE0

current

IN_x= 0 V; SEL₀= 5 V;

T_j= -40°C to 150°C (no standby)

0

IN_x= 5 V; PWM = 5 V:

T_j= -40°C to 150°C; I_OUT= 0 A

5

µA

12/38

DocID028092 Rev 4

VNH7100AS

Electrical specifications

Table 10. CS (7 V < V_CC< 18 V; -40 °C < T_j< 150 °C) (continued)

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

V_CC= 13 V; R_SENSE= 1 kΩ

MultiSense output

voltage in fault

condition

– E.g: OUT_Ain open-load

IN_A= 0 V; I_OUTA= 0 A;

V_OUTA= 4 V; V_SEL0= 5 V

V_SENSEH

5

7

V

V_INA= 5 V; V_INB= 0 V;

V_SEL0= 5 V; R_SENSE= 2.7 kΩ

I_OUT= 2.5 A

Output Voltage for

MultiSense shutdown

(2)

V_{OUT_MSD}

5

V

mA

A

V_CC= 13 V; V_SENSE= 4 V;

V_INA= 5 V; V_INB= 0 V;

V_SEL0= 5 V; T_j= 150 °C

MultiSense

saturation current

(2)

I_{SENSE_SAT}

5.8

7

V_CC= 13 V; V_SENSE= 4 V;

V_INA= 5 V; V_INB= 0 V;

V_SEL0= 5 V; I_OUT= 7 A; T_j= 150°C

Output saturation

current

(2)

I_{OUT_SAT}

MultiSense output

voltage in fault

condition

I_SENSEH

V_CC= 13 V; V_SENSE= V_SENSEH

7

20

30 mA

1. Analog sense current drift is deviation of factor K for a given device over (-40 °C to 150 °C and

9 V < V < 18 V) with respect to its value measured at T = 25 °C, V = 13 V.

CC

j

CC

2. Parameter guaranteed by design and characterization; not subjected to production test.

Figure 4. T_DSTKON

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DocID028092 Rev 4

13/38

37

Electrical specifications

VNH7100AS

Figure 5. Definition of the low-side switching times

PWM

t

V_{OUTA, B}

90%

80%

t

f

t

10%

20%

r

Figure 6. Definition of the high-side switching times

V_INA

t_D(on)

t_D(off)

t

V_OUTA

90%

10%

t

14/38

DocID028092 Rev 4

VNH7100AS

Electrical specifications

Figure 7. Low-side turn-on delay time

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DocID028092 Rev 4

15/38

37

Electrical specifications

VNH7100AS

Figure 9. Input reset time for HSD - fault unlatch

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16/38

DocID028092 Rev 4

VNH7100AS

Electrical specifications

Figure 11. OFF-state diagnostic delay time from rising edge of V_OUT(t_{D_VOL}

)

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DocID028092 Rev 4

17/38

37

Electrical specifications

VNH7100AS

Table 11. Operative condition - truth table

Pin status HSDs and LDSs Status

IN_A

IN_B

SEL₀

PWM

CS

HSDA

LSDA

HSDB

LSDB

Current

Monitoring

HSDA

1

x

On

Off

On

Off

Current

Monitoring

0

1

HSDB

1

0

Current

Monitoring

HSDA

On

Off

On

Off

1

0

1

0

1

0

1

On

Off

On

Off

On

Off

On

Off

1

0

1

0

1

Hi-Z

Current

Monitoring

0

1

0

1

Off

On

Off

On

HSDB

Hi-Z

1

0

1

Off

0

x⁽¹⁾

0⁽²⁾

1. Refer to Table 13: Off-state - truth table

2. For IN =IN =SEL = PWM = 0, the device enters in standby after t

D_STBY

A

B

0

Table 12. On-state fault conditions - truth table

IN_A

IN_B

SEL₀

PWM

Out_A

Out_B

CS

Fault description

On state diagnostic

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

H

X

H

L

H

X

L

V_SENSEH

Short to V_BATTon Leg B

Short to V_BATTon Leg A

Out B short to GND

Out A short to V_CC

X

1

H

L

1

Out B short to V_CC

X

Out A short to GND

Short to GND on Leg B

Short to GND on Leg A

X

L

X

18/38

DocID028092 Rev 4

VNH7100AS

Electrical specifications

Description

Table 13. Off-state - truth table

IN_A

IN_B

SEL₀

PWM

Out_A

Out_B

CS

Off-state diagnostic

Case 1. Out_Ashorted to V_CCif no

pull-up is applied

Case 2. No open-load in full bridge

configuration with an external pull-

up on Out_B

V_outA>V_OL

x

V_SENSEH

Case 3. open-load in half bridge

configuration with an external pull-

up on Out_A(motor connected

between Out_Aand Ground)

1

Case 1. Open-load in full Bridge

configuration with an external pull-

up on Out_B

V_outA<V_OL

x

Hi-Z

V_SENSEH

Hi-Z

Case 2. No open-load in half Bridge

configuration with external pull-up

on Out_A(motor connected between

Out_Aand Ground)

0

Case 1. Out_Bshorted to V_CCif

no pull-up is applied

Case 2. No open-load in full

bridge configuration with

external pull-up on Out_A

Case 3. Open-load in half bridge

configuration with external pull-up

on Out_B(motor connected between

Out_Band Ground)

X

V_outB>V_OL

0⁽¹⁾⁽²⁾

Case1. Open-load in full Bridge

configuration with an external pull-

up on Out_A

X

V_outB<V_OL

Case 2. No open-load in half Bridge

configuration with external pull-up

on Out_B(motor connected between

Out_Band Ground)

1. The device enters standby mode after t

D_STBY

2. To power on the device from the standby, it is recommended to toggle IN or IN from 0 to 1 first and then PWM from 0 to 1

A

B

to avoid any over-stress on the device in case of short-to-battery.

DocID028092 Rev 4

19/38

37

Electrical specifications

VNH7100AS

2.4

Waveforms

Figure 12. Normal operative conditions

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20/38

DocID028092 Rev 4

VNH7100AS

Electrical specifications

Figure 14. OUT shorted to Vcc and short clearing

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DocID028092 Rev 4

21/38

37

Application information

VNH7100AS

3

Application information

Here following there is the typical application schematic suggested for a proper operation of

the device in DC or PWM conditions.

Figure 15. Application schematic with reverse battery protection connected to Vbatt

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Figure 16. Application schematic with reverse battery protection connected to GND

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22/38

DocID028092 Rev 4

VNH7100AS

Application information

Figure 17. Suggested PCB layout

Note:

PCB layout recommendation:

Optimized connection (short) between Drain LSD and Source HSD

Optimized GNDa and GNDb connection (symmetric connection)

3.1

Reverse battery protection

Three possible solutions can be considered:

•

A Schottky diode D connected to V_CCpin

•

An N-channel MOSFET connected to the GND pin

A P-channel MOSFET connected to the V_CCpin

In case the reverse battery protection is not present, the device sustains no more than -15 A

because of the two Body diodes of the Power MOSFETs. Additionally, in reverse battery

condition the I/Os of the device is pulled down to the V_CCline (approximately -1.5 V).

Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If

I_Rmaxis the maximum target reverse current through microcontroller I/Os, series resistor is:

V

– V

CC

IOs

R = ------------------------------

I

Rmax

3.2

OFF-state open-load detection – External circuitry

dimensioning

The detection of an open-load in off state requires an external circuitry to be connected

between Output and V_BATT

.

For the detection it is necessary to put one network on each leg in case of Half Bridge

operation or one network on one of the output in case of full bridge (see Table 13: Off-state -

truth table).

The external circuitry is made up by an external pull-up resistor R_{pull_up}connecting the

output to a positive supply voltage V_PU(V_Batt).

DocID028092 Rev 4

23/38

37

Application information

VNH7100AS

It is preferable to switch-off V_PUby using an external pull_up switch to reduce the overall

standby current during he module standby mode.

R

_{pull_up}must be dimensioned to ensure that in normal operative conditions V_OUT> V_OLmax

.

To satisfy this condition the R_{pull_up}must be selected according to:

•

if the device is used in half bridge configuration, the equation is:

V

– V

OLmax

BATTmin

R

< -------------------------------------------------------

pull_up

I

L(off2)min[@VOLmax]

if the device is used in H-bridge configuration, the equation is:

V

– V

OLmax

BATTmin

R

< -------------------------------------------------------------

pull_up

2 × I

L(off2)min[@VOLmax]

3.3

Immunity against transient electrical disturbances

The immunity of the device against transient electrical emissions, conducted along the

supply lines and injected into the V_CCpin, is tested in accordance with ISO7637-2:2011 (E)

and ISO 16750-2:2010.

The related function performance status classification is shown in Table 14.

Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and

in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device

only, without components and accessed through V_CCand GND terminals.

Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as

follows: “The function does not perform as designed during the test but returns automatically

to normal operation after the test”.

Table 14. ISO 7637-2 - electrical transient conduction along supply line

Test pulse severity

Test

Pulse

Minimum

number of

pulses or test

time

level with Status II

functionalperformance

status

Burst cycle / pulse

repetition time

Pulse duration and

pulse generator

internal impedance

2011(E)

(1)

Level

U_S

min

max

1

III

IV

-112 V

+55 V

-220 V

+150 V

-7 V

500 pulses

1h

0,5 s

0,2 s

2ms, 10 Ω

50µs, 2 Ω

2a

3a

3b

4⁽²⁾

5 s

90 ms

100 ms

0.1µs, 50 Ω

100ms, 0.0 1Ω

1h

1 pulse

Load dump according to ISO 16750-2:2010

Test B⁽³⁾

40 V

5 pulse

1 min

400 ms, 2 Ω

1.

U

is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.

S

24/38

DocID028092 Rev 4

VNH7100AS

Application information

2. Test pulse from ISO 7637-2:2004(E).

3. With 40 V external suppressor referred to ground (-40°C < T < 150°C).

j

3.4

Device configurations

Figure 18. Half-bridge configuration (case a)

9FF

,1%

,1$

3:0

6(/ꢃ

&6

2XWꢀ$

2XWꢀ%

0

*1'

("1(ꢆꢃꢀꢃꢁꢉꢁꢆꢀꢂ$'5

Note:

The VNH7100AS can be used in half bridge configuration as the two legs can be

independently driven. The SEL0 pin can be used to address the diagnostic on the CS

according to the operative truth table.

Figure 19. Half-bridge configuration (case b)

9FF

,1$

,1%

,1$

,1%

6(/ꢃ

&6

3:0

2XWꢀ%

3:0

2XWꢀ%

6(/ꢃ

&6

0

2XWꢀ$

*1'

("1(ꢊꢀꢀꢃꢁꢉꢁꢌꢀꢇ$'5

Note:

The VNH7100AS can be used in applications where an half-bridge with a resistance of

50 mΩ per leg is needed.

DocID028092 Rev 4

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37

Application information

VNH7100AS

Figure 20. Multi-motors configuration

9FF

,1$

3:0

6(/ꢃ

&6

,1%

,1$

3:0

6(/ꢃ

&6

,1%

0

2XWꢀ$

2XWꢀ%

2XWꢀ$

*1'

0

("1(ꢊꢀꢀꢃꢁꢉꢁꢌꢁꢀ$'5

Note:

The VNH7100AS can easily be designed in multi motor driving configuration in the

applications where only one motor at a time must be activated. The SEL0 pin can be used to

read the diagnostic on the CS according to the operative truth table.

26/38

DocID028092 Rev 4

VNH7100AS

Package and PCB thermal data

4

Package and PCB thermal data

4.1

SO16-N thermal data

Figure 21. PCB layout (top and bottom): footprint, 2+2+2 cm², 8+8+8 cm²

DocID028092 Rev 4

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37

Package and PCB thermal data

VNH7100AS

Figure 22. PCB 4 layer

Note:

Board finish thickness 1.6 mm +/- 10%; Board double layer and four layers; Board

dimension 77x86 mm; Board Material FR4; Cu thickness 0.070mm (outer layers); Cu

thickness 0.035mm (inner layers); Thermal vias separation 1.2 mm; Thermal via diameter

0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm.

4.2

Package thermal data

4.2.1

Thermal characterization in steady state conditions

Figure 23. Chipset configuration configuration in steady state conditions

$IJQꢀꢁ

3_UI#

3_UI"#

$IJQꢀꢂ

3_UI"

3_UI"$

3_UI#$

$IJQꢀꢃ

3_UI$

("1(ꢆꢃꢀꢃꢁꢉꢀꢃꢁꢂ$'5

28/38

DocID028092 Rev 4

VNH7100AS

Package and PCB thermal data

Figure 24. Auto and mutual R_thj-ambvs. PCB heat-sink area in open box free air

condition

ꢅꢁꢀ

5WK$

5WK%ꢆ ꢆ5WK&

ꢅꢀꢀ

5WK$%ꢆ ꢆ5WK$&

5WK%&

ꢄꢀ

ꢃꢀ

ꢂꢀ

ꢁꢀ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅꢀ

FP^ꢁRIꢃ&Xꢃ$UHDꢃꢅUHIHUꢃWRꢃ3&%ꢃꢁ/D\HUꢃOD\RXWꢆ

("1(ꢆꢃꢀꢃꢁꢉꢀꢃꢆꢌ$'5

Table 15. Thermal model for junction temperature calculation in steady-state

conditions\

Chip 1 Chip 2 Chip 3

Tjchip1

Tjchip2

Tjchip3

P_dchip1• R_thA+ P_dchip3P_dchip1• R_thAB+ P_dchip3P_dchip1• R_thAC+ P_dchip3

ON

OFF

ON

• R_thAC+ T_amb• R_thBC+ T_amb• R_thC+ T_amb

P_dchip1• R_thA+ P_dchip2P_dchip1• R_thAB+ P_dchip2P_dchip1• R_thAC+ P_dchip2

ON

OFF

• R_thAB+ T_amb

• R_thB+ T_amb

• R_thBC+ T_amb

OFF

P_dchip1• R_thA+ T_amb

P_dchip1• R_thAB+ T_amb

P_dchip1• R_thAC+ T_amb

P

_dchip1• R_thA+ (P_dchip2P_dchip2• R_thB+ P_dchip1• P_dchip1• R_thAB+ P_dchip2

ON

+ P_dchip3) • R_thAB

T_amb

+

R_thAB+ P_dchip3• R_thBC• R_thBC+ P_dchip3• R_thC

+ T_amb+ T_amb

4.2.2

Thermal characterization during transients

T_hs= Pd_hs• Z_hs+ Z_hsls• (Pd_lsA+ Pd_lsB) + T_amb

T_lsA= Pd_lsA• Z_ls+ Pd_hs• Z_hsls+ Pd_lsB• Z_lsls+ T_amb

T_lsB= Pd_lsB• Z_ls+ Pd_hs• Z_hsls+ Pd_lsA• Z_lsls+ T_amb

DocID028092 Rev 4

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37

Package and PCB thermal data

VNH7100AS

Figure 25. HSD thermal impedance junction ambient single pulse

=7+ꢆꢋꢆ+6'ꢆ#ꢆFXꢆDUHD

&ꢈ:

ꢅꢀꢀ

+6'ꢋIRRWSULQW

+6'ꢋꢁꢆFPAꢁꢆ&X

+6'ꢋꢄꢆFPAꢁꢆ&X

+6'ꢋꢂ/D\HU

+V/V'ꢋIRRWSULQW

+V/V'ꢋꢁꢆFPAꢁꢆ&X

+V/V'ꢋꢄꢆFPAꢁꢆ&X

+V/V'ꢋꢂ/D\HU

=

KV

ꢅꢀ

ꢅ

ꢀꢇꢅ

=

KVOV

ꢀꢇꢀꢅ

ꢀꢇꢀꢀꢀꢅ

ꢀꢇꢀꢀꢅ

ꢀꢇꢀꢅ

ꢀꢇꢅ

ꢅ

ꢅꢀ

ꢅꢀꢀ

ꢅꢀꢀꢀ

WLPHꢆꢉVHFꢊ

("1(ꢆꢃꢀꢃꢁꢉꢁꢀꢀꢁ$'5

Figure 26. LSD thermal impedance junction ambient single pulse

=7+ꢆꢋ/6'ꢆ#ꢆFXꢆDUHD

&ꢈ:

ꢅꢀꢀ

/6'ꢋIRRWSULQW

/6'ꢋꢁꢆFPAꢁꢆ&X

/6'ꢋꢄꢆFPAꢁꢆ&X

/6'ꢋꢂ/D\HU

/V/V'ꢋIRRWSULQW

/V/V'ꢋꢁꢆFPAꢁꢆ&X

/V/V'ꢋꢄꢆFPAꢁꢆ&X

/V/V'ꢋꢂ/D\HU

=

OV

ꢅꢀ

ꢅ

ꢀꢇꢅ

=

OVOV

ꢀꢇꢀꢅ

ꢀꢇꢀꢀꢀꢅ

ꢀꢇꢀꢀꢅ

ꢀꢇꢀꢅ

ꢀꢇꢅ

ꢅ

ꢅꢀ

ꢅꢀꢀ

ꢅꢀꢀꢀ

WLPHꢆꢉVHFꢊ

("1(ꢆꢃꢀꢃꢁꢉꢁꢀꢀꢂ$'5

30/38

DocID028092 Rev 4

VNH7100AS

Package and PCB thermal data

Figure 27. Electrical equivalent model

Table 16. Thermal parameters

2

Area/island (cm²)

FP

8

4L

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

R7 (°C/W)

R8 (°C/W)

R9 (°C/W)

R10 (°C/W)

R11 (°C/W)

R12 (°C/W)

R13 (°C/W)

R14 (°C/W)

R15 (°C/W)

R16 (°C/W)

R17 (°C/W)

R18 (°C/W)

R19 (°C/W)

R20 (°C/W)

5.3

12

5.3

12

5.3

12

5.3

12

30

25

30

42

12

2

85

45

30

17

5.3

5.1

12

5.3

5.1

12

5.3

5.1

12

5.3

5.1

12

30

42

68

52

48

10

75

80

60

26

5.1

12

5.1

12

5.1

12

5.1

12

30

42

68

52

48

10

75

80

60

26

120

180

100

170

100

170

100

170

DocID028092 Rev 4

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37

Package and PCB thermal data

Area/island (cm²)

VNH7100AS

4L

Table 16. Thermal parameters (continued)

FP

2

8

C1 (W·s/°C)

C2 (W·s/°C)

C3 (W·s/°C)

C4 (W·s/°C)

C5 (W·s/°C)

C6 (W·s/°C)

C7 (W·s/°C)

C8 (W·s/°C)

C9 (W·s/°C)

C10 (W·s/°C)

C11 (W·s/°C)

C12 (W·s/°C)

C13 (W·s/°C)

C14 (W·s/°C)

C15 (W·s/°C)

C16 (W·s/°C)

0.00065

0.018

0.08

0.2

0.00065

0.018

0.1

0.00065

0.018

0.1

0.00065

0.018

0.1

0.5

1

2

1.5

2

6

12

0.00065

0.001

0.02

0.06

0.08

1

0.00065

0.001

0.02

0.06

0.1

0.00065

0.001

0.02

0.06

0.2

0.00065

0.001

0.02

0.06

0.5

2.5

3

6

0.00065

0.02

0.06

0.08

1

0.00065

0.02

0.06

0.1

0.00065

0.02

0.06

0.2

0.00065

0.02

0.06

0.5

2.5

3

6

32/38

DocID028092 Rev 4

VNH7100AS

Package and packing information

5

Package and packing information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK^®packages, depending on their level of environmental compliance. ECOPACK^®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK^®is an ST trademark.

5.1

SO-16N mechanical data

Figure 28. SO-16N package dimensions

("1($'5ꢀꢀꢂꢁꢂ

DocID028092 Rev 4

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37

Package and packing information

VNH7100AS

Table 17. SO-16N mechanical data

Millimeters

Symbol

Min.

Typ.

Max.

1.75

0.25

A

A1

A2

b

0.10

1.25

0.31

0.17

9.80

5.80

3.80

0.51

0.25

10.00

6.20

4.00

c

D

9.90

6.00

3.90

1.27

E

E1

e

h

0.25

0.40

0

0.50

1.27

8

L

k

ccc

0.10

5.2

SO-16N packing information

Figure 29. SO-16N reel 13”

"DDFTTꢅ)PMFꢅBU

4MPUꢅ-PDBUJPO

ꢍꢅꢅꢅꢅꢇꢀꢅNNꢅNJOꢎꢏ

8ꢆ

/

%

"

$

8ꢁ

*GꢅQSFTFOUꢐ

UBQFꢅTMPUꢅJOꢅDPSF

GPSꢅUBQFꢅTUBSUꢑ

ꢆꢎꢉꢅNNꢅNJOꢎꢅXJEUIꢅY

ꢁꢀꢎꢀꢅNNꢅNJOꢎꢅEFQUI

#

5"1(ꢆꢀꢀꢇꢁꢉꢁꢌꢉꢉ$'5

34/38

DocID028092 Rev 4

VNH7100AS

Package and packing information

Table 18. Reel dimensions

Description

Value⁽¹⁾

Base quantity

2500

Bulk quantity

A (max)

2500

330

1.5

B (min)

C (+0.5, -0.2)

D (min)

13

20.2

100

16.4

22.4

N

W1 (+2 /-0)

W2 (max)

1. All dimensions are in mm.

Figure 30. SO-16N carrier tape

("1(ꢀꢂꢀꢈꢁꢉꢁꢆꢆꢃ$'5

Table 19. SO-16N carrier tape dimensions

Description

Value

A

0

6.55 ± 0.1

10.38 ± 0.1

2.10 ± 0.1

1.80 ± 0.1

7.50 ± 0.1

B

0

K

0

1

K

F

DocID028092 Rev 4

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37

Package and packing information

VNH7100AS

Table 19. SO-16N carrier tape dimensions (continued)

Description

Value

P

1

8.00 ± 0.1

W

16.00 ± 0.3

Figure 31. SO-16N schematic drawing of leader and trailer tape

5.3

SO-16N marking information

Figure 32. SO-16N marking information

.BSLJOHꢅBSFB

ꢁ

ꢆ

ꢊ

ꢇ

ꢉ

ꢌ

ꢈ

ꢂ

ꢃ ꢁꢀ ꢁꢁ ꢁꢆ

4QFDJBMꢀGVODUJPOꢀEJHJU

ꢄ&4ꢑꢅ&OHJOFFSJOHꢅTBNQMF

ꢒCMBOLꢓꢑꢅ$PNNFSDJBMꢅTBNQMF

40ꢄꢁꢌ/ꢅ501ꢅ7*&8ꢅ

ꢍOPUꢅJOꢅTDBMFꢏ

("1(ꢀꢂꢀꢈꢁꢉꢁꢉꢉꢂ$'5

Note:

Engineering Samples: these samples can be clearly identified by a dedicated special

symbol in the marking of each unit. These samples are intended to be used for electrical

compatibility evaluation only; usage for any other purpose may be agreed only upon written

authorization by ST. ST is not liable for any customer usage in production and/or in reliability

qualification trials.

Commercial Samples: fully qualified parts from ST standard production with no usage

restrictions.

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VNH7100AS

Revision history

6

Revision history

Table 20. Document revision history

Changes

Date

Revision

16-Jul-2015

1

Initial release.

Table 8: Switching (VCC = 13 V; RLOAD = 5.2 Ω):

– t_cross: updated values

Table 9: Protections and diagnostics (VCC = 7 V up to 18 V; -40°C < Tj

< 150°C):

01-Sep-2015

04-Sep-2015

2

3

– I_{SD_LS}, t_DSTKON: updated values

Table 10: CS (7 V < VCC < 18 V; -40 °C < Tj < 150 °C):

– K₂, K₃, I_{SENSE_SAT}: updated values

Table 4: Absolute maximum ratings:

– I_R: updated value

Table 4: Absolute maximum ratings:

– -I_GND: removed row

Updated Table 5: Thermal data

Table 6: Power section:

– V_f: updated parameter

07-Oct-2015

4

Updated Figure 9: Input reset time for HSD - fault unlatch and

Figure 10: Input reset time for LSD - fault unlatch

Added Section 2.4: Waveforms and Chapter 4: Package and PCB

thermal data

Updated Chapter 3: Application information

DocID028092 Rev 4

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37

VNH7100AS

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and

improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order

acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or

the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

38/38

DocID028092 Rev 4


型号：	VNH7100AS
厂家：	ST
描述：	Automotive fully integrated H-bridge motor driver
文件：	总38页 (文件大小：1772K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VNH7100AS [STMICROELECTRONICS]

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