SPM1005-1V8C [SUMIDA]
3.3V/5V Input 6A Output Power Supply in Inductor (PSI2) Module Thermal Shutdown;
| 型号： | SPM1005-1V8C |
| 厂家： | 
SUMIDA CORPORATION |
| 描述： | 3.3V/5V Input 6A Output Power Supply in Inductor (PSI2) Module Thermal Shutdown |
| 文件： | 总29页 (文件大小：2187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPM1005
3.3V/5V Input 6A Output Power Supply in Inductor (PSI2) Module
FEATURES
DESCRIPTION
Integrated Point of Load power module using PSI2
Power Supply in Inductor technology
Small footprint, low-profile, 11mm x 9mm x 3mm,
with LGA Package (0.63 mm Pads)
SPM1005 is an easy-to-use 6A output integrated Point of
Load (POL) power supply module. It contains integrated
power MOSFETs, driver, PWM controller, a high
performance inductor, input and output capacitors and
other passive components in one low profile LGA package
using PSI2 technology.
Efficiency up to 96%
High output current, 6A without derating at 85°C
ambient with no air flow
Only one input capacitor and one output capacitor are
needed for typical applications. There is no need for loop
compensation, sensitive PCB layout, inductor selection or
in-circuit production testing. Each module is fully tested.
Wide output voltage adjustment: 0.6V to 3.6V
Pre-bias startup capability
User adjustable switching frequency
Synchronization to external clock signal
Adjustable soft-start time for output voltage
Output voltage sequencing / tracking
Enable signal input and Power Good signal output
Programmable Under Voltage Lock Out (UVLO)
Output Over Current Protection (OCP)
Over temperature protection
SPM1005 integrated POL module series are offered in two
versions: universal output voltage version (SPM1005-Z)
and single voltage version. With the SPM1005-Z version,
the user can select the output voltage and switching
frequency with external resistors. The single voltage
versions provide fixed output voltage at 3.3V, 2.5V, 1.8V,
1.5V, 1.2V, 1.0V, 0.8V or 0.6V. The user can trim the
output voltage by ±10% using an external resistor.
Operating temperature range -40°C to 85°C
Qualified to IPC9592B, Class II
MSL3 and RoHS compliant
All SPM1005 models deliver full 6A load current without
derating at 85°C ambient temperature with no airflow.
Small size (11mm x 9mm) and low profile (3mm) allows
the SPM1005 to be placed very close to its load or on the
back side of the PCB for high density applications.
Sumida's PSI2 technology ensures optimal inductor
design, uniform temperature distribution and very low
temperature difference between case and IC die.
APPLICATIONS
Broadband and communications equipment
DSP and FPGA Point of Load applications
High density distributed power systems
Systems using PCI / PCI express / PXI express
Automated test and medical equipment
SIMPLIFIED APPLICATION
EFFICIENCY VS LOAD CURRENT
100
98
96
94
92
90
88
86
COMP
SS/TR
PWRGD
VIN
PHASE
VOUT
VOUT =1.8V
VIN= 2.95-6V
COUT
100uF
CIN
47uF
SPM1005 – 1V8
VSENSE
RT/CLK
Vin = 5 V, Vout = 3.3 V
Vin = 3.3 V, Vout = 1.8 V
84
82
80
EN
VADJ
ON/OFF
CONTROL
STSEL
PGND
AGND
0
1
2
3
4
5
6
Output Current (A)
Version 1.4
February 19, 2016
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SPM1005
ABSOLUTE MAXIMUM(1) RATINGS over operating temperature range (unless
otherwise noted)
VALUE
Unit
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.6
MAX
7
7
VIN
EN
VSENSE
COMP
PWRGD
SS / TR
STSEL
RT / CLK
VOUT
EN
RT / CLK
COMP
PWRGD
SS / TR
V
V
3
3
6
3
3
6
VIN
100
100
100
10
100
150
150
260
V
V
V
V
V
V
V
μA
μA
μA
mA
μA
°C
°C
°C
Input Voltage
Output Voltage
Source Current
Sink Current
Temperature
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering)
-40
-65
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the module. These are
stress ratings only, and functional operation of the module at these or any other conditions beyond those indicated under
recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods
may affect reliability.
Version 1.4
February 19, 2016
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SPM1005
ELECTRICAL CHARACTERISTICS:
The electrical characteristics are presented in two parts. Part 1 provides the electrical characteristics that are
common to all models and Part 2 provides the electrical characteristics that are specific to each model.
The electrical performance is based on the following conditions unless otherwise stated: 25°C ambient temperature,
no air flow; VIN = 5V, (1) VOUT = 1.8V, IOUT = 6A, CIN1 = 47μF ceramic, COUT = 2×47μF ceramic.
Part 1: Electrical Characteristics Common to All Models:
PARAMETERS
Output current
Input voltage
TEST CONDITIONS
TA = -40°C to 85°C, natural convection
Over IOUT range, -40°C to 85°C
Over IOUT range, -40°C to 85°C
Over IOUT range, -40°C to 85°C
MIN
0
2.95
2.6
2.3
TYP
MAX
6
6
3.0
2.7
UNIT
IOUT
VIN:
:
A
V
V
V
V
VSTART Startup voltage (1)
2.8
2.5
0.3
UVLO Under Voltage Lock Out (1)
Hysteresis between VSTART and UVLO (1) Over IOUT range
Set point accuracy
Temperature variation
Line regulation
TA = 25°C, IOUT = 3A
±1%
-40°C < TA < +85°C, IOUT = 3A
Over VIN range, TA = 25°C, IOUT = 3A
Over IOUT range, TA = 25°C, VIN = 5V
Includes set-point, line, load, temperature
variation
±0.3%
±0.2%
±0.2%
VOUT
Load regulation
Total variation
±3%
Output voltage ripple
20MHz bandwidth
20
9.0
1.25
mVpp
A
V
V
μA
ILIM
Current Limit Point
VEN-H
VEN-L
Istby
Enable control
Enable control
Input standby current
Enable high voltage
Enable low voltage
EN pin to AGND
Good
VOUT rising threshold
Fault
Good
VOUT falling threshold
Fault
Thermal shutdown
Thermal shutdown recovery hysteresis
Ceramic
open
1.0
100
-0.3
70
93%
105%
103%
91%
170
PWR Good:
°C
°C
Thermal shutdown
15
47
47
μF
μF
μF
μF
kHz
CIN: External input capacitor
Non-ceramic
Ceramic
Non-ceramic
220
200
100
650
2000
1000
COUT: External output capacitor
FS_MAX Maximum switching frequency
(1) With REN1 = 14.7k Ω and REN2 = 12.7k Ω as shown in Fig. 32.
Version 1.4
February 19, 2016
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SPM1005
Part 2: Electrical Characteristics for Each Individual Model:
SPM1005-Z (VOUT adjustable from 0.6V to 3.6V)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT(adj): Output voltage adjust range
Over IOUT range, TA = -40°C to 85°C
0.6
3.6
V
VOUT = 3.3V, IOUT = 3A
96.1%
94.2%
95.4%
92.3%
750
VIN = 5V
VOUT = 3.3V, IOUT = 6A
VOUT = 2.5V, IOUT = 3A
VOUT = 2.5V, IOUT = 6A
η
Efficiency
VIN = 3.3V
FS
Switching frequency(1)
RT = 127KΩ between RT/CLK and AGND
kHz
(1) 750kHz is suitable for 3.3V output, but lower switching frequencies are recommended for lower output voltage models.
See following tables for desired switching frequency, and refer to page 22 for information on adjusting the frequency.
SPM1005-3V3
PARAMETERS
VOUT(adj): Output voltage trim range
TEST CONDITIONS
Over IOUT range, TA = -40°C to 85°C
MIN
2.97
TYP
3.3
MAX
3.63
UNIT
V
VOUT = 3.3V, IOUT = 3A
VOUT = 3.3V, IOUT = 6A
96.1%
94.2%
750
η
Efficiency
VIN = 5V
FS
Switching frequency
kHz
SPM1005-2V5
PARAMETERS
VOUT(adj): Output voltage trim range
TEST CONDITIONS
Over IOUT range, TA = -40°C to 85°C
MIN
2.25
TYP
2.5
MAX
2.75
UNIT
V
VOUT = 2.5V, IOUT = 3A
94.4%
92.3%
95.4%
92.3%
650
VIN = 5V
VOUT = 2.5V, IOUT = 6A
VOUT = 2.5V, IOUT = 3A
VOUT = 2.5V, IOUT = 6A
η
Efficiency
VIN = 3.3V
FS
Switching frequency
kHz
SPM1005-1V8
PARAMETERS
VOUT(adj): Output voltage trim range
TEST CONDITIONS
Over IOUT range, TA = -40°C to 85°C
MIN
1.62
TYP
1.8
MAX
1.98
UNIT
V
VOUT = 1.8V, IOUT = 3A
92.2%
90.0%
93.3%
89.7%
600
VIN = 5V
VOUT = 1.8V, IOUT = 6A
VOUT = 1.8V, IOUT = 3A
VOUT = 1.8V, IOUT = 6A
η
Efficiency
VIN = 3.3V
FS
Switching frequency
kHz
SPM1005-1V5
PARAMETERS
VOUT(adj): Output voltage trim range
TEST CONDITIONS
Over IOUT range, TA = -40°C to 85°C
MIN
1.35
TYP
1.5
MAX
1.65
UNIT
V
VOUT = 1.5V, IOUT = 3A
91.3%
88.5%
91.7%
88.0%
550
VIN = 5V
VOUT = 1.5V, IOUT = 6A
VOUT = 1.5V, IOUT = 3A
VOUT = 1.5V, IOUT = 6A
η
Efficiency
VIN = 3.3V
FS
Switching frequency
kHz
Version 1.4
February 19, 2016
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SPM1005
SPM1005-1V2
PARAMETERS
VOUT(adj): Output voltage trim range
TEST CONDITIONS
Over IOUT range, TA = -40°C to 85°C
MIN
1.08
TYP
1.2
MAX
1.32
UNIT
V
VOUT = 1.2V, IOUT = 3A
90.2%
86.0%
90.2%
84.9%
500
VIN = 5V
VOUT = 1.2V, IOUT = 6A
VOUT = 1.2V, IOUT = 3A
VOUT = 1.2V, IOUT = 6A
η
Efficiency
VIN = 3.3V
FS
Switching frequency
kHz
SPM1005-1V0
PARAMETERS
VOUT(adj): Output voltage trim range
TEST CONDITIONS
Over IOUT range, TA = -40°C to 85°C
MIN
0.9
TYP
1.0
MAX
1.1
UNIT
V
VOUT = 1.0V, IOUT = 3A
89.6%
84.6%
89.1%
83.1%
500
VIN = 5V
VOUT = 1.0V, IOUT = 6A
VOUT = 1.0V, IOUT = 3A
VOUT = 1.0V, IOUT = 6A
η
Efficiency
VIN = 3.3V
FS
Switching frequency
kHz
SPM1005-0V8
PARAMETERS
VOUT(adj): Output voltage trim range
TEST CONDITIONS
Over IOUT range, TA = -40°C to 85°C
MIN
0.72
TYP
0.8
MAX
0.88
UNIT
V
VOUT = 0.8V, IOUT = 3A
88.2%
82.0%
85.4%
78.0%
450
VIN = 5V
VOUT = 0.8V, IOUT = 6A
VOUT = 0.8V, IOUT = 3A
VOUT = 0.8V, IOUT = 6A
η
Efficiency
VIN = 3.3V
FS
Switching frequency
kHz
SPM1005-0V6
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT: Output voltage trim (trim up
only)
Over IOUT range, TA = -40°C to 85°C
0.6
0.6
0.66
V
VOUT = 0.6V, IOUT = 3A
85.6%
77.8%
83.0%
74.1%
450
VIN = 5V
VOUT = 0.6V, IOUT = 6A
VOUT = 0.6V, IOUT = 3A
VOUT = 0.6V, IOUT = 6A
η
Efficiency
VIN = 3.3V
FS
Switching frequency
kHz
Version 1.4
February 19, 2016
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SPM1005
POWER MODULE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
Thermal
Shutdown
PWRGD
Logic
Shutdown
Logic
PWRGD
EN
COMP
VADJ
VIN
UVLO
VIN
Compensation
Network
PHASE
Power
Stage
and
Control
Logic
SS/TR
STSEL
VOUT
VREF
VSENSE
PGND
AGND
RT/CLK
OSC w/PLL
OCP
Version 1.4
February 19, 2016
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SPM1005
PIN DESCRIPTIONS (All SPM1005 Models Unless Specified)
PIN Name
VIN
(E2-E3, F1-F3, G1-G3)
Description
The positive input voltage power pin, which is referenced to PGND. Connect external input
filter capacitors between these pins and PGND plane, close to module.
Switching node pin. Connect this pin to a small copper island under the module for best
thermal performance. Do not connect any external component to this pin or use this pin for
any other functions.
PHASE
(G6)
VOUT
(A1-A4, B2-B4)
PGND
Output voltage. Connect external output filter capacitors between these pins and PGND
plane, close to the module.
Zero DC voltage reference for power circuitry. These pins should be connected directly to the
PCB ground plane. The module's heat transfer is through these pins and all of them must be
(A6-A8, B5-B8, C1-C7,
D1-D7, E4-E7, F4-F7, G4- connected together externally with a copper plane located directly under the module.
G5)
Zero DC voltage reference for the analog control circuitry. A small analog ground plane is
AGND
(C8)
recommended. RT/CLK, STSEL, SS/TR pins should be referenced to analog ground. AGND and
PGND should be connected at a single point is such a way that load current does not flow in
the AGND plane.
Startup mode selection. Short to AGND for soft-start operation with extended soft-start time
determined by a capacitor connected between SS/TR pin and AGND. Leave this pin open for
tracking operation or selecting default soft-start time that is nominally 1.1ms. See SS/TR pin
description below for more details.
STSEL
(G7)
Soft-start or tracking operation. When SS/TR pin is open and STSEL pin is shorted to AGND,
the power module operates in soft-start mode with the default soft-start time of 1.1ms.
Longer soft-start time can be achieved with an additional capacitor connected between SS/TR
pin and AGND.
Capacitor value can be selected based on Equation 4 or values provided in Table 3. For
tracking operation, leave STSEL open and do not connect additional capacitor between SS/TR
and AGND. Connect this pin to the voltage to be tracked. Refer to Fig. 34 for more details.
Switching frequency and external synchronization pin. For SPM1005-Z model, an internal
90.9KΩ resistor is connected between RT/CLK and AGND to set the switching frequency to
450KHz. For all other models, the default switching frequencies are shown in the Electrical
Characteristics tables above. For all models, an external synchronization clock can be
connected to RT/CLK pin to synchronize the switching frequency of the module. More details
are provided on page 22.
SS/TR
(G8)
RT/CLK
(F8)
Enable pin with internal pull-up current source. Pull this pin to below 1.18V to disable the
power module. Float this pin or pull to above 1.3V to enable the power module. This pin can
be used to adjust the under voltage lockout (UVLO) level with two additional resistors forming
a voltage divider from VIN to AGND as shown in Fig. 32.
EN
(E1)
COMP
(E8)
Optional external compensation pin for additional loop adjustment. A capacitor between
COMP and AGND can make the module more stable. Generally, the COMP pin should be open.
Output voltage adjustment pin. For SPM1005-Z, connect a resistor, RADJ, between VADJ pin
and AGND pin to set the desired output voltage, as shown in Fig. 27. For all other models
except SPM1005-0V6, the output voltage can be trimmed ±10% by connecting a trim resistor
between VADJ and AGND (trim up) as shown in Fig. 16, or a trim resistor between VADJ, and
VSENSE (trim down), as shown in Fig. 17. The output voltage of SPM1005-0V6 can be trimmed
up only.
VADJ
(D8)
Power Good pin. An open drain output that is pulled low when VSENSE voltage is less than
91% or greater than 105% of the nominal output voltage. PWRGD is floating when the voltage
at VSENSE pin is between 93% and 103% of the nominal output voltage.
PWRGD
(B1)
Version 1.4
February 19, 2016
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SPM1005
PIN Name
Description
Remote sensing pin for the output voltage. Connect this signal to VOUT close to the load for
improved regulation. Do not use an LC filter between VOUT pins of the module and the point
where VSENSE is connected.
VSENSE
(A5)
Note: this pin is not connected to VOUT inside the module and must be connected externally.
LGA PACKAGE
56 PINS
(TOP VIEW)
1 2 3 4 5 6 7 8
G
F
PHASE STSEL SS/TR
PGND
VIN
RT/CLK
COMP
VADJ
E
D
C
B
A
EN
PGND
AGND
PWRGD
PGND
VOUT
VSENSE
Version 1.4
February 19, 2016
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SPM1005
TYPICAL CHARACTERIESTICS(Note 1)
SPM1005-3V3, VOUT = 3.3V
100
98
1.4
1.2
1
Vin = 5 V
Vin = 6 V
96
0.8
0.6
0.4
0.2
0
94
92
90
Vin = 5 V
Vin = 6 V
88
86
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Fig. 1 Efficiency vs Output Current
Fig. 2 Power Dissipation vs Output Current
SPM1005-2V5, VOUT = 2.5V
100
98
96
94
92
90
88
86
84
82
80
1.4
1.2
1
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0.8
0.6
0.4
0.2
0
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Fig. 3 Efficiency vs Output Current
Fig. 4 Power Dissipation vs Output Current
Version 1.4
February 19, 2016
Page 9 of 29
SPM1005
SPM1005-1V8, VOUT = 1.8V
100
98
96
94
92
90
88
1.4
1.2
1
Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0.8
0.6
0.4
0.2
0
Vin = 2.95 V
86
84
82
80
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Fig. 5 Efficiency vs Output Current
Fig. 6 Power Dissipation vs Output Current
SPM1005-1V5, VOUT = 1.5V
98
96
94
92
90
88
86
84
82
80
78
1.4
1.2
1
Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0.8
0.6
0.4
0.2
0
Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Fig. 7 Efficiency vs Output Current
Fig. 8 Power Dissipation vs Output Current
Version 1.4
February 19, 2016
Page 10 of 29
SPM1005
SPM1005-1V0, VOUT = 1.0V
96
94
92
90
88
86
1.4
1.2
1
Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0.8
0.6
0.4
0.2
0
84
82
80
78
Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Fig. 10 Power Dissipation vs Output Current
Fig. 9 Efficiency vs Output Current
SPM1005-0V8, VOUT = 0.8V
94
92
90
88
86
84
1.4
Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
1.2
1
Vin = 6 V
0.8
0.6
0.4
0.2
0
82
80
78
76
Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Fig. 12 Power Dissipation vs Output Current
Fig. 11 Efficiency vs Output Current
Version 1.4
February 19, 2016
Page 11 of 29
SPM1005
SPM1005-0V6, VOUT = 0.6V
90
88
86
84
82
80
78
1.4
1.2
1
Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
0.8
0.6
0.4
0.2
0
Vin = 2.95 V
Vin = 3.3 V
Vin = 5 V
Vin = 6 V
76
74
72
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Fig. 13 Efficiency vs Output Current
Fig. 14 Power Dissipation vs Output Current
Note 1: The above curves (Figure 1 to Figure 14) are derived from measured data taken on samples of the SPM1005
tested at room temperature (25°C), and are considered to be typical for the product.
Version 1.4
February 19, 2016
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SPM1005
APPLICATION INFORMATION
Output Voltage Adjustment
The output voltage of SPM1005-Z can be adjusted from 0.6V to 3.6V using an external resistor between VADJ pin
and AGND pin, as shown in Fig. 15. The required resistor value RADJ can be calculated using equation (1).
SPM1005
VOUT
VOUT
COUT
VSENSE
VADJ
RADJ
0.6V
AGND
Fig. 15 Output Voltage Setting for SPM1005-Z
R1 0.6
VO 0.6
RADJ (K)
(For SPM1005-Z only)
(1)
where R1 = 20kΩ and VO is the desired output voltage in Volts. [Note: R1 is internal to the module, as indicated in
Fig. 17]
For other models in the SPM1005 series, the output voltage is already set internally but can be trimmed within a
10% band by connecting a trim resistor between VADJ pin and AGND pin (for trim up) or between VADJ pin and
VSENSE pin (for trim down), as shown in Fig. 16 and Fig. 17, respectively. [Note: SPM1005-0V6 cannot be trimmed
down.]
Internal R1 and R2 values for all versions of SPM1005 are given in Table 1.
Table 1. Internal Voltage Setting Resistors of SPM1005
Version
R1 (KΩ)
R2 (KΩ)
-Z
20.0
NC
3V3
20.0
4.42
2V5
20.0
6.34
1V8
20.0
10.0
1V5
20.0
13.3
1V2
20.0
20.0
1V0
20.0
30.0
0V8
20.0
60.4
0V6
20.0
NC
These values along with Equations (2) and (3) can be used to calculate the RDOWN or RUP for trimming output voltage.
Vo is the desired output voltage.
1
RDOWN (K)
(For SPM1005 trim down)
1
0.6
1
(2)
(3)
R2 VO 0.6
R
1
1
RUP (K)
(For SPM1005 trim up)
1 V 0.6
1
O
R
0.6
R2
1
Version 1.4
February 19, 2016
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SPM1005
VOUT
VOUT
VOUT
VOUT
SPM1005
SPM1005
VSENSE
VSENSE
R1
R1
COUT
RDOWN
COUT
VADJ
VADJ
VREF
VREF
R2
R2
RUP
AGND
AGND
Fig. 16 Output Voltage Trim Up Circuit
Fig. 17 Output Voltage Trim Down Circuit
Transient Response
The following table summarizes the measured output voltage overshoot and undershoot when the load current
undergoes a step change between 2A and 5A for each SPM1005 model. The slew rate for the current change is
1A/µs. The measured waveforms are given from Fig. 18 to Fig. 25. The measurement is obtained when the input
capacitor consists of one 47µF ceramic capacitor in parallel with one 220µF electrolytic capacitor, and the output
capacitor consists of four 47µF ceramic capacitors in parallel. If smaller output voltage deviation is required, larger
output capacitor values can be used.
Table 2. Output Voltage Transient Response
Testing Conditions: CIN1 = 1 x 47µF CERAMIC, CIN2 = 220µF ELECTROLYTIC, COUT = 4 × 47µF CERAMIC
3A LOAD STEP, 2A to 5A, (1A/µs)
VIN (V)
VOUT (V)
VOLTAGE DEVIATION (mV)
RECOVERY TIME (µs)
3.3
5.0
3.3
5
3.3
5
50
45
55
50
70
65
80
95
155
145
150
150
170
165
175
195
1.0
1.2
1.8
5
5
2.5
3.3
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Fig. 19 VIN = 3.3V, VOUT = 1.0V, 3A Load Step
Fig. 18 VIN = 5V, VOUT = 1.0V, 3A Load Step
Fig. 20 VIN = 5V, VOUT = 1.2V, 3A Load Step
Fig. 22 VIN = 5V, VOUT = 1.8V, 3A Load Step
Fig. 21 VIN = 3.3V, VOUT = 1.2V, 3A Load Step
Fig. 23 VIN = 3.3V, VOUT = 1.8V, 3A Load Step
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Fig. 25 VIN = 5V, VOUT = 3.3V, 3A Load Step
Fig. 24 VIN = 5V, VOUT = 2.5V, 3A Load Step
Application Schematics
Figure 26 shows a typical schematic with SPM1005-1V2 for a 1.2V output application with switching frequency of
500 kHz. RT/CLK is left open to select the default switching frequency. STSEL pin is connected to AGND to select the
default startup time. The ON/OFF CONTROL signal is used to turn on and off the power module.
Fig. 26 Typical Schematic VIN = 2.95V to 6.0V, VOUT = 1.2V, FS = 500kHz
Figure 27 shows a typical schematic for a 5V input, 3.6V output application using SPM1005-Z. The adjustment
resistor, RADJ, is selected as 4.02kΩ calculated based on Equation (1). In this example, the switching frequency is
selected as 1MHz by connecting the timing resistor of 68kΩ between RT/CLK pin and AGND pin.
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Fig. 27 Typical Schematic VIN = 4.4V to 6.0V, VOUT = 3.6V, FS = 1MHz
Power Good (PWRGD)
The PWRGD pin is an open drain output, and can be used to indicate when the output voltage is within the normal
operating range. This pin is pulled low when VSENSE voltage is less than 91% or greater than 105% of the nominal
output voltage. Also, the PWRGD pin is pulled low if the input UVLO or thermal shutdown is asserted, or if the EN
pin is pulled low.
There is a 2% hysteresis, so once the VSENSE pin is within 93% to 103% of the nominal output voltage the PWRGD
pin is de-asserted and the pin floats.
It is recommended to use a pull-up resistor between 1kΩ and 100kΩ to a voltage source that is 5.5V or less. The
PWRGD will be in a valid state (high or low as above) once the VIN input voltage is greater than 1.2V.
Power-Up Characteristics
When configured as shown in the front page schematic (page 1), SPM1005 produces a regulated output voltage
whenever a valid input voltage is present.
During the power-up, internal soft-start circuitry slows the rate that the output voltage rises, thereby limiting the
charging current to the output capacitor.
Fig. 28 shows the startup waveforms for SPM1005-Z, operating from a 5V input and with the output voltage
adjusted to 1.8V. The waveform is measured with a 3A constant current load.
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VIN
(5 V/div)
VPWRGD
(5 V/div)
VOUT
(1 V/div)
Time (2 ms/div)
Fig. 28 Startup Waveforms
Enable (On/Off) Operation and Under Voltage Lockout (UVLO) Setup
The EN pin provides an external on/off control of the power module and is lightly pulled up internally with a current
source. The module is enabled if this pin is left open or its voltage exceeds the VEN-H threshold voltage, and the
power module starts operation once the input voltage is higher than VSTART
.
When the voltage at EN pin is below the VEN-L threshold voltage, the power module stops switching and enters low
quiescent current state.
If an application requires controlling the EN pin, an open drain or open collector logic can be used to interface with
the pin, as shown in Fig. 29. In this figure, high ON/OFF CONTROL signal level (Low EN) disables the power module.
SPM1005
EN
ON/OFF
Q1
CONTROL
AGND
Fig. 29 Typical ON/OFF Control Schematic
Fig. 30 and Fig. 31 show the typical output voltage waveforms when SPM1005 is enabled (turned on) and disabled
(turned off) by the EN pin. In these figures, the top trace is the power good signal, the middle trace is the EN pin
voltage, and the bottom trace is the output voltage.
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VPWRGD
(5 V/div)
VPWRGD
(5 V/div)
VEN
(5 V/div)
VEN
(5 V/div)
VOUT
(2 V/div)
VOUT
(2 V/div)
Time (1 ms/div)
Time (1 ms/div)
Fig. 30 Waveforms at Enable Turn-On
Fig. 31 Waveforms at Enable Turn-Off
Under-voltage lockout can be used to prevent the output from starting until the input voltage is within its normal
range. For input under voltage lockout (UVLO) adjustment, use the EN pin as shown in Fig. 32 to set the UVLO level
by using two external resistors. Once the EN pin voltage exceeds 1.3V, an additional 2.8μA of current is added to
provide input voltage hysteresis. Resistor REN1 and REN2 can be calculated using Equations (4) and (5) based on the
required startup voltage and shutdown voltage.
Fig. 32 Input Under-Voltage Lockout Setup
VEN _ FALLING
VSTART
UVLO
VEN _ RISING
REN1 103
(4)
(5)
VEN _ FALLING
Ip 1
Ih
VEN _ RISING
REN1 VEN _ FALLING
REN 2 103
UVLO VEN _ FALLING REN1 (Ip Ih )
Where REN1 and REN2 are in kΩ, Ih = 2.8μA, Ip = 0.7μA, VEN_RISING = 1.3V, VEN_FALLING = 1.18V.
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As an example, if REN1 = 14.7k Ω and REN2 = 12.7k Ω, VSTART will be 2.8V and UVLO will be 2.5V.
It is recommended to set the minimum UVLO level of the module at 2.45V or higher to ensure proper operation
before shutdown.
Soft-Start or Tracking Pin (SS/TR)
The soft-start function forces the output voltage to rise gradually to its nominal value rather than rising as rapidly
as possible. Soft-Start mode is selected when the module is used independently without tracking or sequencing. To
select soft-start operation mode the STSEL pin is connected to AGND. This will activate the internal soft-start
capacitor for a nominal soft-start time of 1.1ms. An external capacitor between the SS/TR pin to ground can be used
to increase the soft-start time to higher values if desired.
Table 3 shows the soft-start time using typical soft-start capacitor values.
Table 3. Soft-start capacitor values and soft-start time
External capacitor (nF)
SS Time (ms)
open
1.1
4.7
2.7
10
4.4
20
7.8
33
12.1
47
16.8
100
34.4
If other startup time is needed, Equation (6) provides the relationship between the external soft-start capacitor
value CSS and the soft-start time, TSS.
CSS 3TSS (ms) 3.3(nF)
(6)
During the soft-start period, VSENSE voltage will follow the SS/TR pin voltage up to 90% of the nominal voltage
setpoint. When the SS/TR voltage is greater than 90% of the nominal voltage, the effective system reference voltage
will be changed from the SS/TR voltage to the internal voltage reference to close the voltage loop.
If the input voltage falls below the UVLO, or a thermal shutdown event occurs, or the EN pin is pulled down to below
1.18V, the SPM1005 will stop switching and the SS/TR will be discharged to below 60mV before the module restarts.
Sequencing and Tracking
The term sequencing is used when two or more separate modules are configured to start one after the other, in
sequence. The term tracking is used when two or more modules are configured so that they start together, with
their output voltages tracking each other during startup. This is done by having one module act as a master and the
other(s) act as slave(s). Sequencing and tracking startup can be implemented using the SS/TR, EN and PWRGD pins.
The sequential startup connection is shown in Fig. 33. The power good pin (PWRGD) of the first SPM1005 module
is connected to the EN pin of the second SPM1005 module, which will be enabled only after the output voltage of
the first SPM1005 module reaches regulation range and its PWRGD is asserted. Note: The SPM1005 can start in
sequence with another SPM1005 or with any other POL having a compatible Power Good output.
With tracking mode the output voltage of the SPM1005 is controlled by another voltage applied to its SS/TR input.
Tracking startup of two SPM1005 modules can be achieved by connecting a resistor network of R1 and R2 as shown
in Fig. 34, where the output voltage of the second SPM1005 module (bottom) will track the output voltage of the
first SPM1005 module (top). In this case, the soft-start time of SPM1005 module #1 is determined by the capacitor
connected to its SS/TR pin and the STSEL pin is connected to ground. The voltage at SS / TR pin of the second
SPM1005 module is directly controlled by the output voltage of the first SPM1005 module through the resistor
divider (R1 and R2). The STSEL pin of the second SPM1005 module should be left open.
Resistor divider R1 and R2 in Fig. 34 can be calculated using Equations (7) and (8). Note: The SPM1005 can track any
external voltage, so the master can be an SPM1005 or any other POL. Tracking may also be used to adjust the
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SPM1005
module output voltage in real time by controlling the input voltage to the TR pin of the module from a suitable input
source. Please consult Sumida for more details.
VOUT1 5
0.9
0.9 R1
(7)
(8)
R1
(k)
R2
(k)
VOUT1 0.9
Fig. 35 gives the output voltage waveforms of two SPM1005 modules operating in sequential startup mode. It shows
that PWRGD signal becomes high when the first SPM1005 (2.5V output in this example) enters into regulation and
then the second SPM1005 (1.2V output in the example) begins to start up.
Fig. 36 gives the output voltage waveforms of two SPM1005 modules operating in tracking startup mode. It shows
that VOUT1 follows VOUT2 until the lower voltage rail (VOUT2) enters into regulation (1.2V in this example). Then, VOUT1
continues to rise to its steady state value (2.5V in the example).
VOUT1
VOUT
EN
SPM1005 #1
STESL
SS/TR
VOUT2
VOUT
EN
R1
SPM1005 #2
STESL
SS/TR
R2
Fig. 33 Sequencing Startup Schematic
Fig. 34 Tracking Startup Schematic
Note: when used in tracking mode, if the slave unit (module #2 in Fig. 34) shuts down while the other module is still
operating, a latch-up condition can occur where the slave unit does not restart. To avoid this, it is necessary to pull
down the SS/TR pin of module #2 to below 60mV momentarily, to initiate a normal start-up sequence.
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Fig. 35 Sequencing Startup,
VOUT1 = 2.5V, VOUT2 = 1.2V
Fig. 36 Tracking Startup,
VOUT1 = 2.5V, VOUT2 = 1.2V
Switching Frequency Selection and Timing Resistor (RT/CLK Pin)
The switching frequency of the SPM1005-Z can be adjusted over a wide range from approximately 450 kHz to 1MHz.
A resistor between RT/CLK and AGND can be used to increase the switching frequency. For SPM1005-Z, an internal
resistor, RCLK = 90.9kΩ, sets the minimum (default) switching frequency to 450 KHz. Generally a higher frequency is
preferred for higher output voltages, as indicated on page 4.
The user can increase the switching frequency by adding an external resistor, RT, between RT/CLK pin and AGND, as
shown in Fig. 37, where RT is calculated using Equation (9). The relationship between switching frequency and
equivalent resistor (REQ = RCLK‖RT) is also shown in Fig. 38.
RCLK
RT (kΩ)
FSW(kHz) 1.052
(9)
RCLK 1
56183
1500
1400
1300
1200
1100
1000
900
SPM1005
RT/CLK
OSC
RCLK
800
700
RT
AGND
600
500
0
50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800
REQ Resistance in KΩ
Fig. 37 Switching Frequency Adjustment
Fig. 38 Switching Frequency vs REQ for SPM1005-Z
The default switching frequency of all other SPM1005 models is provided in the electrical characteristics table. It is
not recommended to change those switching frequencies, but please contact Sumida if other switching frequencies
are needed.
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Synchronization with RT/CLK pin
RT/CLK pin can also be used to synchronize the SPM1005 to an external system clock, as shown in Fig. 39. To
implement the synchronization feature, a clock signal with on time of at least 75ns should be applied to the RT/CLK
pin. The logic zero level of the clock signal must be lower than 0.6V and the logic high level of the clock signal must
be higher than 1.6V. The synchronization frequency range is between 450kHz and 1MHz.
The rising edge of the phase node (PHASE) will be synchronized to the falling edge of RT/CLK pin.
SPM1005
RT/CLK
OSC
RCLK
Clock
Source
AGND
Fig. 39 Synchronizing to a System Clock
Over-Current Protection
A hiccup current limiting function is provided in the SPM1005 to protect against output overload or short-circuit.
During an over-current condition, the load current is initially limited to approximately 9A and the output voltage is
reduced to approximately 0.8V as shown in Fig. 40. If the over-current condition is not removed within
approximately 1ms, the module will be shut down, as shown in Fig. 41. [Please note that the time scale is different
for these two figures.]
IOUT
(5 A/div)
IOUT
(5 A/div)
VOUT
(2 V/div)
VOUT
(1 V/div)
Time (400 µs/div)
Time (100 µs/div)
Fig. 40 Over-current Limiting
Fig. 41 Hiccup Mode Current Limit Shut-down
When the over-current condition is removed, the output voltage recovers automatically to the nominal voltage, as
shown in Fig. 42. If the over-current condition is not removed, the power module operates in hiccup mode, as shown
in Fig. 43. The hiccup period is about 25ms.
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SPM1005
IOUT
(5 A/div)
IOUT
(5 A/div)
VOUT
(1 V/div)
VOUT
(2 V/div)
Time (4 ms/div)
Time (10 ms/div)
Fig. 42 Recovery from Over-current Shut-down
Fig. 43 Hiccup Mode Current Limit Restart into
Short-Circuit
Input protection
In most applications the input power source provides current limiting (typically fold-back or hiccup mode) and as
long as the average fault current is limited to approximately 10A or less, no further protection is required.
If the SPM1005 is powered from a battery or other high current source, it is recommended to include an external
fuse (maximum 10A) in the input to the module. The SPM1005 includes full protection against output overcurrent
or short-circuit, and the fuse will not operate under any output overload condition. For more information refer to
PM_AN-2 “Input Protection”.
Thermal Considerations
The absolute maximum junction temperature is 150°C but it is recommended to keep the operating temperature
well below this value. Maximum recommended case temperature is 115°C, which corresponds to a junction
temperature of approximately 125°C.
The thermal resistance from case to ambient (θCA) depends on the PCB layout as well as the amount of cooling
airflow. When mounted on the EVM, θCA is approximately 15°C/watt in still air. Please refer to the EVM User Guide
for EVM PCB layout information.
SPM1005 implements an internal thermal shutdown to protect itself if the junction temperature of the power
MOSFET exceeds 170°C. The thermal shutdown forces the module to stop switching when the junction temperature
exceeds the thermal shutdown threshold. Once the die temperature reduces by about 15°C, the module restarts
automatically.
Layout Considerations
To achieve the best electrical and thermal performance, an optimized PCB layout is required. Some considerations
for the PCB layout are:
Use large copper areas for power planes (VIN, VOUT, and especially PGND) to minimize conduction loss and
thermal stress.
Place ceramic input and output capacitors close to the module pins to minimize high frequency noise.
Place any additional output capacitors between the main ceramic capacitor and the load.
Connect the AGND and PGND copper areas at a single point, preferable under the AGND pin of the module.
Place RSENSE, RT, and CSS as close as possible to their respective pins.
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SPM1005
Do not connect the PHASE pin to any other components.
Use multiple vias to connect the power planes to internal layers.
Refer to SPM1005 EVM User Manual for suggested PCB layout.
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SPM1005
MECHANICAL DATA
Package dimensions and PCB pads
ALL DIMENSIONS IN MILLIMETERS
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SPM1005
Tape and Reel Packaging Information
Fig. 44 Tape Dimensions and Loading Information
Fig. 45 Reel Dimensions
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SPM1005
0.10-1.3 N
Fig. 46 Peel Speed and Strength of Cover Tape
Note:
1. The peel speed should be approximately 300mm/min.
2. The peel force of the top cover tape should be between 0.1N and 1.3N.
Storage and handling
Moisture barrier bag
The modules are packed in a reel, and then an aluminum foil moisture barrier bag is used to pack the reel in order
to prevent moisture absorption. Silica gel is put into the moisture barrier bag as absorbent material.
Storage
SPM1005 is classified MSL level 3 according to JEDEC J-STD-033 and J-STD-020 standards, with a floor life of 168
hours after the outer bag is opened. Any unused SPM1005 modules should be resealed in the original moisture
barrier bag as soon as possible. If the modules’ floor life exceeds 168 hours, they should be dehumidified before
use by baking in an oven at 125°C/1% RH (e.g. hot nitrogen gas atmosphere) for 48 hours.
Handling precautions
1. Handle carefully to avoid unnecessary mechanical stress. Excessive external stress may cause damage.
2. Normal ESD handling procedures are recommended to be used whenever handling the module.
3. If cleaning the module is necessary, use isopropyl alcohol solution at normal room temperature. Avoid the use of
other solvents.
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SPM1005
Reflow soldering
Fig. 47 Recommended Reflow Solder Profile (Lead-free)
Ordering Information
Output Voltage
Adjustable
3.3V
Module Part Number
Pad Finish
Au (RoHS)
Au (RoHS)
Au (RoHS)
Au (RoHS)
Au (RoHS)
Au (RoHS)
Au (RoHS)
Au (RoHS)
Au (RoHS)
Package Type
LGA
Temperature Range
-40˚C to 85˚C
-40˚C to 85˚C
-40˚C to 85˚C
-40˚C to 85˚C
-40˚C to 85˚C
-40˚C to 85˚C
-40˚C to 85˚C
-40˚C to 85˚C
-40˚C to 85˚C
SPM1005-ZC
SPM1005-3V3C
SPM1005-2V5C
SPM1005-1V8C
SPM1005-1V5C
SPM1005-1V2C
SPM1005-1V0C
SPM1005-0V8C
SPM1005-0V6C
LGA
LGA
LGA
LGA
LGA
LGA
LGA
LGA
2.5V
1.8V
1.5V
1.2V
1.0V
0.8V
0.6V
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