S42WD61S2.7S
更新时间：2024-09-18 07:52:23
品牌：SUMMIT
描述：Dual Voltage Supervisory Circuit With Watchdog Timer
概述
数据手册S42WD61S2.7S 概述
Dual Voltage Supervisory Circuit With Watchdog Timer 双电压监控电路，看门狗定时器
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PDF下载S4242/S42WD42/S4261/S42WD61
Dual Voltage Supervisory Circuit
With Watchdog Timer(S42WD61) (S42WD42)
•
High Reliability
FEATURES
– Endurance: 100,000 erase/write cycles
– Data retention: 100 years
•
Precision Dual Voltage Monitor
– VCC Supply Monitor
- Dual reset outputs for complex
microcontroller systems
- Integrated memory write lockout function
- No external components required
OVERVIEW
The S42xxx are a precision power supervisory circuit. It
automatically monitors the device’s VCC level and will
generatearesetoutputontwocomplementaryopendrain
outputs.InadditiontotheVCC monitoring,theS42xxxalso
provides a second voltage comparator input. This input
has an independent open drain output that can be wire-
OR’ed with the RESET I/O or it can be used as a system
interrupt.
•
•
Second Voltage Monitor Output
– Separate VLOW output
– Generates interrupt to MCU
– Generates RESET for dual supply systems
- Guaranteed output assertion to VCC - 1V
Watchdog Timer (S42WD42, S42WD61)
– 1.6s
The S42xxx also has an integrated 4k/16k-bit nonvolatile
•
•
Memory Internally Organized 2 x8
memory. The memory conforms to the industry standard
two-wire serial interface. In addition to the reset circuitry,
the S42WD42/S42WD61 also has a watchdog timer.
Extended Programmable Functions
Available on SMS24
BLOCK DIAGRAM
V
CC
8
SCL
SDA
NONVOLATILE
MEMORY
ARRAY
6
5
WRITE
CONTROL
RESET#
2
PROGRAMMABLE
RESET PULSE
GENERATOR
+
V
TRIP
RESET
CONTROL
–
RESET
VLOW#
7
1
PROGRAMMABLE
WATCHDOG
TIMER
(S42WD42,
S42WD61)
UV
OV
+
3
V
SENSE
–
1.26V
4
2025 T BD 2.0
GND
SUMMIT MICROELECTRONICS, Inc.
•
300 Orchard City Drive, Suite 131
•
Campbell, CA 95008
•
Telephone 408-378-6461
•
Fax 408-378-6586
•
www.summitmicro.com
Characteristics subject to change without notice
© SUMMIT MICROELECTRONICS, Inc. 2000
2025 6.0 4/17/00
1
S4242/S42WD42/S4261/S42WD61
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias
Storage Temperature
............................................................................................................................... -40°C to +85°C
..................................................................................................................................... -65°C to +125°C
Soldering Temperature (less than 10 seconds) ................................................................................................................... 300°C
Supply Voltage ............................................................................................................................................................. 0 to 6.5V
Voltage on Any Pin ....................................................................................................................................... -0.3V to VCC+0.3V
ESD Voltage (JEDEC method) .......................................................................................................................................... 2,000V
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses
beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min
0°C
Max
+70°C
+85°C
-40°C
2025 PGM T1.0
DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Symbol
Parameter
Conditions
Min
Max
Units
SCL = CMOS Levels @ 100KHz
SDA = Open
V
=5.5V
3
mA
CC
ICC
Supply Current (CMOS)
Standby Current (CMOS)
All other inputs = GND or VCC
VCC =3.3V
VCC =5.5V
2
mA
µA
µA
50
25
ISB
SCL = SDA = VCC
All other inputs = GND
V
=3.3V
CC
ILI
Input Leakage
VIN = 0 To VCC
10
10
µA
µA
V
ILO
VIL
Output Leakage
Input Low Voltage
VOUT = 0 To VCC
SCL, SDA, RESET# (pin 2)
0.3xVCC
VIH
Input High Voltage
Output Low Voltage
SCL, SDA, RESET (pin7)
IOL = 3mA SDA
0.7xVCC
0.4
V
V
VOL
2025 PGM T2.0
AC ELECTRICAL CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)
2.7V to 4.5V
4.5V to 5.5V
Min Max
Symbol
Parameter
Conditions
Min
Max
Units
fSCL
SCL Clock Frequency
Clock Low Period
0
100
400
KHz
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
tLOW
tHIGH
tBUF
4.7
4.0
4.7
4.7
4.0
4.7
0.3
0.3
1.3
0.6
1.3
0.6
0.6
0.6
0.2
0.2
Clock High Period
Bus Free Time
Before New Transmission
tSU:STA
tHD:STA
tSU:STO
tAA
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
Clock to Output
SCL Low to SDA Data Out Valid
3.5
0.9
tDH
Data Out Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
SCL Low to SDA Data Out Change
tR
1000
300
300
300
tF
tSU:DAT
tHD:DAT
TI
250
0
100
0
Noise Spike Width
@ SCL, SDA Inputs
Noise Suppression Time Constant
100
10
100
10
tWR
Write Cycle Time
ms
2025 PGM T3.0
2025 6.0 4/17/00
2
S4242/S42WD42/S4261/S42WD61
CAPACITANCE
T = 25°C, f = 100KHz
A
Symbol
CIN
Parameter
Max
5
Units
pF
Input Capacitance
Output Capacitance
COUT
8
pF
2025 PGM T4.0
t
t
LOW
HIGH
t
t
R
F
SCL
t
t
t
t
t
HD:DAT
SU:SDA
SU:DAT
SU:STO
HD:SDA
t
BUF
SDA In
t
t
AA
DH
SDA Out
2025 Fig01 1.0
FIGURE 1. BUS TIMING
START
STOP
Condition
Condition
SCL
SDA In
2025 Fig02 1.0
FIGURE 2. START AND STOP CONDITIONS
2025 6.0 4/17/00
3
S4242/S42WD42/S4261/S42WD61
t
GLITCH
V
TRIP
V
CC
V
RVALID
t
RPD
t
PURST
t
PURST
RESET#
RESET
t
RPD
2025 T fig03 2.0
FIGURE 3. RESET OUTPUT TIMING
RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS
T =-40°C to +85°C
A
Symbol
Parameter
Part no.
Suffix
Min.
Typ.
Max.
Unit
VTRIP
Reset Trip Point
A (or) Blank
4.250
4.50
2.7
4.375
4.625
2.9
4.5
V
V
B
4.75
3.10
2.7
V
tPURST
tRPD
Reset Timeout
200
ms
µs
V
VTRIP to RESET Output Delay
5
VRVALID
tGLITCH
VOLRS
VOHRS
VULH
RESET Output Valid to VCC min. Guarantee
Glitch Reject Pulse Width note 1
RESET Output Low Voltage IOL = 1mA
RESET High Voltage Output IOH = 800µA
VSENSE Under-voltage threshold low to high
VSENSE Under-voltage threshold high to low
VSENSE Over-voltage threshold low to high
VSENSE Over-voltage threshold high to low
Delay to VLOW Active
1
30
ns
V
0.4
VCC-.75
1.20
V
1.25
1.25
1.25
1.25
1.30
1.30
1.30
1.30
5
V
VUHL
1.20
V
VOLH
VOHL
tVD1
1.20
V
1.20
V
µs
µs
ms
tVD2
Delay to VLOW Released
5
tWDTO
Watchdog timeout Period (S42WD61)
(S42WD42)
1600
2025 PGM T5.2
2025 6.0 4/17/00
4
S4242/S42WD42/S4261/S42WD61
VULH
V
UHL
(Under-voltage detect)
VSENSE
t
VD1
t
VD2
VLOW
#
2025 T fig04 2.0
FIGURE 4. VSENSE UNDER-VOLTAGE FUNCTION
RESET# (in)
RESET# (out)
RESET (out)
t
PURST
t
PURST
2025 T fig05 2.0
FIGURE 5. RESET AS AN INPUT
2025 6.0 4/17/00
5
S4242/S42WD42/S4261/S42WD61
PIN CONFIGURATIONS
8-Pin PDIP
or 8-Pin SOIC
PIN NAMES
Symbol
VLOW
Pin
1
Description
Open drain output, active when
VSENSE < 1.24V
#
RESET#
VSENSE
2
Active low I/O
1
2
3
4
8
7
6
5
V
CC
RESET
SCL
SDA
V
#
LOW
RESET#
2nd monitor voltage input.VLOW
output when < 1.24V
#
3
V
SENSE
GND
GND
SDA
4
5
6
7
8
Analog & digital ground
Serial memory I/O data line
Serial memory clock
Active high I/O
2025 T PCon 2.0
SCL
RESET
VCC
Supply voltage
V
= 3.0V or 5.0V
PB_RST#
CC
VBAT TO
REGULATOR
INTO (P1.5)
S42xxx
8051 Type
MCU
RST
SCL (P0.0)
SDA (P0.1)
V
#
V
CC
LOW
RESET#
RESET
SCL
V
BAT
V
GND
SENSE
TRIP
SDA
2
I C Peripheral
RESET#
SCL
SDA
2025 T fig06 2.0
FIGURE 6. TYPICAL SYSTEM CONFIGURATION USING A PUSH BUTTON RESET AND BATTERY MONITOR CIRCUIT
V
= 5.0V ±10%
CC
SECOND CARD
VOLTAGE
3.0V ±5%
General
Purpose
MCU
S42xxx
V
#
V
CC
LOW
RESET#
RESET
SCL
SCL
SDA
V
GND
SENSE
SDA
RESET#
2
I C Peripheral
RESET#
SCL
SDA
2025 T fig07 2.0
FIGURE 7. TYPICAL SYSTEM CONFIGURATION FOR DUAL RESET WITH VCC MONITOR AND 3.3VOLT MONITOR
2025 6.0 4/17/00
6
S4242/S42WD42/S4261/S42WD61
PIN DESCRIPTIONS
ENDURANCE AND DATA RETENTION
Serial Clock (SCL) - The SCL input is used to clock data The S42xxx is designed for applications requiring
100,000 erase/write cycles and unlimited read cycles. It
remainstablewhileSCLisHIGH.IntheREADmode,data provides 100 years of secure data retention, with or
into and out of the device. In the WRITE mode, data must
without power applied, after the execution of 100,000
is clocked out on the falling edge of SCL.
erase/write cycles.
Serial Data (SDA) - The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may Reset Controller Description
changeonlywhenSCLisLOW,exceptSTARTandSTOP The S42xxx provides a precision RESET controller that
conditions. It is an open-drain output and may be wire- ensures correct system operation during brown-out and
ORed with any number of open-drain or open-collector power-up/-downconditions. Itisconfiguredwithtwoopen
outputs.
drain RESET outputs; pin 7 is an active high output and
pin 2 is an active low output. For proper operation pin 7
should be tied low through a pull-down resistor while pin
RESET# - RESET# is an active low open-drain output. It
shouldbetiedhighthroughapull-upresistorconnectedto
VCC. RESET# is an I/O, therefore it may also be used to
condition a RESET# signal generated by another device;
it can also be used to debounce a pushbutton input.
2 should be tied high through a resistor connected to VCC
.
During power-up, the RESET outputs remain active until
VCC reaches the VTRIP threshold and will continue driving
the outputs for tPURST (200 msec)after reaching VTRIP
The RESET outputs will be valid so long as VCC is > 1.0V.
During power-down, the RESET outputs will begin driving
.
RESET - RESET is an active high open drain (PFET)
output. It should be tied low through a pull-down resistor
connected to ground. RESET is an I/O, therefore it may
also be used to condition a RESET signal generated by
another device.
active when VCC falls below VTRIP
.
The RESET pins are I/Os; therefore, the S42xxx can act
as a signal conditioning circuit for an externally applied
reset. The inputs are edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a low to
high transition and the RESET# input will initiate a reset
VSENSE - The VSENSE input is used as a second voltage
sensinginput. Thepinistiedtoacomparatorthatusesthe
precision internal 1.25V reference.
VLOW# - VLOW# is an active low open drain output driven
low whenever VSENSE is below 1.25V. It is not a timed
timeoutafterdetectingahightolowtransition.Refertothe
applications information section for more details on de-
vice operation as a reset conditioning circuit.
output and only responds to the state of VSENSE
.
Voltage Sensor Description
VSENSE is an auxiliary voltage detection circuit. Its thresh-
old is set at 1.25V and it generates a VLOW# output for an
under-voltage condition. Because the VLOW# output is
open-drain, it can be wire-ORed with the RESET# output
or tied directly to an IRQ input on a microcontroller.
2025 6.0 4/17/00
7
S4242/S42WD42/S4261/S42WD61
SCL from
Master
1
9
8
Start
Condition
Data Output
from
t
AA
Transmitter
Data Output
from
ACKnowledge
t
AA
Receiver
2025 ILL8.0
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
CHARACTERISTICS OF THE I2C BUS
willpulltheSDAlineLOWtoACKnowledgethatitreceived
the eight bits of data (See Figure 8).
General Description
The S42xxx will respond with an ACKnowledge after
recognition of a START condition and its slave address
byte. If both the device and a write operation are selected,
the S42xxx will respond with an ACKnowledge after the
receipt of each subsequent 8-bit word.
The I2C bus was designed for two-way, two-line serial
communicationbetweendifferentintegratedcircuits. The
two lines are: a serial data line (SDA), and a serial clock
line (SCL). The SDA line must be connected to a positive
supply by a pull-up resistor, located somewhere on the
bus (See Figure 6). Data transfer between devices may
be initiated with a START condition only when SCL and
SDA are HIGH (bus is not busy).
In the READ mode, the S42xxx transmits eight bits of
data, then releases the SDA line, and monitors the line for
an ACKnowledge signal. If an ACKnowledge is detected,
and no STOP condition is generated by the master, the
S42xxx will continue to transmit data. If an ACKnowledge
is not detected, the S42xxx will terminate further data
transmissions and awaits a STOP condition before return-
ing to the standby power mode.
Input Data Protocol
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock
HIGH time, because changes on the data line while SCL
is HIGH will be interpreted as start or stop condition, refer
to Figure 2.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see figure 7). For the S42xxx this is fixed as 1010[B].
START and STOP Conditions
When both the data and clock lines are HIGH, the bus is
saidtobenotbusy.AHIGH-to-LOWtransitiononthedata
line, while the clock is HIGH, is defined as the “START”
condition. A LOW-to-HIGH transition on the data line,
while the clock is HIGH, is defined as the “STOP” condi-
tion (See Figure 2).
Word Address
The next three bits of the slave address are an extension
ofthearray’saddressandareconcatenatedwiththeeight
bits of address in the word address field, providing direct
access to the 2,048 x8 array of the S4261 and S42WD61.
A10 and A9 are “Don’t Care” on S4242 and S42WD42.
DEVICE OPERATION
The S42xxx is a 16K-bit serial E2PROM. The device
supports the I2C bidirectional data transmission protocol.
The protocol defines any device that sends data onto the
busasa“transmitter”andanydevicewhich receivesdata
as a “receiver.” The device controlling data transmission
is called the “master” and the controlled device is called
the “slave.” In all cases, the S42xxx will be a “slave”
device, since it never initiates any data transfers.
Read/Write Bit
The last bit of the data stream defines the operation to be
performed. When set to “1,” a read operation is selected;
when set to “0,” a write operation is selected.
DEVICE
HIGH ORDER
IDENTIFIER
WORD ADDRESS
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
themasterortheslave, willreleasethebusaftertransmit-
ting eight bits. During the ninth clock cycle, the receiver
*
*
1
0
1
0
A10
A9
A8
R/W
*S4261/S42WD61 only
FIGURE 9. SLAVE ADDRESS BYTE
2025 ILL9.1
2025 6.0 4/17/00
8
S4242/S42WD42/S4261/S42WD61
WRITE OPERATIONS
Page WRITE
The S42xxx is capable of a 16-byte page write operation.
The S42xxx allows two types of write operations: byte It is initiated in the same manner as the byte-write opera-
write and page write. The byte write operation writes a tion,butinsteadofterminatingthewritecycleafterthefirst
single byte during the nonvolatile write period (tWR). The data word, the master can transmit up to 15 more words
page write operation allows up to 16 bytes in the same of data. After the receipt of each word, the S42xxx will
page to be written during tWR
.
respond with an ACKnowledge.
Byte WRITE
The S42xxx automatically increments the address for
After the slave address is sent (to identify the slave subsequent data words. After the receipt of each word,
device, specify high order word address and a read or the four low order address bits are internally incremented
write operation), a second byte is transmitted which byone. Thehighorderfivebitsoftheaddressbyteremain
contains the low 8 bit addresses of any one of the 2,048 constant. Should the master transmit more than sixteen
words in the array.
words, prior to generating the STOP condition, the ad-
dress counter will “roll over,” and the previously written
data will be overwritten. As with the byte-write operation,
all inputs are disabled during the internal write cycle.
Refer to Figure 10 for the address, ACKnowledge and
data transfer sequence.
Upon receipt of the word address, the S42xxx responds
with an ACKnowledge. After receiving the next byte of
data, it again responds with an ACKnowledge. The mas-
ter then terminates the transfer by generating a STOP
condition, at which time the S42xxx begins the internal
write cycle.
While the internal write cycle is in progress, the S42xxx
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 10 for the
address, ACKnowledge and data transfer sequence.
If single byte-write only,
Stop bit issued here.
Acknowledges Transmitted from
42xxx to Master Receiver
Acknowledges Transmitted from
42xxx to Master Receiver
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SDA
Bus
A
10
A
9
A
8
R
W
Word Address
Data Byte n
Data Byte n+1
Data Byte n+15
Activity
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 1 0
0
S
T
O
P
S
T
A
R
T
Device
Type
Address
A10,A9,A8
Read/Write
0= Write
Slave Address
Master Sends Read
Request to Slave
Master Writes Word
Address to Slave
Master Writes
Data to Slave
Master Writes
Data to Slave
Master Writes
Data to Slave
Master Transmitter
to
Master Transmitter
to
Master Transmitter
to
Master Transmitter
to
Master Transmitter
to
Slave Receiver
Slave Receiver
Slave Receiver
Slave Receiver
Slave Receiver
Slave Transmitter
to
Slave Transmitter
to
Slave Transmitter
to
Slave Transmitter
to
Slave Transmitter
to
Master Receiver
Master Receiver
Master Receiver
Master Receiver
Master Receiver
2025 ILL10.1
Shading Denotes
42xxx
SDA Output Active
FIGURE 10. PAGE/BYTE WRITE MODE
2025 6.0 4/17/00
9
S4242/S42WD42/S4261/S42WD61
Acknowledge Polling
READ OPERATIONS
WhentheS42xxxisperforminganinternalWRITEopera-
tion, it will ignore any new START conditions. Since the Read operations are initiated with the R/W bit of the
device will only return an acknowledge after it accepts the identification field set to “1.” There are four different read
START, the part can be continuously queried until an options:
acknowledgeisissued, indicatingthattheinternalWRITE
1. Current Address Byte Read
cycle is complete.
2. Random Address Byte Read
To poll the device, give it a START condition, followed by
a slave address for a WRITE operation (See Figure 9).
3. Current Address Sequential Read
4. Random Address Sequential Read
Current Address Byte Read
Internal WRITE Cycle
In Progress;
Begin ACK Polling
The S42xxx contains an internal address counter which
maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a read or write) was to address location n, the next read
operation would access data from address location n+1
and increment the current address pointer. When the
S42xxx receives the slave address field with the R/W bit
set to “1,” it issues an acknowledge and transmits the 8-
bit word stored at address location n+1.
Issue Start
Issue Slave
Address and
R/W = 0
Issue Stop
ACK
Returned?
No
The current address byte read operation only accesses a
singlebyteofdata. Themasterdoesnotacknowledgethe
transfer, but does generate a stop condition. At this point,
the S42xxx discontinues data transmission. See
Figure 12 for the address acknowledge and data transfer
sequence.
Yes (Internal WRITE Cycle is completed)
Next
operation a
WRITE?
No
Yes
Issue Byte
Address
Issue Stop
Await Next
Command
Proceed with
WRITE
2025 ILL11.0
FIGURE 11. ACKNOWLEDGE POLLING
A
C
K
A
10
A
9
A
8
R
W
Data Byte
1
SDA Bus Activity
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1 0 1 0
1
S
T
A
R
T
S
T
O
P
Device
Type
Address
A10,A9,A8
Read/Write
1= Read
Lack of ACK (low)
from Master
determines last
data byte to be read
Slave Address
Slave sends
Data to Master
Master sends Read
request to Slave
Slave Transmitter
to
Shading Denotes
Master Transmitter
to
42xxx
Master Receiver
SDA Output Active
Slave Receiver
2025 ILL12.1
FIGURE 12. CURRENT ADDRESS BYTE READ MODE
2025 6.0 4/17/00
10
S4242/S42WD42/S4261/S42WD61
Random Address Byte Read
After the word address acknowledge is received by the
Random address read operations allow the master to master, the master immediately reissues a start condition
access any memory location in a random fashion. This followed by another slave address field with the R/W bit
operation involves a two-step process. First, the master set to READ. The S42xxx will respond with an acknowl-
issues a write command which includes the start condi- edge and then transmit the 8-data bits stored at the
tion and the slave address field (with the R/W bit set to addressed location. At this point, the master does not
WRITE) followed by the address of the word it is to read. acknowledgethetransmissionbutdoesgeneratethestop
This procedure sets the internal address counter of the condition. The S42xxx discontinues data transmission
S42xxx to the desired address.
and reverts to its standby power mode. See Figure 13 for
the address, acknowledge and data transfer sequence.
A
C
K
A
C
K
A
C
K
*
A
10 9
*
A
A
8
R
W
A
10
A
9
A
8
R
W
Word Address
Data Byte
SDA Bus
Activity
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 1 0
0
1 0 1 0
1
1
S
T
A
R
T
S
T
A
R
T
S
T
O
P
Device
Device
Type
Address
A10,A9,A8
A10,A9,A8
Type
Address
Read/Write
0= Write
Read/Write
1= Read
Lack of ACK (low)
from Master
determines last
data byte to be read
Slave Address
Slave Address
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
Master Transmitter
to
Master Transmitter
to
Master Transmitter
to
Slave Transmitter
to
Slave Receiver
Slave Receiver
Slave Receiver
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Shading Denotes
42xxx
SDA Output Active
2025 ILL13.1
* S4261/S42WD61 only
FIGURE 13. RANDOM ADDRESS BYTE READ MODE
2025 6.0 4/17/00
11
S4242/S42WD42/S4261/S42WD61
Sequential READ
Sequential READs can be initiated as either a current During a sequential read operation, the internal address
address READ or random access READ. The first word is counter is automatically incremented with each acknowl-
transmitted as with the other byte read modes (current edge signal. For read operations, all address bits are
address byte READ or random address byte READ); incremented, allowing the entire array to be read using a
however, themasternowrespondswithanACKnowledge, single read command. After a count of the last memory
indicating that it requires additional data from the address, the address counter will ‘roll-over’ and the
S42xxx. The S42xxx continues to output data for each memory will continue to output data. See Figure 14 for the
ACKnowledge received. The master terminates the se- address, acknowledge and data transfer sequence.
quential READ operation by not responding with an
ACKnowledge, and issues a STOP conditions.
Lack of
Acknowledge from
Master Receiver
Acknowledge from
Master Receiver
Acknowledges from 42xxx
*
A
10
*
A
9
*
A
8
A
C
K
A
C
K
A
C
K
A
C
SDA Bus
Activity
R
W
A
10
A
9
A
8
R
W K
Word Address
First Data Byte
Last Data Byte
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 1 0
0
1 0 1 0
1
1
S
T
S
T
A
R
T
S
T
O
P
Device
Type
Device
Type
A
A10,A9,A8
A10,A9,A8
R Address
T
Address
Read/Write
0= Write
Read/Write
1= Read
Lack of ACK (low)
determines last
data byte to be read
Slave Address
Slave Address
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
Slave sends
Data to Master
Master Transmitter
to
Master Transmitter
to
Master Transmitter
to
Slave Transmitter
to
Slave Transmitter
to
Slave Receiver
Slave Receiver
Slave Receiver
Master Receiver
Master Receiver
Slave Transmitter
to
Master Transmitter
to
Slave Transmitter
to
Slave Transmitter
to
Master Receiver
Slave Receiver
Master Receiver
Master Receiver
2025 ILL14.1
Shading Denotes
42xxx
SDA Output Active
* S4261/S42WD61 only
FIGURE 14. SEQUENTIAL READ OPERATION (starting with a Random Address READ)
2025 6.0 4/17/00
12
S4242/S42WD42/S4261/S42WD61
Watchdog Timer Operation
VTRIP,thewatchdogwillcontinuetobeheldinaresetstate
The S42WD42/S42WD61 has a watchdog timer with a for the duration of tPURST. After tPURST, the timer will be
nominal timeout period of 1.6 seconds. Whenever the released and begin counting.
watchdog times out it will generate a reset output on both
If either reset input is asserted the watchdog timer will be
RESET# and RESET. The watchdog timer will reset to t0
reset and remain in the reset condition until either tPURST
whenever the S42WD42/S42WD61 issues an ACKnowl-
has expired or the reset input is released, whichever is
edge. Therefore, thehostsystemwillneedtoissueastart
longer.
condition, followed by a valid address and command. It
can be a normal command as in the sequence of reading If the watchdog times out and no action is taken by the
or writing to the memory, or it can be a dummy command host, the S42xxx will drive the reset outputs active for the
issued solely for the purpose of resetting the watchdog duration of tPURST at which point it will release the outputs
timer. Refer to Figure 17 for detailed sequence of opera- andbeginthewatchdogtimeragain.RefertoFigure18for
tions.
detailed sequence of operations.
The watchdog timer will be held in the reset state during
power-onwhileVCC islessthanVTRIP.OnceVCC exceeds
S
T
A
R
T
S
S
T
A
R
T
T
A
R
T
S
T
O
P
S
T
O
P
S
T
O
P
R
R
R
1 0 1 0 x x x
1 0 1 0 x x x
W
W
1 0 1 0 x x x
W
SCL and SDA Idle
SCL and SDA Idle
A
C
K
A
C
K
A
C
K
tPURST
ACK response from S42xxx
Resets The Watchdog Timer
RESET#
t < 1.6sec
t > 1.6sec
t0
t0
t0
2025 T fig17 2.0
FIGURE 17. SEQUENCE ONE
S
T
A
R
T
S
T
A
R
S
T
O
P
S
T
O
P
R
R
1 0 1 0 x x x
W
T
1 0 1 0 x x x
W
SCL and SDA Idle
SCL and SDA Idle
A
C
K
A
C
K
No Affect On tPURST
Watchdog Timer t0
tPURST
RESET#
t > 1.6sec
t > 1.6sec
t0
t0
2025 T fig18 2.0
FIGURE 18. SEQUENCE TWO
2025 6.0 4/17/00
13
S4242/S42WD42/S4261/S42WD61
8 Pin PDIP (Type P) Package
.375
(9.525)
.250
PIN 1 INDICATOR
(6.350)
.300 (7.620)
.070 (1.778)
5°-7°TYP.
(4 PLCS)
.0375 (0.952)
.015 (.381) Min.
0°-15°
SEATING PLANE
.130 (3.302)
.060 ± .005
(1.524) ± .127
TYP.
.009 ± .002
(.229 ± .051)
.100 (2.54)
TYP.
.018 (.457)
TYP.
.350 (8.89)
.130 (3.302)
8pn PDIP/P ILL.3
8 Pin SOIC (Type S) Package JEDEC (150 mil body width)
.050 (1.27) TYP.
.050 (1.270) TYP.
8 Places
.157 (4.00)
.150 (3.80)
.275 (6.99) TYP.
.030 (.762) TYP.
8 Places
1
.196 (5.00)
.189 (4.80)
FOOTPRINT
.061 (1.75)
.053 (1.35)
.020 (.50)
.010 (.25)
x45°
.0098 (.25)
.004 (.127)
.035 (.90)
.016 (.40)
.0192 (.49)
.0138 (.35)
.244 (6.20)
.228 (5.80)
.05 (1.27) TYP.
8pn JEDEC SOIC ILL.2
2025 6.0 4/17/00
14
S4242/S42WD42/S4261/S42WD61
ORDERING INFORMATION
S42 xxx P A
Base Part Number
V
TRIP
Prefix
A = 4.5V
B = 4.75V
2.7 = 2.7V
Blank = 4.5V
Suffix
42 = 4k Bits
61 = 16k Bits
WD42 = 4k, Watchdog timer
WD61 = 16k, Watchdog timer
Package
P = PDIP
S = SOIC
2025 6.0 4/17/00
15
S4242/S42WD42/S4261/S42WD61
NOTICE
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.
shall not be liable for any damages arising as a result of any error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety
or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written
assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and
(c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.
I2C is a trademark of Philips Corporation.
© Copyright 2000 SUMMIT Microelectronics, Inc.
2025 6.0 4/17/00
16
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