SML2120_技术文档

SML2120

Programmable Adaptive Laser Power Controller with Dual Lookup Tables

1

Preliminary Information (See Last Page)

–

FEATURES AND APPLICATIONS

INTRODUCTION

The SML2120 is an advanced, programmable laser diode

power controller ideal for optical networking applications.

The integrated automatic power control (APC) circuit adapts

to variations in the laser’s power output as detected by a

photo diode.

Features:

•

Integrated Automatic Power Control (APC) circuit

100 mA bias current sink capability

Dual low-current outputs (up to 2.5 mA) based on two

independent 256x8 Lookup Table values

Bias current and/or temperature monitoring capability

Dual high/low alert registers

•

The SML2120 drives two low current outputs derived from

values stored in independent 256x8 Lookup Tables. The low

current outputs are suitable for controlling the MODSET

input of typical laser driver IC’s. The input stimulus for each

Lookup Table can be configured as the laser temperature,

the bias current, or an external signal. Characteristics of the

laser’s performance over time and temperature are stored

in the lookup tables, allowing the outputs to adapt to system

conditions and optimize overall performance.

Advanced lookup algorithm eliminates unnecessary

output changes

•

Flexible voltage operation;

0 to 5V, 0 to 3.3V, or -5.2V to +3.3V

2

I C 2-wire serial bus interface for programming

configuration, control values, monitoring, and

operational status - 100KHz and 400KHz

Small 5X5 28-Pin QFN Package

•

Programming of configuration and control values by the

user are simplified with the I²C interface adapter

(SMX3200) and Windows Programming software available

from Summit Microelectronics.

Applications:

•

Laser power management for Telecom/Datacom

motherboards

•

Direct modulation and electro-absorptive modulation

applications

–

SIMPLIFIED APPLICATION DRAWING

DATA+

CAPC

Typical

V_DD(+3.3V)

DATA–

APCSET

Laser Driver

BIASMAX

+3.3V

V_DD

MODSET

OUT+

OUT–

25 VHI

ILU0

13

12

24

VDD

VBRIDGE

VDD

15

NTC

THERMISTOR 11

2

3

4

5

A1

A2

LD

BIAS 20

SML2120

EXT_TEMP

ILU1

23

14

SDA

SCL

AM#

MPD

MPD 18

16

6

7

C2

C_INT

ALERT#

Typical Laser

Diode with

Photo Diode

and Thermistor

C1 17

R_INT

Figure 1. Typical SML2120 Connections to a Laser Driver and Laser Diode

Note: This is an applications example only. Some pins, components and values are not shown.

2066 6.3 1/22/04

1

Functional Description

SML2120

–\

FUNCTIONAL DESCRIPTION

Ideally the laser requires a constant extinction ratio over its

entire operating temperature range, as the receiver module

is calibrated to this level. Operating the laser driver at a

higher extinction ratio indicates that power is being wasted,

whereas operating at a lower extinction ratio indicates that

data may possibly be lost.

The SML2120 is an adaptive power controller for laser

diodes. The device contains an active feedback loop used

to calibrate and control the mean and modulation power of

high-speed high-power laser diodes.

Inherent manufacturing tolerances introduce variations of

performance in laser diodes. These variations, combined

with parametric changes over the laser's extreme operating

temperature range and laser aging, require an efficient

compensation solution. The SML2120, together with a

minimum number of external components, is designed to

compensate for these variations using a digital control loop

and dual programmable nonvolatile calibration lookup

tables.

The required bias current increases to I_BIAS2when the laser

is operated at a second temperature (T_Hot). The laser

requires a modulation of I_MOD2to maintain a constant

extinction ratio as in the T_Coldcurve. The SML2120, with its

dual lookup table architecture (Figure 3), is capable of

providing variable output currents based on a function of

either the bias current or the external temperature, and

thereby enables the system designer to optimize the

extinction ratio of the laser driver module.

Figure 2 shows the output light power of a typical laser

diode versus its operating current. Depicted in the graph are

laser diode characteristics at two different temperatures. At

the first temperature (T_Cold), the laser requires an average

bias current of I_BIAS1. The modulation current required to

switch the laser between its ON and OFF states is labeled

The SML2120 eliminates the need for any manual

calibration of the laser control circuit. All calibration values

are programmed through the I²C industry-standard 2-wire

communication interface whose protocol and functions can

be controlled by automated test equipment (ATE).

I_MOD1

.

The ratio of light power of its ON state divided by the light

power of its OFF state is referred to as the extinction ratio.

Figure 2. Laser Current Increase Caused by Temperature Increase, Constant Light Power Out

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Summit Microelectronics

SML2120

Functional Block Diagram

–

FUNCTIONAL BLOCK DIAGRAM

VAPC

22

MPD

18

C1

17

C2

16

ENA#

1

VBURST

19

Internal

0.75V

Reference

-

Current Generator

20 BIAS

+

Quick

Start

Bias to Voltage

Converter

28 BIASMON

23

EXT_TEMP

Bridge

Circuit

CH1 Previous

12

VBRIDGE

Conversion

+

-

+

-

11 THERMISTOR

CH2 Previous

Conversion

VSS

Temp to Voltage

Converter

27

26

TEMPMON

Scale

Comparison

Logic

10-BIT ADC

&

Offset

8

MPD to Voltage

Converter

POWERMON

Address Decode

CH1 High/Low

Limits

256 x 8

E²PROM

Lookup

Table

256 x 8

E²PROM

Lookup

Table

Alarm

Logic

CH2 High/Low

Limits

A1

A2

2

3

4

5

6

7

I²C

High Range

DAC

SDA

2-Wire

Serial

SCL

Interface

AM#

ALERT#

8-BIT DAC

13

Current Generator

ILU0

256 x 8

E²PROM

Low Range

DAC

General

Purpose

VLOW

VSS

8

9

High Range

DAC

VSS 10

VSS 21

VDD 15

VDD 24

VHI 25

Power

Distribution

8-BIT DAC

Current Generator

14 ILU1

Low Range

DAC

Figure 3. SML2120 Block Diagram

Summit Microelectronics

2066 6.3 1/22/04

3

Package and Pin descriptions

SML2120

–

PACKAGE AND PIN DESCRIPTIONS

Pin 1

ENA#

A1

VSS

BIAS

VBURST

MPD

A2

SDA

SCL

AM#

C1

C2

ALERT#

VDD

Figure 4. 28-Pin QFN Package Pinout (top view)

PIN DESCRIPTIONS

PACKAGE AND PIN DESCRIPTIONS

PIN DESCRIPTIONS

Pin Number Pin Type

Pin Name

ENA#^*

A1*

Description

1

2

3

4

5

I

Active low input enables the BIAS, ILU0 and ILU1 output currents.

I

The address pins are connected to either the VHI or VLOW pins to provide a

mechanism for assigning a unique I²C bus address to the SML2120.

A2^*

I/O

I

SDA^*

SCL^*

Bi-directional I²C serial data pin

I²C serial clock input

AM# is an active low input, when asserted the SML2120 is placed in the Auto-

Monitor mode. AM# must be high for programming the Configuration registers

and the Lookup Tables, ILU0 and ILU1 and the general purpose E²PROM.

6

I

AM#^*

Active low, open-drain output indicates when one of the monitored inputs

exceeds its user-programmable high or low alert levels.

7

8

O

ALERT#^*

VLOW

In dual-rail supply voltage systems, VLOW is tied to the system logic low

potential. It is a logic low reference for all pins marked with an asterisk (*).

PWR

9

PWR

VSS

VSS must be tied to the lowest system voltage potential.

10

Connect a thermistor to this pin to provide an alternative source of temperature

sensing (see VBRIDGE description).

11

I

THERMISTOR

* See VLOW and VHI pin descriptions.

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SML2120

Pin Descriptions

Pin Number Pin Type

Pin Name

Description

Connection to an external Full-Bridge Sensor when used with the Thermistor pin.

Two of the full-bridge resistors are internal. See the Bridge Circuit Diagram in

Figure 1 and 3. Voltage level is 0.2V with respect to VSS.

12

O

VBRIDGE

Current output resulting from Lookup Table 0. User-programmable to either sink

(to VSS) or source (to VDD) up to 2.5mA.

13

14

I/O

ILU0

ILU1

Current output resulting from Lookup Table 1. User-programmable to either sink

(to VSS) or source (to VDD) up to 2.5mA.

15

16

17

PWR

VDD

C2

VDD is the positive rail for most internal functions.

I

Place a capacitor (C_INT) between C1 and C2 to increase the time constant for the

APC integrator.

C1

Monitor Photo Diode anode input. Connect a resistor between MPD and C1 to

work in conjunction with C_INTto establish the integrator time constant.

18

19

20

I

MPD

VBURST

BIAS

In burst mode, this input supplies a ballast current that allows the SML2120 to

quickly restart when ENA# is asserted.

Supplies the main laser current as controlled by the APC circuit; capable of

sinking up to 100mA to VSS.

21

22

PWR

I/O

VSS

VSS must be tied to the lowest system voltage potential.

APC Override pin.

VAPC

This input can be configured to sense either a voltage or current generated from

an external temperature monitoring device.

23

24

25

I

EXT_TEMP

VDD

PWR

VDD is the positive rail for most internal functions.

In dual-voltage rail systems, VHI is tied to the system logic high potential. It is the

logic high reference for all pins marked with an asterisk (*).

VHI

Analog output voltage indicating the state of the Monitor Photo Diode (MPD)

input.

26

O

POWERMON^*

Analog output voltage proportional to the temperature as sensed by the

EXT_TEMP or THERMISTOR input.

27

28

O

TEMPMON^*

BIASMON^*

Analog output voltage proportional to BIAS current.

* See VLOW and VHI pin descriptions.

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2066 6.3 1/22/04

5

Absolute Maximum Ratings

SML2120

–

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

Temperature Under Bias.............................–55°C to 125°C

Power Supply Current (I_DD).....................................115 mA

Storage Temperature ..................................–65°C to 150°C

Solder Temperature (10 seconds) ............................300 °C

Temperature Range (Ambient) ................. -40^oC to +85^oC

Supply Voltage(V_DD).................................... 3.135V to 5.5V

Package Thermal Resistance (θ_JA) 28-pin QFN..... 80^oC/W

Moisture Classification Level 1 (MSL 1) per J-STD-020

Reliability Characteristics

Terminal Voltage with Respect to V_SS

:

All inputs..................................................-0.3V to 6.0V

Open Drain Output Short Circuit Current.................100 mA

Junction Temperature ................................................150^oC

ESD Rating per JEDEC.............................................2000V

Latch-Up testing per JEDEC..................................± 100mA

Data Retention.....................................................100 Years

Endurance¹................................................. 100,000 Cycles

Stresses listed under Absolute Maximum Ratings may cause permanent

damage to the device. These are stress ratings only, and functional operation

of the device at these or any other conditions outside those listed in the

operational sections of this specification is not implied. Exposure to any

absolute maximum rating for extended periods may affect device

performance and reliability.

DC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to V .)

SS

Unit

Symbol

Parameter

Conditions

Min

Typ

Max

Supply voltage

Max bias and modulation

current

V_DD

3.135

5.5

V

I_DD3

I_DD5

Power supply current

Stand-by supply current

Input leakage current

Output leakage current

Output low voltage

V_DD=3.3V, Bias and Mod open

V_DD=5.5V, Bias and Mod open

V_DD=3.3V, ENA#,AM#=V_IH

V_DD=5.5V, ENA#,AM#=V_IH

Vin = 0V to Vdd

2

2.5

5.0

mA

µA

V

I_SB3

2.0

I_SB5

5.0

I_LI

1

I_LO

Vout = 0V to Vdd

1

V_OL

I_OL= 2 mA

0.4

V_IL

Input low voltage

-0.1

0.3 x Vdd

Vdd

V

V_IH

Input high voltage

0.7 x Vdd

V

Analog Inputs

V_MPD

MPD input active range

0

2

V

µA

V

I_{EXT_TEMP}Full Scale Input Current range Note ¹

V_{EXT_TEMP}Full Scale Input Voltage range V_DD=3.3V to 5V

Analog Outputs

78.1

3.3

Maximum full-scale sink

I_LUNMAX

I_LUPMAX

I

_LU0,I_LU1

-2.350

-2.650

mA

modulation current

Maximum full-scale source

modulation current

I_{LU0, LU1}

I

2.280

-90

2.720

-110

mA

I_BIASMAXMaximum full-scale bias current

1. Guaranteed by design.

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2066 6.3 1/22/04

Summit Microelectronics

SML2120

DC Operating Characteristics

–

DC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to V .)

SS

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Analog Outputs

Automatic power control loop

default voltage

V_APC

V_POR

0.735

0.765

V

Supply voltage level required to

guarantee register readout

2.9

0.19

-2

V

V_BRIDGEV_BRIDGEoutput voltage

0.21

+2

BIASMON Full Scale Accuracy

(see page 13)

V_BIASMON

%

POWERMON Full Scale

V_POWERMON

-4

+4

40

%

Accuracy (see page 13)

I_LOAD= ±10µA

TEMPMON Full Scale

V_TEMPMON

Accuracy (see page 13)

BIASMON, POWERMON,

V_MONZSO

mV

TEMPMON Zero Scale Offset

AC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to V .)

SS

Symbol

Description

Conditions

Min

Typ

Max

Unit

Time when VDD reaches VPOR threshold to

when the device is ready

t_POR

Power-On-Reset Time

5

ms

t

t_HOLDOFFHoldoff timeout period

t_SAMPLESample Time Interval

-20

+20

%

HOLDOFF

t

SAMPLE

ADC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to V .)

SS

Symbol

Description

Conditions

Min

Typ

Max

Unit

N

Resolution

Note ¹

8

Bits

Minimum resolution for which no

missing codes are guaranteed

Note ¹

MC

S/N

INL

Missing Codes

8

50

-1

Bits

db

Signal to Noise Ratio

Relative accuracy

Differential nonlinearity

EXT_TEMP voltage input; 0 to

3.3V

+1

LSB

DNL

-1/2

+1/2

1. Guaranteed by design.

Summit Microelectronics

2066 6.3 1/22/04

7

DAC Operating Characteristics

SML2120

DAC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to V .)

SS

Symbol

Description

Conditions

Min

Typ

Max

Unit

8-bit Current DAC Accuracy (When configured to sink current to VSS, V_ILU=1V)

N

Resolution

8

-3

bits

LSB

%

Note ¹, 10% to 90% of current scale

Note ², 10% to 90% of current scale

+3

+7

INL

Relative accuracy

-7

DNL

Gain

Differential nonlinearity

-1

+1

Positive full scale gain error

-2

+2

Note ¹

Note ²

V_DD=5.5V, Note ¹

-4

+4

LSB

µA

Offset Offset error

-10

0

+10

25

_DD=5.5V, Note ²

V_DD=3.135V, Note ²

0

50

µA

3

I_ZSE

Zero-scale error current

V

0

165

+150

µA

3

I_FSE

Full-scale error current

-150

µA

8-bit Current DAC Accuracy (When configured to source current from VDD, V_ILU=1V)

N

Resolution

8

-7

bits

LSB

%

INL

Relative accuracy

10% to 90% of current scale

+7

+1

+2

+12

0

DNL

Gain

Differential nonlinearity

Positive full scale gain error

-1

-2

Offset Offset error

-12

-30

-50

165

-220

LSB

µA

V

_DD=5.5V, Note ¹

3

I_ZSE

Zero-scale error current

V_DD=5.5V, Note ²

V_DD=3.135V, Note ²

0

µA

0

µA

3

I_FSE

Full-scale error current

+220

µA

1. Low Range DAC at lowest value; High Range DAC at highest value.

2. Any Combination of DAC settings.

3. I_ZSEand I_FSEnot adjusted for Gain and Offset.

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2066 6.3 1/22/04

8

SML2120

I2C 2-Wire Serial Interface AC Operating Characteristics

–

2

I C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to V .)

SS

100kHz

Max

400kHz

Max

Symbol

Parameter

Conditions

Min

0

Units

kHz

µs

Min

0

Units

kHz

µs

f_SCL

SCL clock frequency

100

400

t_LOWClock period low

t_HIGHClock period high

4.7

4.0

4.7

4.0

1.3

0.6

1.3

0.6

µs

t_BUF

Bus free time¹

Before new transmission

µs

t_SU:STAStart condition setup time

t_HD:STAStart condition hold time

t_SU:STOStop condition setup time

µs

Clock edge to valid output

t_AA

SCL low to valid

SDA (cycle n)

0.3

3.5

µs

0.3

0.9

µs

Data out hold time

t_DH

SCL low (cycle n+1)

to SDA change

t_R

t_F

SCL and SDA rise time¹

SCL and SDA fall time¹

1000

300

ns

ms

1000

300

ns

ms

t_SU:DATData in setup time

t_HD:DATData in hold time

250

0

150

0

t_I

Noise filter SCL and SDA¹

Noise suppression

100

10

100

10

t_WR

Write cycle time

1. Guaranteed by the design.

t_{WR (For Write Operation Only)}

t_HIGH

t_LOW

t_R

t_F

SCL

t_BUF

t_HD:DAT

t_SU:DAT

t_SU:STA

t_SU:STO

t_HD:STA

SDA

(IN)

t_AA

t_DH

SDA

(OUT)

2

Basic I C Timing Diagram

Summit Microelectronics

2066 6.3 1/22/04

9

Applications Information

SML2120

–

APPLICATIONS INFORMATION

Power-Up Sequence

When power is first applied to the SML2120, the device

reads configuration register information from the array and

loads it to volatile latches. This procedure begins once the

supply voltage exceeds the power-on reset voltage (VPOR)

and requires about 3 ms to complete. During this

initialization period, all current outputs (BIAS, ILU0, ILU1)

are placed into a high impedance state.

C1

C2

Photodiode

Laser

BIAS

MPD

-

+

Quick

Start

At the conclusion of the initialization period, the ENA# pin

determines the state of the current output. However, the

autonomous monitoring (auto-monitor) function is not yet

allowed to activate, regardless of the state of the AM# pin.

A holdoff timer period (t_HOLDOFF) is counted off at the

conclusion of the initialization period to allow the laser

control loop to stabilize. After t_HOLDOFF, the AM# pin

determines whether the device begins its auto-monitor

sequence or not. If AM# is asserted, the device enters auto-

monitor mode.

GND

VAPC

20KΩ

Internal

Reference

Voltage

0.75

SML2120

Figure 5. Bias Control Circuit

Bias Output

Automatic Power Control (APC) Loop

The user may limit the maximum BIAS current in increments

of 12.5mA (up to a maximum of 100mA), using register 14

bits 2:0. This feature is useful in preventing damage to the

laser even during start-up or open-loop conditions.

The SML2120 provides an efficient feedback mechanism

for controlling the light output of the laser. Once the power-

on initialization period has expired, current to the laser is

driven by the BIAS pin, which can sink up to 100 mA of

current to Vss. An on-board amplifier controls the bias

output circuitry. The Monitor Photo Diode (MPD) pin is

driven from the anode of a photo-diode that monitors the

light power being given off by the laser. Adding an

Additionally, the BIAS output may be configured to provide

a fixed current. The value of current is based on the ILU1

output and scales proportionally. This fixed bias current may

be configured so that it is available at power-up only, or

whenever ENA# is disabled. This feature is useful in

systems without a monitor diode, or in systems where feed-

forward current is desired. A fixed current is also useful for

providing reasonable BIAS when no data is yet flowing, and

for diagnostics and board debugging.

integration capacitor between C1 and C2, and

corresponding resistor between MPD and C1, completes

and stabilizes the loop, as is shown in Figure 5.

a

The APC loop attempts to drive the C1 node to the internal

VAPC voltage reference of 0.75V. If the voltage on the MPD

pin exceeds VAPC, the SML2120 reduces the amount of

current on the BIAS pin accordingly, thereby reducing the

amount of current to the laser. Conversely, if the voltage on

MPD falls below VAPC, the amount of current supplied to

the laser is increased. Note that the VAPC pin may be over-

driven using an external reference if a different steady state

value is desired.

Autonomous Monitoring Function (Auto-

Monitor)

The Autonomous Monitoring (Auto-Monitor) Function

provides a control loop for setting two independent output

currents (ILU0 and ILU1) based on various programmable

input stimuli within the system. For each channel, the user

selects: 1) an input stimulus for the Analog/Digital Converter

(ADC), 2) scale and offset values for the conversion to

maximize the usable input range, 3) lookup table values that

translate the resulting ADC conversion to an output current,

and 4) minimum and maximum limits for the output current

driver. Refer to Figure 6.

The integration time constant of the APC loop is typically set

to a relatively long period (such as 1ms) in order to reduce

pattern dependent jitter. Unfortunately, a long time constant

also leads to a long start-up time. The SML2120 provides an

internal 'Quick Start' transistor, shown in Figure 5, that can

be used to accelerate the turn-on time of the laser. When

this feature is enabled, the Quick Start transistor effectively

shorts out the external resistor for a brief time period after

the outputs are first enabled.

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SML2120

Applications Information

Table 1. Channel Configuration and Full Scale Value

CFG 6/7,

Bits [6:5]

Input Stimulus

Nominal ADC

Input Range

EXT_TEMP

10

8

Compare

Logic

Scale/

Offset

THERMISTOR

BIAS

ADC

00

01

10

11

Thermistor

.1V - .2V

0 - 3.3V

EXT_TEMP Voltage

EXT_TEMP Current

Bias Current

Decode Logic

0 - 78.125uA

0 - BIAS MAX

Lookup Lookup

Table

0

Table

1

LU0

LU1

DAC

Each LUT is configured to be associated with any one of the

four ADC inputs. The only restriction is that you may not

associate one LUT to the EXT_TEMP voltage and the other

LUT to EXT_TEMP current. The EXT_TEMP pin is

configured to accept only one or the other.

Figure 6. Simplified Autonomous Monitoring Diagram

The Lookup (translation) Table (LUT) values are generally

loaded once during test and calibration using ATE

equipment. More sophisticated systems may periodically

take the system off-line, take some measurements, and

update the table throughout the life of the laser module. Well

characterized phenomenon may be ordered from Summit

Microelectronics with table values pre-programmed. One

advantage of a LUT is that arbitrary, or nth-order, functions

may be easily mapped. Also, table values may be tweaked

late in the design stage to improve or modify performance

characteristics.

In addition to selecting the ADC input source for each LUT,

the user must also select a scale value (1x, 2x, 4x or 8x) and

offset value (0 through 7 eighths of full scale) for each LUT.

The purpose of the scale and offset selection is to maximize

the resolution of the ADC output. In order to maintain

accuracy while using scale values greater than 1x, a 10-bit

ADC has been employed, even though only eight bits are

used.

The following example illustrates the use of scale and offset

to achieve the maximum resolution out of the ADC.

Configure one LUT to be driven from the laser bias current.

The laser manufacturer specs a maximum current of 90mA;

the laser module has a useful bias current range that spans

from a minimum of 46mA to a maximum of 83mA.

As the name implies, the Auto-Monitor function requires no

input from external controllers or processors. This function

may be initiated by pulling the AM# pin low, or by addressing

the SML2120 through the Status Register. On power-up, a

holdoff timer prevents the auto-monitor function from

commencing until the system has had time to stabilize.

When the current outputs are disabled (by pulling ENA#

high), the auto-monitor function is internally suspended until

the outputs are once again enabled.

First, configure the maximum bias current to 100mA*7/8 =

87.5mA to protect the laser. Determine the proper scale

factor by taking the full scale current (87.5mA) and divide by

the target input range (83mA - 46mA = 37mA) and round

down to the nearest scale value (87.5mA / 37mA = 2.36 ->

2x). The offset is determined by finding the highest offset

value that is less than the minimum input value (46mA).

Offset values are integer multiples of 1/8 of the full scale

amount (87.5mA). In this example choose an offset of

43.75mA ( = 4*87.5mA / 8).

Analog-to-Digital Converter (ADC)

The internal analog-to-digital converter can be configured to

measure various critical system parameters, which allows

the SML2120 to dynamically react to changes in its

operating environment. There are four different inputs that

may be multiplexed to the ADC: bias current, thermistor

voltage, external voltage or external current. The external

voltage or current is sensed via the EXT_TEMP pin. The

input range for each of the different inputs is shown in Table

1.

By using the values for scale and offset in this example, a

zero reading out of the ADC corresponds to a bias current

of 43.75mA (or less), and a full scale reading (0FFh) out of

the ADC corresponds to a bias current of 87.5mA (or

greater).

Summit Microelectronics

2066 6.3 1/22/04

11

Applications Information

SML2120

Thermistor Interface

Burst Mode

The SML2120 has circuits built-in to help facilitate using a

thermistor to measure laser temperature. The VBRIDGE pin

provides a .2V output reference to drive half of a bridge

circuit that includes the thermistor and one other external

resistor. The other half of the bridge is internal to the device.

The external components are placed between the

VBRIDGE, THERMISTOR, and VSS pins as shown in

Figure 3.

The SML2120 is designed to work in applications that

require burst mode operation. The output currents (ILU0,

ILU1 and BIAS) may be switched on and off by using the

ENA# pin. In applications that require very high speed

operation, the VBURST pin may be used as a ballast load

for the BIAS current. When ENA# is de-asserted, all current

that was flowing through the BIAS output is diverted to the

VBURST pin. For optimal performance, the load attached to

VBURST should closely resemble the load of the laser in

order to keep internal nodes biased at the correct levels.

Additionally, the ENA# pin should be configured for "FAST

MODE" by setting Config Reg 15, Bit 7 high. This setting

increases the throughput of the enabling signal by

eliminating noise filters on the input; this setting also

eliminates the VHIGH/VLOW level shifter. Thus, when using

the ENA# pin in FAST MODE, the input levels need to range

between VDD and VSS, rather than VHIGH and VLOW.

(Applicable only in dual voltage systems.)

Programmable Current Outputs

There are two fully independent, programmable current

outputs on the SML2120: ILU0 and ILU1. The output

polarity (source or sink current), as well as the upper and

lower current limit may be individually programmed to meet

varying output requirements. The upper and lower limits for

each channel may be set between 0 and 2.5 mA in 256

steps. These limits can help prevent damage to

components receiving the output current, and they increase

resolution in the desired operating range. The final output

current is determined by an 8-bit DAC that ranges between

the upper and lower current limits (refer to Figure 7). A

power-up register determines the initial DAC setting; during

Auto-Monitor operation, data read out of the array is loaded

into the DAC register to determine the output current.

2

E PROM

The SML2120 contains 6k bits of user-accessible E²PROM

memory. Each LUT is comprised of 2k bits arranged as 256

words by 8 bits. LUT0 occupies addresses 000h - 0FFh and

LUT1 occupies addresses 100h - 1FFh, both using the I²C

slave address of 1011. A third 2k block of E²PROM is

available to the user as a general-purpose memory. This

block is accessed via slave address 1010, memory

addresses 000h - 0FFh.

256x8

EPROM

(register 14, bit 6)

Polarity

Lookup

Table

0

Device configuration information is stored in 16 non-volatile

registers located at addresses 100h - 10Fh, also under the

slave address 1010. Note that the user may program the

device to prevent any further writes to this configuration

space.

Select

(register 11)

High Range

Source

Current

DAC

ILU0

Power Up

Register

Current

Sink

(register 8)

Low Range

(register 10)

Refer to the "Configuration Register Description" section

below for details of the available configuration settings.

Refer to "I²C Interface" section for further details and

examples of communicating with the SML2120 over the I²C

bus.

ILU0 Lookup

256x8

EPROM

(register 14, bit 7)

Polarity

Lookup

Table

1

Status Register

Select

(register 13)

High Range

Source

Current

The Status register is a volatile register that allows the user

to control and receive feedback from the device, accessible

using the 1001 slave address at memory address 00Fh.

Table 2 describes the status byte:

DAC

ILU1

Power Up

Register

Current

Sink

(register 9)

Low Range

(register 12)

ILU1 Lookup

Figure 7. Independent Lookup Tables

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Summit Microelectronics

SML2120

Applications Information

Table 2. Status Register

Slave Address 1001, Word Address 00Fh

Table 3. Voltage Supply Modes

Single

Dual Supply

Supply

Bit

7

I/O

Output

-

Description

Alert Channel

Alert Limit (Hi/Low)

Unused

VDD

VSS

3.0V to 3.6V

0V

4.5V to 5.5V

0V

-5.5V to

-4.9V

6

5:4

3

3.0V to

3.6V

VHI

3.0V to 3.6V

0V

4.5V to 5.5V

0V

I/O

Alert

2

I/O

Auto-Monitor

Output Enable

Write Protect

VLOW

0V

1

I/O

Digital

Interface

0V TO 3.6v

0V TO 5.5V

0V to 3.6V

0

I/O

Analog Monitor Outputs

Bits 7 and 6 are read-only bits that indicate the offending

channel and limit, respectively, during an alert condition.

Bits 3:0 are I/O's that indicate the status of the device when

read out, and affect operation of the device when written to.

Bit 3 represents the state of the ALERT# output; when this

bit is high, the ALERT# output is asserted. Writing a zero to

this bit will de-assert the ALERT# output. Bits 2 and 1

represent the state of the Auto-Monitor and Output Enable

functions, respectively. On power-up, these functions are

controlled by the appropriate pin, AM# or ENA#; however,

the state of either pin may be overridden by writing to the

selected bit of the status register. Bit 0 controls the write

protect status of the device; no data may be changed until

this bit is cleared.

There are three analog monitor outputs on the SML2120

that provide a continuous measure of the critical parameters

in the system. The POWERMON output reflects the state of

the APC loop, which is an indirect measure of the laser

power output. The TEMPMON output has different

characteristics depending on which input has been selected

as the temperature pin. If the ADC input for either LUT0 or

LUT1 is selected to be from the THERMISTOR pin, then the

TEMPMON output is a level-shifted and amplified version of

the THERMISTOR input. Otherwise, the TEMPMON output

is generated based on the voltage on the EXT_TEMP pin.

The BIASMON output indicates the instantaneous bias

current. All three of these outputs are level-shifted up to the

VHIGH/VLOW rail as described by the following equations:

Dual Voltage Operation

V_POWERMON- V_LOW= (V_C1- V_SS

)

The SML2120 was designed to operate with a single-ended

supply (i.e. 3.3V or 5V), or in a dual voltage environment of

–5.2V, 0V, and +3.3V. It is common for many lasers to be

driven off the –5.2V rail, while the interface runs on the

positive supply. The SML2120 runs entirely between VDD

and VSS, with the exception of the digital interface pins

(pins 1-6) and three analog monitor pins (26-28), which are

driven between VHI and VLOW. Table 3 details the different

modes of operation. In all cases, current outputs are

sourced from VDD and sink to VSS.

V_TEMPMON- V_LOW= (V_{EXT_TEMP}- V_SS) or

25 * ((V_THERMISTOR- V_SS) - 0.1)

V_BIASMON- V_LOW= 2 * I_{BIAS BIASMAX}

/I

Serial Interface

The SML2120 uses the industry standard I²C, 2-wire serial

interface. This interface provides access to the status

registers, ADC, general purpose E²PROM, configuration

registers and LUT tables according to Table 4. Associated

with the interface are two address pins (A2 and A1), which

allow up to four devices on the same bus.

Summit Microelectronics

2066 6.3 1/22/04

13

Applications Information

SML2120

Table 4. SML2120 Access Types

Compatible Laser Drivers

Slave

A0

Access Type

The SML2120 is compatible with a wide array of laser

drivers from many different manufacturers. The SML2120

controls the power, biasing and modulation current

independent of the data rate of the laser driver. Therefore, it

can be applied with drivers that operate at sub-GHz,

2.5GHz, 10GHz and 40GHz rates. An example application

for an electro-absorptive modulated laser is shown in

Figure 8. The SML2120 interfaces to the laser module

thermistor, monitor diode and laser diode to control bias and

modulation levels over temperature.

Address (Address bit 8)

0

Read/Write Status registers

Read A/D converter

1001

1

0

General Purpose E²PROM

1010

1

Configuration registers

0

Read/Write Lookup Table 0

Read/Write Lookup Table 1

1011

1

Another application example is shown in Figure 9. Here,

the SML2120 is shown controlling a laser diode and an

external thermistor. The thermistor output is monitored and

also buffered to drive the external temperature pin which is

connected to one of the LUTs on the SML2120. Also shown

are the optional connections for dual supply operation and

connections to the SMX3200 programmer header.

Device configuration and access is simplified using the

SML2120 graphical user interface (GUI) software available

from the Summit website (www.summitmicro.com). This

software utilizes

a programming dongle (SMX3200)

connected to the parallel port of a PC to read and write the

device.Compatible Laser Drivers

14

2066 6.3 1/22/04

Summit Microelectronics

SML2120

Applications Information

–

+

T A D A

T U V O

V A P C

2 2

1 1

T H E R M IST O R

V S S

2 1

1 0

9

V B R ID G E

B IA S

1 2

2 0

E X T _T E M P

2 3

1 8

1 7

1 6

M P D

C 1

V L O W

E N A #

V D D

8

1

C 2

2 4

1 5

A d d res s

= 0

V D D

Figure 8. Typical Electro-Absorptive Modulated Laser Application (-5.2V Supply)

Summit Microelectronics

2066 6.3 1/22/04

15

Applications Information

SML2120

Figure 9. Typical laser applications schematic showing programming and dual supply connection options.

2066 6.3 1/22/04 Summit Microelectronics

16

SML2120

DEVELOPMENT HARDWARE & Support

–

DEVELOPMENT HARDWARE & SUPPORT

The end user can obtain the Summit SMX3200

programming system for device prototype development.

The SMX3200 system consists of a programming Dongle,

cable and Windows GUI software. It can be ordered on the

website or from a local representative. The latest revisions

of all software and an application brief describing the

The Windows GUI software will generate the data and send

it in I²C serial bus format so that it can be directly

downloaded to the SML2120 via the programming Dongle

and cable. An example of the connection interface is shown

in Figure 10.

SMX3200

is

available

from

the

website

When design prototyping is complete, the software can

generate a HEX data file that should then be transmitted to

Summit for approval. Summit will then assign a unique

customer ID to the HEX code and program production

devices before the final electrical test operations. This will

ensure proper device operation in the end application.

(www.summitmicro.com).

The SMX3200 programming Dongle/cable interfaces

directly between a PC’s parallel port and the target

application. The device is then configured on-screen via an

intuitive graphical user interface employing drop-down

menus.

Top view of straight 0.1" x 0.1 closed-side

connector. SMX3200 interface cable connector

Pin 10, Reserved

Pin 8, Reserved

Pin 6, MR#

Pin 9, 5V

Pin 7, 10V

D1

Pin 5, Reserved

Pin 3, GND

Pin 1, GND

Pin 4, SDA

15,24

VDD

Pin 2, SCL

10

9

7

5

3

1

8

6

4

2

C1

0.1 F

SML2120_{AM# 6}

SDA 4

SCL 5

VSS

9,10,21

Common

Ground

Figure 10. SMX3200 Programmer and I²C serial bus connections to program the SML2120. For the SML2120, the

AM# pin must be high in order to program the device. Normally, SDA and SCL signals require on board pull-up

resistors, however, the SMX3200 has internal pull-up resistors. D1 is needed between the Dongle Supply and the

VDD pin so that there will be no contention between the two supplies. C1 is for noise bypassing. Note, AM# must

be high for programming, it can be pulled high externally or by the SMX3200 programmer. AM# must be low for

auto-monitor mode operation.

Summit Microelectronics

2066 6.3 1/22/04

17

I2C Interface

SML2120

–

2

I C INTERFACE

The I2C bus is a standard two-wire serial communication

interface used between different integrated circuits. The

two lines are serial data (SDA), which is a bi-directional pin,

and serial clock (SCL). The SML2120 supports a 100kHz

and 400kHz clock rate.

is called the Slave. In all cases the SML2120 is referred to

as a Slave device since it never initiates any data transfers.

Acknowledge

Data is always transferred in bytes. Acknowledge (ACK) is

used to indicate a successful data transfer. The transmitting

device releases the bus after transmitting eight bits. During

the ninth clock cycle the Receiver pulls the SDA line low to

acknowledge that it received the eight bits of data. This is

shown by the ACK callout in Figure 12.

The SDA line must be connected to a positive supply by a

pull-up resistor located on the bus. The SML2120 contains

a Schmitt input on both the SDA and SCL signals.

When the slave address is 1001 and address bit 8 is low,

the Status register is accessed. When bit 8 is high, the A/D

converter is read. The channel read from the ADC is deter-

mined by the word address (see Figure 18).

When the last byte has been transferred to the Master

during a read of the SML2120, the Master leaves SDA high

for a Not Acknowledge (NACK) cycle. This causes the

SML2120 part to stop sending data, and the Master issues

a Stop on the clock pulse following the NACK.

When the slave address is 1010 and address bit 8 is low, the

General Purpose E²PROM is accessed. When bit 8 is high,

the Configuration registers are accessed.

Figure 12 shows the Acknowledge timing.

When the slave address is 1011, address bit 8 determines

whether Lookup Table 0 or 1 is accessed. If bit 8 is ‘0’,

Lookup Table 0 is accessed. A ‘1’ accesses Lookup Table 1.

See Figure 23 and 24.

3

9

1

2

8

SCL

SDA

Trans

Start and Stop Conditions

SDA

Rec

ACK

Both the SDA and SCL pins remain high when the bus is not

busy. Data transfers between devices may be initiated with

a Start condition only when SCL and SDA are high. A high-

to-low transition of the SDA while the SCL pin is high is

defined as a Start condition. A low-to-high transition SDA

while SCL is high is defined as a Stop condition. Figure 11

shows a timing diagram of the start and stop conditions.

2050 Fig11

Figure 12. Acknowledge Timing

Read and Write

The first byte from a Master is always made up of a 7-bit

Slave address and the Read/Write (R/W) bit. The R/W bit

tells the Slave whether the Master is reading data from the

bus or writing data to the bus (1 = Read, 0 = Write). The first

four of the seven address bits are called the Device Type

START

STOP

Condition

SCL

Identifier (DTI). The DTI for the SML2120 is 1010_BIN

.

The next three bits are Address values for A2, A1, and A0

(if multiple devices are used). In the SML2120, A0 functions

as address bit 8. Refer to Table 4 for more information on

the state of address bit 8 and the access types supported.

SDA In

2050 Fig10 2.0

Figure 11. Start and Stop Conditions

Master/Slave Protocol

The SML2120 issues an Acknowledge after recognizing a

Start condition. Figure 13 shows an example of a typical

master address byte transmission.

The master/slave protocol defines any device that sends

data onto the bus as a transmitter, and any device that

receives data as a receiver. The device controlling data

transmission is called the Master, and the controlled device

18

2066 6.3 1/22/04

Summit Microelectronics

SML2120

and the Slave address field (with the R/W bit set to Write)

followed by the address of the word it is to read. This

procedure sets the internal address counter of the SML2120

to the desired address.

SCL

3

1

5

x

1

2

4

0

6

x

7

x

8

9

1

0

R/W

ACK

SDA

2050 Fig12

Figure 13. Typical Master Address Byte Transmission

After the word address Acknowledge is received by the

Master, it immediately reissues a Start condition followed by

another Slave address field with the R/W bit set to Read.

The SML2120 responds with an Acknowledge and then

transmits the 8 data bits stored at the addressed location. At

this point, the Master sets the SDA line to NACK and

generates a Stop condition. The SML2120 discontinues

data transmission and reverts to its standby power mode.

During a read by the Master device, the SML2120 transmits

eight bits of data, then releases the SDA line, and monitors

the line for an Acknowledge signal. If an Acknowledge is

detected, and no Stop condition is generated by the Master,

the SML2120 continues to transmit data. If an Acknowledge

is not detected (NACK), the SML2120 terminates any

subsequent data transmission. The read transfer protocol

on SDA is shown in Figure 14.

Sequential Reads

Sequential reads can be initiated as either a current address

read or a random access read. The first word is transmitted

as with the other byte Read modes (current address byte

Read or random address byte Read). However, the Master

now responds with an Acknowledge, indicating that it

requires additional data from the SML2120.

S

T

A

R

T

N S

A

T

C O

K

P

R

/

W

A

C

K

Master

SDA

x x x

0 1 0

x x x x x x x x

x x

R

1

A

C

K

Slave

The SML2120 continues to output data for each

Acknowledge received. The Master sets the SDA line to

NACK and generates a Stop condition. During a sequential

Read operation the internal address counter is

automatically incremented with each Acknowledge signal.

2050 Fig13

Figure 14. Read Protocol

During a Master write, the SML2120 receives eight bits of

data, then generates an Acknowledge signal. It device

continues to generate the ACK condition on SDA until a

Stop condition is generated by the Master. The write transfer

protocol on SDA is shown in Figure 15.

For Read operations all address bits are incremented,

allowing the entire array to be read using a single Read

command. After a count of the last memory address the

address counter rolls over and the memory continues to

output data.

S

Transaction Types

T

A

R

T

S

T

O

P

R

/

W

Master

SDA

The figures below show timing diagrams for the following

transaction types.

• Status Register Read

x

x x

1

0

1

0

W

A

C

K

A

C

K

A

C

K

Slave

• Status Register Write

• ADC Read

2050 Fig14

• Configuration E²PROM Read

• Configuration E²PROM Write

• General Purpose E²PROM Read

• General Purpose E²PROM Write

• Lookup Table Read

Figure 15. Write Protocol

Random Access Read

Random address read operations allow the Master to

access any memory location in a random fashion. This

operation involves a two-step process. First, the Master

issues a Write command which includes the Start condition

• Lookup Table Write

Summit Microelectronics

2066 6.3 1/22/04

19

SML2120

S

T

A

R

T

S

T

A

R

T

N

A

C

K

S

T

Device

Bus

R

/

R

/

A

C

K

A

C

K

A

C

K

Identifier

Address

O

P

W

N

S

2

S

1

D D D D D D D D

S

2

S

1

S

0

A S 1 0 0

A

1

0 0

1

A

0

1

0

1

7

6 5 4 3 2 1 0

A

S = Start, S2:S1 = Bus Select Bits, A = Acknowledge (ACK)

NA = No Acknowledge (NACK), P = Stop, n = Lookup Table (LUT) 0 or 1

Figure 16. Status Register Read

S

T

A

R

T

S

Device

Bus

A

C

K

A

C

K

A

T

O

P

R

/

Identifier

Address

C

K

W

D D D D

S

2

S

1

A

P

0

0 0

0

1

X X X

X

A

1

0 0

1

A

1

S

0

3

2 1 0

S = Start, S2:S1 = Bus Select Bits, A = Acknowledge (ACK)

NA = No Acknowledge (NACK), P = Stop, n = Lookup Table (LUT) 0 or 1

Figure 17. Status Register Write

S

T

A

R

T

S

T

N

S

T

Device

Bus

A

C

K

R

/

A

C

K

A

C

K

A

R

T

R

A

Identifier

Address

O

P

/

C

K

W

N

A

S

1

S

2

S

1

D D D D D D D D

A

S

1

A

n

x

A

S

1

0

1

P

1

0

1

2

7

6

5

4

3

2

1

0

S = Start, S2:S1 = Bus Select Bits, A = Acknowledge (ACK)

NA = No Acknowledge (NACK), P = Stop, n = Lookup Table (LUT) 0 or 1

Figure 18. ADC Read

S

T

A

R

T

N

S

Device

Bus

R

/

A

C

K

A

C

K

A

C

K

T

O

P

R

A

Identifier

Address

/

C

K

W

S

1

S

2

S

D

N

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

1

0

1

A

S

1

A

P

1

0

1

0

S

1

2

1

7

6

5

4

3

2

1

0

S = Start, S2:S1 = Bus Select Bits, A = Acknowledge (ACK)

NA = No Acknowledge (NACK), P = Stop, n = Lookup Table (LUT) 0 or 1

Figure 19. Configuration E²PROM Read

S

T

A

R

T

S

Device

Bus

T

O

P

A

C

K

R

/

A

C

K

A

C

K

Identifier

Address

W

D D D D D D D D

A

S

2

S

1

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

A

P

A

0

1

0

1

0

S

7

6

5

4 3 2 1 0

S = Start, S2:S1 = Bus Select Bits, A = Acknowledge (ACK)

NA = No Acknowledge (NACK), P = Stop, n = Lookup Table (LUT) 0 or 1

Figure 20. Configuration E²PROM Write

20

2066 6.3 1/22/04

Summit Microelectronics

SML2120

S

T

S

T

A

R

T

N

A

C

K

S

T

Device

A

Bus

Address

A

C

K

R

/

A

C

K

R

/

A

C

K

Identifier

R

T

O

P

W

N

A

S

1

S

2

S

1

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

S

A

0

S

1

P

1

0

1

0

2

S = Start, S2:S1 = Bus Select Bits, A = Acknowledge (ACK)

NA = No Acknowledge (NACK), P = Stop, n = Lookup Table (LUT) 0 or 1

Figure 21. General Purpose E²PROM Read

S

T

A

R

T

S

Device

Bus

R

/

A

C

K

A

C

K

T

O

P

Identifier

Address

C

W

K

A

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

S

2

S

1

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

A

S

P

A

0

1

0

1

0

S = Start, S2:S1 = Bus Select Bits, A = Acknowledge (ACK)

NA = No Acknowledge (NACK), P = Stop, n = Lookup Table (LUT) 0 or 1

Figure 22. General Purpose E²PROM Write

S

T

A

R

T

N

S

Device

Bus

A

C

K

R

/

R

A

C

K

A

C

K

T

O

P

A

C

K

Identifier

Address

/

W

N

A

S

1

S

2

S

1

D

N

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

A

S

1

n

S

1

n

P

1

0

1

0

2

7

6

5

4

3

2

1

0

S = Start, S2:S1 = Bus Select Bits, A = Acknowledge (ACK)

NA = No Acknowledge (NACK), P = Stop, n = Lookup Table (LUT) 0 or 1

Figure 23. Lookup Table Read

S

T

A

R

T

S

T

Device

Bus

A

C

K

A

C

K

R

/

A

C

K

Identifier

Address

O

P

W

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

S

2

S

1

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

A

P

0

A

0

1

n

1

S

0

S = Start, S2:S1 = Bus Select Bits, A = Acknowledge (ACK)

NA = No Acknowledge (NACK), P = Stop, n = Lookup Table (LUT) 0 or 1

Figure 24. Lookup Table Write

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21

CONFIGURATION REGISTERS

SML2120

–

CONFIGURATION REGISTERS

The SML2120 has sixteen 8-bit user programmable, nonvolatile, configuration registers. Table 5 shows a listing of the

configuration registers and the correspond decimal and hexadecimal addresses.

Table 5. Configuration Register Map

Decimal Address

Hexadecimal Address

Register Name

Contents

Default

00

256

257

258

259

260

261

0x100

0x101

0x102

0x103

0x104

0x105

Configuration Register 0

Configuration Register 1

Configuration Register 2

Configuration Register 3

Configuration Register 4

Configuration Register 5

Low alarm value for Lookup Table 0.

High alarm value for Lookup Table 0.

Low alarm value for Lookup Table 1.

High alarm value for Lookup Table 1.

Minimum Update Delta, LU tables 0 and 1.

FF

00

FF

00

Conversion Count, Alarm Count, AUTOMOM

hold off timer.

00

262

263

264

265

266

267

268

269

270

271

0x106

0x107

0x108

0x109

0x10A

0x10B

0x10C

0x10D

0x10E

0x10F

Configuration Register 6

Configuration Register 7

Configuration Register 8

Configuration Register 9

Configuration Register 10

Configuration Register 11

Configuration Register 12

Configuration Register 13

Configuration Register 14

Configuration Register 15

ADC input, scale, and offset for LU table 0.

ADC input, scale, and offset for LU table 1.

Power-up DAC settings for LU table 0.

Power-up DAC settings for LU table 1.

Low DAC value, LU table 0.

60

00

03

High DAC value, LU table 0.

Low DAC value, LU table 1.

High DAC value, LU table 1.

Output polarity, Bias current, Quick Start

Fast Mode enable, alarm reset,

configuration lockout, write protection.

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SML2120

Configuration Register 0 - Address 0x100

This register is used to set the low alarm value for Lookup Table 0. An ADC conversion on Lookup Table 0 that

is less than the value programmed in this register causes the ALERT# pin to be asserted.

Bits

Default

Description

7

6

5

4

3

2

1

0

Low Alarm

0x00 Low alarm value for Lookup Table 0. Values range from 0 to 255.

Table 6. Configuration Register 0 Bitmap

Configuration Register 1 - Address 0x101

This register is used to set the high alarm value for Lookup Table 0. An ADC conversion on Lookup Table 0 that

is greater than the value programmed in this register causes the ALERT# pin to be asserted.

Bits

Default

Description

7

6

5

4

3

2

1

0

High Alarm

0xFF High alarm value for Lookup Table 0. Values range from 0 to 255.

Table 7. Configuration Register 1 Bitmap

Configuration Register 2 - Address 0x102

This register is used to set the low alarm value for Lookup Table 1. An ADC conversion on Lookup Table 1 that

is less than the value programmed in this register causes the ALERT# pin to be asserted.

Bits

Default

Description

7

6

5

4

3

2

1

0

Low Alarm

0x00 Low alarm value for Lookup Table 1. Values range from 0 to 255.

Table 8. Configuration Register 2 Bitmap

Configuration Register 3 - Address 0x103

This register is used to set the high alarm value for Lookup Table 1. An ADC conversion on Lookup Table 1 that

is greater than the value programmed in this register causes the ALERT# pin to be asserted.

Bits

Default

Description

7

6

5

4

3

2

1

0

High Alarm

0xFF High alarm value for Lookup Table 1. Values range from 0 to 255.

Table 9. Configuration Register 3 Bitmap

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23

SML2120

Configuration Register 4 - Address 0x104

This register is used to set the minimum update delta for Lookup Tables 0 and 1. The contents of this register

are used when the lookup table address translation by the ADC is compared against the previous value. The

current value must differ from the previous stored value by the amount in this register in order for the translation

to occur.

Bits

Default

Description

7

6

5

4

3

2

1

0

Bits 7:4 determine the minimum update delta for Lookup Table 1. Valid

values range from 0 to 15. 0000 = 0, 1111 = 15.

Delta 1

x

0x0

Bits 3:0 determine the minimum update delta for Lookup Table 0. Valid

values range from 0 to 15. 0000 = 0, 1111 = 15.

Delta 0

Table 10. Configuration Register 4 Bitmap

Configuration Register 5 - Address 0x105

This register is used to set the consecutive count source for Lookup Table 0 and 1, the alarm count, the auto-

monitor (AM#) lockout, and auto-monitor hold-off timer.

Bits

Default

Description

7

6

5

4

3

2

1

0

Indicates the minimum delta between addresses for Lookup table 1. 00

= 0, 11 = 3. Note that there must be at least COUNT1 consecutive

0b00 conversions that differ from the previously stored conversion by at least

DELTA 1 (bits 7:4 of Configuration register 4) in order for a new

translation to occur.

COUNT

1

Indicates the minimum delta between addresses for Lookup table 0.

0b00 = 0, 0b11 = 3. Note that there must be at least COUNT0

0b00 consecutive conversions that differ from the previously stored

conversion by at least Delta 0 (bits 3:0 of Configuration register 4) in

order for a new translation to occur.

COUNT

0

ALERT# pin assertion. When this bit is cleared, the ALERT# pin is

0

1

asserted by the SML2120 on the first alert event.

0b0

ALERT# pin assertion. When this bit is set, the ALERT# pin is asserted

by the SML2120 on consecutive alert events.

0

1

Assertion of the AM# pin by external logic does lock out interface.

0b1

Assertion of the AM# pin by external logic does NOT lock out interface.

0

1

0

1

0

1

0.4 ms delay for auto-monitor holdoff timer.

3.2 ms delay for auto-monitor holdoff timer.

0b0

12.8 ms delay for auto-monitor holdoff timer.

51.2 ms delay for auto-monitor holdoff timer.

Table 11. Configuration Register 5 Bitmap

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Summit Microelectronics

SML2120

Configuration Register 6 - Address 0x106

This register contains the ADC input, scale, and offset fields for Lookup Table 0 (LUT0).

Bits

Default

Description

7

6

5

4

3

2

1

0

Lookup Table 0 update disable. When this bit is cleared, updates to

ILU0 are allowed.

0

0b0

Lookup Table 0 update disable. When this bit is set, updates to ILU0

are not allowed.

1

ADC input source for LUT0. Indicates the THERMISTOR pin as the

ADC input source for lookup table 0.

0

1

0

1

0

1

ADC input source for LUT0. Indicates the EXT_TEMP pin (voltage) as

the ADC input source for lookup table 0.

0b11

0b00

ADC input source for LUT0. Indicates the EXT_TEMP pin (current) as

the ADC input source for lookup table 0.

ADC input source for LUT0. Indicates the BIAS current as the ADC

input source for lookup table 0.

0

1

0

1

0

1

ADC scale source 0. Indicates a scale factor of 1x.

ADC scale source 0. Indicates a scale factor of 2x.

ADC scale source 0. Indicates a scale factor of 4x.

ADC scale source 0. Indicates a scale factor of 8x.

ADC offset source 0. Indicates the ADC offset for Lookup Table 0.

Offset = Full Scale * 0/8

0

1

0

1

0

1

0

1

0

1

0

1

Offset = Full Scale * 7/8

Offset = Full Scale * 6/8

Offset = Full Scale * 5/8

Offset = Full Scale * 4/8

Offset = Full Scale * 3/8

Offset = Full Scale * 2/8

Offset = Full Scale * 1/8

0b000

Table 12. Configuration Register 6 Bitmap

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2066 6.3 1/22/04

25

SML2120

Configuration Register 7 - Address 0x107

This register contains the ADC input, scale, and offset fields for Lookup Table 1 (LUT1).

Bits

Default

Description

7

6

5

4

3

2

1

0

Lookup Table 1 update disable. When this bit is cleared, updates to

ILU1 are allowed in auto-monitor mode.

0

0b0

Lookup Table 1 update disable. When this bit is set, updates to ILU1

are not allowed in auto-monitor mode.

1

ADC input source for LUT1. Indicates the THERMISTOR pin as the

ADC input source for lookup table 1.

0

1

0

1

0

1

ADC input source for LUT1. Indicates the EXT_TEMP pin (voltage) as

the ADC input source for lookup table 1.

0b00

ADC input source for LUT1. Indicates the EXT_TEMP pin (current) as

the ADC input source for lookup table 1.

ADC input source for LUT1. Indicates the BIAS current as the ADC

input source for lookup table 1.

0

1

0

1

0

1

ADC scale source 1. Indicates a scale factor of 1x.

ADC scale source 1. Indicates a scale factor of 2x.

ADC scale source 1. Indicates a scale factor of 4x.

ADC scale source 1. Indicates a scale factor of 8x.

ADC offset source 1. Indicates the ADC offset for Lookup Table 1.

Offset = Full Scale * 0/8

0

1

0

1

0

1

0

1

0

1

0

1

Offset = Full Scale * 7/8

Offset = Full Scale * 6/8

Offset = Full Scale * 5/8

Offset = Full Scale * 4/8

Offset = Full Scale * 3/8

Offset = Full Scale * 2/8

Offset = Full Scale * 1/8

0b000

Table 13. Configuration Register 7 Bitmap

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2066 6.3 1/22/04

Summit Microelectronics

SML2120

Configuration Register 8 - Address 0x108

This register contains the power-up DAC settings for Lookup Table 0.

Bits

Default

Description

7

6

5

4

3

2

1

0

Lookup current for DAC 0 ((High-Low) * n/256 + Low), where ‘High’

0x00 refers to High DAC 0, ‘Low’ refers to Low DAC 0, and ‘n’ equals the

value programmed in this register.

Power up DAC 0

Table 14. Configuration Register 8 Bitmap

Configuration Register 9 - Address 0x109

This register contains the power-up DAC settings for Lookup Table 0.

Bits

Default

Description

7

6

5

4

3

2

1

0

Lookup current for DAC 1 ((High-Low) * n/256 + Low), where ‘High’

0x00 refers to High DAC 1, ‘Low’ refers to Low DAC 1, and ‘n’ equals the

value programmed in this register.

Power up DAC 1

Table 15. Configuration Register 9 Bitmap

Configuration Register 10 - Address 0x10A

This register contains the low DAC settings for Lookup Table 0.

Bits

Default

Description

7

6

5

4

3

2

1

0

Low DAC Lookup current for table 0 (2.5 mA * n/256), where ‘n’ equals

the value programmed in this register.

Low DAC 0

0x00

Table 16. Configuration Register 10 Bitmap

Summit Microelectronics

2066 6.3 1/22/04

27

SML2120

Configuration Register 11 - Address 0x10B

This register contains the high DAC settings for Lookup Table 0.

Bits

Default

Description

7

6

5

4

3

2

1

0

High DAC Lookup current for table 0 (2.5 mA * (256 - n)/256), where ‘n’

equals the value programmed in this register.

High DAC 0

0x00

Table 17. Configuration Register 11 Bitmap

Configuration Register 12 - Address 0x10C

This register contains the low DAC settings for Lookup Table 1.

Bits

Default

Description

7

6

5

4

3

2

1

0

Low DAC Lookup current for table 1 (2.5 mA * n/256), where ‘n’ equals

the value programmed in this register.

Low DAC 1

0x00

Table 18. Configuration Register 12 Bitmap

Configuration Register 13 - Address 0x10D

This register contains the high DAC settings for Lookup Table 1.

Bits

Default

Description

7

6

5

4

3

2

1

0

High DAC Lookup current for table 1 (2.5 mA * (256 - n)/256), where ‘n’

equals the value programmed in this register.

High DAC 1

0x00

Table 19. Configuration Register 13 Bitmap

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2066 6.3 1/22/04

Summit Microelectronics

SML2120

Configuration Register 14 - Address 0x10E

This register contains output polarity and bias current information.

Bits

Default

Description

7

0

1

6

5

4

3

2

1

0

Output polarity for ILU1. 0 = sink current.

Output polarity for ILUI. 1 = source current.

Output polarity for ILU0. 0 = sink current.

Output polarity for ILU0. 1 = source current.

Quick start enabled.

0b0

0

1

0

1

Quick start disabled.

0

1

Bias current controlled by APC loop, or conditions from bit 3, Note 1

Bias current fixed by ILU1 only while AM# is not asserted.

Bias current controlled by APC loop, or conditions from bit 4, Note 1

Bias current fixed by ILU1 at all time.

0

1

0

.

0

.

0

.

Maximum bias current setting. 100 mA * (n+1)/8, where ‘n’ equals the

value programmed in this register.

0b000

1

Table 20. Configuration Register 14 Bitmap

Note 1 - If bit 3 is set to a '1', then the APC feedback loop is not

used at all - the bias current is a fixed value based on ILU1. If bit 3

is '0' and bit 4 is '1', then the APC loop does determine the bias

current as long as AM# is asserted. When AM# is not asserted,

then the bias current is fixed based on ILU1. If both bits are 0,

then the bias current is only determined by the APC loop.

Summit Microelectronics

2066 6.3 1/22/04

29

SML2120

Configuration Register 15 - Address 0x10F

This register contains fast mode enable, alarm control, configuration lockout, and write protect information.

Bits

Default

Description

7

0

1

6

5

4

3

2

1

0

Fast Mode on ENA# is disabled

0b0

Fast Mode on ENA# is enabled.

E²PROM write protect. E²PROM Write Protect is determined by the

WP status bit

E²PROM write protect. E²PROM is write protected when ENA# is

asserted.

0

1

0b0

0

1

Alarm reset. A write to the status register will reset Alarm.

0b0

Alarm reset. When the AM# pin is de-asserted, the Alarm is reset.

Alarm Forces Shutdown. When this bit is cleared, an alarm does not

cause a shutdown.

0

1

Alarm Forces Shutdown. When this bit is set, an alarm causes a

shutdown.

Configuration Lockout. When this bit is cleared, the configuration

registers are not locked out and can be accessed.

0

1

0b0

Configuration Lockout. When this bit is set, the configuration registers

are locked out and cannot be accessed.

0

1

Write-protect not set on power-up.

Write-protect set on power-up.

Sample interval is 0.4 ms.

0

1

0

1

0

1

Sample interval is 3.2 ms.

0b11

Sample interval is 51.2 ms.

Sample interval is 409.6 ms.

Table 21. Configuration Register 15 Bitmap

30

2066 6.3 1/22/04

Summit Microelectronics

SML2120

Package Drawing

–

PACKAGE DRAWING

Figure 25 shows the package dimensions for the 28-pin QFN package.

Figure 25. 28-Pin QFN Package Drawing

Summit Microelectronics

2066 6.3 1/22/04

31

Ordering Information

SML2120

–

ORDERING INFORMATION

SML2120

N

nnn

Base Part Number

Part Number Suffix

Package

N = QFN

–

PART MARKING

Summit part number

SUMMIT

SML2120N xx

Annn AYYWW

Pin 1 Designator

Status tracking code

(Summit use only)

Date code (YY = year, WW = week)

Lot tracking code (Summit use only)

Part number suffix

Product tracking code (Summit use only)

NOTICE

NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited

characterization.

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,

performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no

license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules

contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the

information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a

result of any error or omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure

or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or

effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances,

to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of

SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.

Revision 6.3 - This document supercedes all previous revisions. Please check the Summit Microelectronics, Inc. web site at

www.summitmicro.com for data sheet updates.

I²C is a trademark of Philips Corporation.

32

2066 6.3 1/22/04

Summit Microelectronics


型号：	SML2120
厂家：	SUMMIT MICROELECTRONICS, INC.
描述：	Programmable Adaptive Laser Power Controller with Dual Lookup Tables 可编程自适应激光功率控制器，双查找表功率控制控制器
文件：	总32页 (文件大小：1397K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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