SMM465FCR00 [SUMMIT]
4-Channel Active DC Output Controller, Monitor, Marginer and Sequencer; 4通道有源直流输出控制器，监视器， Marginer和定序
| 型号： | SMM465FCR00 |
| 厂家： | 
SUMMIT MICROELECTRONICS, INC. |
| 描述： | 4-Channel Active DC Output Controller, Monitor, Marginer and Sequencer |
| 文件： | 总30页 (文件大小：950K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMM465
Preliminary Information1 (See Last Page)
4-Channel Active DC Output Controller, Monitor, Marginer and Sequencer
FEATURES & APPLICATIONS
INTRODUCTION
• Extremely accurate (±0.1%) Active
The SMM465 is an Active DC Output power supply
Controller (ADOCTM) that monitors, margins and
cascade sequences. The ADOC feature is unique and
maintains extremely accurate settings of system
supply voltages to within ±0.2% under full load. The
device actively controls up to four DC/DC converters
that use a Trim or Regulator VADJ/FB pin to adjust the
output voltage. For system test, the part also controls
margining of the supplies using I2C commands. It can
margin supplies with either positive or negative control
within a range of 0.3V to VDD depending on the
specified range of the converter. The SMM465 also
intelligently sequences or cascades the power
supplies on and off in any order using enable outputs
with programmable polarity. It can operate off any
intermediate bus supply ranging from 8V to 15V or
from 5.5V to as low as 2.7V. The part monitors four
power supply channels as well as VDD, 12V input, two
general-purpose analog inputs and an internal
temperature sensor using a 10-bit ADC. The 10-bit
ADC can measure the value on any one of the monitor
channels and output the data via the I2C bus. A host
system can communicate with the SMM465 status
register, optionally control Power-on/off, margining and
utilize 4K-bits of nonvolatile memory.
DC Output Control (ADOCTM)
• Undervoltage Lockout function (UVLO)
• ADOCTM Automatically adjusts supply output
voltage level under all DC load conditions
• Monitors, controls, sequences and margins up
to 4 supplies from 0.3V to 5.5V with 1.25V Vref
ꢀ Wide Margin/ADOC range from 0.3V to VDD
• Programmable Power-on/-off sequencing
• Monitors internal temperature sensor
• Operates from any intermediate bus supply
from 8V to 15V and from 2.7V to 5.5V
• Monitors 12V input and VDD
• Monitors two general-purpose 10-bit ADC inputs
• Programmable threshold limits (2 OV/2 UV) for
each monitored input
• Programmable RESET, HEALTHY and FAULT
• 4k-bit general purpose nonvolatile memory
• I2C 2-wire serial bus for programming
configuration and monitoring status, including
10-bit ADC conversion results
Applications
• Monitor/Control Distributed and POL Supplies
• Multi-voltage Processors, DSPs, ASICs used in
Telecom, CompactPCI or server systems
SIMPLIFIED APPLICATIONS DRAWING
12V
12VIN (+6V to +15V Range)
3.3VIN (+2.7V to +5.5V Range)
3.3V
DC/DC
Converter C
CAPA
VIN
TRIM_CAPA
SDA
DC/DC
I2C
Converter A
SCL
2.5VIN
Vout
BUS
A2
TRIM
TRIMA
PUPA
ON/OFF
External
2 of 4 DC-DC
Converters shown
or
Internal
TEMP
AIN1
VMA
SENSOR
DC/DC
µP/
SMM465
CAPB
Converter D
ASIC
Environ
mental
VIN
TRIM_CAPB
AIN2
DC/DC
SENSOR
Converter B
Vout
1.2VIN
VREF_CNTL
VREF_ADC
External or
Internal
TRIMB
PUPB
TRIM
REFERENCE
ON/OFF
VMB
RESET
READY
HEALTHY
Figure 1 – Applications Schematic using the SMM465 Controller to actively control the output levels of up
to four DC/DC Converters while also providing power on/off, cascade sequencing and output margining.
Note: This is an applications example only. Some pins, components and values are not shown.
© SUMMIT Microelectronics, Inc. 2004 • 1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897 www.summitmicro.com
2085 1.1 05/27/04
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SMM465
Preliminary Information
VDD (+2.7V to +5.5V)
2.7V
2.5V
or 12VIN ( +8V to +15V)
1.8V
1.5V
---
---
t1
RST#
Figure 2 – Example Power Supply Sequencing and System Start-up Initialization using the SMM465. Any
order of supply sequencing can be applied using the SMM465. Power supply ordering, trimming and Active
DC control allows supply cascade sequencing, automatic level adjustment, margin testing and reset control.
GENERAL DESCRIPTION
The SMM465 is a highly integrated and accurate
power supply controller, monitor and sequencer. It
has the ability to automatically control, monitor and
cascade sequence up to four power supplies. Also,
the SMM465 can monitor the VDD input, the 12V
input, two general-purpose analog inputs and the
internal temperature sensor. The SMM465 has four
operating modes: Power-on sequencing mode,
monitor mode, supply margining mode using Active
DC Output Control (ADOCTM), and Power-off
sequencing mode.
external voltage reference). The part also enables the
triggering of outputs by monitored fault conditions.
The 10-bit ADC cycles through all 9 channels every
2ms and checks the conversions against the
programmed threshold limits. The results can be used
to trigger RST, HEALTHY and FAULT outputs as well
as to trigger a Power-off or a Force Shutdown
operation.
While the SMM465 is in its monitoring mode, an I2C
command to margin the supply voltages can bring the
part into margining mode. In margining mode the
SMM465 can margin four supply voltages in any
combination of nominal, high and low voltage settings
using the ADOC feature, all to within ±0.2% using a
±0.1% external reference. The margin high and low
voltage settings can range from 0.3V to VDD around
the converters’ nominal output voltage setting
depending on the specified margin range of the DC-
DC converter. During this mode the HEALTHY output
is always active and the RST output is always inactive
regardless of the voltage threshold limit settings and
triggers. Furthermore, the triggers for Power-off and
Force Shutdown are temporarily disabled.
Power-on sequencing can be initiated via the
PWR_ON/OFF pin or I2C control. In this mode, the
SMM465 will sequence the power supply channels on
in any order by activating the PUP outputs and
monitoring the respective converter voltages to ensure
cascading of the supplies. Cascade sequencing is the
ability to hold off the next sequenced supply until the
first supply reaches a programmed threshold. A
programmable sequence termination timer can be set
to disable all channels if the Power-on sequence
stalls. Once all supplies have sequenced on and the
voltages are above the UV settings, the Active DC
Control, if enabled, will bring the supply voltages to
The Power-off sequencing mode can only be entered
while the SMM465 is in the monitoring mode. It can
be initiated by either bringing the PWR_ON/OFF pin
inactive, through I2C control or triggered by a channel
exceeding its programmed thresholds. Once Power-
off is initiated, it will disable the Active DC Control and
sequence the PUP outputs off in either the same or
reverse order as Power-on sequencing and monitor
the supply voltages to ensure cascading of the
supplies as they turn off. The sequence termination
timer can be programmed to immediately disable all
channels if the Power-off sequencing stalls. The RST
output will remain active throughout this mode while
the HEALTHY output remains inactive.
their nominal settings.
During this mode, the
HEALTHY output will remain inactive and the RST
output will remain active.
Once the Power-on sequencing mode is complete, the
SMM465 enters monitor mode. In the monitor mode,
the SMM465 starts the ADOC control of the supplies
and adjusts the output voltage to the programmed
setting under all load conditions, especially useful for
supplies without sense lines. Typical converters have
±2% accuracy ratings for their output voltage, the
Active DC Output Control feature of the SMM465
increases the accuracy to ±0.2% (using a ±0.1%
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2085 1.1 05/27/04
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SMM465
Preliminary Information
INTERNAL FUNCTIONAL BLOCK DIAGRAM
12VIN
VDD
VDD_CAP
PWR_ON/OFF FS
3.6V or
5.5V
Power Supply
Arbitrator
VREF_ADC
AIN1
PUPA
PUPB
PUPC
PUPD
Regulator
UVLO
AIN2
Cascade
Sequence
Control
Control
Temperature
Sensor
VMA
10-Bit ADC
CAPA
VMD
MR
CAPD
RST
Output
Control
HEALTHY
FAULT
TRIMA
TRIM_CAPA
SDA
SCL
A2
Active DC
Control
Memory, Limit
I2C
and Status
Registers
(ADOCTM
)
Interface
TRIMD
TRIM_CAPD
VREF_CNTL
FILT_CAP
GND
Figure 3 – SMM465 Internal Functional Block Diagram.
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SMM465
Preliminary Information
PIN DESCRIPTIONS
Pin
Pin
Pin Name
Pin Description
Number Type
1
I2C Bi-directional data line
I2C Clock line
DATA SDA
2
CLK
SCL
The address pin is biased either to VDD_CAP or GND.
When
3
IN
A2
communicating with the SMM465 over the 2-wire bus A2 provides a
mechanism for assigning a unique bus address.
Programmable active high/low input. When asserted the RST output will be
go active. When de-asserted the RST output will go inactive immediately
after a reset timeout period (tPRTO) if there are no RST trigger sources active.
This timeout period makes it suitable to use a pushbutton for manual reset.
Programmable active high/low input signals the start of the power
sequencing. When asserted the part will sequence the supplies on and
when de-asserted the part will sequence the supplies off.
Note: The SMM465 does not monitor for faults during sequencing. The
PWR_ON/OFF pin is overridden by the I2C power on/off command. To get
the pin to work again requires the part be given an I2C 'Clear' command (see
page 16, “RESTART OF POWER-ON CASCADE SEQUENCING”).
4
5
IN
IN
MR
PWR_ON/OFF
Programmable active high/low input. Force shutdown is used to immediately
6
7
IN
FS
turn off all converter enable signals (PUP outputs) when a fault is detected.
Programmable active high/low open drain Fault output. Active when a
programmed fault condition exists on AIN1, AIN2, or the internal temperature
sensor.
OUT
FAULT
Programmable active high/low open drain Healthy output. Active when all
programmed power supply inputs and monitored inputs are within OV and
UV limits.
Programmable active high/low open drain Reset output. Active when a
programmed fault condition exists on any power supply inputs or monitored
inputs or when MR is active. RST has a programmable timeout period with
options for 0.64ms, 25ms, 100ms and 200ms.
8
9
OUT
OUT
HEALTHY
RST
10
11
General purpose monitored analog input
General purpose monitored analog input
Ground
IN
AIN1
AIN2
GND
IN
12, 19,
24
GND
Voltage reference input used for A/D conversion where:
(4XVREF_ADC) = Full Scale (FS) for VMA-F and VDD
(12XVREF_ADC) = FS for 12VIN
13
IN
VREF_ADC
(2XVREF_ADC) = FS for AIN1 and AIN2.
VREF_ADC can be connected to VREF_CNTL in most applications.
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2085 1.1 05/27/04
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SMM465
Preliminary Information
Pin
Pin
Pin Name
Pin Description
Number Type
Voltage reference input used for DC output control and margining.
14
15
I/O
VREF_CNTL
VREF_CNTL can be programmed to output the internal 1.25V reference.
External capacitor input used to filter VMX inputs
Positive converter sense line, VMA through VMD
CAP
IN
FILT_CAP
VMX
41,36,
31,26
42,37,
32,27
External capacitor input used to filter the VMX inputs to the 10-bit ADC, CAPA
CAP
OUT
OUT
CAP
CAPX
through CAPD. This provides an RC filter where R = 25kΩ.
43,38,
Programmable active high/low open drain converter enable output, PUPA
PUPX
33,28
through PUPD
44,39,
34,29
Output voltage used to control the output of DC/DC converters, TRIMA
through TRIMD
TRIMX
45,40,
External sample and hold capacitor input used to set the voltage on the
TRIM_CAPX
35,30
TRIM pins, TRIM_CAPA through TRIM_CAPD
46
47
48
Power supply of the part
PWR
PWR
CAP
VDD
12V power supply input internally regulated to either 3.6V or 5.5V
External capacitor input used to filter the internal supply
12VIN
VDD_CAP
16, 17,
18, 20,
21, 22,
23, 25
Leave open, do not connect.
NC
No Connect
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2085 1.1 05/27/04
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SMM465
Preliminary Information
PACKAGE AND PIN CONFIGURATION
48 LEAD TQFP
SDA
SCL
1
2
3
4
5
6
7
8
9
36 VMB
35 TRIM_CAPC
34 TRIMC
33 PUPC
32 CAPC
31 VMC
A2
MR
PWR_ON/OFF
FS
FAULT
HEALTHY
RST
30 TRIM_CAPD
29 TRIMD
28 PUPD
27 CAPD
26 VMD
AIN1 10
AIN2 11
GND 12
25 NC
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SMM465
Preliminary Information
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Temperature Under Bias....................... -55°C to 125°C
Storage Temperature............................ -65°C to 150°C
Terminal Voltage with Respect to GND:
Temperature Range (Industrial)...........–40°C to +85°C
(Commercial)............–5°C to +70°C
VDD Supply Voltage ..................................2.7V to 5.5V
12VIN Supply Voltage (1) ........................8.0V to 14.0V
VIN ............................................................ GND to VDD
VOUT...................................................... GND to 14.0V
Package Thermal Resistance (θJA)
VDD Supply Voltage ......................... -0.3V to 6.0V
12VIN Supply Voltage..................... -0.3V to 15.0V
PUPA, through PUPD....................... -0.3V to 15.0V
All Others ................................-0.3V to VDD + 0.7V
Output Short Circuit Current ............................... 100mA
Lead Solder Temperature (10 secs)....................300°C
Junction Temperature.......................…….....…...150°C
ESD Rating per JEDEC…………………....……..2000V
Latch-Up testing per JEDEC………..…....……±100mA
48 Lead TQFP……………………………….…80oC/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
Note 1 – Range depends on internal regulator set to 3.6V or 5.5V,
see 12VIN specification below.
Note - The device is not guaranteed to function outside its operating rating.
Stresses listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only and functional operation
of the device at these or any other conditions outside those listed in the
operational sections of the specification is not implied. Exposure to any
absolute maximum rating for extended periods may affect device performance
RELIABILITY CHARACTERISTICS
Data Retention…………………………..…..100 Years
Endurance…………………….……….100,000 Cycles
and reliability.
recommended.
Devices are ESD sensitive. Handling precautions are
DC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Supply Voltage
Notes
Min
2.7
10
Typ
Max
5.5
14
Unit
V
V
VDD
Internally regulated to 5.5V
Internally regulated to 3.6V
12VIN
Supply Voltage
6
14
V
All TRIM pins floating,
12VIN floating
All TRIM pins floating,
VDD floating
IDD
Power Supply Current from VDD
Power Supply Current from 12VIN
3
3
5
mA
I12VIN
5
mA
TRIM characteristics
TRIM Sourcing Maximum
1.5
mA
mA
V
TRIM output current through 100Ω to Current
ITRIM
1.0V
TRIM Sinking Maximum
1.5
Current
Depends on Trim range of
DC-DC Converter
VREF_CNTL/4
VTRIM
Margin Control and ADOC Range
VDD
All other input and output characteristics
VDD = 2.7V
VDD = 5.0V
VDD = 2.7V
VDD = 5.0V
Internally regulated to 3.6V
Internally regulated to 5.5V
Internally regulated to 3.6V
Internally regulated to 5.5V
0.9xVDD
0.7xVDD
-0.1
VDD
VDD
0.1xVDD
0.3xVDD
VDD
VDD
0.1xVDD
0.3xVDD
V
V
V
V
V
V
V
V
Input High Voltage (FS,
VIH
PWR_ON/OFF, MR#, SDA, SCL)
Input Low Voltage (FS,
VIL
PWR_ON/OFF, MR#, SDA, SCL)
-0.1
0.9xVDD
0.7xVDD
-0.1
Input High Voltage (FS,
VIH
PWR_ON/OFF, MR#, SDA, SCL)
Input Low Voltage (FS,
VIL
PWR_ON/OFF, MR#, SDA, SCL)
-0.1
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SMM465
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Programmable Open Drain
Outputs (RST, HEALTHY,
FAULT, PUPx)
VOL
ISINK = 1mA
0
0.4
V
Note – Total ISINK from all PUPx pins
should not exceed 3mA or ADOCACC
specification will be affected
IOL
Output Low Current
0
1.0
mA
VDD_CAP
VSENSE
VMonitor
Positive Sense Voltage
Monitor Threshold Step Size
VM pin
+0.3
V
mV
oC
oC
oC
V
VM, AIN1/AIN2 pins
Commercial Temp Range
Industrial Temp Range
5
-3
-5
+3
+5
Internal Temperature Sensor
Accuracy
TSA
TMonitor
VREF
Temperature Threshold Step Size Internal Temp Sensor
Internal 1.25VREF Output Voltage
0.25
1.25
1.24
-0.25
-0.15
1.26
+0.25
+0.15
%
%
–40°C to +85°C
–5°C to +70°C
Internal VREF Temperature
Coefficient
VREF TC
VREF ACC Internal VREF Accuracy
Ext VREF External VREF Voltage Range
-0.4
0.5
+0.4
VDD_CAP
%
V
External VREF=1.25V, ±0.1%,
Total PUPx ISINK < 3ma,
-0.2
+0.2
%
%
±0.1
±0.3
VSENSE ≤ 3.5V
External VREF=1.25V, ±0.1%,
ADOCACC ADOC/Margin Accuracy
Total PUPx ISINK < 3ma,
-0.5
-0.5
+0.5
+0.5
VSENSE ≥ 3.5V
Internal VREF=1.25V, Total
PUPx ISINK < 3ma
%
V
±0.3
VDD_CAP voltage at which
the PUP, RST, HEALTHY
and FAULT outputs are valid
VOUT_VALID Minimum Output Valid Voltage
1
VDD_CAP Rising
VDD_CAP Falling
2.6
2.5
V
V
Under Voltage Lockout
UVLO
Threshold1
Note 1 - (100mV typ Hysteresis)
Summit Microelectronics, Inc
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SMM465
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
AIN1/AIN2 ADC characteristics
Symbol
Parameter
Notes
Min
Typ
Max
Unit
N
Resolution
10
Bits
Minimum resolution for which no
missing codes are guaranteed
MC
Missing Codes
10
Bits
S/N
DNL
INL
GAIN
Offset
Signal-to-Noise Ratio
Differential Non-Linearity
Integral Non-Linearity
Positive full scale gain error
Offset Error
Conversion rate = 500Hz
72
db
LSB
LSB
%
-1/2
-1
-0.5
-1
+1/2
+1
+0.5
+1
Note 1
Note 1
Note 1
LSB
Full Scale Temperature
ADC_TC
PPM/oC
±15
Coefficient
IMADC
IIVREF_ADC
Analog ADC Input Impedance
VREF_ADC Input Current
10
250
200
1
MΩ
nA
pF
ICVREF_ADC VREF_ADC Input Capacitance
IRVREF_ADC VREF_ADC Input Impedance
kΩ
Note 1 - The formula for the total ADC inaccuracy is: [((ADC read voltage) +/- INL)*(range of gain error)]+range of offset error
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SMM465
Preliminary Information
AC OPERATING CHARACTERISTICS
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See
Figure 5 and 6 Timing diagrams.
Symbol
Description
Conditions
tDPON = 0.64ms
Min
Typ
Max
Unit
Programmable Power-on delay from tDPON = 12.5ms
tDPON
-15
tDPON
+15
%
VMX out-of-fault to PUPX active
tDPON = 25ms
tDPON = 50ms
tDPOFF = 0.64ms
Programmable Power-off delay from tDPOFF = 12.5ms
tDPOFF
tPRTO
tSTT
-15
-15
-15
tDPOFF
tPRTO
tSTT
+15
+15
+15
%
%
%
VMX off to PUPX inactive
tDPOFF = 25ms
tDPOFF = 50ms
tPRTO = 0.64ms
tPRTO = 25ms
tPRTO = 100ms
Programmable Reset Time-Out
Period
t
PRTO = 200ms
tSTT = OFF
Programmable Sequence
Termination Timer
tSTT = 100ms
tSTT = 200ms
tSTT = 400ms
Time for ADC conversion
of all 11 channels
Update period for Active
DC Control of channels
A – F
10-bit ADC sampling period
tADC
2
ms
ms
Active DC Control sampling period
tDC_CONTROL
1.7
Slow Margin, + 10%
change in voltage with
0.1% ripple
850
85
ms
ms
TRIM_CAP=1µF
Fast Margin, + 10%
change in voltage with
0.1% ripple
TMARGIN
Margin Time from Nominal
TRIM_CAP=1µF
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SMM465
Preliminary Information
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100/400kHz
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.
See Figure 4 Timing Diagram.
Conditions
100kHz
Min Typ
400kHz
Min Typ
Symbol Description
Max
Max Units
fSCL
SCL Clock Frequency
0
100
0
400
KHz
tLOW
tHIGH
Clock Low Period
Clock High Period
4.7
4.0
1.3
0.6
µs
µs
Before New Transmission
- Note 1/
tBUF
Bus Free Time
4.7
1.3
µs
Start Condition Setup
Time
tSU:STA
4.7
0.6
µs
tHD:STA
tSU:STO
tAA
Start Condition Hold Time
Stop Condition Setup Time
4.0
4.7
0.6
0.6
µs
µs
SCL low to valid
SDA (cycle n)
SCL low (cycle n+1)
to SDA change
Note 1/
Clock Edge to Data Valid
Data Output Hold Time
0.2
0.2
3.5
0.2
0.2
0.9
µs
tDH
µs
tR
tF
tSU:DAT
tHD:DAT
TI
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
Noise Filter SCL and SDA Noise suppression
Configuration
1000
300
1000
300
ns
ns
ns
ns
ns
Note 1/
250
0
150
0
100
100
tWR_CONFIG Write Cycle Time Config
10
5
10
5
ms
ms
Registers
Memory Array
tWR_EE
Write Cycle Time EE
Note: 1/ - Guaranteed by Design.
TIMING DIAGRAMS
tWR (For W rite Operation Only)
tHIGH
tLOW
tR
tF
SCL
tBUF
tHD:DAT
tSU:DAT
tSU:SDA
tSU:STO
tHD:SDA
SDA
(IN)
tAA
tDH
SDA
(OUT)
Figure 4 - Basic I2C Serial Interface Timing
Summit Microelectronics, Inc
2085 1.1 05/27/04
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SMM465
Preliminary Information
TIMING DIAGRAMS (CONTINUED)
0
1
2
tDPONA
PUPA
VMA
PUPB
VMB
tDPONB
tDPONC
PUPC
VMC
PUPD
VMD
tDPOND
Figure 5 - The SMM465 cascade sequencing the supplies on and then monitoring for fault conditions.
2
1
0
PUPA
VMA
tDPOFFA
PUPB
VMB
tDPOFFB
PUPC
VMC
tDPOFFC
PUPD
VMD
tDPOFFD
Figure 6 - The SMM465 cascade sequencing the supplies off.
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2085 1.1 05/27/04
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SMM465
Preliminary Information
APPLICATIONS INFORMATION
monitoring and margining mode. A detailed description
of each mode and feature follows.
DEVICE OPERATION
POWER SUPPLY
ACTIVE DC OUTPUT CONTROL (ADOCTM)
The SMM465 can be powered by either a 12V input
through the 12VIN pin or by a 3.3V or 5.0V input
through the VDD pin. The 12VIN pin feeds an internal
programmable regulator that internally generates
either 5.5V or 3.6V. A voltage arbitration circuit allows
the device to be powered by the highest voltage from
either the regulator output or the VDD input. This
voltage arbitration circuit continuously checks for these
voltages to determine which will power the SMM465.
The resultant internal power supply rail is connected to
the VDD_CAP pin that allows both filtering and hold-
up of the internal power supply. To ensure that the
input voltage is high enough for reliable operation, an
under voltage lockout circuit holds the controlled
supplies off until the UVLO thresholds are met.
The SMM465 can actively control the DC output
voltage of bricks or DC/DC converters that have a trim
pin during monitoring and margining mode. The
converter may be an off-the shelf compact device, or
may be a “roll your own” circuit on the application
board. In either case, the SMM465 dramatically
improves voltage accuracy (down to 0.2%) by
implementing closed-loop ADOC active control. This
utilizes the DC-DC’s “trim” pin as shown in Figure 12,
or an equivalent output voltage feedback adjustment
“VADJ” or “FB” node in a user’s custom circuit, Figure
13. Each of the TRIMX pins on the SMM465 is
connected to the trim input pins on the power supply
converters. A sense line from the channel’s point-of-
load connects to the corresponding VM input. The
ADOC function cycles through all four channels (A-D)
every 1.7ms making slight adjustments to the voltage
on the associated TRIMX output pins based on the
voltage inputs on the VMX pins. These voltage
adjustments allow the SMM465 to control the output
voltage of power supply converters to within ±0.2%
when using a ±0.1% external voltage reference.
MODES OF OPERATION
The SMM465 has four basic modes of operation
(shown in Figures 5 through 8): Power-on cascade
sequencing mode, ongoing operations-monitoring
mode, supply margining mode and Power-off cascade
sequencing mode. In addition, there are two features:
ADOC and forced shutdown which can be used during
Figure 7 - Waveform shows four SMM465 channels Figure 8 - Waveform shows two SMM465 channels
exhibiting Sequence-on to Nominal voltage, Margin Sequencing-on to Nominal voltage, Margin High and
High or Low, Nominal voltage and then sequence-off
Low, and then sequence-off. Channel 3 and 4 shows
the RST and HEALTHY signals.
Ch 1 = 2.5V DC-DC converter output (Yellow trace)
Ch 2 = 1.8V DC-DC converter output (Blue trace)
Ch 3 = 1.5V DC-DC converter output (Purple trace)
Ch 4 = 1.2V DC-DC converter output (Green trace
Ch 1 = 2.5V DC-DC converter output (Yellow trace)
Ch 2 = 1.5V DC-DC converter output (Blue trace)
Ch 3 = RST signal output (Purple trace)
Ch 4 = HEALTHY signal output (Green trace
Summit Microelectronics, Inc
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SMM465
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
A pulse of current, either sourced or sunk for 5µs
every 1.7ms, to the capacitors connected to the
TRIM_CAPX pins adjusts the voltage output on the
TRIMX pins. The voltages on the TRIM_CAPX pins are
buffered and applied to the TRIMX pins. The voltage
adjustments on the TRIMX pins cause a slight ripple of
less than 1mV on the power supply voltages. The
amplitude of this ripple is a function of the TRIM_CAP
capacitor and the trim gain of the converter.
Application Note 37 details the calculation of the
TRIM_CAP capacitor to achieve a desired minimum
ripple.
Power-on sequence. To enable software control of
the sequencing feature, the SMM465 offers an I2C
command to initiate Power-on sequencing while the
PWR_ON/OFF pin is in its inactive state.
The SMM465 can be programmed to wait until either
or both VDD and 12VIN inputs are within their
respective voltage threshold limits before Power-on
sequencing is allowed to begin. This ensures that the
converters have their full supply voltage before they
are enabled.
Once Power-on sequencing begins, the SMM465 will
wait a Power-on delay time (tDPON) for any channel in
the first sequence position (0) and then activate the
PUPX outputs for those channels. The Power-on
delay times are individually programmable for each
channel. The SMM465 will then wait until all VMX
inputs of the channels assigned to the first sequence
position (0) are above their programmed UV1
thresholds which is called cascade sequencing. At
this point, the SMM465 will enter the second sequence
position (1) and begin to timeout the Power-on delay
times for the associated channels. This process
continues until all of channels in the sequence have
turned on and are above their UV1 threshold. The
status registers indicates that all sequenced power
Each channel can be programmed to either enable or
disable the Active DC Control function.
When
disabled or not active, the TRIMX pins on the SMM465
are high impedance inputs. If disabled and not used,
they can be connected to ground. The voltages on the
TRIMX pins are buffered and applied to the
TRIM_CAPX pins charging the capacitors. This allows
a smooth transition from the converter powering up to
its nominal voltage; to the SMM465 controlling that
voltage, and to the Active DC Control nominal setting.
The pulse of current can be increased to a 10X pulse
of current until the power supply voltages are at their
nominal settings by selecting the programmable
Speed-Up Convergence option. As the name implies,
this option decreases the time required to bring a
supply voltage from the converter’s nominal output
voltage to the Active DC Control nominal voltage
setting.
supply channels have turned on.
Once these
channels are above their UV1 thresholds, the
SMM465 will begin the Active DC Control of the
enabled channels. The Power-on sequencing mode
ends when the Active DC Controlled channels are at
their nominal voltage setting. The “Ready” bit in the
status registers signifies that the voltages are at their
set points.
POWER-ON CASCADE SEQUENCING
The SMM465 can be programmed to sequence up to
four power supplies in any order. Each of these four
channels (A-D) has an associated open drain PUP
output that, when connected to a converter’s enable
The programmable sequence termination timer can be
used to protect against a stalled Power-on sequence.
This timer resets itself at the beginning of each
sequence position. All channels in the sequence
position must go above their UV1 threshold before the
sequence termination timer times out (tSTT) or the
sequence will terminate and all PUPX outputs will be
switched to their inactive state. The status registers
contain bits that indicate the sequence has been
terminated and in which sequence position the timer
timed out. This timer has four settings of OFF, 100ms,
200ms and 400ms.
pin, controls the turn-on of the converter.
The
channels are assigned sequence positions to
determine the order of the sequence. Any channel
can also be programmed to not take part in the
sequencing in applications with fewer than four
supplies. The polarity of each of the PUPX outputs is
programmable for use with various types of
converters.
Power-on sequencing can be initiated by the
PWR_ON/OFF pin or via I2C control. The polarity of
the PWR_ON/OFF pin is programmable. If hard wired
in its active state the SMM465 will automatically
initiate the Power-on sequence. Otherwise, toggling
the PWR_ON/OFF pin to its active state will initiate the
Summit Microelectronics, Inc
2085 1.1 05/27/04
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SMM465
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
While the SMM465 is in the Power-on sequencing
mode the RST output is held active and the HEALTHY
output is held inactive regardless of trigger sources
(Figure 8). The Power-off and Force Shutdown trigger
options are also disabled while in this mode.
Furthermore, the SMM465 will not respond to activity
on the PWR_ON/OFF pin or to a Power-off I2C
command during Power-on sequencing mode.
The status registers provide the real-time status of all
monitored inputs.
The voltage threshold limits for inputs VMA-F, VDD and
12VIN can be programmed to trigger the RST and
HEALTHY outputs as well as a Force Shutdown and
Power-off operation when exceeded. The threshold
limits for the internal temperature sensor and the AIN1
and AIN2 inputs can be programmed to trigger the
RST, HEALTHY, and FAULT outputs.
ONGOING OPERATIONS-MONITORING MODE
During ongoing operations mode, the part can (1)
monitor (2) actively control via ADOC, and (3) use
force shutdown if necessary.
The HEALTHY and FAULT outputs of the SMM465
are active as long as the triggering limit remains in a
fault condition. The RST output also remains active as
long as the triggering limit remains in a fault condition;
however, once the trigger source goes away the RST
will remain active for a reset timeout period (tPRTO).
Once the Power-on sequence is complete and before
a Power-off sequence has been initiated, the SMM465
continues to monitor all VMX inputs, the VDD and
12VIN inputs, and two temperature sensor inputs with
a 10-bit ADC. Each of these inputs is sampled and
converted by the ADC every 2ms. The ADC input has
a range of 0V to four times the voltage on VREF_ADC
for inputs VMA-D and the VDD input. The range is
extended to 12 times VREF_ADC for the 12VIN input
and is reduced to two times VREF_ADC for the AIN1
and AIN2 inputs.
TEMPERATURE SENSOR ACCURACY
The internal temperature sensor accuracy is ±5oC from
-40 to +90oC. The sensor measures the temperature
of the SMM465 die and the ambient temperature. If
VDD is at 5V, the die temperature is +2oC and at 12V,
it is +4oC. In order to calculate this difference in
specific applications measure the Vdd or 12VIN supply
current and calculate the power dissipated and
multiply by 80oC/W. For instance, 5V and 5mA is
25mW, which creates a 2oC offset.
The SMM465 monitors internal temperature using the
10-bit ADC and the automonitor function. Two under
temperature and two over temperature thresholds can
be set, each with its own programmable trigger options
and consecutive conversion before trigger counter.
Resolution is 0.25 C per bit scaled over the range of
-128 C to 127.75 C. The temperature value can be
acquired over the I2C bus as a 10-bit signed two's
complement value.
MARGINING
The SMM465 has two additional Active DC Output
Control voltage settings for channels A-D, margin high
and margin low. The margin high and margin low
voltage settings can range from 0.3V to VDD of the
converters’ nominal output voltage depending on the
specified margin range of the DC-DC converter.
These settings are stored in the configuration registers
and are loaded into the Active DC Control voltage
setting by margin commands issued via the I2C bus.
The channel must be enabled for Active DC Control in
order to enable margining. The margin command
registers contain two bits for each channel that decode
the commands to margin high, margin low, or control
to the nominal setting. Therefore, any combination of
margin high, margin low, and nominal control is
allowed in the margining mode.
The SMM465 compares each resulting ADC
conversion with two programmable 10-bit under-
voltage limits (UV1, UV2) and two programmable 10-
bit over-voltage limits (OV1, OV2) for the
corresponding input.
A consecutive conversion
counter is used to provide filtering of the ADC inputs.
Each limit can be programmed to require 1, 2, 4 or 6
consecutive out-of-limit conversions before it is said to
be in fault. One in-limit conversion will remove the
fault from the threshold limit. This provides digital
filtering of the monitored inputs. The ADC inputs VMA-D
can use additional filtering by connecting a capacitor
from the corresponding CAPX pins to ground to form
an analog RC filter (R=25kΩ). The input is considered
to be in a fault condition if any of its limit thresholds
are in fault. Setting an OV threshold limit to full-scale
(3FFHEX), or setting an UV threshold limit to 000HEX
ensures that the limit can never be in fault.
Once the SMM465 receives the command to margin
the supply voltages, it begins adjusting the supply
voltages to move toward the desired setting. When all
channels are at their voltage setting, a bit is set in the
margin status registers.
Summit Microelectronics, Inc
2085 1.1 05/27/04
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SMM465
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Note: Configuration writes or reads of registers 00HEX
to 0FHEX should not be performed while the SMM465 is
margining.
POWER-OFF CASCADE SEQUENCING
The SMM465 can be programmed to perform Power-
off sequencing in either the same order or reverse
order of Power-on cascade sequencing.
Power-off cascade sequencing can be initiated by the
PWR_ON/OFF pin, via I2C control or triggered by a
fault condition on any of the monitored inputs.
Toggling the PWR_ON/OFF pin to its inactive state will
initiate the Power-off sequence.
While the SMM465 is in the Power-off sequencing
mode the RST output is held active and the HEALTHY
output is held inactive regardless of trigger sources
(Figure 8). The Force Shutdown trigger option is also
disabled while in this mode.
Furthermore, the
SMM465 will not respond to activity on the
PWR_ON/OFF pin or to a Power-on I2C command
during Power-off sequencing mode.
FORCE SHUTDOWN
The Force Shutdown operation brings all PUPX
outputs to their inactive state. This operation is used
for an emergency shutdown when there is not enough
time to sequence the supplies off.
The Force
To enable software control of the Power-off
sequencing feature, the SMM465 offers an I2C
command to initiate Power-off sequencing regardless
of the state of the PWR_ON/OFF pin. Furthermore,
Power-off sequencing can be initiated by a fault
condition on a monitored input.
Once Power-off sequencing begins, the SMM465 will
wait a Power-off delay time (tDPOFF) for any channel in
the last sequence position (reverse order) and then
deactivate the PUP outputs for those channels. The
Power-off delay times are individually programmable
for each channel. The SMM465 will then wait until all
VMX inputs of the channels assigned to that sequence
position are below the programmed OFF thresholds.
At this point, the SMM465 will decrement to the next
sequence position and begin to timeout the Power-off
delay times for the associated channels. This process
continues until all of channels in the sequence have
turned off and are below their OFF thresholds. The
status register reveals that all sequenced channels
have turned off. The Power-off sequencing mode
ends when all sequenced supplies are below their
OFF thresholds.
The programmable sequence termination timer can be
used to protect against a stalled Power-off sequence.
This timer resets itself at the beginning of each
sequence position. All channels in the sequence
position must go below their OFF threshold before the
sequence termination timer times out (tSTT) or the
sequence will terminate and all PUP outputs will be
switched to their inactive state. This timer has four
settings of OFF, 100ms, 200ms and 400ms. The
sequence termination timer can be disabled separately
for Power-off sequencing.
Shutdown operation shuts off all sequenced channels
and waits for the supply voltages to drop below their
respective OFF thresholds.
A Force Shutdown operation can be initiated by any
one of four events. The first two methods for initiating
a Force Shutdown are always enabled. Simply taking
the FS pin to its active state will initiate a Force
Shutdown operation and maintain it until the pin is
brought to its inactive state. An I2C Force Shutdown
command allows the Force Shutdown operation to be
initiated via software control. This I2C Force Shutdown
command sets a volatile register bit that triggers a
Force Shutdown.
This bit is cleared after all
sequenced channels have dropped below their OFF
voltage threshold. During Power-on and Power-off
sequencing, the sequence termination timer can
initiate a Force Shutdown operation.
As described in the previous sections, the sequence
termination timer triggers a Force Shutdown operation
if it times out before the power supply voltages
surpass their voltage thresholds.
This Force
Shutdown will remain active until all sequenced power
supply channels have dropped below their OFF
voltage threshold. While the SMM465 is in ongoing
operations-monitor mode,
a
programmed fault
condition on any power supply channel or on the
12VIN or VDD inputs can trigger a Force Shutdown. A
Force Shutdown resulting from this will remain active
until all sequenced power supply channels have
dropped below their OFF voltage threshold.
Summit Microelectronics, Inc
2085 1.1 05/27/04
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SMM465
Preliminary Information
SMM465 Brownout Recovery/Handling
followed by a ‘Power-On’ command and ending with a
‘Clear’ command. If the PWR_ON/OFF pin is in the
asserted state, the SMM465 will initiate a power-on
sequence once all input conditions are met. Otherwise
the PWR_ON/OFF pin may require toggling if, upon
recovery from the ‘brownout’, it is in the de-asserted
state.
During a power ‘brown-out’ (Figure 9) the SMM465
can default to a power-off state, thus requiring toggling
of the PWR_ON/OFF pin to enable the device to
perform a power-on sequence. For applications using
I2C control of the power-on/power-off function, the
same result may be effected by, upon recovery of
power, issuing a software (I2C) ‘Power-Off’ command
-48V Supply
0V
Power Brown-Out
-48V
SMM465 Supplies
+12VIN
SMM465 Hold-Up Time
VDD_CAP
Figure 9 - Power Brown-Out with Resulting Loss of SMM465 Supply Voltages
Summit Microelectronics, Inc
2085 1.1 05/27/04
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SMM465
Preliminary Information
RESTART OF POWER-ON CASCADE SEQUEN-
CING
after the brownout condition is over or if the supplies
do not fully discharge before initiating a Power-on
sequence.
Once a Force Shutdown or Power-off operation has
completed, the SMM465 can restart the Power-on
cascade sequencing. The device can be programmed
to automatically restart after a Force Shutdown
provided the PWR_ON/OFF pin remains in the active
state or the I2C Power-on command remains in the
command register. If this option is not selected, the
SMM465 requires toggling of the PWR_ON/OFF pin or
toggling of the I2C commands by issuing a Power-off
command and then reissuing the Power-on command
in order to restart Power-on sequencing.
In either case, assertion of the FS pin will prevent the
SMM465 from restarting Power-on sequencing. In
addition, the device can be programmed to check that
VDD and the 12VIN are within their programmed
voltage thresholds before restarting Power-on
sequencing.
Recommended Use of the PWR_ON/OFF pin:
The PWR_ON/OFF pin is edge-triggered to lock out
false or nuisance signals during both the power-on
and power-off sequences. If during a system power-
down, whether deliberate or due to a failed power
system, the VDD_CAP voltage falls below 2.5V, the
SMM465 internal UVLO (UnderVoltage LockOut)
circuit resets all internal logic. Once power has
recovered above 2.6V the SMM465 will restart
assuming the PWR_ON/OFF pin is in the asserted
state or an I2C power command is issued. The
SMM465 can be used with the PWR_ON/OFF pin
either toggled by a logic level, controlled by a software
command or tied either high or low as described in the
data sheet.
In cases where brownout conditions (Figure 10) or
loss of power are used to cause a sequence off of the
supplies or a Force Shutdown, it is best to toggle the
PWR_ON/OFF pin or use the I2C Power commands
VDD_CAP
3.6V, 5.5V
2.6V
2.5V
UVLO
(Internal)
Figure 10 - Timing Sequence recovering from a VDD_CAP Power ‘Brown-Out’
Summit Microelectronics, Inc
2085 1.1 05/27/04
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SMM465
Preliminary Information
Figure 11 – SMM465 Distributed power applications schematic. The accuracy of the external reference (U10)
sets the accuracy of the ADOC function. Total accuracy with a ±0.1% external reference is ±0.2%.
Summit Microelectronics, Inc
2085 1.1 05/27/04
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SMM465
Preliminary Information
12V
12V
PUPB
C8
Rtrim
1.6K
SS1
FB1
TRIMB
SDA
R7
R9
SCL
CS
I2C BUS
VMB+
VSW1
FB1S
VOUT1
1.5V
SMM465
PUPA
Not all components Shown
For interface purposes only
Part designators are from
the International Rectifier
iP1202 Demo board .
C7
Rtrim
3.3K
SS2
TRIMA
FB2
IR
R8
R10
iP1202
VMA+
VSW2
FB2S
VOUT2
2.5V
Figure 12 – The SMM465 can be used to sequence and control discrete DC switching regulators. The ADOC
function sets the output voltage of the IR iP1202 Regulator through the FBX feedback pins. Accuracy is
improved even under full load, essentially acting as a “SENSE” pin. The sequence function is applied
through the iP1202 SSX soft start pins.
Figure 13 – Ch1 is set to 2.5V and Ch2 is set to
1.5V on the ip1202 board. Ch1 is set to sequence
on first followed by Ch2 after 50ms. Then Ch1 is
margined high while Ch2 is margined low. Ch2 is
then sequenced off followed by Ch1 after 50ms.
Figure 14 – This is the same sequencing-on
function but with
a
shorter delay between
channels, the HEALTHY and RESET flags are also
shown.
Summit Microelectronics, Inc
2085 1.1 05/27/04
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SMM465
Preliminary Information
DEVELOPMENT HARDWARE & SOFTWARE
The Windows GUI software will generate the data and
send it in I2C serial bus format so that it can be directly
downloaded to the SMM465 via the programming
Dongle and cable. An example of the connection
interface is shown in Figure 15.
The end user can obtain the Summit SMX3200
programming
system
for
device
prototype
development. The SMX3200 system consists of a
programming Dongle, cable and WindowsTM GUI
software. It can be ordered on the website or from a
local representative. The latest revisions of all
software and an application brief describing the
When design prototyping is complete, the software
can generate a HEX data file that should be
transmitted to Summit for approval. Summit will then
assign a unique customer ID to the HEX code and
program production devices before the final electrical
SMX3200
is
available
from
the
website
(www.summitmicro.com).
The SMX3200 programming Dongle/cable interfaces
directly between a PC’s parallel port and the target
application. The device is then configured on-screen
via an intuitive graphical user interface employing
drop-down menus.
test operations.
This will ensure proper device
operation in the end application.
Top view of straight 0.1" x 0.1 closed-side
connector. SMX3200 interface cable connector.
D1
1N4148
Pin 10, Reserved
Pin 8, Reserved
Pin 6, MR#
Pin 9, 5V
Pin 7, 10V
Pin 5, Reserved
Pin 3, GND
Pin 1, GND
Pin 4, SDA
VDD_CAP
Pin 2, SCL
10 9
8
6
4
2
7
5
3
1
SMM465
0.1 F
MR
SDA
SCL
GND
Figure 15 – SMX3200 Programmer I2C serial bus connections to program the SMM465. Note that the MR pin
does not need to be connected to pin 6 for programming purposes.
Summit Microelectronics, Inc
2085 1.1 05/27/04
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SMM465
Preliminary Information
I2C PROGRAMMING INFORMATION
SERIAL INTERFACE
Any access to the SMM465 on the I2C bus will
temporarily halt the monitoring function. This does not
affect the ADOC function, which will continue
functioning and control the DC outputs. This is true
not only during the monitor mode, but also during
Power-on and Power-off sequencing when the device
is monitoring the channels to determine if they have
turned on or turned off.
The SMM465 halts the monitor function from when it
acknowledges the address byte until a valid stop is
received.
WRITE
Writing to the memory or a configuration register is
illustrated in Figures 16, 17, 19, 21 and 22. A Start
condition followed by the address byte is provided by
the host; the SMM465 responds with an Acknowledge;
the host then responds by sending the memory
address pointer or configuration register address
pointer; the SMM465 responds with an acknowledge;
the host then clocks in on byte of data. For memory
and configuration register writes, up to 15 additional
bytes of data can be clocked in by the host to write to
consecutive addresses within the same page. After
the last byte is clocked in and the host receives an
Acknowledge, a Stop condition must be issued to
initiate the nonvolatile write operation.
Access to the configuration registers, general-purpose
memory and command and status registers is carried
out over an industry standard 2-wire serial interface
(I2C). SDA is a bi-directional data line and SCL is a
clock input. Data is clocked in on the rising edge of
SCL and clocked out on the falling edge of SCL. All
data transfers begin with the MSB. During data
transfers SDA must remain stable while SCL is high.
Data is transferred in 8-bit packets with an intervening
clock period in which an Acknowledge is provided by
the device receiving data. The SCL high period (tHIGH
)
is used for generating Start and Stop conditions that
precede and end most transactions on the serial bus.
A high-to-low transition of SDA while SCL is high is
considered a Start condition while a low-to-high
transition of SDA while SCL is high is considered a
Stop condition.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
unique device addressing.
The address byte is
comprised of a 4-bit device type identifier (slave
address) and a 3-bit bus address. The remaining bit
indicates either a read or a write operation. Refer to
Table 1 for a description of the address bytes used by
the SMM465.
The device type identifier for the memory array is
generally set to 1010BIN following the industry standard
for a typical nonvolatile memory. There is an option to
change the identifier to 1011BIN allowing it to be used
on a bus that may be occupied by other memory
devices. The configuration registers are grouped with
the memory array and thus use 1010BIN or 1011BIN as
the device type identifier. The command and status
registers as well as the 10-bit ADC are accessible with
READ
The address pointer for the configuration registers,
memory, command and status registers and ADC
registers must be set before data can be read from the
SMM465. This is accomplished by a issuing a dummy
write command, which is simply a write command that
is not followed by a Stop condition. The dummy write
command sets the address from which data is read.
After the dummy write command is issued, a Start
command followed by the address byte is sent from
the host. The host then waits for an Acknowledge and
then begins clocking data out of the slave device. The
first byte read is data from the address pointer set
during the dummy write command. Additional bytes
can be clocked out of consecutive addresses with the
host providing an Acknowledge after each byte. After
the data is read from the desired registers, the read
operation is terminated by the host holding SDA high
during the Acknowledge clock cycle and then issuing a
Stop condition. Refer to Figures 18, 20 and 23 for an
illustration of the read sequence.
the separate device type identifier of 1001BIN
.
The bus address bits A[1:0] are programmed into the
configuration registers. Bus address bit A[2] can be
programmed as either 0 or biased by the A2 pin. The
bus address accessed in the address byte of the serial
data stream must match the setting in the SMM465
and on the A2 pin.
Summit Microelectronics, Inc
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SMM465
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
WRITE PROTECTION
The word address must be set each time the memory
is accessed. Memory writes and reads are shown in
Figures 22, 23 and 24.
The SMM465 powers up into a write protected mode.
Writing a code to the volatile write protection register
can disable the write protection. The write protection
register is located at address 87HEX of slave address
COMMAND AND STATUS REGISTERS
The command and status registers are located at
1001BIN
.
slave address 1001BIN
.
Writes and reads of the
Writing 0101BIN to bits [7:4] of the write protection
register allow writes to the general-purpose memory
while writing 0101BIN to bits [3:0] allow writes to the
configuration registers. The write protection can re-
enable by writing other codes (not 0101BIN) to the write
protection register. Writing to the write protection
register is shown in Figure 16.
command and status registers are shown in Figures
25 and 26.
ADC CONVERSIONS
An ADC conversion on any monitored channel can be
performed and read over the I2C bus using the ADC
read command. The ADC read command, shown in
Figure 27, starts with a dummy write to the 1001BIN
slave address. Bits [6:3] of the word address byte are
used to address the desired monitored input. Once
the device acknowledges the channel address, it
begins the ADC conversion of the addressed input.
This conversion requires 70µs to complete. During
this conversion time, acknowledge polling can be
used. The SMM465 will not acknowledge the address
bytes until the conversion is complete. When the
conversion has completed, the SMM465 will
acknowledge the address byte and return the 10-bit
conversion along with a 4-bit channel address echo.
CONFIGURATION REGISTERS
The majority of the configuration registers are grouped
with the general-purpose memory located at either
slave address 1010BIN or 1011BIN. The bus address
bits, A[1:0], used to differentiate the general-purpose
memory from the configuration registers are set to
11BIN. Bus address bit A[2] can be programmed as
either 0 or biased by the A2 pin.
Two additional configuration registers are located at
addresses 83HEX and 84HEX of slave address 1001BIN
.
Writing and reading the configuration registers is
GRAPHICAL USER INTERFACE (GUI)
shown in Figures 17, 18, 19, 20 and 21
Device configuration utilizing the Windows based
SMM465 graphical user interface (GUI) is highly
recommended. The software is available from the
Summit website (www.summitmicro.com). Using the
GUI in conjunction with this datasheet and Application
Note 33, simplifies the process of device prototyping
and the interaction of the various functional blocks. A
programming Dongle (SMX3200) is available from
Summit to communicate with the SMM465. The
Dongle connects directly to the parallel port of a PC
and programs the device through a cable using the I2C
bus protocol.
Note: Configuration writes or reads of registers 00HEX
to 0FHEX should not be performed while the SMM465 is
margining.
GENERAL-PURPOSE MEMORY
The 4k-bit general-purpose memory is located at
either slave address 1010BIN or 1011BIN
.
The bus
address bits, A[1:0], used to differentiate the general-
purpose memory from the configuration registers are
set to 00BIN for the first 2k-bits and 01BIN for the second
2k-bits. Bus address bit A[2] can be programmed as
either 0 or biased by the A2 pin.
Slave Address Bus Address Register Type
Write Protection Register,
Command and Status Registers,
Two Configuration Registers,
ADC Conversion Readout
1001BIN
A2 A1 A0
A2 0 0
A2 0 1
A2 1 1
1st 2-k Bits of General-Purpose Memory
2nd 2-k Bits of General-Purpose Memory
Configuration Registers
1010BIN
or
1011BIN
Table 1 - Address bytes used by the SMM465.
Summit Microelectronics, Inc
2085 1.1 05/27/04
23
SMM465
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S
T
S
T
O
P
A
Configuration
Register Address = 87HEX
R
T
Master
Slave
Bus Address
Data = 55HEX
A
2
A
1
A
0
1
0
0
1
W
1
0
0
0
0
1
1
1
0
1
0
1
0
1
0
1
A
C
K
A
C
K
A
C
K
8HEX
Write Protection
Register Address
7HEX
5HEX Unlocks
5HEX Unlocks
Configuration
Registers
General Purpose
EE
Figure 16 – Write Protection Register Write
S
T
S
T
A
R
T
Configuration
Register Address
O
P
Master
Slave
Bus Address
Data
S
A
0
A
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
0
1
1
1
W
2
A
C
K
A
C
K
A
C
K
Figure17 – Configuration Register Byte Write
S
T
A
R
T
Configuration
Register Address
Master
Bus Address
Data (1)
S
A
0
A
2
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
0
1
1
1
W
Slave
A
C
K
A
C
K
A
C
K
S
T
O
P
Master
Slave
Data (2)
Data (16)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
A
C
K
Figure 18 – Configuration Register Page Write
Summit Microelectronics, Inc
2085 1.1 05/27/04
24
SMM465
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S
T
S
T
A
A
R
T
Configuration
R
Master
Slave
Bus Address
Bus Address
Register Address
T
S
A
0
S
A
0
A
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
2
1
0
1
1
1
W
1
0
1
1
1
R
2
A
C
K
A
C
K
A
C
K
N
A
C
K
S
T
A
C
K
A
C
K
O
P
Master
Slave
Data (1)
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 19 - Configuration Register Read
S
T
S
T
A
R
T
Configuration
Register Address
O
P
Master
Slave
Bus Address
Data
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
0
0
1
W
A
C
K
A
C
K
A
C
K
Figure 20 - Configuration Register with Slave Address 1001BIN Write
S
S
T
T
A
R
T
A
R
T
Configuration
Master
Slave
Bus Address
Bus Address
Register Address
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
2
A
1
A
0
1
0
0
1
W
1
0
0
1
R
A
C
K
A
C
K
A
C
K
N
A
C
K
S
T
A
C
K
A
C
K
O
P
Master
Slave
Data (1)
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 21 - Configuration Register with Slave Address 1001BIN Read
Summit Microelectronics, Inc
2085 1.1 05/27/04
25
SMM465
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S
T
A
S
T
R
T
O
P
Memory Address
Master
Slave
Bus Address
Data
S
A
0
0
A
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
D
3
D
2
D
1
D
0
1
0
1
0
/
W
2
4
1
A
C
K
A
C
K
A
C
K
Figure 22 – General Purpose Memory Byte Write
S
T
A
R
T
Memory Address
Bus Address
Master
Data (1)
S
A
0
0
/
A
2
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
0
1
0
W
1
Slave
A
C
K
A
C
K
A
C
K
S
T
O
P
Master
Slave
Data (2)
Data (16)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
A
C
K
Figure 23 - General Purpose Memory Page Write
S
T
S
T
A
A
R
T
R
T
Memory Address
Master
Bus Address
Bus Address
S
A
0
0
S
A
0
0
A
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
1
0
1
0
/
W
1
0
1
0
/
R
2
2
1
1
Slave
A
C
K
A
C
K
A
C
K
N
A
C
K
S
T
A
C
K
A
C
K
O
P
Master
Slave
Data (1)
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 24 - General Purpose Memory Read
Summit Microelectronics, Inc
2085 1.1 05/27/04
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SMM465
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S
T
S
T
A
Command and Status
Register Address
R
O
P
Master
Slave
Bus Address
Data
T
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
D
3
D
2
D
1
D
0
1
0
0
1
W
4
A
C
K
A
C
K
A
C
K
Figure 25 – Command and Status Register Write
S
T
S
T
A
R
T
A
Command and Status
Register Address
R
Master
Slave
Bus Address
Bus Address
T
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
2
A
1
A
0
1
0
0
1
W
1
0
0
1
R
A
C
K
A
C
K
A
C
K
N
A
C
K
S
T
A
C
K
A
C
K
O
P
Master
Slave
Data (1)
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 26 - Command and Status Register Read
S
T
S
T
A
R
T
A
R
Master
Slave
Bus Address
Channel Address
Bus Address
T
C
H
3
C
H
2
C
H
1
C
H
0
A
2
A
1
A
0
A
2
A
1
A
0
1
0
0
1
W
0
0
0
0
1
0
0
1
R
A
C
K
A
C
K
N
A
C
K
S
T
N
A
C
K
S
T
A
R
T
A
C
K
O
P
Master
Slave
Bus Address
Channel Address Echo
10-Bit ADC Data
C
H
3
C
H
2
C
H
1
C
H
0
A
2
A
1
A
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
0
0
1
R
0
0
A
C
K
Figure 27 – ADC Conversion Read
Summit Microelectronics, Inc
2085 1.1 05/27/04
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SMM465
Preliminary Information
DEFAULT CONFIGURATION REGISTER SETTINGS – SMM465FC-249
Register
R00
Contents
0D
Register
R42
Contents
0E
Register
R9A
Contents
81
Register
Contents
38
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
RC9
RCA
RCB
RCC
RCD
RCE
RCF
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
RE8
RE9
REA
REB
R01
R02
R03
R04
R05
R06
R07
R08
R09
R0A
R0B
R0C
R0D
R0E
R0F
R10
R11
R12
R13
R18
R19
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R3A
R3B
R3C
R3D
R3E
R40
R41
83
0D
FF
0E
61
0E
C7
0F
54
0B
22
7F
0F
07
01
8F
9F
AF
BF
00
00
0D
60
0D
DC
0E
45
0E
A2
0F
08
0F
D6
00
12
48
0D
B9
R43
R44
R45
R46
R47
R48
R49
R4A
R4B
R4C
R4D
R4E
R80
R81
R82
R83
R84
R85
R86
R87
R88
R89
R8A
R8B
R8C
R8D
R8E
R8F
R90
R91
R92
R93
R94
R95
R96
R97
R98
R99
39
0E
A4
0F
16
0F
B4
06
7F
00
12
50
42
48
82
3E
2A
B8
12
F6
41
C8
81
B9
2A
34
12
49
49
5C
81
52
29
D7
11
EB
41
3E
R9B
R9C
R9D
R9E
R9F
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RAA
RAB
RAC
RAD
RAE
RAF
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RB8
RB9
RBA
RBB
RBC
RBD
RBE
RBF
RC0
33
29
9A
11
AE
41
0B
80
F6
29
5D
11
71
40
CE
80
8F
29
1F
11
33
2A
67
0A
52
03
FF
03
FF
0D
9A
0D
56
0F
E0
0F
E0
0B
0B
38
09
90
09
90
0C
00
0C
00
0F
FF
0F
FF
0C
00
0C
00
0F
D8
0F
D8
00
3D
00
3D
00
3D
00
3D
00
3D
00
3D
RC1
The default device ordering number is SMM465FC-249. It is programmed with the register contents as shown above
and tested over the commercial temperature range with a VREF setting of 1.25V. Other standard external VREF
voltage settings that can be specified and tested are values of: 1.024, 1.225, 1.250, 2.048, 2.500, 3.000 or 3.300.
The value is derived from the customer supplied hex file. New device suffix numbers are assigned to non-default
requirements. If other VREF values are required, please contact a Summit Microelectronics Sales Representative.
Application Note 47 contains a complete description of the Windows GUI and the default settings of each of
the 154 individual Configuration Registers.
Summit Microelectronics, Inc
2085 1.1 05/27/04
28
SMM465
Preliminary Information
PACKAGE
48 PIN TQFP PACKAGE
Inches
(Millimeters)
0.354
(9.00)
BSC
BSC
(A)
(B)
0.276
(7.00)
0.02
BSC
(0.5)
0.007 - 0.011
(0.17 - 0.27)
DETAIL "A"
(B)
(A)
Ref Jedec MS-026
0.037 - 0.041
0.95 - 1.05
Pin 1
Indicator
0.039
(1.00)
Ref
0.047
MAX.
(1.2)
0o Min to
7o Max
0.002 - 0.006
(0.05-0.15)
A
B
0.018 - 0.030
(0.45 - 0.75)
DETAIL "B"
Summit Microelectronics, Inc
2085 1.1 05/27/04
29
SMM465
Preliminary Information
PART MARKING
Summit Part Number
SUMMIT
Status Tracking Code
(Blank, MS, ES, 01, 02,...)
(Summit Use)
SMM465F
xx
AYYWW
Annn
Date Code (YYWW)
Pin 1
Identifier
Lot tracking code (Summit use)
Part Number suffix
(Contains Customer specific ordering requirements)
Product Tracking Code (Summit use)
Drawing not to scale
ORDERING INFORMATION
SMM465
nnn
C
F
Summit
Part
Part Number Suffix (see page 28)
Specific requirements are contained in the suffix such as
Hex code, Hex code revision, etc. The calibrated VREF voltage
Number
Temp Range settings are standard values of: 1.024, 1.225, 1.250, 2.048,
Package
F=48 Lead TQFP
C=Commercial
Blank=Industrial
2.500, 3.000 or 3.300
NOTICE
NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization.
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,
performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license
under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained
herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this
publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or
omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or
malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness.
Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that:
(a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc.
is adequately protected under the circumstances.
Revision 1.1
-
This document supersedes all previous versions.
Please check the Summit Microelectronics Inc. web site at
www.summitmicro.com for data sheet updates.
© Copyright 2004 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE ANALOG FOR A DIGITAL WORLD™
ADOCTM is a registered trademark of Summit Microelectronics Inc., I C is a trademark of Philips Corporation.
2
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2085 1.1 05/27/04
30
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