SMS47GR02
更新时间：2024-09-18 05:36:41
品牌：SUMMIT
描述：Quad Programmable Precision Cascade Sequencer and Supervisory Controller
概述
数据手册SMS47GR02 概述
Quad Programmable Precision Cascade Sequencer and Supervisory Controller 四可编程精密梯级定序和监控器
SMS47GR02 数据手册
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SMS47
MICROELECTRONICS, Inc.
PRELIMINARY INFORMATION1 (SEELASTPAGE)
Quad Programmable Precision Cascade Sequencer and Supervisory
Controller
FEATURES
INTRODUCTION
The SMS47 is a nonvolatile user-programmable voltage
supply cascade sequencer and supervisory circuit de-
signed specifically for advanced systems that need to
monitor multiple voltages. The SMS47 can monitor four
separatevoltageswithouttheneedofanyexternalvoltage
divider circuitry unlike other devices that need factory-
trimmed threshold voltages and external components to
accommodate different supply voltages and tolerances.
z Operational from any of four Voltage Monitoring
Inputs
z ProgrammablePower-upCascadeSequencing
z Programmability allows monitoring any voltage
between 0.6V and 5.6V with no external
components
z Programmable 5mV steps in the low range
z ProgrammableWatchdogTimer
TheSMS47canalsobeusedtoenableDC/DCconverters
orLDOstoprovideaclosedloopcascadingofthesupplies
duringpower-up.
z Programmable Reset Pulse Width
z ProgrammableNonvolatileCombinatorialLogic
forgenerationofReset
z FaultStatusRegister
The SMS47 watchdog timer has a user programmable
time-out period and it can be placed in an idle mode for
system initialization or system debug. All of the functions
areuseraccessiblethroughanindustrystandardI2C2-wire
serial interface.
APPLICATIONS
z Desktop/Notebook/TabletComputers
z Multi-voltageSystems
z Telecom/NetworkServers
z PortableBattery-poweredEquipment
z Set-topBoxes
Programming of configuration, control and calibration
valuesbytheuserissimplifiedwiththeSMX3200program-
mingadapterandWindowsGUIsoftwareobtainablefrom
Summit Microelectronics.
z Data-storageEquipment
SIMPLIFIED APPLICATION DRAWING
5V
2
I C
7
6
9
10
12
SCL
PUP#1
SDA
A2 A1
VDD_CAP
4
DC/DC
3.3V
2.5V
1.8V
16
2
3
14
V
V
V
V
0
1
2
3
0.1µF
5
PUP#2
PUP#3
DC/DC
SMS47
1
MR#
WLDI
GND
Reset#
15
13
LDO
RESET#
11
8
2047 SAD 2.0
Applications Schematic using the SMS47 Controller to provide closed loop power-up cascade sequenc-
ingandsupervisoryfunctions.
NOTE: THIS IS AN APPLICATIONS EXAMPLE ONLY. SOME PINS, COMPONENTS AND VALUES ARE NOT SHOWN.
©SUMMIT MICROELECTRONICS, Inc., 2005
Characteristics subject to change without notice
• 1717 Fox Dr. • San Jose, CA 95131 • Phone 408-436-9890 • FAX 408-436-9897 •
www.summitmicro.com
1
2087 1.1 04/11/05
SMS47
PreliminaryInformation
INTERNAL BLOCK DIAGRAM
VDD_CAP
CONFIGURATION
REGISTER
50kΩ
11
RESET#
MR#
1
V
0
16
PROGRAMMABLE
RESET PULSE
GENERATOR
NV DAC
REF
+
–
4
5
PUP#1
PUP#2
PUP#3
PROGRAMMABLE
POWER
CASCADING
V
1
2
3
13
NV DAC
REF
+
–
9
SDA
SERIAL
BUS
V
2
10 SCL
CONTROL
LOGIC
7
A2
A1
NV DAC
REF
6
+
–
PROGRAMMABLE
WATCHDOG
TIMER
V
3
14
NV DAC
REF
VDD_CAP
+
–
50kΩ
15
WLDI
V
0
CONFIGURATION
REGISTER
SUPPLY
ARBITRATION
V
1
2
V
V
3
12
8
VDD_CAP
GND
CASCADE SEQUENCING
Time basedsequencinghastheabilitytoturnsupplieson
inaspecificorder. However,itcannotguaranteethateach
supply has reached valid voltage levels before the next
supplyissequencedon. Cascadesequencingguarantees
thesuppliesareenabledaprogrammedperiodoftimeafter
the previous voltage has reached its minimum pro-
grammedvalidlevel. Figure1showsthateachsucceeding
voltagemustreachitsminimumvalidlevelbeforethetimer
is started to time the interval, t, for the next voltage. The
duration of each t is programmable for each supply to
supply transition. The next supply is not enabled until the
timer has elapsed. See also Figure 5.
6V
4V
2V
0V
5V
5V Valid
3.3V Valid
3.3V
V
2.5V
1.8V
2.5V Valid
t
t
t
T
2047 Fig01
Figure 1. Cascading Power Supplies
SUMMIT MICROELECTRONICS, Inc.
2087 1.1 04/11/05
2
SMS47
PreliminaryInformation
PIN CONFIGURATION
PIN NAMES
Pin
1
2
3
4
Name
MR#
V1
Function
Manual reset input
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
0
WLDI
MR#
Voltage supply and monitor input
Voltage supply and monitor input
Power up permitted output
Power up permitted output
Address input
V
V
1
V2
V
3
2
PUP#3
VDD_CAP
RESET#
SCL
PUP#1
PUP#2
A1
A2
GND
PUP#1
PUP#2
A1
5
6
SDA
7
A2
Address input
8
9
GND
SDA
SCL
Power supply return
Serial data I/O
Serial data clock
2047 PCon 2.0
10
11
12
13
14
15
16
RESET#
VDD_CAP Power supply output
PUP#3
V3
WLDI
V0
Reset out
Power up permitted
Voltage supply and monitor input
Watchdog Timer interrupt
Voltage supply and monitor input
2047 Pins Table 2.0
SUMMIT MICROELECTRONICS, Inc.
2087 1.0 04/11/05
3
SMS47
PreliminaryInformation
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED OPERATING CONDITIONS
Industrial Temperature Range............... –40ºC to +85ºC.
Commercial Temperature Range..............–5ºC to +70ºC.
VSUPPLY Supply Voltage............................2.7V to 5.5V
Temperature Under Bias ...................... –55°C to 125°C
StorageTemperature ............................. –65°Cto150°C
LeadSolderTemperature(10s) ........................... 300°C
Terminal Voltage with Respect to GND:
VSUPPLY = Device supply voltage provided by the
highest VX input.
V , V , V , and V ......... –0.3V to 6.0V
0
1
2
3
All Others ....................... –0.3V to 6.0V
Junction Temperature.......................…….....…...150°C
ESDRatingperJEDEC……………………..….…..2000V
Latch-Up testing per JEDEC………..…….......…±100mA
Package Thermal Resistance (θJA)
16 Lead SSOP…………………….………….…23oC/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
*Note - Stresses beyond the listed Absolute Maximum Ratings may
RELIABILITYCHARACTERISTICS
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
DataRetention………………….…………..…..100Years
Endurance……………………….…..…….100,000Cycles
DC OPERATING CHARACTERISTICS
(OverRecommendedOperatingConditions;VoltagesarerelativetoGND)
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
1V Min. refers to a valid reset out-
put being generated
1.0
5.5
V
VSUPPLY Operating supply voltage
Read/Write operations: at
least one of the V inputs must be
at or above VSUPPLYX min.
2.7
5.5
V
VDD_CAP = 5.5V; V0 trip point 4.7V; V1, V2,
V3 = GND; MR# = VCC; all outputs
floating
200
400
µA
ICC
Supply current
Configuration register access
3
mA
V
Reset threshold voltage range V0
V
Programmable threshold
RaPnTgHe range (low range)
0.6
1.8
1.875
to V3 (5mV increments)
V
Programmable threshold
Reset threshold voltage range V0
to V3 (15mV increments)
RaPnTgHe range (high range)
5.625
1.0
V
Programmable threshold
VPTH is the programmed threshold
VPTHACC
–1.0
VPTH
30
%
Accuracy
setpoint within the VPTH Range
VHYST VRST hysteresis
See Note 1 below
mV
V
ISINK = 1mA, VVDD_CAP ≥ 2.7V
0.3
0.3
0.6
VOL
Low voltage output
I
SINK = 200µA, VVDD_CAP = 1.0V
V
VIL
VIH
V
Input threshold
0.7 ´ VCC
V
Note 1: Low Range Hysteresis = 4.2 X (Vtrip - 0.5 volts) mV. For Vtrip = 1.0 volts, Hysteresis = 2.1 mV (0.21 %),
High Range Hysteresis = 12.6 X (Vtrip -0.5 volts) mV. For Vtrip = 5.0 volts, Hysteresis = 56.7 mV (1.13%).
SUMMIT MICROELECTRONICS, Inc.
2087 1.1 04/11/05
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SMS47
PreliminaryInformation
AC OPERATING CHARACTERISTICS
(OverRecommendedOperatingConditions;VoltagesarerelativetoGND, alsoseeconfigurationregisters)
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
WD2
WD1
WD0
0
0
1
1
1
1
0
1
0
0
1
1
X
1
0
1
0
1
OFF
400
—
300
600
500
Programmable Watchdog
timer period
tPWDTO
800
1000
2000
4000
8000
1200
2400
4800
1600
3200
6400
ms
PUP#X-1 PUP#X-0
0
0
1
1
0
1
0
1
0ms
25
—
Programmable delay from
VPTH to PUP# out
t
PDLYX
19
38
75
31
63
50
ms
100
100
300
125
IMR
MR# pullup current
µA
ns
TMR
MR# input pulse width
Minimum
Delay from MR# low to
RESET# low
TDMRRST
200
ns
RTO1
RTO0
0
0
1
1
0
1
0
1
19
38
25
50
31
63
ms
ms
ms
ms
µs
Programmable reset pulse
width
tPRTO
75
100
200
20
125
250
150
tDRST
V in to RESET# delay
100mV overdrive
SUMMIT MICROELECTRONICS, Inc.
2087 1.0 04/11/05
5
SMS47
PreliminaryInformation
PIN DESCRIPTIONS
V0, V1, V2, V3 (16, 2, 3, 14)
These inputs are used as the voltage monitor inputs and
as the voltage supply for the SMS47. Internally they are
diode ORed and the input with the highest voltage
potential will be the default supply voltage (VDD_CAP).
V
PTH-UV
V
— V
3
0
t
t
DRST
PRTO
TheRESET#outputwillbevalidifanyoneofthefourinputs
isabove1V. However,forfulldeviceoperationatleastone
of the inputs must be at 2.7V or higher.
RESET#
The sensing threshold for each input is independently
programmable in 5mV increments from 0.6V to 1.875V or
15mV increments from 1.8V to 5.625V. Also, the occur-
renceofanunder-orover-voltageconditionthatisdetected
asaresultofthethresholdsettingcanbeusedtogenerate
a RESET#. The programmable nature of the threshold
voltage eliminates the need for external voltage divider
networks.
Figure 3. RESET# Timing
ration register 4). Refer to Figures 2 and 3 for a detailed
illustrationoftherelationshipbetweenMR#,RESET#and
the VIN levels.
VDD_CAP(12)
TheVDD_CAPpinconnectstotheinternalsupplyvoltage
for the SMS47. A capacitor is placed on this pin to filter
supply noise as well as hold up the device in the event of
powerfailure. Thevoltageonthisnodeisdeterminedbythe
highest input voltage. Loading of this pin should be
minimized to prevent excessive power dissipation in the
part.
GND
Power supply return.
MR# (1)
The manual reset input always generates a RESET#
output whenever it is driven low. The duration of the
RESET#outputpulsewillbeinitiatedwhenMR#goeslow
and it will stay low for the duration of MR# low plus the
programmed reset time-out period (tPRTO). If MR# is
brought low during a power-on cascade of the PUP#s the
cascade will be halted for the reset duration, and will then
resume from the point at which it was interrupted. MR#
mustbeheldlowduringaconfigurationregisterwrite. This
signal is pulled up internally through a 50kΩ resistor.
WLDI(15)
Watchdogtimer input. Ahigh-to-lowtransitionontheWLDI
input will clear the watchdog timer, effectively starting a
new time-out period. This signal is pulled up internally
through a 50kΩ resistor.
If WLDI is stuck low and no high-to-low transition is
received within the programmed tPWDTO period (pro-
grammedwatchdogtime-out)RESET# willbedrivenlow.
Refer to Figure 4 for a detailed illustration.
RESET#(11)
The reset output is an active low open drain output. It will
be driven low whenever the MR# input is low or whenever
anenabledunder-voltageorover-voltageconditionexists.
Thefourvoltagemonitorinputsarealwaysfunctioning,but
theirabilitytogeneratearesetisprogrammable(configu-
Holding WLDI low will not block the watchdog from timing
outandgeneratingareset. RefertoFigure4foradetailed
illustrationoftherelationshipbetweenRESET#andWLDI.
t
0
t
PWDTO
t
t
t
t
0
0
0
0
t
MR#
PRTO
RESET#
WLDI
t
DMRRST
t
t
PWDTO
PRTO
t
RESET#
PRTO
2047 Fig04 3.0
Figure 4. Watchdog and WLDI Timing
Figure 2. RESET# Timing with MR#
SUMMIT MICROELECTRONICS, Inc.
2087 1.1 04/11/05
6
SMS47
PreliminaryInformation
PIN DESCRIPTIONS (CONTINUED)
A1,A2 (6, 7)
A1 and A2 are the address inputs. When addressing the
SMS47 configuration registers the address inputs distin-
guish which one of four possible devices sharing the
common bus is being addressed.
SDA(9)
SDA is the serial data input/output pin. It should be tied to
VDD_CAP through a pull-up resistor.
SCL(10)
SCListheserialclockinput. ItshouldbetiedtoVDD_CAP
through a pull-up resistor.
PUP#1, PUP#2, PUP#3 (4, 5, 13)
These are the power-up permitted (PUP) active low open
drain outputs. The PUP pins are used when the SMS47 is
programmed to provide the cascade sequencing of LDOs
or DC/DC converters (see Figures 1 and 5 for illustra-
tionsofcascading). Eachdelayisindependentlyenabled
andprogrammableforitsduration(configurationregister
7). If all PUP# outputs are enabled the order of events
would be as follows: V0 above threshold then delay to
PUP#1turningon;V1abovethresholdthendelaytoPUP#2
turningon;V2abovethresholdthendelaytoPUP#3turning
on. The delays are programmable.
SUMMIT MICROELECTRONICS, Inc.
2087 1.0 04/11/05
7
SMS47
PreliminaryInformation
DEVICE OPERATION
V
PTH0
V
0
t
PRTO
RESET#
PUP1#
t
PDLY1
V
PTH1
V
1
t
PDLY2
PUP2#
V
PTH2
V
2
t
PDLY3
PUP3#
V
3
2047 Fig05
Figure 5. VX Input and Resulting PUP# Cascade (RESET# set to trip on V3 Undervoltage)
V
PTH0
V0
50ms
PUP1#
V1
PUP2#
V
PTH2
V2
50ms
PUP3#
2047 Fig06
Figure 6. Timing with Register 7 Contents 22HEX
SUMMIT MICROELECTRONICS, Inc.
2087 1.1 04/11/05
8
SMS47
PreliminaryInformation
DEVICE OPERATION (CONTINUED)
Cascading
Enabled
No
V
0
>V
?
PTH
Yes
tPDLY1
Turn On PUP#1
No
V1
>V
?
PTH
Yes
tPDLY2
Turn On PUP#2
No
V2
>V
?
PTH
Yes
tPDLY3
Turn On PUP#3
2047 Fig07
Figure 7. Cascade Flow Chart
SUMMIT MICROELECTRONICS, Inc.
2087 1.0 04/11/05
9
SMS47
PreliminaryInformation
CONFIGURATION REGISTERS
If cascading is enabled, the designer must insure V0 is the
primary supply and is the first to become active.
SUPPLY AND MONITOR FUNCTIONS
TheV0, V1, V2, andV3 inputsareinternallydiode-ORedso
that any one of the four can act as the device supply. The
RESET# output will be guaranteed true so long as one of
the four pins is at or above 1V.
Associatedwitheachinputisacomparatorwithaprogram-
mable threshold for detection of under-voltage or over-
voltage conditions on any of the four supply inputs. The
threshold can be programmed in 5mV increments any-
where within the range of 0.6V to 1.875V or 15mV incre-
ments within the range of 1.8V to 5.625V. Configuration
registers 0, 1, 2, and 3 adjust the thresholds for V0, V1, V2,
and V3 respectively.
Note: for performing a Read or Write to the con-
figuration register contents, at least one supply
input must be above 2.7V.
Read/Write operations require a 0.1µF capacitor from the
VDD_CAP node to GND. For optimum performance
connect capacitors from each of the Vx inputs to GND.
LocatethecapacitorsasphysicallyclosetotheSMS47as
possible.
If the value contained in any register is all zeroes, the
correspondingthresholdwillbe0.6V. Ifthecontentswere
lowrange 05HEX thethresholdwouldthenbe0.625V[0.6V
+ (5 × 0.005V)]. All four registers are configured as 8-Bit
registers.
D7
D0
D6
D5
D4
D3
D2
D1
Action
MSB
LSB
Highest threshold adjustment = 5.625V
1
1
1
1
1
1
1
1
(High Range)
Lowest threshold adjustment = 0.6V
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
(Low Range)
0
Threshold = 0.6V + (6×0.005V) = 0.625V (e.g.)
Table 1. Configuration Registers 0, 1, 2, and 3
RESET FUNCTION AND THRESHOLD RANGE
conditiononV1. Whenthisconditionceases,theRESET#
output will remain active for tPRTO (programmable reset
time-out). This reset time-out interval takes priority over
the PUP outputs for use of the timer.
The reset output has four programmable sources for
activation. Configurationregister4isusedforselectingthe
activationsource(D7:4),whichcanbeanycombinationof
V0, V1, V2 and V3. A monitor input can be programmed to
activate on either an under-voltage or over-voltage condi-
tion. The low-order four bits of configuration register 5
programtheseoptions. Theresetthresholdvoltagerange
for V0 to V3 can be set for 5mV increments below 1.875V
(lowRange="0")orfor15mVincrementsabove1.8V(high
range = "1") using Bits D3:0.
TheRESET#outputhastwohardwiredsourcesforactiva-
tion: the MR# input, and the expiration of the Watchdog
timer. RESET# will remain active so long as MR# is low,
and will continue driving the RESET# output for tPRTO
(programmableresettimeout)afterMR#returnshigh. The
MR# input cannot be bypassed or disabled.
TheRESET#outputwillbecomeactivewhentriggeredby
a selected activation source such as an under-voltage
Refer to Figures 2, 3 and 4 for a detailed illustration of the
relationships among the affected signals.
D7
D0
D6
D5
D4
D3
D2
D1
Action
MSB
LSB
X
X
X
X
V3
V2
V1
V0
Thestatusofthefoursuppliesisavailableatanytimeover
theI2Cbusinthehighorderconfigurationbitsofregister5
(Table 3). A "1" in a bit location indicates a fault on that
supply.
Voltage Threshold Range
Select
Low
RESET Trigger Enable
0
0
0
0
Range
High
1
1
1
1
Range
Table 2. Configuration Register 4
SUMMIT MICROELECTRONICS, Inc.
2087 1.1 04/11/05
10
SMS47
PreliminaryInformation
CONFIGURATION REGISTERS (CONTINUED)
D3
MSB
D0
LSB
D2
D1
D7
D6
D5
D4
D3
Action
MSB
V3
0
V2
V1
V0
0
Read1
Read Read
Only Only
x
x
x
x
Writing a 0 enables
undervoltage detection for
the selected V input
RTO1 RTO0
Action
Only
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
1
x
x
x
x
tPRTO = 25ms
tPRTO = 50ms
PRTO = 100ms
PRTO = 200ms
Writing a 1 enables
overvoltage detection for
the selected V input
1
1
t
t
Table 3. Configuration Register 5 (D0 through D3)
WATCHDOG TIMER
The Watchdog Timer will generate a reset if it times out. It
can be cleared by a high-to-low transition on WLDI and
restarted.
Table 5. Configuration Register 6 (D3 through D7)
Note 1 - Read Only bit D7 is set to a 0. Read only bits
D4 and D3 are revision control and the value indi-
cates the status code of the device (ie. 01 is status
code 1).
If the Watchdog times out RESET# will be driven low until
tPRTO at which time it will return high. Refer to Figure 4
which illustrates the action of RESET# with respect to the
Watchdog timer and the WLDI input.
D0
LSB
D2
D1
Action
OFF
WD2
WD1 WD0
IfWLDIisheldlowthetimerwillfree-rungeneratingaseries
of resets.
0
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
D7
D4
400ms
800ms
1600ms
3200ms
6400ms
D6
D5
MSB
LSB
Action
V3
V2
0
V1
0
V0
0
0
Reading a 1 indicates a
supply fault
1
1
1
1
Table 6. Configuration Register 6 (D0, D1, D2)
Table 4. Configuration Register 5 (D4 through D7)
The delay from VPTH0 until PUP#1 low is tPDLY1. There is
a similar tPDLYX delay for V1 to PUP#2 and for V2 to
PUP#3. Theyareprogrammedinregister7. Cascadingwill
always occur as indicated in the flow chart (Figure 7).
WhentheWatchdogtimesoutRESET#willbegenerated.
WhenRESET#returnshigh(aftertPRTO)thetimerisreset
to time zero.
Register6isalsousedtosettheprogrammableresettime-
out period (tPRTO) and to select the cascade option.
CascadeDelayProgramming
Thecascadedelaysareprogrammedinregister7. Bit7of
register6mustbesettoa0inordertoenablethecascading
of the PUP# outputs. Cascading will not commence until
V0 is above its programmed threshold.
EachPUP#(-3,-2and-1)isdelayedaccordingtothestates
ofitsBit1andBit0asindicatedinTable9. RefertoFigures
1 and 5 for the detailed timing relationship of the program-
mablepower-oncascading.
SUMMIT MICROELECTRONICS, Inc.
2087 1.0 04/11/05
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SMS47
PreliminaryInformation
CONFIGURATION REGISTERS (CONTINUED)
D0
LSB
D7
D6
D5
D4
D3
PUP#2
Bit 1 Bit 0
D2
D1
MSB
PUP#3
PUP#1
Action
Bit 1
Bit 0
Bit 1
Bit 0
2047 Table08 3.0
Lock AS0
Table 8. Configuration Register 7 (D5 through D0)
x
0
1
x
x
x
Config. Reg. Read/Write enabled
Config. Reg. Read/Write locked out 1
Bit 1
Bit 0
tPDLYX
0
0
1
1
0
1
0
1
0ms (no) Delay
25ms Delay
50ms Delay
100ms Delay
Note 1 - Setting this bit will cause a permanent Read/Write Lock out.
Table 7. Configuration Register 7 (D7, D6)
2047 Table09 1.0
Table 9. PUP Delays, Configuration Register 7
DEVELOPMENT HARDWARE & SOFTWARE
SMX3200 PROGRAMMER
TheendusercanusethesummitSMX3200programming
cable and software that have been developed to operate
with a standard personal computer. The programming
cable interfaces directly between a PC’s parallel port and
TheWindowsGUIsoftwarewillgeneratethedataandsend
it in I2C serial bus format so that it can be directly
downloaded to the SMS47 via the programming Dongle
and cable. An example of the connection interface is
shown in Figure 8.
thetargetapplication. Theapplication’svaluesareentered
via an intuitive graphical user interface employing drop-
downmenus.
When design prototyping is complete, the software can
generate a HEX data file that should be transmitted to
Summit for approval. Summit will then assign a unique
customer ID to the HEX code and program production
devicesbeforethefinalelectricaltestoperations. Thiswill
Thelatestrevisionsofallsoftwareandanapplicationbrief
describing the SMX3200 is available from the website
(www.summitmicro.com).
ensure proper device operation in the end application.
Top view of straight 0.1" x 0.1 closed-side
connector. SMX3200 interface cable connector.
D1
Pin 10, Reserved
Pin 8, Reserved
Pin 6, MR#
Pin 9, 5V
Pin 7, 10V
1N4148
Pin 5, Reserved
Pin 3, GND
Pin 1, GND
Pin 4, SDA
VDD_CAP
Pin 2, SCL
10
9
7
5
3
1
8
C1
0.1µF
SMS47
6
MR#
4
2
SDA
SCL
GND
Figure 8. SMX3200 Programmer I2C serial bus connections to program the SMS47.
SUMMIT MICROELECTRONICS, Inc.
2087 1.1 04/11/05
12
SMS47
PreliminaryInformation
2
I C PROGRAMMING INFORMATION
InputDataProtocol
CONFIGURATION REGISTER OPERATION
The protocol defines any device that sends data onto the
bus as a transmitter and any device that receives data as
a receiver. The device controlling data transmission is
called the Master and the controlled device is called the
Slave. InallcasestheSMS47willbeaSlavedevice,since
it never initiates any data transfers.
Data for the configuration registers is read and written via
theI2Cindustrystandardtwo-wireinterface. Thebuswas
designed for two-way, two-line serial communication be-
tween different integrated circuits. The two lines are a
serial data line (SDA) and a serial clock line (SCL). The
SDA line must be connected to a positive supply by a pull-
upresistor,locatedsomewhere onthebus. See Operating
Characteristics: Table 10 and Figure 9 below.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time because changes on the data line while SCL is high
will be interpreted as start or stop condition.
Symbol
fSCL
Parameter
SCL clock frequency
Clock low period
Conditions
MIN
0
TYP
MAX
Units
kHz
µs
100
tLOW
tHIGH
tBUF
4.7
4.0
4.7
4.7
4.0
4.7
0.2
0.2
Clock high period
µs
Bus free time (1)
Before new transmission
µs
tSU:STA
tHD:STA
tSU:STO
tAA
Start condition setup time
Start condition hold time
Stop condition setup time
Clock edge to valid output
Data Out hold time
µs
µs
µs
SCL low to valid SDA (cycle n)
3.5
µs
tDH
SCL low (cycle n+1) to SDA change
µs
tR
SCL and SDA rise time (1)
SCL and SDA fall time (1)
Data In setup time
1000
300
ns
tF
ns
tSU:DAT
tHD:DAT
TI
250
0
ns
Data In hold time
ns
Noise filter SCL and SDA
Write cycle time
Noise suppression
100
ns
tWR
5
ms
Note (1): These values are guaranteed by design.
Table 10. I2C Operating Characteristics
t
t
LOW
HIGH
t
t
R
F
SCL
t
t
t
t
SU:STO
t
HD:DAT
SU:STA
SU:DAT
HD:STA
t
BUF
SDA In
t
t
AA
DH
SDA Out
2047 Fig09
Figure 9. I2C Operating Characteristics
SUMMIT MICROELECTRONICS, Inc.
2087 1.0 04/11/05
13
SMS47
PreliminaryInformation
2
I C PROGRAMMING INFORMATION (CONTINUED)
START and STOP Conditions
Whenboththedataandclocklinesarehighthebusissaid
D7
D0
D6
D5
D4
D3
D2
D1
to be not busy. A high-to-low transition on the data line,
MSB
LSB
while the clock is high, is defined as the Start condition.
A low-to-high transition on the data line, while the clock
is high, is defined as the Stop condition. See Figure 10.
Address Bits
Device Type
SMS47
Bus
MSB R/W
x
x
x
x
1
0
0
1
Configuration Register
START
STOP
Condition
Condition
2047 Table11 1.0
Table 11. Slave Addresses
Read/WriteBit
SCL
SDA In
The last bit of the data stream defines the operation to be
performed. When set to 1 a Read operation is selected;
when set to 0 a Write operation is selected.
2047 Fig10
Figure 10. START and STOP Conditions
WRITE OPERATIONS
The SMS47 uses byte Write operations. A byte Write
operation writes a single byte during the nonvolatile write
period(tWR).
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device,
either the Master or the Slave, will release the bus after
transmitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line low to Acknowledge that it
received the eight bits of data. The Master will leave the
SDA line high (NACK) when it terminates a read function.
ByteWrite
AftertheSlaveaddressissent(toidentifytheSlavedevice
andselecteitheraReadorWriteoperation),asecondbyte
is transmitted which contains the low order 8 bit address
of any one of the 256 words in the array. Upon receipt of
the word address the SMS47 responds with an Acknowl-
edge. After receiving the next byte of data it again
responds with an Acknowledge. The Master then termi-
natesthetransferbygeneratingaStopcondition,atwhich
timetheSMS47beginstheinternalWritecycle. Whilethe
internal Write cycle is in progress the SMS47 inputs are
disabled and the device will not respond to any requests
from the Master.
TheSMS47willrespondwithanAcknowledgeafterrecog-
nitionofaStartconditionanditsslaveaddressbyte. Ifboth
the device and a write operation are selected the SMS47
willrespondwithanAcknowledgeafterthereceiptofeach
subsequent 8-Bit word. In the READ mode the SMS47
transmitseightbitsofdata,thenreleasestheSDAline,and
monitorsthelineforanAcknowledgesignal. IfanAcknowl-
edgeisdetectedandnoStopconditionisgeneratedbythe
Master, the SMS47 will continue to transmit data. If a
NACK is detected the SMS47 will terminate further data
transmissionsandawaitaStopconditionbeforereturning
to the standby power mode.
AcknowledgePolling
WhentheSMS47isperforminganinternalWriteoperation
itwillignoreanynewStartconditions. Sincethedevicewill
only return an acknowledge after it accepts the Start the
part can be continuously queried until an acknowledge is
issued,indicatingthattheinternalWritecycleiscomplete.
Seetheflowchartforthepropersequenceofoperationsfor
polling.
Device Addressing
Following a Start condition the Master must output the
address of the Slave it is accessing. The most significant
four bits of the Slave address are the device type
identifier/address. For the SMS47 the default is 1001BIN
.
The next two bits are the Bus Address. The next bit (the
7th) is the MSB of the configuration register address.
SUMMIT MICROELECTRONICS, Inc.
2087 1.1 04/11/05
14
SMS47
PreliminaryInformation
2
I C PROGRAMMING INFORMATION (CONTINUED)
READ OPERATIONS
Write Cycle
In Progress
Read operations are initiated with the R/W bit of the
identification field set to 1. There are two different Read
options: 1. Current Address Byte Read, and 2. Random
Address Byte Read.
Issue Start
Issue Stop
RandomAddressRead
Issue Slave
Address and
R/W = 0
Random address Read operations allow the Master to
access any register location in a random fashion. This
operation involves a two-step process. First, the Master
issuesawritecommandwhichincludesthestartcondition
and the Slave address field (with the R/W bit set to Write),
followed by the address of the word it is to Read. This
proceduresetstheinternaladdresscounteroftheSMS47
to the desired address. After the word address acknowl-
edge is received by the Master it immediately reissues a
Start condition, followed by another Slave address field
withtheR/WbitsettoREAD. TheSMS47willrespondwith
anAcknowledgeandthentransmitthe8databitsstoredat
the addressed location. At this point the Master sets the
SDA line to NACK and generates a Stop condition. The
SMS47 discontinues data transmission and reverts to its
standbypowermode.
No
ACK
Returned
Yes
Next
Operation
a Write?
No
Yes
Issue Stop
Issue
Address
Proceed
With
Write
Await
Next
Command
Figure 12. Write Flow Chart
S
S
T
O
P
T
Writing Configuration Registers
A
Master
R
T
R
/
W
B B
A A
D D D D D D D D
C C C C C C C C
SDA
X
0 1
1 0
7
6 5 4 3 2 1 0
7
6
5
4
3
2
1
0
2
1
A
C
K
A
C
K
A
C
K
Slave
S
T
A
R
T
S
T
A
R
T
N
A
C
K
S
T
O
P
A
C
K
Reading the Configuration Register
Master
SDA
B B
A A
R
B B
A A
R
/
W
D D D D D D D D
C C C C C C C C
X
/
X
0 1
1 0
0 1
1 0
7
6 5 4 3 2 1 0
7
6 5 4 3 2 1 0
2
1
W
2
1
A
C
K
A
C
K
Slave
Figure 11. Read and Write Operations
SUMMIT MICROELECTRONICS, Inc.
2087 1.0 04/11/05
15
SMS47
PreliminaryInformation
APPLICATIONS
MR#
VDD_CAP
VDD_CAP
D6
DIODE
J1
1
3
5
7
9
2
Gnd
SCL
SDA
MR#
4
R4
Gnd3
Rsrv5
6
10K
8
+10V Rsrv 8
+5V Rsrv 10
10
RESET#
WLDI
I2C SMX3200
VDD_CAP
U1
R2
10K
R1
R3
10K
10K
16
4
PUP#1
PUP#2
PUP#3
V0
V0
V1
V2
V3
PUP#1
PUP#2
PUP#3
2
3
5
SMS47
V1
13
V2
V3
14
C1
C2
C3
C4
VDD_CAP
0.01uF 0.01uF 0.01uF 0.01uF
0.1uF
C5
Figure 13. Typical applications schematic, the SMX3200 programmer has internal SDA and SCL pull-up
resistors.
SUMMIT MICROELECTRONICS, Inc.
2087 1.1 04/11/05
16
SMS47
PreliminaryInformation
DEFAULT CONFIGURATION REGISTER SETTINGS - SMS47GC-359
Register
Contents
Function
R00
56
V0 threshold set to 3.090V
R01
R02
28
V1 threshold set to 2.400V
V2 threshold set to 1.400V
A0
R03
R04
14
F3
V3 threshold set to 0.700V
Reset Trigger source set for all channels, V0, V1 set to high range and V2, V3
set to low range
R05
R06
R07
X0
4D
6A
Upper bits are volatile status indication of input supply condition. V0, V1, V2
and V3 set to m onitor UV Under Voltage.
Reset tim eout set to 100m s, W atchdog Tim er set to 1.6s. Bits D4 and D3
indicate revision control.
Configuration registers are unlocked, cascading delays are all 50m s
The default device ordering number is SMS47GC-359, is programmed as described above and tested
over the commercial temperature range.
SUMMIT MICROELECTRONICS, Inc.
2087 1.0 04/11/05
17
SMS47
PreliminaryInformation
PACKAGE
16 PIN SSOP PACKAGE
0.189 - 0.197
(4.80 - 5.00)
Ref. JEDEC MO-137
0.228 - 0.244
(5.79 - 6.20)
Pin 1
Inches
(Millimeters)
0.150 - 0.157
(3.81 - 3.99)
0.053 - 0.069
(1.35 - 1.75)
0.059
MAX
(1.50)
0.007 - 0.010
(0.18 - 0.25)
0” Min to
8” Max
0.016 - 0.050
(0.41 - 1.27)
0.004 - 0.010
(0.10 - 0.25)
0.025
0.008 - 0.012
(0.20 - 0.31)
(0.635)
16 Pin SSOP
SUMMIT MICROELECTRONICS, Inc.
2087 1.1 04/11/05
18
SMS47
PreliminaryInformation
PART MARKING
Summit Part Number
SUMMIT
SMS47G
Status Tracking Code
(Blank, MS, ES, 01, 02,...)
(Summit Use)
xx
AYYWW
Annn
Pin 1
Identifier
Date Code (YYWW)
Lot tracking code (Summit use)
Part Number suffix
(Contains Customer specific ordering requirements)
Product Tracking Code (Summit use)
Drawing not to scale
ORDERING INFORMATION
S M S 4 7
G
C
n n n
P a rt N u m b e r S u ffix (s e e p a g e 1 7 )
S p e c ific re q u ire m e n ts a re c o n ta in e d in th e
S u m m it P a rt
N u m b e r
s u ffix s u c h a s H e x c o d e , H e x c o d e re v is io n , e tc .
P a c k a g e
G = 1 6 L e a d S S O P
T e m p R a n g e
C = C o m m e rc ia l
B la n k = In d u s tria l
NOTICE
NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited
characterization.
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,
performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license
under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained
herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this
publicationhasbeencarefullychecked,SUMMITMicroelectronics,Inc.shallnotbeliableforanydamagesarisingasaresultofanyerrororomission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or
malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness.
Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction,
that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics,
Inc. is adequately protected under the circumstances.
Revision 1.1 - This document supersedes all previous versions. Please check the Summit Microelectronics, Inc. web site at
www.summitmicro.com for data sheet updates.
© Copyright 2005 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLEANALOGFORADIGITALWORLD™
2
I C is a trademark of Philips Corporation.
SUMMIT MICROELECTRONICS, Inc.
2087 1.0 04/11/05
19
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