HV513K7-GM935 [SUPERTEX]
8-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs, POL, Hi-Z, and Short Circuit Detect;
| 型号： | HV513K7-GM935 |
| 厂家： | 
Supertex, Inc |
| 描述： | 8-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs, POL, Hi-Z, and Short Circuit Detect 驱动 接口集成电路 |
| 文件： | 总10页 (文件大小：1028K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supertex inc.
HV513
8-Channel Serial to Parallel Converter with High Voltage
Push-Pull Outputs, POL, Hi-Z, and Short Circuit Detect
Features
General Description
► HVCMOS® technology
The HV513 is a low voltage serial to high voltage parallel converter
with 8 high voltage push-pull outputs. This device has been designed
to drive small capacitve loads such as piezoelectric transducers. It can
also be used in any application requiring multiple high voltage outputs,
with medium current source and sink capabilities.
► Operating output voltage of 250V
► Low power level shifting from 5.0 to 250V
► Shift register speed 8.0MHz @ VDD = 5.0V
► 8 latch data outputs
► Output polarity and blanking
► Output short circuit detect
The device consists of an 8-bit shift register, 8 latches, and control logic
to perform the polarity select and blanking of the outputs. Data is shifted
through the shift register on the low to high transition of the clock.Adata
output buffer is provided for cascading devices. Operation of the shift
register is not affected by the LE, BL, POL, or the HI-Z control inputs.
Transfer of data from the shift register to the latch occurs when the LE
is high. The data in the latch is stored when LE is low. A high-Z (HI-Z)
pin is provided to set all the outputs in a high-Z state.
► Output high-Z control
► CMOS compatible inputs
Applications
► Piezoelectric transducer driver
► Braille driver
► Weaving applications
► Printer drivers
► MEMs
All outputs have short circuit protection that detects if the outputs have
reached the required output state. If output does not track the required
state, then the SHORT pin will be low. This output will pulse low during
the output transistion period under normal operation; see SC Timing
Diagram for details.
► Displays
All outputs will have a break-before-make circuitry to reduce cross-over
current during output state changes.
The POL, BL, LE, and HI-Z inputs have an internal pull up resistor.
Typical Application Circuit
Low Voltage
High Voltage
Power Supply
Power Supply
HVOUT
1
DIN
CLK
High Voltage
Low Voltage
LE
BL
Level
Translators
&
Push-Pull
Output
Buffers
FPGA
Shift Register
Latches
8
/
POL
HiZ
Output
Controller
HVOUT
8
DOUT
Piezo
SHORT
Element
DIN
Supertex HV513
to the next HV513 for cascading
Doc.# DSFP-HV513
C072413
Supertex inc.
www.supertex.com
HV513
Pin Configuration
Ordering Information
Part Number
Package
Packing
400/Tray
2000/Reel
1000/Reel
1
24
32
HV513K7-G
32-Lead QFN
32-Lead QFN
24-Lead SOW
HV513K7-G M935
HV513WG-G
1
-G denotes a lead (Pb)-free / RoHS compliant package
Absolute Maximum Ratings
Parameter
Value
Logic supply, VDD
-0.5V to 6.0V
VDD to 275V
-0.5V to VDD +0.5V
0.3A
32-Lead QFN
24-Lead SOW
High voltage supply, VPP
(top view)
(top view)
Logic input levels
Ground current1
Product Marking
L = Lot Number
High voltage supply current1
Continuous total power dissipation2
Operating junction temperature
Storage temperature range
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect device
reliability. All voltages are referenced to device ground.
0.25A
HV513
LLLLLL
YYWW
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
750mW
-40°C to +85°C
AAACCC
C = Country of Origin
= “Green” Packaging
-65°C to +150°C
Package may or may not include the following marks: Si or
32-Lead QFN
Top Marking
YY = Year Sealed
Notes:
YYWW AAA
1. Connection to all power and ground pads is required. Duty cycle is limited
by the total power dissipated in the package.
2. For operation above 25°C ambient derate linearly to 85°C at 12mW/°C.
WW = Week Sealed
HV513WG
LLLLLLLLLL
A = Assembler ID
L = Lot Number
Bottom Marking
C = Country of Origin*
Typical Thermal Resistance
CCCCCCCCCCC
= “Green” Packaging
*May be part of top marking
Package
θja
Package may or may not include the following marks: Si or
32-Lead QFN
24-Lead SOW
22OC/W
44OC/W
24-Lead SOW
Typical Operating Conditions
Sym
VDD
VPP
VIH
Parameter
Min
4.5
Typ Max Units Conditions
Logic supply voltage
High voltage supply
High-level input voltage
Low-level input voltage
Operating junction temperature
5.0
5.5
250
VDD
0.9
V
V
---
50
-
-
-
-
Note 1
---
VDD -0.9
0
V
VIL
V
---
TJ
-40
+85
°C
---
Notes:
1. Below minimum VPP the output may not switch.
2. Power-up sequence should be the following:
1. Connect ground
2. Apply VDD
3. Set all inputs (Data, CLK, Enable, etc.) to a known state
4. Apply VPP
Power-down sequence should be the reverse of the above
Doc.# DSFP-HV513
C072413
Supertex inc.
www.supertex.com
2
HV513
DC Electrical Characteristics (Over typical operating conditions unless otherwise specified, TJ = 25OC)
Sym
Parameter
Min
Typ Max Units Conditions
IDD
VDD supply current
-
-
-
-
-
-
4.0
0.1
2.0
mA
fCLK = 8.0Hz, LE = Low
All VIN = VDD
All VIN = 0V
IDDQ
Quiescent VDD supply current
VPP supply current
mA
VPP = 250V, fOUT = 300Hz,
no load
IPP
-
-
100
µA
IPPQ
IIH
Quiescent VPP supply current
High-level logic input current
-
-
-
-
-
100
10
µA
µA
VPP = 240V, outputs are static
VIH = VDD
VIL = 0V
-10
IIL
Low-level logic input current
µA
VIL = 0V,
for inputs w/pull-up resistors
-
-
-350
HVOUT
140
-
-
-
-
-
-
VPP = 200V, IHVOUT = -20mA
IDOUT = -0.1mA
VOH
VOL
High level output
V
V
Data out
VDD -1.0V
HVOUT
-
-
60
1.0
VDD = 4.5V, IHVOUT = 20mA
IDOUT = 0.1mA
Low level output
Data out
AC Electrical Characteristics (Over typical operating conditions unless otherwise specified, TJ = 25OC)
Sym
Parameter
Min
Typ Max Units Conditions
fCLK
Clock frequency
0
-
8.0
-
MHz ---
Output switching frequency
(SOA limited)
fOUT
-
300
Hz
CL = 50nF, VPP = 200V
tW
tSU
Clock width high and low
62
15
30
80
35
40
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
---
Data setup time before clock rises
Data hold time after clock rises
Width of latch enable pulse
-
-
---
tH
---
tWLE
tDLE
tSLE
-
---
LE delay time after rising edge of clock
LE setup time before rising edge of clock
-
---
-
---
tOR, tOF HVOUT rise/fall time
1000
500
110
110
5.0
CL = 100nF, VPP = 200V
td ON/OFF Delay time for output to start rise/fall
-
---
tDHL
tDLH
Delay time clock to DOUT high to low
Delay time clock to DOUT low to high
All logic inputs
-
CL = 15pF
CL = 15pF
---
-
tR, tF
-
CL = 15pF,
Short to output fall of SHORT
tSD
Output short circuit detection
-
-
500
ns
Short clear to output rise of
SHORT
tSC
Output short circuit clear
Output HI-Z state
-
-
-
-
3000
500
ns
ns
tHI-Z
---
Doc.# DSFP-HV513
C072413
Supertex inc.
www.supertex.com
3
HV513
Input and Output Equivalent Circuits
VDD
VDD
VPP
DATA OUT
HVGND
20kΩ*
HVOUT
INPUT
GND
GND
High Voltage Outputs
Logic Data Output
Logic Inputs
Short Circuit Detect Detail Timing
LE
VH
POL
VL
BL
VIH
HI-Z
VIL
tHi-Z
VOH
Within
xV of rail
HVOUT
VOL
tSD
tSC
Short
VH
VL
Detect
Note:
For VPP greater than 150V:
Short detect output will flag short conditions
- HVOUT is higher than 10V when expected low
- HVOUT is lower than VPP - 100V when expected high
Short detect output will stay clear
- HVOUT is lower than 2.0V when expected low
- HVOUT is higher than VPP - 60V when expected high
Doc.# DSFP-HV513
C072413
Supertex inc.
www.supertex.com
4
HV513
Switching Waveforms
VIH
VIL
Data Valid
50%
50%
DATA INPUT
50%
tSU
tH
VIH
VIL
CLK
50%
50%
50%
tWH
tWL
VOH
VOL
50%
50%
tDLH
DATA OUT
VOH
VOL
VIH
tDHL
50%
50%
LE
VIL
tWLE
tSLE
tDLE
VOH
VOL
90%
10%
HVOUT
w/S/R Low
td(OFF)
tOR
90%
tOR
VOH
VOL
HV
w/S/R HiOgUhT
10%
td(ON)
Doc.# DSFP-HV513
C072413
Supertex inc.
www.supertex.com
5
HV513
Functional Block Diagram
POL
BL
VPP
LE
HVOUT
1
L/T
L/T
DIN
•
•
•
CLK
8-Bit
Static
Shift
8 Latches
6 Additional
Outputs
Register
•
•
•
HVOUT8
DOUT
HI-Z
Short Detect
Short
Note:
POL, BL, LE, and Hi-Z have internal 20kΩ pull-up resistors.
Function Table
Inputs
Outputs
HV Outputs
Function
Shift Reg
Data Out
Data
CLK
LE
BL
POL
HI-Z
1
2...8
1
2...8
●
All on
All off
X
X
X
X
↑
X
X
L
L
L
L
H
L
H
H
H
●
●
●
●...●
●...●
●...●
H
L
H...H
L...L
●
●
●
●
●
●
●
●
X
Invert mode
Load S/R
X
H
H
H
H
H
H
●
●...● (b)
●...●
H OR L
L
H
H
L
H
H
H
H
H
H or L ●...●
●
●
X
X
L
X
X
↑
L
●
●
L
●...●
●...●
●...●
●...●
●...●
Store data in
latches
L
●
●...● (b)
●...●
H
H
H
H
L
Transparent
mode
H
↑
H
H
●...●
High impedence
outputs
Outputs High-Z
X
X
X
X
X
X
X
X
X
X
L
●
●
●...●
●...●
●
●
Outputs on
H
●
●...●
Notes:
H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition
● = dependent on previous stage’s state before the last CLK or last LE high.
Doc.# DSFP-HV513
C072413
Supertex inc.
www.supertex.com
6
HV513
Pin Description - 32-Lead QFN
Pin # Function Description
1
2
NC
No internal connection
Low voltage ground
3
4
LGND
5
HVGND High voltage ground
6
7
NC
No internal connection
8
9
HVOUT1
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
2
3
4
5
6
7
8
NC
No internal connection
High voltage supply
VPP
VDD
Logic supply voltage
Data output
DOUT
NC
No internal connection
BL
NC
Blanking pin, logic input low sets all HVOUTS low
No internal connection
POL
CLK
LE
Polarity bar input logic
Clock pin, shift registers shifts data on rising edge of input clock
Latch enable bar input logic
SHORT
HI-Z
DIN
If output does not reach its required state, SHORT pin will output logic low
High impedance pin, logic input low sets all outputs in a high impedance state
Data input
Center
Pad
VPP
Center pad is at VPP potential. Connect to VPP or leave floating.
Doc.# DSFP-HV513
C072413
Supertex inc.
www.supertex.com
7
HV513
Pin Description - 24-Lead SOW
Pin #
1
Function
NC
Description
No internal connection
2
VDD
DOUT
BL
Logic supply voltage
3
Data output
4
Blanking pin, logic input LOW sets all HVOUTS low
Polarity bar input logic
5
POL
CLK
6
Clock pin, shift registers shifts data on rising edge of input clock
Latch enable bar input logic
7
LE
8
SHORT
HI-Z
If output does not reach its required state, SHORT pin will output logic LOW
High impedance pin, logic input LOW sets all outputs in a high impedance state
Data input
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DIN
LGND
NC
Low voltage ground
No internal connection
HVGND
High voltage ground
HVOUT1
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
2
3
4
5
6
7
8
VPP
High voltage supply
Doc.# DSFP-HV513
C072413
Supertex inc.
www.supertex.com
8
HV513
32-Lead QFN Package Outline (K7)
6.00x6.00mm body, 0.80mm height (max), 0.50mm pitch
Detail Bx32
L1
D1
D
25
32
32
L1
Detail C
(note 2)
e1
1
1
24
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
7 x e
E1
E
e
17
8
e1
L1
Detail Ax3
(note 2)
9
16
7 x e
e2
e2
L1
Bottom View
Top View
LC1
b
LC
Seating
Plane
A
LC
LC
L
0.30x45O
A1
Side View
Detail A
Detail B
Detail C
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. The 4 corner pads are for mechanical placement only, they are not internally connected.
Symbol
A
A1
0.00
-
b
D
D1
E
E1
e
e1
e2
L
L1
LC
LC1
0.25
0.35
0.45
MIN
0.70
0.20
0.30
0.40
5.90
6.00
6.10
3.20
3.30
3.40
5.90
6.00
6.10
4.30
4.40
4.50
0.20
0.30
0.40
0.20
0.30
0.40
Dimension
(mm)
0.50
BSC
1.00 0.975
REF REF
0.10
REF
NOM 0.75
MAX 0.80
0.05
Drawings not to scale.
Supertex Doc. #: DSPD-32QFNK76X6P050, Version B092309.
Doc.# DSFP-HV513
C072413
Supertex inc.
www.supertex.com
9
HV513
24-Lead SOW (Wide Body) Package Outline (WG)
15.40x7.50 body, 2.65mm height (max), 1.27mm pitch
D
24
θ1
E1 E
Note 1
Gauge
(Index Area
Plane
L2
θ
0.25D x 0.75E1)
L
L1
Seating
Plane
e
1
b
Top View
View B
View B
Note 1
h
A
h
A2
A
Seating
Plane
A1
A
Side View
View A-A
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
A
A1
MIN 2.15* 0.10 2.05 0.31 15.20* 9.97* 7.40*
NOM 15.40 10.30 7.50
MAX 2.65 0.30 2.55* 0.51 15.60* 10.63* 7.60*
A2
b
D
E
E1
e
h
L
L1
L2
θ
0O
-
θ1
5O
-
0.25 0.40
Dimension
(mm)
1.27
BSC
1.40 0.25
REF BSC
-
-
-
-
-
-
0.75 1.27
8O 15O
JEDEC Registration MS-013, Variation AD, Issue E, Sep. 2005.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-24SOWWG, Version E041309.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-HV513
C072413
10
相关型号：
HV513WG-G
8-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs, POL, Hi-Z, and Short Circuit Detect
SUPERTEX
HV513_13
8-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs, POL, Hi-Z, and Short Circuit Detect
SUPERTEX
HV514WG-G
Buffer/Inverter Based Peripheral Driver, PDSO20, 12.80 X 7.50 MM, 2.65 MM HEIGHT, 1.27 MM PITCH, GREEN, MS-013AC, SOW-20
SUPERTEX
©2020 ICPDF网 联系我们和版权申明