HV5530PJ-GM903 [SUPERTEX]
32-Channel Serial to Parallel Converter With Open Drain Outputs;
| 型号： | HV5530PJ-GM903 |
| 厂家： | 
Supertex, Inc |
| 描述： | 32-Channel Serial to Parallel Converter With Open Drain Outputs |
| 文件： | 总8页 (文件大小：798K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV5530
Supertex inc.
32-Channel Serial to Parallel Converter
With Open Drain Outputs
Features
General Description
► Processed with HVCMOS® technology
► Sink current minimum 100mA
► Shift register speed 8.0MHz
► Polarity and Blanking inputs
► CMOS compatible inputs
The HV5530 is a low-voltage serial to high-voltage parallel
converter with open drain outputs. This device has been designed
for use as a driver for AC-electroluminescent displays. It can also
be used in any application requiring multiple output high voltage
current sinking capabilities such as driving inkjet and electrostatic
print heads, plasma panels, vacuum fluorescent, or large matrix
LCD displays.
► Forward and reverse shifting options
► Diode to VPP allows efficient power recovery
This device consists of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the
outputs. Data is shifted through the shift register on the high to low
transition of the clock. The HV5530 shifts in the counter clockwise
direction when viewed from the top of the package. A data output
buffer is provided for cascading devices. This output reflects the
current status of the last bit of the shift register. Operation of the
shift register is not affected by the LE (latch enable), BL (blanking),
or the POL (polarity) inputs. Transfer of data from the shift register
to the latch occurs when the LE (latch enable) input is high. The
data in the latch is stored when LE is low.
Functional Block Diagram
POL
BL
LE
HVOUT1
DATA
Latch
IN
HVOUT
2
CLK
Latch
32-Bit
Shift
Register
(Outputs 3 to 30 not shown)
HVOUT31
Latch
Latch
HVOUT32
DATA
OUT
Doc.# DSFP-HV5530
C072313
Supertex inc.
www.supertex.com
HV5530
Pin Configuration
Ordering Information
Part Number
Package
Packing
96/Tray
HV5530PG-G
44-Lead PQFP
HV5530PG-G M919 44-Lead PQFP
HV5530PJ-G 44-Lead PLCC
500/Reel
27/Tube
500/Reel
HV5530PJ-G M903 44-Lead PLCC
44
1
-G denotes a lead (Pb)-free / RoHS compliant package
44-Lead PQFP
(top view)
Absolute Maximum Ratings
Parameter
Value
6
40
1 44
1
Supply voltage, VDD
-0.5V to +15V
-0.5V to +315V
-0.5V to VDD +0.5V
1.5A
1
Output voltage, VPP
Logic input levels1
Ground current2
Continuous total power dissipation3
Operating temperature range
Storage temperature range
1200mW
44-Lead PLCC
(top view)
-40OC to +85OC
-65OC to +150OC
Product Marking
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device at
the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Top Marking
YYWW
HV5530PG
LLLLLLLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
Notes:
1. All voltages are referenced to VSS
2. Duty cycle is limited by the total power dissipated in the package
3. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20mW/°C.
C = Country of Origin*
A = Assembler ID*
Bottom Marking
CCCCCCCC
AAA
= “Green” Packaging
*May be part of top marking
Recommended Operating Conditions
Package may or may not include the following marks: Si or
Sym Parameter
Min
10.8
-0.3
Max Units
44-Lead PQFP
VDD Logic voltage supply
HVOUT High voltage output
13.2
V
V
Top Marking
YY = Year Sealed
+300
YYWW AAA
HV5530PJ
LLLLLLLLLL
WW = Week Sealed
L = Lot Number
VIH
VIL
Input high voltage
Input low voltage
VDD -2.0 VDD
V
A = Assembler ID
Bottom Marking
0
-
2.0
8.0
V
C = Country of Origin*
= “Green” Packaging
fCLK Clock frequency
MHz
OC
CCCCCCCCCCC
*May be part of top marking
TA
Operating free-air temperature
-40
+85
Package may or may not include the following marks: Si or
44-Lead PLCC
Power-Up Sequence
Power-up sequence should be the following:
1. Connect ground
Typical Thermal Resistance
2. Apply VDD
3. Set all inputs to a known state
Package
θja
44-Lead PQFP
44-Lead PLCC
51OC/W
37OC/W
Power-down sequence should be the reverse of the above.
Doc.# DSFP-HV5530
C072313
Supertex inc.
www.supertex.com
2
HV5530
Electrical Characteristics (over recommended operating conditions unless otherwise noted)
DC Characteristics
Sym
Parameter
Min
Max Units Conditions
IDD
VDD supply current
-
15
100
10
mA fCLK = 8.0MHz, FDATA = 4.0MHz
IDDQ
IO(OFF)
IIH
VDD supply current (quiescent)
Off state output current
High-level logic input current
Low-level logic input current
High-level output data out
-
µA
µA
µA
µA
V
VIN = 0V
-
All outputs high, all SWS parallel
VIH = VDD
-
1.0
-1.0
-
IIL
-
VIL = 0V
VOH
VDD -1.0V
IDOUT = -100µA
IHVOUT = +100mA
IDOUT = +100µA
IOL = -100mA
HVOUT
DATA OUT
-
-
-
15
V
VOL
VOC
Low-level output voltage
1.0
-1.5
V
HVOUT clamp voltage
V
AC Characteristics (VDD = 12V, TC = 25OC)
Sym
fCLK
tW
Parameter
Min
-
Max Units Conditions
Clock frequency
Clock width, high or low
8.0
MHz ---
62
25
10
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
---
tSU
Data set-up time before CLK falls
Data hold time after CLK falls
Turn-on time, HVOUT from enable
Delay time clock to data high to low
Delay time clock to data low to high
Delay time clock to LE low to high
Width of LE pulse
-
---
tH
-
500
100
100
-
---
tON
RL = 2.0KΩ to VPP max.
tDHL
tDLH
tDLE
tWLE
tSLE
-
CL = 15pF
-
CL = 15pF
50
50
50
---
---
---
-
LE setup time before clock falls
-
Input and Output Equivalent Circuits
VDD
VDD
HVOUT
DATA
OUT
DATA
IN
HVIN
VSS
VSS
VSS
High Voltage Outputs
Logic Data Output
Logic Inputs
Doc.# DSFP-HV5530
C072313
Supertex inc.
www.supertex.com
3
HV5530
Switching Waveforms
VIH
VIL
VIH
DATA
50%
Data Valid
50%
50%
IN
tSU
tH
CLK
50%
50%
50%
VIL
tWH
tWL
VOH
VOL
50%
DATA
OUT
tDLH
VOH
VOL
50%
tDHL
VIH
VIL
50%
50%
LE
tWLE
tSLE
tDLE
VOH
VOL
HVOUT
w/ S/R HIGH
10%
tON
Functional Table
Inputs
LE
Outputs
HV Outputs
Function
Shift Reg
Data Out
*
Data
CLK
BL
POL
1
*
2...32
*...*
*...*
*...*
*...*
*...*
*...*
*...*
*...*
1
2...32
On...On
Off...Off
*...*
All on
All off
X
X
X
X
L
L
L
L
H
L
On
Off
*
*
*
*
*
*
*
*
*
X
X
*
Invert mode
Load S/R
X
X
H
H
H
H
H
H
*
H or L
↓
H or L
H or L
↓
L
H
H
L
H or L
*
*...*
X
X
L
↑
*
*
*
*...*
Load latches
↑
*
*...*
H
H
H
H
L
H
Off
On
*...*
Transparent latch
mode
H
↓
*...*
Notes:
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion.
dependent on previous stage’s state before the last CLK ↓ or last LE high.
*
Doc.# DSFP-HV5530
C072313
Supertex inc.
www.supertex.com
4
HV5530
44-Lead PQFP Pin Description
Pin #
Function
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
HVOUT32
DATA OUTPUT
N/C
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
High voltage outputs.
Data output pin.
No connect.
N/C
N/C
POL
Inverts the polarity of the HVOUT pins
CLK
Clock pin, shift registers shifts data on falling edge of input clock.
Reference voltage, usually ground.
VSS
VDD
Logic supply voltage.
LE
Latch enable pin, data is shifted from shift register to latches on logic input high.
Data input pin.
DATA INPUT
Blanking pin sets all HVOUT pins low or high depending upon state of polarity.
See function table.
33
BL
34
35
36
37
38
39
40
41
42
43
44
N/C
No connect.
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
1
2
3
4
5
6
7
8
9
High voltage outputs.
HVOUT10
Doc.# DSFP-HV5530
C072313
Supertex inc.
www.supertex.com
5
HV5530
44-Lead PLCC Pin Description
Pin #
Function
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
HVOUT32
DATA OUTPUT
N/C
Description
1
2
3
4
5
6
7
8
9
High voltage outputs.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Data output pin.
No connect.
N/C
N/C
POL
Inverts the polarity of the HVOUT pins
CLK
Clock pin, shift registers shifts data on falling edge of input clock.
Reference voltage, usually ground.
VSS
VDD
Logic supply voltage.
LE
Latch enable pin, data is shifted from shift register to latches on logic input high.
Data input pin.
DATA INPUT
Blanking pin sets all HVOUT pins low or high depending upon state of polarity.
See function table.
28
BL
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
N/C
No connect.
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
1
2
3
4
5
6
7
8
9
High voltage outputs.
HVOUT10
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
Doc.# DSFP-HV5530
C072313
Supertex inc.
www.supertex.com
6
HV5530
44-Lead PQFP Package Outline (PG)
10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch
D
D1
E1
E
Note 1
(Index Area
D1/4 x E1/4)
44
1
b
e
θ1
Top View
View B
Gauge
A2
A1
L2
θ
Plane
A
Seating
Plane
L
L1
Seating
Plane
Side View
View B
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
A
A1
MIN 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80*
NOM 2.00 13.90 10.00 13.90 10.00
MAX 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20*
A2
b
D
D1
E
E1
e
L
L1
L2
θ
0O
0.73
0.88
1.03
Dimension
(mm)
0.80
BSC
1.95 0.25
REF BSC
-
-
-
3.5O
7O
JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995.
* This dimension is not specified in the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44PQFPPG, Version C041309.
Doc.# DSFP-HV5530
C072313
Supertex inc.
www.supertex.com
7
HV5530
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max), .050in pitch
D
.048/.042
D1
x 45O
.056/.042
x 45O
6
1
44
40
.150max
Note 1
(Index Area)
.075max
E
E1
Note 2
e
.020max
(3 Places)
Top View
Vertical Side View
View
B
b1
Base
Plane
A
.020min
A2
A1
Seating
Plane
b
R
Horizontal Side View
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Actual shape of this feature may vary.
Symbol
A
A1
A2
.062
-
b
.013
-
b1
.026
-
D
D1
E
E1
e
R
MIN
.165
.172
.180
.090
.105
.120
.685
.690
.695
.650
.653
.656
.685
.690
.695
.650
.653
.656
.025
.035
.045
Dimension
(inches)
.050
BSC
NOM
MAX
.083
.021
.036†
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44PLCCPJ, Version F031111.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to:
http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-HV5530
C072313
8
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