HV7331K6-G_技术文档

HV7331

Supertex inc.

Four Channel, High Speed ±70V 2.0A

Ultrasound RTZ Pulser

Features

General Description

► HVCMOS technology for high performance

► High density integrated ultrasound transmitter

► 0 to ±70V output voltage

The Supertex HV7331 is a four-channel, monolithic, high voltage,

high speed pulse generator with built in fast return to zero damping

FETs. This high voltage and high-speed integrated circuit is

designed for portable medical ultrasound imaging devices, and can

also be used for NDT applications.

► ±2.0A source and sink minimum pulse current

► Up to 20MHz operation frequency

► ±2.5ns matched delay times

► 2.5 to 5.0V CMOS logic interface

► Built-in output drain diode and bleed resistors

► CW/RTZ Doppler quick switching

► Two damping mode options

The HV7331 consists of a controller logic interface circuit, level

translators, MOSFETgatedrives, andhighcurrentpowerP-channel

and N-channel MOSFETs as the output stage for each channel.

The peak output currents of each channel are guaranteed to be

over 2.0A with up to a ±70V pulse swing. The integrated regulators

for the gate drivers not only saves two ﬂoating voltage supplies, but

also makes the PCB layout easier. The split common source for

the P or N damping MOSFETs provide pulse or CW Doppler mode

quick switch-over for cost and power savings.

Applications

► Portable medical ultrasound imaging

► Piezoelectric transducer drivers

► NDT ultrasound transmission

► Pulse waveform generator

Typical Application Circuit

+2.5 to 3.3V

+5.0V

+5.0 to +70V

VDD

CPF

VPP

LRP

V_SS

VLL

V_PP

RGND

V_PP

V_PF

HV_OUT

EN

LR

V_PF

V_NF

1 of 4-Channels Shown

TX1

Logic

CW/RTZ

PIN1

V_NN

V_GN

& Level

RGND

Translator

V_NN

R_GN

R_GP

NIN1

CGP

VGP

VGN

+VCW

-VCW

AGND

RGP

CGN

RGN

V_DD

V_GP

SUB

LRN

VNF

DGND

VSS

VSUB

CNF

VNN

RGND

CW/RTZ

-5.0V

-5.0 to -70V

Doc.# DSFP-HV7331

B011513

Supertex inc.

www.supertex.com

HV7331

Pin Conﬁguration

Ordering Information / Availability

64

Part Number

Package Option

Packing

1

HV7331K6-G

64-Lead QFN (9.0x9.0)

260/tray

-G indicates package is RoHS compliant (‘Green’)

Absolute Maximum Ratings

Parameter

Value

64-Lead QFN

AGND, DGND and V_SUB

0V

(top view)

V_LL, Positive logic supply

-0.5 to +5.5V

+0.5 to -5.5V

+160V

V_DD, Positive logic and level translator supply

V_SS, Negative level translator supply

(V_PP-V_NN) Differential high voltage supply

V_PP, High voltage positive supply

Package Marking

L = Lot Number

HV7331K6

LLLLLLLLL

YYWW

YY = Year Sealed

WW = Week Sealed

A = Assembler ID

-0.5 to +80V

+0.5 to -80V

-0.5 to +5.5V

+160V

C = Country of Origin

AAA CCC

= “Green” Packaging

V_NN, High voltage negative supply

All logic input PIN_X, NIN_X, EN and CW voltages

(V_PP-TX_n) V_PPto TX_nvoltage difference

(TX_n-V_NN) TX_nto V_NNvoltage difference

(RGP - GND) RGP to GND voltage difference

(RGN - GND) RGN to GND voltage difference

Storage temperature

Package may or may not include the following marks: Si or

64-Lead QFN

+160V

Typical Thermal Resistance

-0.5 to +5.5V

+0.5 to -5.5V

-65 to 150°C

Package

θ_ja

64-Lead QFN

21^OC/W

Absolute Maximum Ratings are those values beyond which damage to the device may

occur. Functional operation under these conditions is not implied. Continuous operation

of the device at the absolute rating level may affect device reliability. All voltages are

referenced to device ground.

Power-Up Sequence

Power-Down Sequence

Step

Description

Step

Description

1

2

3

4

V_LLwith logic signal low

V_DD, V_SS

1

2

3

4

All logic signals go to low

V_PP, V_NN

V_DD, V_SS

V_LL

V_PP, V_NN

Logic control signals active

Note:

Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering up/down sequence is only recommended in

order to minimize possible inrush current.

Doc.# DSFP-HV7331

B011513

Supertex inc.

www.supertex.com

2

HV7331

Operating Supply Voltages and Current (Four Active Channels)

(Operating conditions, unless otherwise speciﬁed, V_LL= +3.3V, V_DD= +5V, V_SS= -5V, V_PP= +70V, V_NN= -70V, V_SUB= 0V, T_A= 25°C)

Sym

V_LL

Parameter

Min

2.25

4.85

-5.15

Typ

3.3

Max

5.25

5.15

-4.85

Units Conditions

Logic voltage reference

Positive voltage supply

Negative voltage supply

V

---

V_DD

V_SS

5.0

-5.0

When CW/RTZ = 0 (in B-Mode)

must be 0 ≤ V_RGP≤ +0.5V and

0 ≥ V_RGN≥ -0.5V

V_RGP

V_RGN

Positive voltage supply

Negative voltage supply

1.0

-

5.5

V

-5.5

-1.0

V_PP

V_NN

Positive HV supply

VDD

-

+70

VSS

3.0

180

6.0

20

6.0

55

75

50

-

V

---

Negative HV supply

V_LL, Current EN = 0

V_DD, Current EN = 0

V_DD, Current EN = 1

V_SSCurrent EN = 0

V_SSCurrent EN = 1

V_DDCurrent EN = CW = 1

V_SSCurrent EN = CW = 1

-70

-

I_LL

1.0

100

2.5

10

μA ---

mA

I_DDQ

I_DDEN

I_SSQ

-

f = 0MHz, CW/RTZ = Low

RGN = RGP = 0V

-

μA

mA

μA

I_SSEN

I_DDCW

I_SSCW

-

2.0

45

-

f = 5.0MHz, CW/RTZ = High

RGN/RGP = ±5.0V,

No Load

-

45

I_RGPCWRGP Current EN = CW = 1

I_RGNCWRGP Current EN = CW = 1

-

60

-

35

I_PPQ

I_NNQ

V_PPCurrent EN = 0

-

32

---

V_NNCurrent EN = 0

-

32

μA

I_PPEN

I_NNEN

I_PPEN

I_NNEN

I_PPEN

I_NNEN

V_PPCurrent EN = 1

-

290

0.25

32

mA

μA

f = 5.0MHz, continuous,

no loads

V_NNCurrent EN = 1

-

V_PPCurrent EN = 1, LR = 1

V_SSCurrent EN = 1, LR = 1

V_PPCurrent EN = 1, LR = 0

V_NNCurrent EN = 1, LR = 0

-

0.5

50

-

f = 0MHz

-

32

μA

Logic Inputs

Sym

V_IH

V_IL

I_IH

Parameter

Min

Typ

Max

V_LL

0.4

1.0

-

Units Conditions

Input logic high voltage

Input logic low voltage

Input logic high current

Input logic low current

Input logic capacitance

(V_LL- 0.4)

-

V

---

0

-

-1.0

-

μA ---

I_IL

C_IN

5.0

pF

---

Doc.# DSFP-HV7331

B011513

Supertex inc.

www.supertex.com

3

HV7331

Electrical Characteristics

.0

(Operating conditions, unless otherwise speciﬁed, V_LL= +3.3V, V_DD= +5.0V, V_SS= -5.0V, V_PP= +70V, V_NN= -70V, V_SUB= 0V, T_A= 25°C)

Pulser P-Channel MOSFET

Sym

Parameter

Min

Typ

3.3

4.0

50

Max

Units Conditions

I_OUT

Output saturation current

Channel resistance

Output capacitance

2.0

-

5.5

-

A

Ω

---

R_ON

-

I_SD= 100mA

C_OSS

pF

V_DS= 25V, f = 1.0MHz

Pulser N-Channel MOSFET

Sym

I_OUT

Parameter

Min

Typ

3.3

2.3

50

Max

Units Conditions

Output saturation current

Channel resistance

Output capacitance

2.0

-

3.0

-

A

Ω

---

R_ON

-

I_SD= 100mA

C_OSS

pF

V_DS= 25V, f = 1.0MHz

MOSFET Drain Bleed Resistor

Sym

R_P/N1~4Output bleed resistance

P_ROBleed resistors power limit

Parameter

Min

120

-

Typ

Max

190

40

Units Conditions

kΩ ---

-

mW ---

Damping P-Channel MOSFET

Sym

I_OUT

Parameter

Min

Typ

3.3

3.7

50

Max

Units Conditions

Output saturation current

Channel resistance

Output capacitance

2.0

-

4.8

-

A

Ω

V_RGP= V_RGN= 0V

R_ON

-

I_SD= 100mA

C_OSS

pF

V_DS= 25V, f = 1.0MHz

Damping N-Channel MOSFET

Sym

I_OUT

Parameter

Min

Typ

3.3

2.7

50

Max

Units Conditions

Output saturation current

Channel resistance

Output capacitance

2.0

-

3.5

-

A

Ω

V_RGP= V_RGN= 0V

R_ON

-

I_SD= 100mA

C_OSS

pF

V_DS= 25V, f = 1.0MHz

CW Mode P- & N-Channel MOSFET

Sym

Parameter

Min

Typ

14

Max

Units Conditions

R_ONCW-PCW Mode ON-resistance

R_ONCW-NCW Mode ON-resistance

ΔR_ONCWP- & N-Ch R_ONCWmatching

-

Ω

I_SD= 100mA,

V_RGP= +5.0V, V_RGN= -5.0V

14

Ω

±2.0

Ω

AC Electrical Characteristics

(Operating conditions, unless otherwise speciﬁed, V_LL= +3.3V, V_ADD= V_DD= +5.0V, V_SS= -5.0V ,V_PP= +70V, V_NN= -70V, T_A= 25°C)

Sym

t_r1

Parameter

Min

Typ

15

17

Max

18

Units Conditions

Pulser output rise time

Pulser output fall time

Damping output rise time

Damping output fall time

CWD output rise time

CWD output fall time

-

ns

t_f1

18

330pF//2.5kΩ load

t_r2

18

ns

t_f2

18

t_r3

22

330pF//2.5kΩ load,

RGP/RGN = ±5.0V

t_f3

22

Doc.# DSFP-HV7331

B011513

Supertex inc.

www.supertex.com

4

HV7331

AC Electrical Characteristics (cont.)

(Operating conditions, unless otherwise speciﬁed, V_LL= +3.3V, V_ADD= V_DD= +5.0V, V_SS= -5.0V ,V_PP= +70V, V_NN= -70V, T_A= 25°C)

Sym

f_OUT

Parameter

Min

-

Typ

Max

20

-

Units Conditions

Output frequency range

Second harmonic distortion

-

MHz

100Ω load

dB

HD2

-

-40

t_{EN_ON}Delay on mode change

t_{EN_OFF}Chip disable time

-

200

300

4.0

300

4.0

13

10

13

10

12

-

μs

CPF,

-

2.0

μs

CNF capacitor 0.47μF per pin,

50% to 90%

t_{LR_ON}

Linear regulators enable time

-

200

μs

ns

t_{LR_OFF}Linear regulators disable time

-

2.0

t_drp1

t_dfp1

t_drn1

t_dfn1

t_drp2

t_dfp2

t_drn2

t_dfn2

Pulser delay time on P-rise

Pulser delay time on P-fall

Pulser delay time on N-rise

Pulser delay time on N-fall

CWD delay time on P-rise

CWD delay time on P-fall

CWD delay time on N-rise

CWD delay time on N-fall

8.0

5.0

8.0

5.0

6.0

-

CW/RTZ = 0

R₁= R₂= 1.0Ω to GND

-

CW/RTZ = 1

R₁= R₂= 1.0Ω to GND

-

Δt_DELAYDelay time matching

±2.5

P to N, channel to channel

V_RGP/V_RGN= ±5.0V, input t_r50% to

HV_OUTt_ror t_f50%, with 50Ω load

t_JCWDelay jitter on rise or fall

-

13

-

ps

Logic Control Table (each channel)

Inputs

Output MOSFETs

VPP

to

TX

VNN

to

TX

to

RGP

TX

to

RGN

Operation

EN

1

CW/RTZ

NIN

Mode

0

1

X

0

1

0

1

0

1

0

1

X

0

1

0

1

X

OFF

ON

OFF

ON

OFF

ON

OFF

ON

B-Mode

with RTZ

OFF

CW-Mode

Disable

1

0

OFF

Note:

When CW/RTZ = 0 (in B-Mode) must be 0 ≤ V_RGP≤ +0.5V and 0 ≥ V_RGN≥ -0.5V

When CW/RTZ = 1 (in CW-Mode) must be 0 ≤ V_RGP≤ +5.5V and 0 ≥ V_RGN≥ -5.5V

Doc.# DSFP-HV7331

B011513

Supertex inc.

www.supertex.com

5

HV7331

Switch Timing and Delay Test

CW/RTZ = 0

NINn

PINn

NINn

PINn

t_r1

t_f2

90%

10%

t_f3

t_r3

t_r2

t_f1

TXn

90%

10%

TXn

10%

90%

CW/RTZ = 0

PINn

CW/RTZ = 0

NINn

CW/RTZ = 1

PINn

CW/RTZ = 1

50%

NINn

t_dfp2

t_dfn2

t_dfp1

t_dfn1

t_drp2

t_drn2

t_drp1

t_drn1

I_OUT

50%

I_OUT

50%

TXn 0A

* Note: CW/RTZ = 0, RGP = RGN = 0V

TXn 0A

* Note: CW/RTZ = 1, RGP = +5.0V, RGN = -5.0V

n = 1, 2, 3, 4

50%

I_OUT

+2.5 to 3.3V

+5.0V

+5.0 to +70V

VDD

CPF

VPP

VLL

V_PP

LRP

V_SS

RGND

V_PP

V_PF

EN

LR

V_PF

V_NF

1 of 4-Channels Shown

TX1

R1

Logic

CW/RTZ

PIN1

V_NN

& Level

RGND

V_GN

Translator

V_NN

R_GN

R_GP

NIN1

CGP

RGP

0 to +5.0V

VGP

VGN

AGND

CGN

RGN

V_DD

V_GP

SUB

LRN

VNF

DGND

VSS

VSUB

VNN

RGND

CNF

0 to -5.0V

-5.0V

-5.0 to -70V

Doc.# DSFP-HV7331

B011513

Supertex inc.

www.supertex.com

6

HV7331

Pin Description

Name

Description

1

EN

Chip power enable Hi = ON, Low = OFF

B-Scan or CWD mode control pin, see Control Logic Table

Input logic control signal for channel 1

Input logic control signal for channel 2

Digital logic circuit ground (0V)

2

CW/RTZ

NIN1

PIN1

NIN2

PIN2

AGND

NIN3

PIN3

NIN4

PIN4

VDD

3

4

5

6

7

8

Input logic control signal for channel 3

Input logic control signal for channel 4

Positive voltage power supply (+5.0V)

9

10

11

12

Built-in linear regulators power turned on (enabled) when LR = 1 and EN = 1

Built-in linear regulators power turned off (disabled) when EN = 0 or LR = 0

13

LR

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

VDD

VLL

Positive voltage power supply (+5.0V)

Logic “1” voltage reference input (+2.5 to +5V)

Digital logic circuit ground (0V)

AGND

VDD

DGND

VSS

CPF

VPP

CGP

RGP

CGN

RGN

CNF

VNN

TX4

Positive voltage power supply (+5.0V)

Driver and level translator circuit ground return (0V)

Negative voltage power supply (-5.0V)

VPP to VPF decoupling capacitor (low voltage, 0.22 to 0.47μF 10V) See Note 1

Positive high voltage power supply (+5.0 to +70V)

CGP to RGP decoupling capacitor (low voltage, 0.47μF 10V)

Common return ground or positive CW power supply. When CW/RTZ = 0 (in B-Mode) must

be 0 ≤ V_RGP≤ +0.5V. When CW/RTZ = 1 (in CW-Mode) must be 0 ≤ V_RGP≤ +5.5V.

CGN to RGN decoupling capacitor (low voltage, 0.47μF 10V)

Common return ground or positive CW power supply. When CW/RTZ = 0 (in B-Mode) must

be 0 ≥ V_RGN≥ -0.5V. When CW/RTZ = 1 (in CW-Mode) must be 0 ≥ V_RGN≥ -5.5V.

VNF to VNN decoupling capacitor (low voltage, 0.22 to 0.47μF 10V) See Note 1

Negative high voltage power supply (-5.0 to -70V)

Transmit pulser output for channel 4

TX4

Doc.# DSFP-HV7331

B011513

Supertex inc.

www.supertex.com

7

HV7331

Pin Description (cont.)

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

Name

RGND

TX3

Description

Bleeding resistor common return ground

Transmit pulser output for channel 3

TX3

RGND

TX2

Bleeding resistor common return ground

Transmit pulser output for channel 2

Bleeding resistor common return ground

Transmit pulser output for channel 1

TX2

RGND

TX1

VNN

Negative high voltage power supply (-5.0 to -70V)

VNN

CNF

VNF to VNN decoupling capacitor (low voltage, 0.22 to 0.47μF 10V) See Note 1

Common return ground or negative CW power supply. (0V or -1.0 to -5.5V)

CGN to RGN decoupling capacitor (low voltage, 2.2μF 10V)

Common return ground or positive CW power supply.(0V or +1.0 to +5.5V)

CGP to RGP decoupling capacitor (low voltage, 2.2μF 10V)

Positive high voltage power supply (+5 to +70V)

RGN

CGN

RGP

CGP

VPP

CPF

CGP to RGP decoupling capacitor (low voltage, 0.22 to 0.47μF 10V) See Note 1

Negative voltage power supply (-5.0V)

VSS

DGND

VDD

Driver and level translator circuit ground return (0V)

Positive voltage power supply (+5.0V)

AGND

Digital logic circuit ground (0V)

(Thermal Pad) VSUB

Substrate connect to ground (0V)

Note 1:

To minimize the rush-in current, nominal capacitor values for the CPF to VPP pins and the CNF to VNN pins should not exceed 0.47μF.

Doc.# DSFP-HV7331

B011513

Supertex inc.

www.supertex.com

8

HV7331

64-Lead QFN Package Outline (K6)

9.00x9.00mm body, 1.00mm height (max), 0.50mm pitch

D2

D

64

1

Note 1

(Index Area

D/2 x E/2)

Note 1

(Index Area

D/2 x E/2)

e

b

E

E2

Top View

Bottom View ^{View B}

Note 3

θ

L

A3

A

Seating

Plane

L1

Note 2

Side View

View B

A1

Notes:

1. A Pin 1 identiﬁer must be located in the index area indicated. The Pin 1 identiﬁer can be: a molded mark/identiﬁer; an embedded metal marker; or

a printed indicator.

2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.

3. The inner tip of the lead may be either rounded or square.

Symbol

A

A1

A3

b

D

D2

E

E2

e

L

L1

0.00

-

θ

0^O

-

MIN

NOM

MAX

0.80

0.90

1.00

0.00

0.02

0.05

0.18

0.25

0.30

8.85*

9.00

6.00

7.70*

8.85*

9.00

6.00

7.70*

0.30

0.40

0.50

Dimension

(mm)

0.20

REF

0.50

BSC

9.15* 7.80† 9.15* 7.80†

0.15

14^O

JEDEC Registration MO-220, Variation VMMD-4, Issue K, June 2006.

* This dimension is not speciﬁed in the JEDEC drawing.

† This dimension differs from the JEDEC drawing.

Drawings are not to scale.

Supertex Doc.#: DSPD-64QFNK69X9P050, Version B020112

(The package drawing(s) in this data sheet may not reﬂect the most current speciﬁcations. For the latest package outline

information go to http://www.supertex.com/packaging.html.)

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives

an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability

to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and

specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888

www.supertex.com

Doc.# DSFP-HV7331

B011513

9


型号：	HV7331K6-G
厂家：	Supertex, Inc
描述：	Four Channel, High Speed Â±70V 2.0A Ultrasound RTZ Pulser
文件：	总9页 (文件大小：804K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HV7331K6-G [SUPERTEX]

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