HV7351 [SUPERTEX]
Eight Channel Programmable High Voltage Ultrasound Transmit Beamformer;
| 型号： | HV7351 |
| 厂家： | 
Supertex, Inc |
| 描述： | Eight Channel Programmable High Voltage Ultrasound Transmit Beamformer |
| 文件： | 总15页 (文件大小：924K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supertex inc.
HV7351
Eight Channel Programmable
High Voltage Ultrasound Transmit Beamformer
Features
General Description
► Eight channels with return to zero
► Up to ±70V output voltage
► ±3.0A output current
The Supertex HV7351 is an 8-channel programmable high
voltage ultrasound transmit beamformer. Each channel is
capable of swinging up to ±70V with an active discharge back
to 0V. The outputs can source and sink more than 3.0A to
achieve fast output rise and fall times. The active discharge is
also capable of sourcing and sinking 3.0A for a fast return to
ground. The topology of the HV7351 will significantly reduce
the number of I/O logic control lines needed.
► Store up to four different patterns
► Independent programmable delays
► Single 11x11 QFN-80 package
Application
Each pulser has four associated 64-bit shift registers for
storing pre-determined transmit patterns and a 10-bit delay
counter for controlling the transmit time. One of four arbitrary
patterns can be transmitted with adjustable delay, depending
on the data loaded into these shift registers and the delay
counter. The delay counter can be clocked up to 200MHz,
allowing incremental delays down to 5ns.
► Medical ultrasound imaging
► NDT, non-destructive testing
► Arbitrary pattern generator
► High speed PIN diode driver
Typical Application Circuit
Array
Probe
tDELAY1
tDELAY2
tDELAY3
Tx1
E1
E2
E3
HV7351
8-channel
Tx2
U1
Tx3
HV7351
8-channel
U2
Trigger
tDELAY127
Tx127
HV7351
8-channel
U16
E127
E128
tDELAY128
Tx128
Trigger
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
HV7351
Pin Configuration
Ordering Information
80
Part Number
Package Option
Packing
1
HV7351K6-G
80-Lead QFN (11x11)
176/Tray
-G denotes a lead (Pb)-free / RoHS compliant package
Absolute Maximum Ratings
Parameter
Value
VLL, Positive logic supply
-0.5V to 5.5V
-0.5V to 5.5V
-0.5V to 5.5V
-0.5V to 5.5V
+0.5V to -5.5V
-0.5V to +80V
+0.5V to -80V
+160V
DVDD, Positive logic supply voltage
PVDD, Positive gate drive supply voltage
AVDD, Positive analog supply voltage
PVSS, Negative gate drive supply voltage
VPP, High voltage positive supply voltage
VNN, High voltage negative supply voltage
(VPP - VNN), Differential high voltage supply
VPF, Positive floating supply voltage
VNF, Negative floating supply voltage
VRP, Positive supply for VNF regulator
VRN, Negative supply for VPF regulator
Operating temperature
80-Lead QFN
(top view)
Package Marking
L = Lot Number
HV7351K6
LLLLLLLLL
YYWW
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
AAA CCC
VPP - 6.0V to VPP
VNN to VNN +6.0V
0V to 15V
= “Green” Packaging
Package may or may not include the following marks: Si or
80-Lead QFN
0V to -15V
Typical Thermal Resistance
-40°C to +125°C
-65°C to +150°C
Package
θja
80-Lead QFN
14OC/W
Storage temperature
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Operating Supply Voltages
(TJ = 25°C unless otherwise specified)
Sym Parameter
Min
3.0
Typ
Max
70
Units Conditions
VPP
VNN
VLL
Positive high voltage supply
-
-
V
V
V
---
---
---
Negative high voltage supply
Logic interface voltage
-70
-3.0
3.6
2.85
3.30
Low voltage positive analog
supply voltage
AVDD
DVDD
PVDD
PVSS
4.75
4.75
4.75
-5.25
5.00
5.00
5.00
-5.00
5.25
5.25
5.25
-4.75
V
V
V
V
---
---
---
---
Low voltage positive digital
supply voltage
Low voltage positive gate drive
supply voltage
Low voltage negative gate drive
supply voltage
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
2
HV7351
Operating Supply Voltages (cont.)
(TJ = 25°C unless otherwise specified)
Sym Parameter
Min
Typ
Max
Units Conditions
Low voltage positive supply for
VNF regulator
VRP
VRN
4.75
-12
-
12
V
V
V
---
---
---
Low voltage negative supply for
VPF regulator
-
-4.75
Reference voltage logic trip
point for TCK pin
TCK
ITCK
0.4VLL
-
0.5VLL
-
0.6VLL
±10
TCK input current
μA VTCK = 0 to VLL
Regulator Outputs
(Operating conditions unless otherwise specified, VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ =25ºC)
Sym Parameter
Min
Typ
Max
Units Conditions
Positive floating gate drive
voltage
4.0µF ceramic capacitor across
VPF and VPP
VPF
VNF
VPP -5.25 VPP -5.00 VPP -4.00
VNN +4.00 VNN +5.00 VNN +5.25
V
V
Negative floating gate drive
voltage
4.0µF ceramic capacitor across
VNF and VNN
Electrical Characteristics
(Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC)
Sym Parameter
Min
Typ
384
12
Max
500
30
Units Conditions
IVLLQ
VLL quiescent current
-
µA EN = Low, all inputs are static
IAVDDQ AVDD quiescent current
IDVDDQ DVDD quiescent current
IPVDDQ PVDD quiescent current
IVRPQ VRP quiescent current
-
-
12
30
µA EN = Low, all inputs are static
-
70
100
6.0
6.0
-
-
0.3
µA EN = Low, all inputs are static
µA EN = Low, all inputs are static
µA EN = Low, all inputs are static
µA EN = High, all inputs are static
µA EN = High, all inputs are static
µA EN = High, all inputs are static
µA EN = High, all inputs are static
µA EN = High, all inputs are static
µA EN = High, all inputs are static
IVRNQ VRN quiescent current
-
-0.01
-45
2.6
IPVSSQ PVSS quiescent current
IVPPQ VPP quiescent current
-85
-
6.0
6.0
500
800
55
IVNNQ VNN quiescent current
-
-1.6
390
600
22
IVLLEN VLL enabled quiescent current
IAVDDEN AVDD enabled quiescent current
IDVDDEN DVDD enabled quiescent current
IPVDDEN PVDD enabled quiescent current
IVRPEN VRP enabled quiescent current
IVRNEN VRN enabled quiescent current
IPVSSEN PVSS enabled quiescent current
IVPPEN VPP enabled quiescent current
IVNNEN VNN enabled quiescent current
-
-
-
-
44
100
650
-
-
450
-350
-44
370
-420
-650
-100
-
-
620
-
-620
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
3
HV7351
Electrical Characteristics (cont.)
(Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC)
Sym Parameter
Min
Typ
500
25
Max
Units Conditions
IVLLCW VLL current at TCK = 80MHz
IDVDDCW DVDD current at CW = 5MHz
IVPPCW VPP current at CW = 5MHz
IVNNCW VNN current at CW = 5MHz
-
-
-
-
-
-
-
-
µA
VPP = +5.0V, VNN = -5.0V, EN = High,
mA
mA
mA
CW = High, 80MHz on TCK, 0.5VLL
on TCK, all 8 channels active at
5.0MHz, No load
141
98
AC Electrical Characteristics
(Operating conditions unless otherwise specified, VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC)
Sym Parameter
fTCK Transmit clock frequency
Min
0
Typ
Max
200
80
70
-
Units Conditions
-
-
MHz ---
0
No daisy chain
MHz
fSCK
Serial clock frequency
0
-
Daisy chained
tSU-DIN Set-up time data in to SCK
tH-DIN Hold time SCK to data in
tSU-CS1 Set-up time CS1 low to SCK
tSU-CS2 Set-up time CS2 low to SCK
tSU-TRIG Set-up time TRIG low to TCK
tW-TRIG TRIG pulse width
2.0
1.0
1.0
-
ns
ns
ns
ns
ns
-
---
2.0
-
---
2.0
-
---
2.0
-
-
---
2.0
-
-
---
2TCK
3.0
-
-
---
9.0
9.0
9.0
9.0
-
12
10
12
10
-
For DOUT
For DOUT
For DOUT
For DOUT
1
2
1
2
SCK to data out low to high
delay time
tLHDO
ns
ns
3.0
3.0
SCK to data out high to low
delay time
tHLDO
3.0
tWA1A0 A1A0 pulse width
tW-TRIG +40
Set-up time A1A0 to TRIG rising
tSUA1A0
edge
-
-
-
20
20
-
-
-
ns
---
Hold time A1A0 to TRIG falling
tHA1A0
edge
1.0µF capacitor on every VPF and
VNF pin.
tEN-ON Device enable time
tEN-OFF Device disable time
1.0
ms
ns
-
-
-
-
100
13
---
tr1
tf1
Output rise time from 0V to +HV
Output fall time from 0V to -HV
9.0
9.0
13
Damping output rise time from
-HV to 0V
tr2
tf2
-
-
9.0
9.0
13
13
ns
ns
Load = 330pF//2.5kΩ
Damping output fall time from
+HV to 0V
tr3
tf3
Output rise time from -HV to +HV
Output fall time from +HV to -HV
CW output rise time
-
-
-
-
17
17
23
23
16
16
trcw
tfcw
9.0
9.0
VPP = +5.0V, VNN = -5.0V,
Load = 330pF//2.5kΩ
CW output fall time
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
4
HV7351
AC Electrical Characteristics (cont.)
(Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC)
Sym Parameter
Output propagation delay rise
Min
Typ
Max
Units Conditions
tdr1
10.85
13.35
15.85
time 1
Output propagation delay fall
time 1
tdf1
11.35
11.25
11.75
11.35
11.45
10.45
10.35
13.85
13.75
14.25
13.85
13.95
12.95
12.85
16.35
16.25
16.75
16.35
16.45
15.45
15.35
Output propagation delay rise
time 2
tdr2
ns
No Load.
Output propagation delay fall
time 2
tdf2
Output propagation delay rise
time 3
tdr3
Output propagation delay fall
time 3
tdf3
CW output propagation delay
time from low to high
tdcwlh
tdcwhl
VPP = +5.0V, VNN = -5.0V,
No Load
ns
CW output propagation delay
time from high to low
Δtdcwhl Delay time matching
-
±0.7
13
-
ns
ps
-
P to N, channel-to-channel matching
VPP = +5.0V, VNN = -5.0V, Load = 50Ω
---
tJCW
Delay jitter on rise or fall
Latency
-
-
LAT
3.5TCK
3.5TCK
3.5TCK
Output P-channel MOSFET to VPP, CW = 0
IOUT
Output saturation current
2.2
3.2
4.2
62
-
-
-
A
Ω
---
RON
Output ON-resistance
-
-
IOUT = 100mA
COSS Output capacitance
pF
VPP - VOUT = 25V, f = 1.0MHz
Output N-channel MOSFET to VNN, CW = 0
IOUT
Output saturation current
-
-
-
-3.2
2.4
50
-2.2
A
Ω
---
RON
Output ON-resistance
-
-
IOUT = -100mA
COSS Output capacitance
pF
VNN - VOUT = -25V, f = 1.0MHz
Output P-channel MOSFET to VPP, CW = 1
IOUT
Output saturation current
1.2
1.5
8.0
62
-
-
-
A
Ω
---
RON
Output ON-resistance
-
-
IOUT = 100mA
COSS Output capacitance
pF
VPP - VOUT = 25V, f = 1.0MHz
Output N-channel MOSFET to VNN, CW = 1
IOUT
Output saturation current
-
-
-
-1.5
6.6
50
-1.2
A
Ω
---
RON
Output ON-resistance
-
-
IOUT = -100mA
COSS Output capacitance
pF
VNN - VOUT = -25V, f = 1.0MHz
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
5
HV7351
AC Electrical Characteristics (cont.)
(Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC)
Sym Parameter
Min
Typ
Max
Units Conditions
Damping P-channel MOSFET to PGND
IOUT
Output saturation current
2.2
3.2
4.0
62
-
-
-
A
Ω
---
RON
Output ON-resistance
-
-
IOUT = 100mA
COSS Output capacitance
pF
VPP - VOUT = 25V, f = 1.0MHz
Damping N-channel MOSFET to PGND
IOUT
Output saturation current
-
-
-
-3.2
2.3
50
-2.2
A
Ω
---
RON
Output ON-resistance
-
-
IOUT = -100mA
COSS Output capacitance
pF
VNN - VOUT = -25V, f = 1.0MHz
Logic Inputs
ITCK
Input current for TCK
-
±1.0
TCK
-
µA VTCK = 0 to VLL
TCK
+0.15
VIH
Input logic high voltage for TCK
VLL
V
V
Only for TCK input, TCK = 0.5VLL
TCK
-0.15
VIL
Input logic low voltage for TCK
0
TCK
Only for TCK input, TCK = 0.5VLL
VIH
VIL
IIH
Input logic high voltage
Input logic low voltage
Input logic high current
Input logic low current
Output logic low voltage
Output logic high voltage
Input logic capacitance
0.8VLL
-
-
-
-
-
-
-
VLL
0.2VLL
1.0
-
V
V
For all logic inputs except TCK
For all logic inputs except TCK
0
-
µA ---
µA ---
IIL
-1.0
VOL
VOH
CIN
0
0.7
VLL
V
V
IOUT = 0 to -10mA
VLL -0.7
-
IOUT = 0 to 10mA
---
5.0
pF
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
6
HV7351
Logic Truth Table
Inputs
10-bit
Counter
Outputs
Mode
Comments
EN CW
INV NIN PIN N-ch P-ch RTZ
RTZ (return-to-zero) is activat-
ed when NIN and PIN are both
low. Output is pulled to ground
through a series diode.
1
0
X
X
0
0
OFF OFF ON
Not inverted. Logic 1 in the
OFF ON OFF P-channel register turns on the
output P-channel MOSFET.
Non-CW mode.
1
1
0
0
X
X
0
0
0
1
1
0
Outputs not inverted.
Outputs are con-
trolled by data in the
shift registers
Not inverted. Logic 1 in the
ON OFF OFF N-channel register turns on the
output N-channel MOSFET.
Avoids cross over current. A
logic 1 in both P- and N-chan-
nel registers will put the output
in a Hi-Z state.
1
0
1
1
0
0
X
X
X
1
1
1
OFF OFF OFF
Non-CW mode.
ON OFF OFF Inverted, for harmonic imaging
Outputs are inverted.
Outputs are con-
trolled by data in the
shift registers
1
1
0
X
1
1
0
OFF ON OFF Inverted, for harmonic imaging
Off channels are the ones with
X
All 1
X
X
X
OFF OFF OFF
all 1’s in their respective 10-bit
counters. Output follows the fCW
signal. Shift registers for NIN
and PIN should remain static to
save power.
CW mode.
Output follows fcw
OFF/ ON/
OFF
1
0
1
Not all 1
X
X
X
X
X
X
X
ON OFF
Device Disabled
X
OFF OFF OFF Hi-Z state
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
7
HV7351
Block Diagram
VLL
AVDD
DVDD
EN
VPP
VPF
VRN
VPP
SIZE
CS1
P-ch Registers
16/32-bit Register
Pattern 1
N-ch Registers
Linear
16/32-bit Register
Regulator
Pattern 1
VPF
SCK
D 1
VRN
DOUINT1
16/32-bit Register
Pattern 2
16/32-bit Register
Pattern 2
16/32-bit Register
Pattern 3
16/32-bit Register
Pattern 3
A0
A1
VRP
VNF
VNN
VRP
16/32-bit Register
Pattern 4
16/32-bit Register
Pattern 4
Linear
Regulator
VNF
VNN
DIN2
OUT2
8 10-bit Registers
for Delay Counters
6-bit for
Divide by N
D
CS2
VPP
Tx1
CW
INV
CW
fCW
VPF
VNF
Divide
by 2
EN
10-bit Delay
Counter
EN
TRIG
6-bit Counter
Divide by N
N = 1 to 64
Control
Logic
INV
VNN
16/32 bit
Serial
EN/LD
CW
PIN
Shift Reg.
CLK
PGND
INV
PVSS
PVDD
16/32 bit
Serial
EN/LD
CW
NIN
Shift Reg.
CLK
PGND
PVDD
PVSS
RTZ GATE Driver
Supply Voltages
VPP
CW
fCW
Divide
by 2
VPF
VNF
EN
EN
Tx8
6-bit Counter
Divide by N
N = 1 to 64
10-bit Delay
Counter
Control
Logic
INV
16/32 bit
Serial
EN/LD
CW
PIN
VNN
Shift Reg.
CLK
-
+
TCK
TCK
PGND
INV
VLL to VDD
Translator
16/32 bit
Serial
EN/LD
CW
PVSS
PVDD
NIN
Shift Reg.
CLK
DGND
AGND
VSUB
PGND
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
8
HV7351
Timing Diagram 1
TCk = 1.65V (0.5VLL
)
3.5 TCk cycles
3.3V
TCk
0V
3.3V
Internal CLK
(for N=2)
0V
tSU-TRIG
3.3V
Trig
0V
tWTRIG
tdr1
tdf2
+70V
90%
90%
tWTRIG needs to be at least
2 rising edges of TCk
Delay time set by
Tx1 10-bit counter
tdf1
tdr2
10%
tr1
10%
tf2
0V
Tx1
10%
10%
90%
tf1
90%
tr2
-70V
+70V
Delay time set by
Tx2 10 bit counter
0V
Tx2
Example with Tx2 delay having
two TCk cycles more than Tx1
-70V
Timing Diagram 2
TCk = 1.65V (0.5VLL
)
3.5 TCk cycles
3.3V
TCk
0V
3.3V
Internal CLk
(for N=2)
0V
tSU-TRIG
3.3V
Trig
0V
tWTRIG
tdf3
tdr3
+70V
90%
90%
tWTRIG needs to be at least
2 rising edges of TCk
Delay time set by
Tx1 10-bit counter
0V
Tx1
10%
10%
-70V
tf3
tr3
+70V
0V
Tx2
Delay time set by
Tx2 10 bit counter
Example with Tx2 delay having
one TCk cycle more than Tx1
-70V
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
9
HV7351
Pattern Register Circuit Diagram
SIZE
SIZE
EN
DIN
SCK
A1 A0 CS1
16/32 bits
Shift Register
P-ch. Pattern 1
16/32 bits
Shift Register
N-ch. Pattern 1
A1 A0 CS1
SIZE
EN
A1 A0 CS1
A1 A0 CS1
A1 A0 CS1
16/32 bits
16/32 bits
CS1
A1
Shift Register
P-ch. Pattern 2
Shift Register
N-ch. Pattern 2
DIN
A1 A0 CS1
A1 A0 CS1
2 to 4
SCK
Decoder
DOUT
1
Size
EN
A0
16/32 bits
Shift Register
N-ch. Pattern 3
16/32 bits
Shift Register
P-ch. Pattern 3
DIN
SCK
Size
EN
16/32 bits
Shift Register
P-ch. Pattern 4
16/32 bits
Shift Register
N-ch. Pattern 4
SCK
DIN1
DIN
A1 A0 CS1
SCK
Loading Data into the Four 16/32 bit Pattern Registers
A detailed circuit diagram of the pattern registers is shown
DIN1
32 bits for
32 bits for
above. There are 4 programmable patterns that can be
stored. One of four patterns can be selected via the two in-
put logic decoder pins, A1 and A0. Data can be loaded on
the selected pattern. Each pattern can be either 16 or 32
bits wide. The SIZE pin determines whether they are 16 or
32 bits wide. SIZE = H will set the pattern to be 32 bits wide
while SIZE = L will set it to 16 bits wide. DIN1 is the input data
for the register. When CS1 is high, data will not be shifted in.
Data is shifted in only when CS1 is low.
DOUT
1
P-ch Pattern 1
N-ch Pattern 1
SCK
32 bits for P-ch Pattern 1
32 bits for N-ch Pattern 1
S64
S63
S34
S33
S32 S31
S2
S1
A 2-to-4 decoder is provided to select which of the four pat-
terns is to be used for all of the outputs. Logic inputs A1 and
A0 determine which patterns are selected per the decoder
truth table shown below. Once A1 and A0 are set, a rising
edge on the trigger logic input pin will automatically load the
With SIZE = H, the circuit is effectively a 64-bit serial shift
register. The data first enters into the P-channel register and selected pattern to all of the outputs.
continues to be shifted though to the N-channel register.
Data is clocked in during the rising edge of the clock. There
Decoder Truth Table
is no activity during the falling edge of the clock. The data,
DIN1, enters from the P-channel register and exits from the
N-channel register from DOUT1.
Logic Decoder Input
Pattern Selected
A1
0
A0
0
1
2
3
4
For size = High, 32 bits wide (size = Low, 16-bits wide)
A1 = A0 = Low, Pattern 1 selected
0
1
1
0
CS1 = Low, data can be shifted in
1
1
64-bit serial shift register: 32 bits for the P-channel and
32 bits for the N-channel
Data is shifted in during the rising edge of the clock. S1 is
the first bit shifted in, entering the P-channel register. After
64 clock cycles, S1 will be located in the N-channel register
as shown below. It will also be clocked out to DOUT1.
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
10
HV7351
though to the 6-bit register for the divide by N counter. Data
is clocked in during the rising edge of the clock. There is no
activity during the falling edge of the clock. The MSB bit in
the 6-bit divide-by-N register is clocked out into DOUT2 for
cascading multiple devices if desired.
Loading Data into the Delay Counters
and the Divide-by-N Counter
Each output channel, TX, has its own programmable 10-bit
delay counter. For 8 channels, 80 bits are needed. A 6-bit
divide-by-N counter is also provided to program the desired
TX frequency. To program all the individual delay counters
and the divide-by-N counter, an 86-bit serial shift register
is provided. It uses the same clock input that the pattern
registers uses. DIN2 is the input data for this register. When
CS2 is high, data will not be shifted in. Data is shifted in only
when CS2 is low.
10-Bit Delay Counter
The input clock for the 10-bit delay counter is the TCK pin.
The TCK pin is the only pin that is capable of high frequency,
200MHz. This helps maximum delay time resolution. The
counter counts upward. Please refer to the table below.
As shown below, the data first enters into the 10-bit regis-
ter for the TX8 delay counter and continues to be shifted
86-bit Serial Shift Register: 80 bits for the delay counters and 6 bits for the divide by N
10 bits Tx8 10 bits Tx7 10 bits Tx6 10 bits Tx5 10 bits Tx4 10 bits Tx3 10 bits Tx2
6 bits
divide by N
DIN2
SCK
DOUT
2
10 bits Tx1
10 bits for Tx8 delay Counter
10 bits for Tx7 delay Counter
6 bits for divide by N
S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67
S6 S5 S4 S3 S2 S1
LSB
MSB LSB
MSB
LSB
MSB
Delay Counter Table
MSB
LSB
Delay Time
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1023 TCK cycles
1022 TCK cycles
1021 TCK cycles
1020 TCK cycles
0
0
0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
3 TCK cycles
2 TCK cycles
1 TCK cycle
No trigger
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
11
HV7351
clock cycle will set the TX output to be either at VPP, VNN,
ground, or high impedance depending on what was prepro-
grammed in their corresponding registers.
6-Bit Divide-by-N Counter
The input clock for the 6-bit divide-by-N counter is the TCK
pin. It generates the clock frequency for the 16/32 bit serial
shift register for the output P- and N-channel patterns. Each
Output Shift Register
MSB
LSB
Clock Frequency
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
f
TCK ÷ 64
fTCK ÷ 63
fTCK ÷ 62
fTCK ÷ 61
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
fTCK ÷ 4
fTCK ÷ 3
fTCK ÷ 2
fTCK ÷ 1
Pin Description
Pin
Name
AVDD
DIN2
CS2
Description
1
Positive analog supply voltage (+5.0V).
2
Serial data in for delay counters and frequency divider.
Activates DIN2. Input logic high = off, input logic low = on.
3
4
SIZE
INV
Sets pattern width to either 16-bits or 32-bits. Logic low = 16-bits, logic high = 32-bits.
Inverts the TX output waveform. See logic truth table for details.
5
6
CW
Activates CW mode. Logic low = non-CW mode, logic high = CW mode. See logic truth table for details.
7
DOUT2 Data out for delay counters and frequency divider.
8
EN
Enables and disables device. Logic low = off, logic high = on.
Serial clock input for serial shift registers.
9
SCK
10
11
DVDD
Positive digital supply voltage (+5.0V).
DGND Digital ground.
Toggles all TX outputs to transmit. Needs to be high for 2 rising edges of TCK. Delay counters will
12
13
TRIG
start on the rising edge of the TCK pin right after the falling edge of the TRIG signal. See timing
diagram for details.
Transmitter clock for the delay counters and input frequency for the divide by N. Can be CMOS,
LVDS, or SSTL.
TCK
14
15
16
17
TCK
VLL
CS1
Logic trip point TCK. Can be set to a DC value from 0.4VLL to 0.6VLL or driven differentially with TCK.
Logic interface supply voltage (3.0V or 3.3V).
Activates DIN1. Input logic high = off, input logic low = on.
DOUT1 Data out for P-channel and N-channel pattern registers.
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
12
HV7351
Pin Description (cont.)
Pin
18
19
20
21
22
23
24
25
Name
Description
A0
Decoded to select 1 of 4 patterns to be loaded.
A1
DIN1
VRN
PVDD
PGND
PGND
PVSS
Serial data in for P-channel and N-channel pattern registers.
Negative supply for VPF regulator (-5.0V).
Positive gate drive supply voltage for RTZ output transistors (+5.0V).
Power ground path for RTZ output transistors.
Negative gate drive supply voltage for RTZ output transistors (-5.0V).
Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total.
26
27
28
VPF
NC
No connection.
Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total.
VNF
29
30
31
32
33
34
35
36
37
38
39
40
41
VNN
TX1
VPP
VPP
TX2
VNN
VNN
TX3
VPP
VPP
TX4
VNN
VNN
Negative high voltage supply (-3.0V to -70V).
Transmit pulser outputs for channel 1.
Positive high voltage supply (+3.0V to +70V).
Transmit pulser outputs for channel 2.
Negative high voltage supply (-3.0V to -70V).
Transmit pulser outputs for channel 3.
Positive high voltage supply (+3.0V to +70V).
Transmit pulser outputs for channel 4.
Negative high voltage supply (-3.0V to -70V).
Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total.
42
VNF
43
44
DGND Digital ground.
VPP
VPF
Positive high voltage supply (+3.0V to +70V).
Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total.
45
46
47
48
49
PGND
PVSS
PGND
PVDD
Power ground path for RTZ output transistors.
Negative gate drive supply voltage for RTZ output transistors (-5.0V).
Power ground path for RTZ output transistors.
Positive gate drive supply voltage for RTZ output transistors (+5.0V).
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
13
HV7351
Pin Description (cont.)
Pin
50
51
52
53
54
55
Name
Description
DVDD
Positive digital supply voltage (+5.0V).
DGND Digital ground.
PVDD
PGND
PVSS
PGND
Positive gate drive supply voltage for RTZ output transistors (+5.0V).
Power ground path for RTZ output transistors.
Negative gate drive supply voltage for RTZ output transistors (-5.0V).
Power ground path for RTZ output transistors.
Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total.
56
VPF
VPP
57
58
Positive high voltage supply (+3.0V to +70V).
DGND Digital ground.
Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF
59
VNF
ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total.
Negative high voltage supply (-3.0V to -70V).
Transmit pulser outputs for channel 5.
60
61
62
63
64
65
66
67
68
69
70
71
72
VNN
VNN
TX5
VPP
VPP
TX6
VNN
VNN
TX7
VPP
VPP
TX8
VNN
Positive high voltage supply (+3.0V to +70V).
Transmit pulser outputs for channel 6.
Negative high voltage supply (-3.0V to -70V).
Transmit pulser outputs for channel 7.
Positive high voltage supply (+3.0V to +70V).
Transmit pulser outputs for channel 8.
Negative high voltage supply (-3.0V to -70V).
Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total.
73
74
75
VNF
NC
No connection.
Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total.
VPF
76
77
78
79
80
PVSS
PGND
PGND
PVDD
VRP
Negative gate drive supply voltage for RTZ output transistors (-5.0V).
Power ground path for RTZ output transistors.
Positive gate drive supply voltage for RTZ output transistors (+5.0V).
Positive supply for VNF regulator (+5.0V).
VSUB
Exposed center pad. Needs to be externally connected to digital ground, DGND.
Doc.# DSFP-HV7351
NR050213
Supertex inc.
www.supertex.com
14
HV7351
80-Lead QFN Package Outline (K6)
11.00x11.00mm body, 1.00mm height (max), 0.50mm pitch
D
D2
80
1
80
1
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
e
b
E2
E
View B
Top View
Bottom View
Note 3
θ
L
A3
A
Seating
Plane
L1
Note 2
A1
View B
Side View
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded
metal marker; or a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Symbol
A
A1
A3
b
D
D2
E
E2
e
L
L1
0.00
-
θ
0O
-
MIN
NOM
MAX
0.80
0.90
1.00
0.00
0.02
0.05
0.18 10.90 9.50 10.90 9.50
0.30
0.40
0.50
Dimension
(mm)
0.20
REF
0.50
BSC
0.25
0.30
11.00
11.10
9.65
9.75
11.00
11.10
9.65
9.75
0.15
14O
Drawings are not to scale.
Supertex Doc.#: DSPD-80QFNK611X11P050, Version A111511
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-HV7351
NR050213
15
相关型号：
©2020 ICPDF网 联系我们和版权申明