LP0701_13 [SUPERTEX]

P-Channel Enhancement-Mode Lateral MOSFET;


型号：	LP0701_13
厂家：	Supertex, Inc
描述：	P-Channel Enhancement-Mode Lateral MOSFET
文件：	总6页 (文件大小：769K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Supertex inc.

LP0701

P-Channel Enhancement-Mode

Lateral MOSFET

Features

General Description

► Ultra-low threshold

These enhancement-mode (normally-off) transistors utilize

a lateral MOS structure and Supertex’s well-proven silicon-

gate manufacturing process. This combination produces

devices with the power handling capabilities of bipolar

transistors and with the high input impedance and negative

temperature coefﬁcient inherent in MOS devices.

► High input impedance

► Low input capacitance

► Fast switching speeds

► Low on-resistance

► Freedom from secondary breakdown

► Low input and output leakage

Characteristic of all MOS structures, these devices are free

from thermal runaway and thermally induced secondary

breakdown. The low threshold voltage and low on-resistance

characteristics are ideally suited for hand held, battery

operated applications.

Applications

► Logic level interfaces

► Solid state relays

► Battery operated systems

► Photo voltaic drives

► Analog switches

► General purpose line drivers

Ordering Information

Product Summary

Part Number

Package Options

8-Lead SOIC

TO-92

Packing

BV_DSS/BV_DGS

R_DS(ON)

V_GS(TH)

I_D(ON)

LP0701LG-G

2500/Reel

1000/Bag

2000/Reel

-16.5V

3.0kΩ

-1.0V (max) 3.0mA (min)

LP0701N3-G

LP0701N3-G P002

LP0701N3-G P003

LP0701N3-G P005

LP0701N3-G P013

LP0701N3-G P014

TO-92

Pin Conﬁguration

TO-92

DRAIN

SOURCE

TO-92

-G denotes a lead (Pb)-free / RoHS compliant package

Refer to ‘P0xx’ Tape & Reel Specs for P002, P003, P005, P013, and P014

TO-92 Taping Speciﬁcations and Winding Styles

GATE

8-Lead SOIC

TO-92

Product Marking

Absolute Maximum Ratings

Parameter

YY = Year Sealed

WW = Week Sealed

L = Lot Number

= “Green” Packaging

YYWW

Value

BV_DSS

P0701

Drain-to-source voltage

Drain-to-gate voltage

Gate-to-source voltage

Operating and storage temperature

LLLL

BV_DGS

Package may or may not include the following marks: Si or

8-Lead SOIC

±10V

-55°C to +150°C

SiLP

0 7 0 1

YYWW

YY = Year Sealed

Absolute Maximum Ratings are those values beyond which damage to the device may

occur. Functional operation under these conditions is not implied. Continuous operation

of the device at the absolute rating level may affect device reliability. All voltages are

referenced to device ground.

WW = Week Sealed

= “Green” Packaging

Package may or may not include the following marks: Si or

TO-92

Doc.# DSFP-LP0701

B071513

Supertex inc.

www.supertex.com

LP0701

Thermal Characteristics

I_D

Power Dissipation

†

θ_ja

(^OC/W)

I_DR

(mA)

I_DRM

(A)

(continuous)^†

(mA)

(pulsed)^†

(A)

@T_C= 25^OC

(W)

Package

8-Lead SOIC

TO-92

-700

-500

-1.25

1.5^‡

1.0

101^‡

132

-700

-500

-1.25

Notes:

†

‡

I_D(continuous) is limited by max rated T_j.

Mounted on FR4 board, 25mm x 25mm x 1.57mm

Electrical Characteristics (T_A= 25°C unless otherwise speciﬁed)

Sym

BV_DSS

V_GS

Parameter

Min

Typ

Max

Units

Conditions

Drain-to-source breakdown voltage

Gate threshold voltage

-16.5

V_GS= 0V, I_D= -1.0mA

V_GS= V_DS, I_D= -1.0mA

-0.5

-0.7

-1.0

-4.0

-100

ΔV_GS(th)Change in V_GS(th)with temperature

mV/^OC V_GS= V_DS, I_D= -1.0mA

I_GSS

Gate body leakage

V_GS= ±10V, V_DS= 0V

V_DS= -15V, V_GS= 0V

I_DSS

Zero gate voltage drain current

V_DS= 0.8 Max Rating,

V_GS= 0V, T_A= 125^OC

-1.0

-0.4

-1.0

-2.30

2.0

1.7

1.3

V_GS= V_DS= -2.0V

V_GS= V_DS= -3.0V

I_D(ON)

On-state drain current

-0.6

-1.25

_GS= V_DS= -5.0V

V_GS= -2.0V, I_D= -50mA

_GS= -3.0V, I_D= -150mA

4.0

2.0

1.5

0.75

Static drain-to-source on-state

resistance

R_DS(ON)

V_GS= -5.0V, I_D= -300mA

ΔR_DS(ON)Change in R_DS(ON)with temperature

%/^OC

G_FS

C_ISS

C_OSS

C_RSS

t_d(ON)

t_r

Forward transconductance

Input capacitance

500

700

120

100

mmho V_GS= -15V, I_D= -1.0A

250

125

-1.5

V_GS= 0V,

V_DS= -15V,

f = 1.0MHz

Common source output capacitance

Reverse transfer capacitance

Turn-on delay time

V_DD= -15V,

I_D= -1.25A,

R_GEN= 25Ω

Rise time

t_d(OFF)

t_f

Turn-off delay time

Fall time

V_SD

Diode forward voltage drop

-1.2

V_GS= 0V, I_SD= -500mA

Notes:

1. All D.C. parameters 100% tested at 25^OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)

2. All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

Pulse

10%

Generator

INPUT

R_GEN

90%

t_(OFF)

-10V

t_(ON)

t_d(ON)

D.U.T.

t_r

t_d(OFF)

t_f

INPUT

OUTPUT

R_L

90%

OUTPUT

VDD

10%

VDD

Doc.# DSFP-LP0701

B071513

Supertex inc.

www.supertex.com

LP0701

Typical Performance Curves

Output Characteristics

Saturation Characteristics

V_GS= -5.0V

-2.5

-2.0

-1.5

-1.0

-0.5

V_GS= -5.0V

-2.0

-1.5

-1.0

-0.5

-4V

-3V

-2V

-1V

-2V

-1V

-4

-8

-12

-16

-1

-2

-3

-4

-5

V_DS(volts)

Transconductance vs. Drain Current

V_DS= -15V

Power Dissipation vs. Case Temperature

1.0

0.8

0.6

0.4

0.2

T_A= -55^OC

SO-8

T_A= 25^OC

TO-92

T_A= 125^OC

⁰0

-1.0

-2.0

100

125

150

T_C(^OC)

I_D(amperes)

Maximum Rated Safe Operating Area

TO-92/SO-8 (pulsed)

Thermal Response Characteristics

-10

1.0

0.8

0.6

-1.0

-0.1

TO-92 (DC)

SO-8 (DC)

TO-92

T = 25V

P^C_D= 1.0W

0.4

0.2

T_C= 25^OC

-0.01

-0.1

-1.0

-10

-100

0.001

0.01

0.1

1.0

V_DS(volts)

t_p(seconds)

Doc.# DSFP-LP0701

B071513

Supertex inc.

www.supertex.com

LP0701

Typical Performance Curves (cont.)

BV_DSSVariation with Temperature

On-Resistance vs. Drain Current

V_GS= -2.0V

1.1

V_GS= -3.0V

V_GS= -5.0V

1.0

0.9

-1

-3

-50

100

150

-2

I_D(amperes)

T_J(^OC)

V_(th)and R_DSVariation with Temperature

V_(th)@ -1.0mA

Transfer Characteristics

V_DS= -15V

1.4

1.2

1.0

0.8

0.6

0.4

1.6

-2

-1

1.4

1.2

1.0

0.8

0.6

_A= -55^O

T_A= 25^O

T_A= 125^O

R_DS(ON)@ -5V, -300mA

-1

-2

-3

-4

-5

-50

100

150

T_J(^OC)

V_{GS (volts)}

Capacitance vs. Drain-to-Source Voltage

f = 1.0MHz

Gate Drive Dynamic Characteristics

V_DS= -10V

200

-10

-8

-6

-4

-2

-20V

C_ISS

100

238pF

C_OSS

C_RSS

C_ISS= 115pF

-5

-10

-15

Q_G(nanocoulombs)

V_DS(volts)

Doc.# DSFP-LP0701

B071513

Supertex inc.

www.supertex.com

LP0701

8-Lead SOIC (Narrow Body) Package Outline (LG)

θ1

Note 1

(Index Area

D/2 x E1/2)

Gauge

Plane

Seating

Plane

Top View

View B

Note 1

Seating

Plane

Side View

View A-A

Note:

1. This chamfer feature is optional. A Pin 1 identiﬁer must be located in the index area indicated. The Pin 1 identiﬁer can be: a molded mark/identiﬁer;

an embedded metal marker; or a printed indicator.

Symbol

0^O

θ1

5^O

MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*

NOM 4.90 6.00 3.90

MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00*

0.25 0.40

Dimension

(mm)

1.27

BSC

1.04 0.25

REF BSC

0.50 1.27

8^O

15^O

JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.

* This dimension is not speciﬁed in the JEDEC drawing.

Drawings are not to scale.

Supertex Doc. #: DSPD-8SOLGTG, Version I041309.

Doc.# DSFP-LP0701

B071513

Supertex inc.

www.supertex.com

LP0701

3-Lead TO-92 Package Outline (N3)

Seating

Plane

Side View

Front View

Bottom View

Symbol

.170

.014^†

.175

.125

.095

.045

.500

MIN

NOM

MAX

.014^†

.080

Dimensions

(inches)

.210

.022^†

.205

.165

.105

.055

.610*

JEDEC Registration TO-92.

* This dimension is not speciﬁed in the JEDEC drawing.

† This dimension differs from the JEDEC drawing.

Drawings not to scale.

Supertex Doc.#: DSPD-3TO92N3, Version E041009.

(The package drawing(s) in this data sheet may not reﬂect the most current speciﬁcations. For the latest package outline

information go to http://www.supertex.com/packaging.html.)

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives

an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability

to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and

specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888

www.supertex.com

Doc.# DSFP-LP0701

B071513

LP0701_13 [SUPERTEX]

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