TC2320_07 [SUPERTEX]

N- and P-Channel Enhancement-Mode Dual MOSFET; N和P沟道增强型MOSFET双


型号：	TC2320_07
厂家：	Supertex, Inc
描述：	N- and P-Channel Enhancement-Mode Dual MOSFET N和P沟道增强型MOSFET双
文件：	总4页 (文件大小：481K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC2320

N- and P-Channel Enhancement-Mode Dual MOSFET

Features

General Description

The Supertex TC2320TG consists of a high voltage, low

threshold N- and P-channel MOSFET in an SO-8 package.

These low threshold enhancement-mode (normally-off)

transistors utilize an advanced vertical DMOS structure

and Supertex’s well-proven silicon-gate manufacturing

process. This combination produces devices with the

power handling capabilities of bipolar transistors and

with the high input impedance and positive temperature

coefﬁcient inherent in MOS devices. Characteristic of

all MOS structures, these devices are free from thermal

runaway and thermally-induced secondary breakdown.

► Low threshold

► Low on resistance

► Low input capacitance

► Fast switching speeds

► Freedom from secondary breakdown

► Low input and output leakage

► Independent, electrically isolated N- and P-

channels

Applications

► Medical ultrasound transmitters

► High voltage pulsers

► Ampliﬁers

Supertex’s vertical DMOS FETs are ideally suited to a

wide range of switching and amplifying applications where

very low threshold voltage, high breakdown voltage, high

input impedance, low input capacitance, and fast switching

speeds are desired.

► Buffers

► Piezoelectric transducer drivers

► General purpose line drivers

► Logic level interface

Ordering Information

R_DS(ON)

BV_DSS/BV_DGS

Package Options

Device

(max)

(V)

(Ω)

8-Lead SOIC (Narrow Body)

N-Channel

P-Channel

N-Channel

P-Channel

TC2320

TC2320TG-G

200

-200

7.0

-G indicates package is RoHS compliant (‘Green’)

Pin Conﬁguration

DRAIN_P

DRAIN_N

Absolute Maximum Ratings

Parameter

GATE_P

SOURCE_P

GATE_N

SOURCE_N

Value

BV_DSS

Drain to source voltage

Drain to gate voltage

BV_DGS

8-Lead SOIC (TG)

Gate to source voltage

20V

Product Marking

Operating and storage temperature

-55°C to +150°C

YY = Year Sealed

WW = Week Sealed

L = Lot Number

YYWW

Soldering temperature*

+300°C

C2320

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

LLLL

= “Green” Packaging

8-Lead SOIC (TG)

* Distance of 1.6mm from case for 10 seconds.

TC2320

N-Channel Electrical Characteristics (@ 25°C unless otherwise speciﬁed)

Symbol Parameter

Min

Typ

Max

Units

Conditions

BV_DSS

V_GS(th)

Drain-to-source breakdown voltage

Gate threshold voltage

200

V_GS= 0V, I_D= 100µA

V_GS= V_DS, I_D= 1.0mA

0.6

2.0

-4.5

100

1.0

ΔV_GS(th)Change in V_GS(th)with temperature

mV/^OC V_GS= V_DS, I_D= 1.0mA

I_GSS

Gate body leakage

µA

V_GS= 20V, V_DS= 0V

V_GS= 0V, V_DS= 100V

V_GS= 0V,

10.0

1.0

µA

I_DSS

Zero gate voltage drain current

V_DS= Max rating

V_GS= 0V, T_A= 125^OC

V_DS= 0.8 Max Rating

0.6

V_GS= 4.5V, V_DS= 25V

I_D(ON)

ON-state drain current

1.2

V_GS= 10V, V_DS= 25V

8.0

7.0

1.0

V_GS= 4.5V, I_D= 150mA

V_GS= 10V, I_D= 1.0A

V_GS= 4.5V, I_D=150mA

Static drain-to-source

ON-state resistance

R_DS(ON)

ΔR_DS(ON)Change in R_DS(ON)with temperature

150

%/^OC

G_FS

C_ISS

C_OSS

C_RSS

t_d(ON)

t_r

Forward transconductance

Input capacitance

mmho V_DS= 25V, I_D= 200mA

110

1.8

V_GS= 0V,

V_DS= 25V,

f = 1.0MHz

Common source output capacitance

Reverse transfer capacitance

Turn-ON delay time

V_DD=25V,

I_D= 150mA,

R_GEN= 25Ω

Rise time

t_d(OFF)

t_f

Turn-OFF delay time

Fall time

V_SD

Diode forward voltage drop

Reverse recovery time

V_GS= 0V, I_SD= 200mA

t_rr

300

Notes:

1.All D.C. parameters 100% tested at 25^OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)

2.All A.C. parameters sample tested.

N- Channel Switching Waveforms and Test Circuit

V_DD

R_L

10V

90%

INPUT

PULSE

GENERATOR

10%

OUTPUT

t_(ON)

t_d(ON)

t_(OFF)

t_d(OFF)

R_GEN

t_r

t_F

V_DD

D.U.T.

10%

INPUT

OUTPUT

90%

TC2320

P-Channel Electrical Characteristics (@ 25°C unless otherwise speciﬁed)

Symbol Parameter

Min

Typ

Max

Units

Conditions

BV_DSS

V_GS(th)

Drain-to-source breakdown voltage

Gate threshold voltage

-200

V_GS= 0V, I_D= -2.0mA

V_GS= V_DS, I_D= -1.0mA

-1.0

-2.4

4.5

-100

-10

ΔV_GS(th)Change in V_GS(th)with temperature

mV/^OC V_GS= V_DS, I_D= -1.0mA

I_GSS

Gate body leakage

µA

V_GS= 20V, V_DS= 0V

V_GS= 0V, V_DS= Max rating

V_GS= 0V, T_A= 125^OC,

I_DSS

Zero gate voltage drain current

-1.0

V_DS= 0.8 Max Rating

-0.25

-0.7

-2.1

8.0

V_GS= -4.5V, V_DS= -25V

V_GS= -10V, V_DS= -25V

V_GS= -4.5V, I_D= -100mA

V_GS= -10V, I_D= -200mA

V_GS= -10V, I_D=-200mA

I_D(ON)

ON-state drain current

-0.75

1.7

Static drain-to-source ON-state resis-

tance

R_DS(ON)

ΔR_DS(ON)Change in R_DS(ON)with temperature

100

%/^OC

G_FS

C_ISS

C_OSS

C_RSS

t_d(ON)

t_r

Forward transconductance

Input capacitance

250

mmho V_DS= -25V, I_D= -200mA

125

-1.8

V_GS= 0V,

V_DS= -25V,

f = 1.0MHz

Common source output capacitance

Reverse transfer capacitance

Turn-ON delay time

Rise time

---

t_d(OFF)

t_f

Turn-OFF delay time

Fall time

V_SD

Diode forward voltage drop

Reverse recovery time

V_GS= 0V, I_SD= -0.5A

t_rr

300

Notes:

1.All D.C. parameters 100% tested at 25^OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)

2.All A.C. parameters sample tested.

P- Channel Switching Waveforms and Test Circuit

PULSE

10%

GENERATOR

INPUT

R_GEN

-10V

90%

t_(OFF)

t_(ON)

t_d(ON)

D.U.T.

Output

t_d(OFF)

t_F

t_r

INPUT

90%

R_L

OUTPUT

10%

V_DD

TC2320

8-Lead SOIC (Narrow Body) Package Outline (TG)

4.9x3.9mm body, 1.75mm height (max), 1.27mm pitch

θ1

Gauge

Plane

Note 1

(Index Area

D/2 x E1/2)

Seating

Plane

Top View

View B

Note 1

Seating

Plane

Side View

View A-A

Note 1:

This chamfer feature is optional. If it is not present, then a Pin 1 identiﬁer must be located in the index area indicated.The Pin 1 identiﬁer may be either a

mold, or an embedded metal or marked feature.

Symbol

1.35

0.10

1.25

0.31

0.25

0.40

0^O

θ1

5^O

MIN

NOM

MAX

4.80

4.90

5.00

5.80

6.00

6.20

3.80

3.90

4.00

Dimension

(mm)

1.27

BSC

1.04

REF

0.25

BSC

1.75

0.25

1.50

0.51

0.50

1.27

8^O

15^O

JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.

Drawings not to scale.

(The package drawing(s) in this data sheet may not reﬂect the most current speciﬁcations. For the latest package outline

information go to http://www.supertex.com/packaging.html.)

Doc.# DSFP-TC2320

A102607

TC2320_07 [SUPERTEX]

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