TC6320_07 [SUPERTEX]
N- and P- Channel Enhancement-Mode Dual MOSFET; N-和P-沟道增强型MOSFET双
| 型号： | TC6320_07 |
| 厂家： | 
Supertex, Inc |
| 描述： | N- and P- Channel Enhancement-Mode Dual MOSFET |
| 文件： | 总4页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC6320
N- and P- Channel Enhancement-Mode Dual MOSFET
Features
General Description
The Supertex TC6320 consists of high voltage low
threshold N-channel and P-channel MOSFETs in an SO-
8 package. Both MOSFETs have integrated gate-source
resistors and gate-source zener diode clamps which are
desired for high voltage pulser applications. The TC6320 is
a complimentary, high-speed, high voltage, gate-clamped
N- and P-channel MOSFET pair in an SO-8 package.
These low threshold enhancement-mode (normally-off)
transistors utilize an advanced vertical DMOS structure
and Supertex’s well-proven silicon-gate manufacturing
process. This combination produces devices with the
power handling capabilities of bipolar transistors and
with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of
all MOS structures, these devices are free from thermal
runaway and thermally induced secondary breakdown.
► Low threshold
► Low on resistance
► Low input capacitance
► Fast switching speeds
► Freedom from secondary breakdown
► Low input and output leakage
► Independent, electrically isolated N- and P-
channels
Applications
► Medical ultrasound transmitters
► High voltage pulsers
► Amplifiers
► Buffers
► Piezoelectric transducer drivers
► General purpose line drivers
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Package Options
BVDSS/BVDGS
RDS(ON) (MAX)
Device
8-Lead SOIC (Narrow Body)
N-Channel
200V
P-Channel
N-Channel
P-Channel
-200V
7.0Ω
8.0Ω
TC6320
TC6320TG
TC6320TG-G
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
S1
G1
S2
G2
1
2
3
4
8
7
6
5
D1
D1
D2
D2
Absolute Maximum Ratings
Parameter
Value
N-Channel
Drain to source voltage
BVDSS
BVDGS
Drain to gate voltage
Operating and storage temperature
Soldering temperature1
-55°C to +150°C
+300°C
P-Channel
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
SO-8 Package
(top view)
Note 1. Distance of 1.6mm from case for 10 seconds.
TC6320
N- Channel Electrical Characteristics (TJ = 25°C unless otherwise specified)
Symbol Parameter
Min
200
1.0
-
Typ
Max
-
Units
V
Conditions
BVDSS
VGS(th)
Drain-to-source breakdown voltage
Gate threshold voltage
-
-
-
-
-
-
VGS = 0V, ID = 2.0mA
VGS = VDS, ID = 1.0mA
2.0
-4.5
50
V
ΔVGS(th) Change in VGS(th) with temperature
mV/OC VGS = VDS, ID = 1.0mA
RGS
ΔRGS
VZGS
Gate-Source Shunt Resistor
Change in RGS with Temperature
Gate-Source Zener Voltage
10
-
KΩ
%/OC
V
IGS = 100µA
IGS = 100µA
IGS = 2.0mA
TBD
25
13.2
-
ΔVZGS Change in VZGS with Temperature
TBD
10.0
mV/OC IGS = 2.0mA
-
-
-
µA
VDS = Max rating, VGS = 0V
IDSS
Zero gate voltage drain current
ON-state drain current
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
-
1.0
mA
1.0
-
-
-
VGS = 4.5V, VDS = 25V
VGS = 10V, VDS = 25V
VGS = 4.5V, ID = 150mA
VGS = 10V, ID = 1.0A
VGS = 4.5V, ID =150mA
ID(ON)
A
2.0
-
-
-
8.0
7.0
1.0
-
Static drain-to-source ON-state resis-
tance
RDS(ON)
Ω
-
-
ΔRDS(ON) Change in RDS(ON) with temperature
-
-
%/OC
GFS
CISS
COSS
CRSS
td(ON)
tr
Forward transconductance
Input capacitance
400
-
mmho VDS = 25V, ID = 200mA
-
-
-
-
-
-
-
-
-
-
110
60
23
10
15
20
15
1.8
-
VGS = 0V,
VDS = 25V,
f = 1MHz
Common source output capacitance
Reverse transfer capacitance
Turn-ON delay time
-
pF
ns
-
-
VDD =25V,
ID = 1.0A,
RGEN = 25Ω
Rise time
-
td(OFF)
tf
Turn-OFF delay time
Fall time
-
-
-
VSD
Diode forward voltage drop
Reverse recovery time
V
VGS = 0V, ISD = 0.5A
VGS = 0V, ISD = 0.5A
trr
300
ns
Notes:
1.All D.C. parameters 100% tested at 25C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.)
2.All A.C. parameters sample tested.
N- Channel Switching Waveforms and Test Circuit
VDD
10V
90%
RL
Input
Pulse
OUTPUT
Generator
10%
0V
t(ON)
td(ON)
t(OFF)
td(OFF)
RGEN
Input
D.U.T
tr
tf
VDD
10%
10%
90%
Output
0V
90%
2
TC6320
P- Channel Electrical Characteristics (TJ = 25°C unless otherwise specified)
Symbol Parameter
Min
Typ
Max
-
Units
V
Conditions
BVDSS
VGS(th)
Drain-to-source breakdown voltage
Gate threshold voltage
-200
-
-
-
-
-
-
-
-
VGS = 0V, ID = -2.0µA
VGS = VDS, ID = -1.0mA
-1.0
-2.4
4.5
50
V
ΔVGS(th) Change in VGS(th) with temperature
-
mV/OC VGS = VDS, ID = -1.0mA
RGS
ΔRGS
VZGS
Gate-source shunt resistor
Change in RGS with temperature
Gate-source zener voltage
10
KΩ
%/OC
V
IGS = 100µA
IGS = 100µA
IGS = -2mA
-
TBD
25
13.2
ΔVZGS Change in RGS with temperature
-
-
TBD
-10
mV/OC IGS = -2mA
µA
VDS = Max rating, VGS = 0V
IDSS
Zero gate voltage drain current
ON-state drain current
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
-
-
-1.0
mA
-1.0
-
-
-
VGS = -4.5V, VDS = -25V
VGS = -10V, VDS = -25V
VGS = -4.5V, ID = -150mA
VGS = -10V, ID = -1.0A
VGS = -10V, ID =-200mA
ID(ON)
A
-2.0
-
-
-
10
8.0
1.0
-
Static drain-to-source ON-state resis-
tance
RDS(ON)
Ω
-
-
ΔRDS(ON) Change in RDS(ON) with temperature
-
-
%/OC
GFS
CISS
COSS
CRSS
td(ON)
tr
Forward transconductance
Input capacitance
400
-
mmho VDS = -25V, ID = -200mA
-
-
-
-
-
-
-
-
-
-
200
55
30
10
15
20
15
-1.8
-
VGS = 0V,
VDS = -25V,
f = 1MHz
Common source output capacitance
Reverse transfer capacitance
Turn-ON delay time
-
pF
ns
-
-
VDD = -25V,
ID = -1.0A,
RGEN = 25Ω
Rise time
-
td(OFF)
tf
Turn-OFF delay time
Fall time
-
-
-
VSD
Diode forward voltage drop
Reverse recovery time
V
VGS = 0V, ISD = -0.5A
VGS = 0V, ISD = -0.5A
trr
300
ns
Notes:
1.All D.C. parameters 100% tested at 25C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.)
2.All A.C. parameters sample tested.
P- Channel Switching Waveforms and Test Circuit
Pulse
Generator
0V
10%
Input
RGEN
90%
D.U.T
-10V
t(ON)
td(ON)
t(OFF)
td(OFF)
Input
tr
tf
OUTPUT
0V
90%
10%
90%
10%
Output
VDD
RL
VDD
3
TC6320
8-Lead SO (TG) Package Outline
4.90 0.10
8
6.00 0.20
Note 2
3.90 0.10
1
5° - 15°
(4 PLCS)
0.25 - 0.50
Note 2
Top View
45°
0.17 - 0.25
1.25 MIN
1.75 MAX
0° - 8°
0.40 - 1.27
0.10 - 0.25
Notes:
0.31 - 0.51
1.27BSC
End View
Side View
1. All dimensions in millimeters. Angles in degrees.
2. If the corner is not chamfered, then a Pin 1 identifier
must be located within the area indicated.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-TC6320
C112106
4
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