TC8220K6-G [SUPERTEX]
Two Pair, N- and P-Channel Enhancement-Mode MOSFET;
| 型号： | TC8220K6-G |
| 厂家： | 
Supertex, Inc |
| 描述： | Two Pair, N- and P-Channel Enhancement-Mode MOSFET |
| 文件： | 总6页 (文件大小：585K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supertex inc.
TC8220
Two Pair, N- and P-Channel
Enhancement-Mode MOSFET
Features
General Description
► High voltage Vertical DMOS technology
► Integrated gate-to-source resistor
► Integrated gate-to-source Zener diode
► Low threshold, Low on-resistance
► Low input & output capacitance
► Fast switching speeds
The Supertex TC8220 consists of two pairs of high voltage, low
threshold N-channel and P-channel MOSFETs in a 12-Lead DFN
package.AllMOSFETshaveintegratedthe gate-to-sourceresistors
and gate-to-source Zener diode clamps which are desired for high
voltage pulser applications. The complimentary, high-speed, high
voltage, gate-clamped N and P-channel MOSFET pairs utilize an
advanced vertical DMOS structure and Supertex’s well-proven
silicon-gate manufacturing process. This combination produces a
device with the power handling capabilities of bipolar transistors
and with the high input impedance and positive temperature
coefficient inherent in MOS devices.
► Electrically isolated N- and P-MOSFET pairs
Applications
► High voltage pulsers
► Amplifiers
► Buffers
Characteristic of all MOS structures, these devices are free from
thermal runaway and thermally induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
and output capacitance, and fast switching speeds are desired.
► Piezoelectric transducer drivers
► General purpose line drivers
► Logic level interfaces
Typical Application Circuit
VPP
+100V
+10V
0.47µF
1.0µF
0.1µF
VDD
VH
OUTA
OE
ENAB
INA
+PULSE
1.8 to 5.0V
Logic Imputs
VNN
OUTB
INB
INC
-100V
-PULSE
DAMP
OUTC
OUTD
1.0µF
IND
GND
VSS
VL
Supertex
MD1822
10nF
Supertex
Doc.# DSFP-TC8220
B080713
Supertex inc.
www.supertex.com
TC8220
Ordering Information
Product Summary
BVDSS/BVDGS
RDS(ON) (max)
Part Number
Package Option
Packing
N-Channel
P-Channel
N-Channel
P-Channel
TC8220K6-G
-G denotes a lead (Pb)-free / RoHS compliant package
12-Lead DFN (4x4)
3000/Reel
200V
-200V
5.3Ω
6.5Ω
Absolute Maximum Ratings
Parameter
Pin Configuration
Value
1
2
3
4
5
6
GN1
GP1
GN2
SN2
GP2
SP2
12
11
SN1
DN1
DP1
SP1
DN2
DP2
Drain-to-source voltage
BVDSS
BVDGS
Thermal
Pad
Drain-to-gate voltage
10
9
Operating and storage temperature
-55°C to +150°C
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
8
7
12-Lead DFN
(top view)
Typical Thermal Resistance
Package
θja
Package Marking
12-Lead DFN
42OC/W
Y = Last Digit of Year Sealed
W = Code for Week Sealed
L = Lot Number
Note:
8220
1.0oz, 4-layer, 3”x4” PCB.
YWLL
= “Green” Packaging
Package may or may not include the following marks: Si or
12-Lead DFN
Doc.# DSFP-TC8220
B080713
Supertex inc.
www.supertex.com
2
TC8220
N-Channel Electrical Characteristics (TA = 25°C unless otherwise specified)
Sym
BVDSS
VGS(th)
Parameter
Min
200
1.0
-
Typ
Max
Units Conditions
Drain-to-source breakdown voltage
Gate threshold voltage
-
-
-
-
-
-
-
V
V
VGS = 0V, ID = 2.0mA
VGS = VDS, ID = 1.0mA
2.4
-4.5
50
ΔVGS(th) Change in VGS(th) with temperature
mV/OC VGS = VDS, ID = 1.0mA
RGS
Gate-to-source shunt resistor
Gate-to-source Zener voltage
10
KΩ
V
IGS = 100µA
VZGS
13.2
-
25
IGS = 2.0mA
10.0
µA
VDS = Max rating, VGS = 0V
IDSS
Zero gate voltage drain current
On-state drain current
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
-
-
1.0
mA
A
1.3
-
-
-
VGS = 5.0V, VDS = 25V
VGS = 10V, VDS = 50V
VGS = 5.0V, ID = 150mA
ID(ON)
2.3
-
-
-
6.5
6.0
1.0
-
RDS(ON) Static drain-to-source on-state resistance
Ω
-
-
VGS = 10V, ID = 1.0A
ΔRDS(ON) Change in RDS(ON) with temperature
-
-
-
%/OC VGS = 10V, ID =1.0A
GFS
CISS
COSS
CRSS
td(ON)
tr
Forward transconductance
Input capacitance
400
mmho VDS = 25V, ID = 500mA
-
-
-
-
-
-
-
-
-
56
13
2.0
-
-
VGS = 0V,
VDS = 25V,
f = 1.0MHz
Common source output capacitance
Reverse transfer capacitance
Turn-on delay time
-
pF
ns
-
10
15
20
15
1.8
-
VDD =25V,
ID = 1.0A,
RGEN = 25Ω
Rise time
-
td(OFF)
tf
Turn-off delay time
-
Fall time
-
VSD
Diode forward voltage drop
Reverse recovery time
-
V
VGS = 0V, ISD = 500mA
VGS = 0V, ISD = 500mA
trr
300
ns
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
N-Channel Switching Waveforms and Test Circuit
10V
90%
VDD
INPUT
RL
10%
Pulse
0V
OUTPUT
Generator
t(ON)
td(ON)
10%
t(OFF)
td(OFF)
RGEN
tr
tf
D.U.T
VDD
OUTPUT
0V
10%
90%
INPUT
90%
Doc.# DSFP-TC8220
B080713
Supertex inc.
www.supertex.com
3
TC8220
P-Channel Electrical Characteristics (TA = 25°C unless otherwise specified)
Sym
BVDSS
VGS(th)
Parameter
Min
-200
-1.0
-
Typ
Max
Units Conditions
Drain-to-source breakdown voltage
Gate threshold voltage
-
-
-
-
-
-
-
V
V
VGS = 0V, ID = -2.0mA
VGS = VDS, ID = -1.0mA
-2.4
4.5
50
ΔVGS(th) Change in VGS(th) with temperature
mV/OC VGS = VDS, ID = -1.0mA
RGS
Gate-to-source shunt resistor
Gate-to-source Zener voltage
10
KΩ
V
IGS = 100µA
VZGS
13.2
-
25
IGS = -2.0mA
-10
µA
VDS = Max rating, VGS = 0V
IDSS
Zero gate voltage drain current
On-state drain current
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
-
-
-1.0
mA
A
-1.2
-
-
-
VGS = -5.0V, VDS = -25V
VGS = -10V, VDS = -50V
VGS = -5.0V, ID = -150mA
VGS = -10V, ID = -1.0A
VGS = -10V, ID = -1.0A
ID(ON)
-2.3
-
-
-
8.5
7.0
1.0
-
RDS(ON) Static drain-to-source on-state resistance
Ω
-
-
ΔRDS(ON) Change in RDS(ON) with temperature
-
-
-
%/OC
GFS
CISS
COSS
CRSS
td(ON)
tr
Forward transconductance
Input capacitance
400
mmho VDS = -25V, ID = -500mA
-
-
-
-
-
-
-
-
-
75
21
6.5
-
-
VGS = 0V,
VDS = -25V,
f = 1.0MHz
Common source output capacitance
Reverse transfer capacitance
Turn-on delay time
-
pF
ns
-
10
15
20
15
-1.8
-
VDD = -25V,
ID = -1.0A,
RGEN = 25Ω
Rise time
-
td(OFF)
tf
Turn-off delay time
-
Fall time
-
VSD
Diode forward voltage drop
Reverse recovery time
-
V
VGS = 0V, ISD = -500mA
VGS = 0V, ISD = -500mA
trr
300
ns
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
P-Channel Switching Waveforms and Test Circuit
0V
10%
Pulse
Generator
INPUT
90%
RGEN
-10V
D.U.T
t(ON)
td(ON)
t(OFF)
td(OFF)
90%
INPUT
tr
tf
OUTPUT
0V
OUTPUT
VDD
90%
10%
RL
VDD
10%
Doc.# DSFP-TC8220
B080713
Supertex inc.
www.supertex.com
4
TC8220
Pin Description
Pin #
Function Description
Pin #
7
Function Description
1
2
3
4
5
6
GN1
GP1
GN2
SN2
GP2
SP2
Gate of N-MOSFET 1
Gate of P-MOSFET 1
Gate of N-MOSFET 2
Source of N-MOSFET 2
Gate of P-MOSFET 2
Source of P-MOSFET 2
DP2
DN2
SP1
DP1
DN1
SN1
Drain of P-MOSFET 2
Drain of N-MOSFET 2
8
9
Source of P-MOSFET 1
Drain of P-MOSFET 1
Drain of N-MOSFET 1
Source of N-MOSFET 1
10
11
12
Thermal Pad
Die attachment substrate, must be grounded externally
Note:
Thermal Pad must be grounded.
Doc.# DSFP-TC8220
B080713
Supertex inc.
www.supertex.com
5
TC8220
12-Lead DFN Package Outline (K6)
4.00x4.00mm body, 1.00mm height (max), 0.50mm pitch
D
D2
12
12
E
E2
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
e
1
b
1
View B
Top View
Side View
Bottom View
Note 3
L
θ
A3
A
Seating
Plane
L1
Note 2
A1
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Symbol
A
A1
A3
b
D
D2
E
E2
e
L
L1
0.00
-
θ
0O
-
MIN
NOM
MAX
0.80
0.90
1.00
0.00
0.02
0.05
0.18
0.25
0.30
3.85
4.00
4.15
3.19
3.34
3.44
3.85
4.00
4.15
2.29
2.44
2.54
0.30
0.40
0.50
Dimension
(mm)
0.20
REF
0.50
BSC
0.15
14O
Drawings not to scale.
Supertex Doc.#: DSPD-12DFNK64X4P050, Version A030210.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-TC8220
B080713
6
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