TN0702N3-GP003 [SUPERTEX]

N-Channel Enhancement-Mode Vertical DMOS FET;


型号：	TN0702N3-GP003
厂家：	Supertex, Inc
描述：	N-Channel Enhancement-Mode Vertical DMOS FET 输入元件开关晶体管
文件：	总5页 (文件大小：631K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Supertex inc.

TN0702

N-Channel Enhancement-Mode

Vertical DMOS FET

Features

General Description

This low threshold, enhancement-mode (normally-off)

transistor utilizes a vertical DMOS structure and Supertex’s

well-proven, silicon-gate manufacturing process. This

combination produces a device with the power handling

capabilities of bipolar transistors and the high input impedance

and positive temperature coefﬁcient inherent in MOS devices.

Characteristic of all MOS structures, this device is free

from thermal runaway and thermally-induced secondary

breakdown.

► Low threshold - 1.6V max.

► High input impedance

► Low input capacitance - 130pF typical

► Fast switching speeds

► Low on-resistance guaranteed at V_GS= 2, 3, and 5V

► Free from secondary breakdown

► Low input and output leakage

Applications

► Logic level interfaces – ideal for TTL and CMOS

► Solid state relays

► Battery operated systems

► Photo voltaic drives

► Analog switches

Supertex’s vertical DMOS FETs are ideally suited to a wide

range of switching and amplifying applications where very

low threshold voltage, high breakdown voltage, high input

impedance, low input capacitance, and fast switching speeds

are desired.

► General purpose line drivers

► Telecom switches

Ordering Information

Product Summary

R_DS(ON)

I_D(ON)

Part Number

Package Option

Packing

V_GS(th)

(max)

BV_DSS/BV_DGS

(max)

(min)

TN0702N3-G

TO-92

1000/Bag

20V

1.3Ω

0.5A

1.0V

TN0702N3-G P002

TN0702N3-G P003

Pin Conﬁguration

TN0702N3-G P005 TO-92

TN0702N3-G P013

2000/Reel

TN0702N3-G P014

-G denotes a lead (Pb)-free / RoHS compliant package.

Contact factory for Wafer / Die availablity.

Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.

DRAIN

SOURCE

Absolute Maximum Ratings

Parameter

GATE

Value

BV_DSS

BV_DGS

±20V

TO-92

Drain-to-source voltage

Drain-to-gate voltage

Product Marking

Gate-to-source voltage

Operating and storage temperature

-55^OC to +150^OC

SiTN

0 7 0 2

YYWW

YY = Year Sealed

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

WW = Week Sealed

= “Green” Packaging

Package may or may not include the following marks: Si or

TO-92

Typical Thermal Resistance

Package

θ_ja

TO-92

132^OC/W

Doc.# DSFP-TN0702

C080813

Supertex inc.

www.supertex.com

TN0702

Thermal Characteristics

I_D

Package

I_D

Power Dissipation

†

I_DR

I_DRM

(continuous)^†

(pulsed)

@T_C= 25^OC

TO-92

530mA

1.0A

1.0W

530mA

1.0A

Notes:

†

I_D(continuous) is limited by max rated T_j.

Electrical Characteristics (T_A= 25^OC unless otherwise speciﬁed)

Sym

BV_DSS

V_GS(th)

Parameter

Min

0.5

Typ

Max Units Conditions

Drain-to-source breakdown voltage

Gate threshold voltage

V_GS= 0V, I_D= 1.0mA

V_GS= V_DS, I_D= 1.0mA

0.8

1.0

ΔV_GS(th)Change in V_GS(th)with temperature

-4.0 mV/^OC V_GS= V_DS, I_D= 1.0mA

I_GSS

Gate body leakage

100

V_GS= ± 20V, V_DS= 0V

V_GS= 0V, V_DS= Max Rating

I_DSS

Zero gate voltage drain current

On-state drain current

_DS= 0.8 Max Rating,

_GS= 0V, T_A= 125°C

100

µA

I_D(ON)

0.5

1.0

4.0

1.9

1.0

V_GS= V_DS= 5.0V

5.0

2.5

1.3

V_GS= 2.0V, I_D= 50mA

V_GS= 3.0V, I_D= 200mA

V_GS= 5.0V, I_D= 500mA

R_DS(ON)Static drain-to-source on-state resistance

ΔR_DS(ON)Change in R_DS(ON)with temperature

0.75 %/^OC V_GS= 5.0V, I_D= 500mA

G_FS

C_ISS

C_OSS

C_RSS

t_d(ON)

t_r

Forward transductance

Input capacitance

100

500

130

mmho V_DS= 5.0V, I_D= 500mA

200

125

V_GS= 0V,

Common source output capacitance

Reverse transfer capacitance

Turn-on delay time

V_DS= 20V,

f = 1.0MHz

V_DD= 20V,

Rise time

I_D= 0.5A,

R_GEN= 25Ω

t_d(OFF)

t_f

Turn-off delay time

Fall time

V_SD

Diode forward voltage drop

1.0

V_GS= 0V, I_SD= 0.5A

Notes:

1. All D.C. parameters 100% tested at 25^OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)

2. All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

10V

VDD

90%

INPUT

Pulse

R_L

10%

Generator

OUTPUT

t_(ON)

t_d(ON)

t_(OFF)

t_d(OFF)

R_GEN

t_f

t_r

VDD

OUTPUT

INPUT

D.U.T.

10%

90%

Doc.# DSFP-TN0702

C080813

Supertex inc.

www.supertex.com

TN0702

Typical Performance Curves

Output Characteristics

Saturation Characteristics

5.0

4.0

3.0

2.0

1.0

_GS= 8V

V_GS= 8V

4.0

3.0

2.0

1.0

5.0

2.0

4.0

6.0

8.0

V_DS(volts)

Transconductance vs. Drain Current

Power Dissipation vs. Case Temperature

2.0

1.0

2.0

V_DS= 5.0V

TO-92

1.0

T_A= -55^OC

25^O

150^O

.05

1.0

1.5

2.0

2.5

100

125

150

T_C(^OC)

I_D(amperes)

Maximum Rated Safe Operating Area

Thermal Response Characteristics

1.0

0.8

0.6

0.4

0.2

1.0

TO-92 (Pulsed)

0.1

TO-92

P_D= 1.0W

T_C= 25^OC

0.01

0.1

1.0

100

0.001

0.01

0.1

1.0

V_DS(volts)

t_P(seconds)

Doc.# DSFP-TN0702

C080813

Supertex inc.

www.supertex.com

TN0702

Typical Performance Curves (cont.)

BV_DSSVariation with Temperature

On-Resistance vs. Drain Current

5.0

4.0

3.0

2.0

1.0

1.2

V_GS= 2.0V

1.0

V_GS= 3.0V

V_GS= 5.0V

0.8

-50

100

150

0.5

1.0

1.5

2.0

2.5

T_j(^OC)

I_D(amperes)

V_(th)and R_DSVariation with Temperature

Transfer Characteristics

5.0

1.6

1.4

V_DS= 5V

25^OC

R_DS@ 10V, 0.5A

4.0

3.0

2.0

1.0

1.4

1.2

1.0

0.8

0.6

V_(th)@ 1.0mA

T_A= -55^OC

1.2

1.0

0.8

0.6

125^OC

2.0

4.0

6.0

8.0

-50

100

150

V_GS(volts)

T_j(^OC)

Capacitance vs. Drain-to-Source Voltage

Gate Drive Dynamic Characteristics

8.0

6.0

4.0

2.0

200

f = 1.0MHz

V_DS= 10V

150

C_ISS

200 pF

V_DS= 20V

100

C_OSS

146 pF

C_RSS

5.0

0.6

1.2

1.8

2.4

3.0

Q_G(nanocoulombs)

V_DS(volts)

Doc.# DSFP-TN0702

C080813

Supertex inc.

www.supertex.com

TN0702

3-Lead TO-92 Package Outline (N3)

Seating

Plane

Side View

Front View

Bottom View

Symbol

.170

.014^†

.175

.125

.080

.045

.500

MIN

NOM

MAX

.014^†

.095

Dimensions

(inches)

.210

.022^†

.205

.165

.105

.055

.610*

JEDEC Registration TO-92.

* This dimension is not speciﬁed in the JEDEC drawing.

† This dimension differs from the JEDEC drawing.

Drawings not to scale.

Supertex Doc.#: DSPD-3TO92N3, Version E041009.

(The package drawing(s) in this data sheet may not reﬂect the most current speciﬁcations. For the latest package outline

information go to http://www.supertex.com/packaging.html.)

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives

an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability

to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and

specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888

www.supertex.com

Doc.# DSFP-TN0702

C080813

TN0702N3-GP003 [SUPERTEX]

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