TP5322_07 [SUPERTEX]

P-Channel Enhancement-Mode Vertical DMOS FETs; P沟道增强型垂直DMOS场效应管


型号：	TP5322_07
厂家：	Supertex, Inc
描述：	P-Channel Enhancement-Mode Vertical DMOS FETs P沟道增强型垂直DMOS场效应管
文件：	总4页 (文件大小：517K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TP5322

P-Channel Enhancement-Mode

Vertical DMOS FETs

Features

General Description

The Supertex TP5322 is a low threshold enhancement-

mode (normally-off) transistor utilizing an advanced vertical

DMOS structure and Supertex’s well-proven silicon-gate

manufacturing process. This combination produces a device

with the power handling capabilities of bipolar transistors

and with the high input impedance and positive temperature

coefﬁcient inherent in MOS devices. Characteristic of all

MOS structures, this device is free from thermal runaway and

thermally-induced secondary breakdown.

► High input impedance

► Low threshold

► Low input capacitance

► Fast switching speeds

► Low on resistance

► Low input and output leakage

► Free from secondary breakdown

► Complementary N- and P-channel devices

Supertex’s vertical DMOS FETs are ideally suited to a

wide range of switching and amplifying applications where

high breakdown voltage, high input impedance, low input

capacitance, and fast switching speeds are desired.

Applications

► Logic level interfaces - ideal for TTL and CMOS

► Battery operated systems

► Photo voltaic devices

► Analog switches

► General purpose line drivers

► Telecom switches

Ordering Information

Package Options

R_DS(ON)

(max)

V_GS(TH)

(max)

I_D(ON)

(min)

BV_DSS/BV_DGS

TO-236AB¹

TO-243AA²

TP5322K1

TP5322N8

-22ꢀV

12Ω

-2.4V

-ꢀ.7A

TP5322K1-G

TP5322N8-G

-G indicates package is RoHS compliant (‘Green’)

Notes: ¹Same as SOT-23, ²Same as SOT-89.

Product marking for TO-236AB:

P3C

Product marking for TO-243AA:

TP3C

where = 2-week alpha date code

Pin Conﬁgurations

Absolute Maximum Ratings

Parameter

Value

Drain

Drain-to-source voltage

Drain-to-gate voltage

BV_DSS

BV_DGS

2ꢀV

Gate-to-source voltage

Operating and storage temperature

Soldering temperature³

-55^OC to +15ꢀ^OC

3ꢀꢀ^OC

Absolute Maximum Ratings are those values beyond which damage to the device may

occur. Functional operation under these conditions is not implied. Continuous operation

of the device at the absolute rating level may affect device reliability. All voltages are

referenced to device ground.

Gate

Source

TO-236AB

TO-243AA

(Top View)

(top view)

³Distance of 1.6mm from case for 10 seconds.

TP5322

Thermal Characteristics

I_D

Power Dissipation

@T_C= 25^OC

Package

Θ_jc(^OC/W) Θ_jc(^OC/W)

I_DR

I_DRM

(continuous)¹

(pulsed)

TO-236AB

-ꢀ.12A

-ꢀ.26A

-ꢀ.7ꢀA

-ꢀ.9ꢀA

ꢀ.36W

1.6W²

2ꢀꢀ

35ꢀ

78²

-ꢀ.12A

-ꢀ.26A

-ꢀ.7A

-ꢀ.9A

TO-243AA

Notes:

1. I_D(continuous) is limited by max rated T_j.

2. Mounted on FR4 board, 25mm x 25mm x 1.57mm. Signiﬁcant P_Dincrease possible on ceramic substrate.

Electrical Characteristics

Symbol

BV_DSS

V_GS(TH)

Parameter

Min

Typ

Max

Units

Conditions

Drain-to-source breakdown voltage

Gate threshold voltage

-22ꢀ

V_GS= ꢀV, I_D= -2.ꢀmA

V_GS= V_DS, I_D= -1.ꢀmA

-1.ꢀ

-2.4

4.5

-1ꢀꢀ

-1ꢀ

ΔV_GS(TH)Change in V_GS(TH)with temperature

mV/^OC V_GS= V_DS, I_D= -1.ꢀmA

I_GSS

Gate body leakage current

Zero gate voltage drain current

ON-state drain current

µA

V_GS= 2ꢀV, V_DS= ꢀV

V_DS= Max rating, V_GS= ꢀV

I_D(SS)

V_DS= ꢀ.8 Max Rating,

-1.ꢀ

V_GS= ꢀV, T_A= 125^OC

I_D(ON)

-ꢀ.7

-ꢀ.95

1ꢀ

V_GS= -1ꢀV, V_DS= -25V

V_GS= -4.5V, I_D= -1ꢀꢀmA

V_GS= -1ꢀV, I_D= -2ꢀꢀmA

Static drain-to-source ON-state

resistance

R_DS(ON)

8.ꢀ

1.7

ΔR_DS(ON)Change in R_DS(ON)with temperature

%/^OC

G_FS

C_ISS

C_OSS

C_RSS

t_d(ON)

t_r

Forward transconductance

Input capacitance

1ꢀꢀ

25ꢀ

mmho V_DS= -25V, I_D= -2ꢀꢀmA

11ꢀ

2ꢀ

1ꢀ

2ꢀ

-1.8

V_GS= ꢀV,

V_DS= -25V,

f = 1MHz

Common source output capacitance

Reverse transfer capacitance

Turn-ON delay time

V_DD= -25V,

I_D= -ꢀ.7A,

R_GEN= 25Ω,

Rise time

t_d(OFF)

t_f

Turn-OFF delay time

Fall time

V_SD

t_rr

Diode forward voltage drop

Reverse recovery time

V_GS= ꢀV, I_SD= -ꢀ.5A

3ꢀꢀ

1.All D.C. parameters 100% tested at 25^OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)

2.All A.C. parameters sample tested.

Notes:

Switching Waveforms and Test Circuit

ꢀV

PULSE

GENERATOR

1ꢀ%

INPUT

R_GEN

-1ꢀV

9ꢀ%

t_(OFF)

t_(ON)

t_d(ON)

D.U.T.

Output

t_d(OFF)

t_F

t_r

ꢀV

INPUT

9ꢀ%

R_L

OUTPUT

1ꢀ%

V_DD

TP5322

3-Lead TO-236AB (SOT-23) Package Outline (K1)

ꢀ.ꢀ173 ꢀ.ꢀꢀ27

(ꢀ.4394 ꢀ.ꢀ685)

ꢀ.ꢀ9ꢀ6 ꢀ.ꢀꢀ79

(2.299 ꢀ.199)

ꢀ.ꢀ512 ꢀ.ꢀꢀ4

(1.3ꢀꢀ4 ꢀ.1ꢀ16)

Dimensions in Inches

(Dimensions in Millimeters)

Measurement Legend =

ꢀ.ꢀ2ꢀ7 ꢀ.ꢀꢀ3

ꢀ.ꢀ754 ꢀ.ꢀꢀ53

(1.915 ꢀ.135)

(ꢀ.5257 ꢀ.ꢀ762)

Top View

ꢀ.115 ꢀ.ꢀꢀ5

ꢀ.ꢀ197

NOM

(2.92ꢀ ꢀ.121)

(ꢀ.5ꢀ)

ꢀ.ꢀꢀ35 ꢀ.ꢀꢀ25

(ꢀ.ꢀ889 ꢀ.ꢀ635)

ꢀ.ꢀ4ꢀꢀ ꢀ.ꢀꢀ7

(1.ꢀ16 ꢀ.178)

ꢀ.ꢀꢀ43 ꢀ.ꢀꢀꢀ9

(ꢀ.1ꢀ92 ꢀ.ꢀ229)

ꢀ.ꢀ21ꢀ ꢀ.ꢀꢀ3

(ꢀ.5334 ꢀ.ꢀ76)

ꢀ.ꢀ382 ꢀ.ꢀꢀ3

(ꢀ.969ꢀ ꢀ.ꢀ762)

End View

Side View

TP5322

3-Lead TO-243AA (SOT-89) Surface Mount Package (N8)

4.5ꢀ ꢀ.1ꢀ

1.72 ꢀ.1ꢀ

1.5ꢀ ꢀ.1ꢀ

ꢀ.4ꢀ ꢀ.ꢀ5

Exclusion Zone

No Vias/Traces in

this area. Shape

of pad may vary.

4.1ꢀ ꢀ.15

2.45 ꢀ.15

2.21 ꢀ.ꢀ8

1.ꢀ5 ꢀ.15

ꢀ.42 ꢀ.ꢀ6

ꢀ.5 ꢀ.ꢀ6

1.5ꢀ BSC

3.ꢀꢀ BSC

Top View

Side View

Bottom View

Notes:

All dimensions are in millimeters; all angles in degrees.

(The package drawing(s) in this data sheet may not reﬂect the most current speciﬁcations. For the latest package outline

information go to http://www.supertex.com/packaging.html.)

Doc.# DSFP-TP5322

A032807

TP5322_07 [SUPERTEX]

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