VN10KN3-G-P014 [SUPERTEX]
Small Signal Field-Effect Transistor,;型号: | VN10KN3-G-P014 |
厂家: | Supertex, Inc |
描述: | Small Signal Field-Effect Transistor, |
文件: | 总5页 (文件大小:626K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Supertex inc.
VN10K
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
General Description
► Free from secondary breakdown
► Low power drive requirement
► Ease of paralleling
This enhancement-mode (normally-off) transistor utilizes
a vertical DMOS structure and Supertex’s well-proven,
silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities
of bipolar transistors and the high input impedance and
positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
► Low CISS and fast switching speeds
► Excellent thermal stability
► Integral source-drain diode
► High input impedance and high gain
Applications
► Motor controls
► Converters
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
► Amplifiers
► Switches
► Power supply circuits
► Drivers (relays, hammers, solenoids, lamps, memories,
displays, bipolar transistors, etc.)
Ordering Information
Product Summary
RDS(ON)
(max)
Part Number
Package Option
Packing
IDSS
(min)
BVDSS/BVDGS
VN10KN3-G
TO-92
1000/Bag
60V
5.0Ω
750mA
VN10KN3-G P002
VN10KN3-G P003
VN10KN3-G P005
VN10KN3-G P013
VN10KN3-G P014
Pin Configuration
TO-92
2000/Reel
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
DRAIN
SOURCE
Absolute Maximum Ratings
Parameter
Value
GATE
TO-92
Drain-to-source voltage
Drain-to-gate voltage
BVDSS
BVDGS
±30V
Gate-to-source voltage
Product Marking
Operating and storage temperature
-55OC to +150OC
SiVN
1 0 K
YYWW
YY = Year Sealed
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
WW = Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
Typical Thermal Resistance
TO-92
Package
θja
TO-92
132OC/W
Doc.# DSFP-VN10K
B031411
Supertex inc.
www.supertex.com
VN10K
Thermal Characteristics
ID
ID
Power Dissipation
†
Package
IDR
IDRM
@TC = 25OC
(continuous)†
(pulsed)
TO-92
310mA
1.0A
1.0W
310mA
1.0A
Notes:
†
ID (continuous) is limited by max rated Tj . (VN0106N3 can be used if an ID (continuous) of 500mA is needed.)
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym
BVDSS
VGS(th)
Parameter
Min
60
0.8
-
Typ
Max Units Conditions
Drain-to-source breakdown voltage
Gate threshold voltage
-
-
2.5
-
V
V
VGS = 0V, ID = 100µA
VGS = VDS, ID= 1.0mA
-
ΔVGS(th) Change in VGS(th) with temperature
-3.8
mV/OC VGS = VDS, ID= 1.0mA
IGSS
Gate body leakage
-
-
-
100
10
nA
VGS = 15V, VDS = 0V
VGS = 0V, VDS = 45V
-
IDSS
Zero gate voltage drain current
On-state drain current
µA
V
GS = 0V, VDS = 45V,
-
-
500
TA = 125°C
ID(ON)
0.75
-
-
-
A
VGS = 10V, VDS = 10V
VGS = 5.0V, ID = 200mA
VGS = 10V, ID = 500mA
-
7.5
5.0
-
RDS(ON) Static drain-to-source on-state resistance
Ω
-
-
ΔRDS(ON) Change in RDS(ON) with temperature
-
0.7
-
%/OC VGS = 10V, ID = 500mA
GFS
CISS
COSS
CRSS
Forward transductance
100
-
mmho VDS = 10V, ID = 500mA
Input capacitance
-
-
-
48
16
2.0
60
25
5.0
VGS = 0V,
VDS = 25V,
f = 1.0MHz
Common source output capacitance
Reverse transfer capacitance
pF
ns
VDD = 15V,
ID = 600mA,
RGEN = 25Ω
t(ON)
Turn-on time
Turn-off time
-
-
-
-
10
10
t(OFF)
VSD
trr
Diode forward voltage drop
Reverse recovery time
-
-
0.8
-
-
V
VGS = 0V, ISD = 500mA
VGS = 0V, ISD = 500mA
160
ns
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
VDD
90%
INPUT
0V
Pulse
RL
10%
Generator
OUTPUT
t(ON)
td(ON)
t(OFF)
td(OFF)
RGEN
tf
tr
VDD
OUTPUT
0V
INPUT
D.U.T.
10%
10%
90%
90%
Doc.# DSFP-VN10K
B031411
Supertex inc.
www.supertex.com
2
VN10K
Typical Performance Curves
BVDSS Variation with Temperature
On-Resistance vs. Gate-to-Source Voltage
100
VDS = 0.1V
1.1
1.0
0.9
10
1.0
-50
0
50
100
150
1.0
10
100
VGS (volts)
Tj (OC)
Output Conductance vs Drain Current
Transfer Characteristics
1.0
1.0
VDS = 25V
80µs, 1%
Duty Cycle,
Pulse Test
VDS = 10V
300µs, 2%
Duty Cycle,
Pulse Test
0.8
0.6
0.4
0.2
0
Reduction
Due to
Heating
0.1
0.01
0
2.0
4.0
6.0
8.0
10
0.01
0.1
1.0
ID (amperes)
VGS (volts)
Transconductance vs Gate-Source Voltage
Capacitance vs. Drain-to-Source Voltage
50
250
CISS
VDS = 10V
3000µs, 2%
40
30
20
200
150
100
50
Duty Cycle
Pulse Test
COSS
10
CRSS
0
0
0
10
20
30
40
50
0
2.0
4.0
6.0
8.0
10
VDS (volts)
VGS (volts)
Doc.# DSFP-VN10K
B031411
Supertex inc.
www.supertex.com
3
VN10K
Typical Performance Curves (cont.)
Output Characteristics
Saturation Characteristics
1.0
VGS = 10V
1.0
0.8
0.6
0.4
0.2
0
8V
7V
VGS = 10V
7V
9V
0.8
8V
6V
6V
5V
4V
0.6
0.4
0.2
5V
4V
3V
2V
3V
2V
0
0
10
20
30
40
50
0
2.0
4.0
6.0
8.0
10
VDS (volts)
VDS (volts)
Transconductance vs. Drain Current
Power Dissipation vs. Case Temperature
2.0
250
200
150
100
50
TO-92
1.0
VDS = 10V
300µs, 2%
Duty Cycle,
Pulse Test
0
0
0
200
400
600
800
1000
0
25
50
75
100
125
150
ID (mA)
TC (OC)
Maximum Rated Safe Operating Area
Switching Waveform
10
10
5.0
0
TC = 25OC
1.0
0.1
TO-92 (DC)
15
10
5.0
0
0.01
0
10
20
30
40
50
1.0
10
100
1000
VDS (volts)
t – Time (ns)
Doc.# DSFP-VN10K
B031411
Supertex inc.
www.supertex.com
4
VN10K
3-Lead TO-92 Package Outline (N3)
D
A
Seating
Plane
1
2
3
L
c
b
e1
e
Side View
Front View
E
E1
1
3
2
Bottom View
Symbol
A
.170
-
b
.014†
-
c
D
.175
-
E
.125
-
E1
e
.095
-
e1
.045
-
L
.500
-
MIN
NOM
MAX
.014†
-
.080
-
Dimensions
(inches)
.210
.022†
.022†
.205
.165
.105
.105
.055
.610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-VN10K
B031411
5
相关型号:
©2020 ICPDF网 联系我们和版权申明