VP1310N3 [SUPERTEX]

P-Channel Enhancement-Mode Vertical DMOS FETs; P沟道增强型垂直DMOS场效应管


型号：	VP1310N3
厂家：	Supertex, Inc
描述：	P-Channel Enhancement-Mode Vertical DMOS FETs P沟道增强型垂直DMOS场效应管
文件：	总4页 (文件大小：31K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VP1304

VP1306

VP1310

P-Channel Enhancement-Mode

Vertical DMOS FETs

Ordering Information

Order Number / Package

BV_DSS

R_DS(ON)

(max)

I_D(ON)

(min)

BV_DGS

TO-92

-40V

-60V

25Ω

-0.25A

VP1304N3

VP1306N3

VP1310N3

-100V

Features

Advanced DMOS Technology

Free from secondary breakdown

Low power drive requirement

Ease of paralleling

These enhancement-mode (normally-off) transistors utilize a

vertical DMOS structure and Supertex’s well-proven silicon-gate

manufacturing process. This combination produces devices with

the power handling capabilities of bipolar transistors and with the

high input impedance and positive temperature coefficient inher-

ent in MOS devices. Characteristic of all MOS structures, these

devices are free from thermal runaway and thermally-induced

secondary breakdown.

Low C_ISSand fast switching speeds

Excellent thermal stability

Integral Source-Drain diode

High input impedance and high gain

Supertex’s vertical DMOS FETs are ideally suited to a wide range

of switching and amplifying applications where high breakdown

voltage, high input impedance, low input capacitance, and fast

switching speeds are desired.

Complementary N- and P-channel devices

Applications

Package Options

Motor controls

Converters

Amplifiers

Switches

Power supply circuits

Drivers (relays, hammers, solenoids, lamps,

memories, displays, bipolar transistors, etc.)

S G D

Absolute Maximum Ratings

Drain-to-Source Voltage

TO-92

BV_DSS

BV_DGS

± 20V

Drain-to-Gate Voltage

Gate-to-Source Voltage

Operating and Storage Temperature

Soldering Temperature*

-55°C to +150°C

300°C

Note: See Package Outline section for dimensions.

* Distance of 1.6 mm from case for 10 seconds.

7-251

VP1304/VP1306/VP1310

Thermal Characteristics

Package

I_D(continuous)*

I_D(pulsed)

Power Dissipation

θ_jc

θ_ja

I_DR*

I_DRM

@ T_C= 25°C

°C/W

TO-92

-0.15A

-0.65A

1.0W

125

170

-0.15A

-0.65A

* I (continuous) is limited by max rated T

T = 25°C

Electrical Characteristics (@ 25°C unless otherwise specified)

Symbol

Parameter

Min

-100

-60

Typ

Max

Unit

Conditions

VP1310

VP1306

VP1304

BV_DSS

Drain-to-Source

I_D= -1mA, V_GS= 0V

Breakdown Voltage

-40

V_GS(th)

∆V_GS(th)

I_GSS

Gate Threshold Voltage

-1.5

-3.5

-3.85

-100

-10

mV/°C

V_GS= V_DS, I_D= -1mA

V_GS= ±20V, V_DS= 0V

Change in V_GS(th)with Temperature

Gate Body Leakage

-3.2

-0.1

I_DSS

Zero Gate Voltage Drain Current

V_GS= 0V, V_DS= Max Rating

-500

µA

V_GS= 0V, V_DS= 0.8 Max Rating

T_A= 125°C

I_D(ON)

ON-State Drain Current

-0.08

-0.25

-0.23

-0.7

0.8

120

V_GS= -5V, V_DS= -25V

V_GS= -10V, V_DS= -25V

V_GS= -5V, I_D= -50mA

V_GS= -10V, I_D= -250mA

V_DS= -25V, I_D= -200mA

R_DS(ON)

Static Drain-to-Source

ON-State Resistance

Ω

∆R_DS(ON)

G_FS

C_ISS

C_OSS

C_RSS

t_d(ON)

t_r

Change in R_DS(ON)with Temperature

Forward Transconductance

Input Capacitance

1.1

%/°C

Ω

V_GS= 0V, V_DS= -25V

Common Source Output Capacitance

Reverse Transfer Capacitance

Turn-ON Delay Time

f = 1 MHz

V_DD= -25V

Rise Time

I_D= -250mA

t_d(OFF)

t_f

Turn-OFF Delay Time

Fall Time

_GEN= 25Ω

V_SD

Diode Forward Voltage Drop

Reverse Recovery Time

-1.2

350

-1.7

I_SD= -0.25A, V_GS= 0V

t_rr

Notes:

1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)

2. All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

10%

PULSE

GENERATOR

INPUT

90%

-10V

R_gen

t_(ON)

t_d(ON)

t_(OFF)

t_d(OFF)

t_r

t_F

D.U.T.

OUTPUT

INPUT

90%

R_L

OUTPUT

V_DD

10%

V_DD

7-252

VP1304/VP1306/VP1310

Typical Performance Curves

Output Characteristics

Saturation Characteristics

-1.0

-0.5

-0.4

-0.3

-0.2

-0.1

= -10V

-0.8

-0.6

-0.4

-0.2

= -10V

-8V

-6V

-8V

-6V

-4V

-3V

-4V

-3V

-2

-4

-6

-8

-10

-20

-30

-40

-50

-1.0

-100

V_DS(volts)

Transconductance vs. Drain Current

V_DS= -25V

Power Dissipation vs. Ambient Temperature

0.2

2.5

2.0

1.5

1.0

0.5

T = -55°C

= 25°C

0.1

= 125°C

TO-92

-0.2

-0.4

-0.6

-0.8

100

125

150

I_D(amperes)

T_C(°C)

Maximum Rated Safe Operating Area

Thermal Response Characteristics

-10

-1.0

1.0

TO-92 (pulsed)

0.5

TO-92 (DC)

-0.1

TO-92

= 25°C

= 1W

= 25°C

-0.01

0.001

0.01

0.1

1.0

-0.1

-1.0

-10

t_p(seconds)

V_DS(volts)

7-253

VP1304/VP1306/VP1310

Typical Performance Curves

BV_DSSVariation with Temperature

On-Resistance vs. Drain Current

100

1.1

1.0

0.9

= -5V

= -10V

-50

100

150

-50

-0.2

-0.4

-0.6

-0.8

-1.0

_D(amperes)

T_j(°C)

Transfer Characteristics

V_(th)and R_DSVariation with Temperature

2.0

1.6

1.2

0.8

0.4

-1.0

-0.8

-0.6

-0.4

-0.2

@ -10V, -0.25A

DS(ON)

1.2

1.1

1.0

0.9

0.8

= -25V

= -55°C

25°C

125°C

@ -1mA

(th)

-2

-4

-6

-8

-10

100

150

_GS(volts)

T_j(°C)

Capacitance vs. Drain-to-Source Voltage

f = 1MHz

Gate Drive Dynamic Characteristics

V_DS= -10V

-10

-8

-6

-4

-2

C_ISS

V_DS

40 pF

= -40V

C_OSS

25 pF

0.1

C_RSS

0.2

0.3

-10

-20

-30

-40

0.4

0.5

Q_G(nanocoulombs)

V_DS(volts)

7-254

相关型号：

VP1310N3P002

Small Signal Field-Effect Transistor, 0.15A I(D), 100V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-92