SM79108_06 [SYNCMOS]
8 - Bit Micro-controller with 8KB flash & 256 Bytes RAM embedded; 8 - 位微控制器，具有8KB闪存和256字节RAM的嵌入式
| 型号： | SM79108_06 |
| 厂家： | 
SYNCMOS TECHNOLOGIES,INC |
| 描述： | 8 - Bit Micro-controller with 8KB flash & 256 Bytes RAM embedded |
| 文件： | 总25页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SyncMOS Technologies International. Inc.
SM79108
8 - Bit Micro-controller
with 8KB flash & 256 Bytes RAM embedded
Product List
Features
SM79108L25, 25 MHz 8KB internal memory MCU
SM79108C40, 40 MHz 8KB internal memory MCU
Working voltage: 3.0V ~ 3.6V For L Version
4.5V ~ 5.5V For C Version
General 8052 family compatible
Description
12 clocks per machine cycle
8 KB internal flash memory
256 bytes on-chip data RAM
Three 16 bit timers/counters
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or
QFP package
The SM79108 series product is an 8 - bit single chip micro
controller with 8 KB flash & 256 bytes RAM embedded. It
has 4-channel, 8-bit ADC function build-in, 1-channel
SPWM and 1-channel PWM build-in and A14(segment) x
4(common) LCD driver. It provides hardware features and
a powerful instruction set necessary to make it a versatile
and cost effective controller for those applications demand
up to 32 I/O pins for PDIP package or up to 36 I/O pins for
PLCC/QFP package, or applications which need up to 64K
byte flash memory for program and/or for data.
A14 x 4 LCD driver (P0, P2, ALE, PSEN)
1 Channel SPWM (P1.2)
1 Channel PWM (P1.5)
To program the flash block, a commercial programmer
is capable to do it.
Full duplex serial channel
Bit operation instruction
Industrail Level
Ordering Information
8-bit unsigned division
8-bit unsigned multiply
yywwv: production date code identifier
SM79108ihhk
BCD arithmetic
Direct addressing
Indirect addressing
yy: year, ww: weak, v: version
Nested interrupt
i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V}
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
Two priority level interrupt
A serial I/O port
Power save modes: Idle mode and power down mode
Code protection function
One watch dog timer (WDT)
Low EMI (inhibit ALE)
Pin/Pad
Configuration
Postfix
Package
40L PDIP
44L PLCC
44L QFP
Dimension
page 22
page 23
page 24
P
J
page 2
page 2
Q
page 2
Taiwan
6F, No. 10-2 Li-Hsin 1st Road ,
Science-based Industrial Park,
Hsinchu, Taiwan 30078
TEL: 886-3-5671820
886-3-5671880
FAX: 886-3-5671891
886-3-5671894
Specifications subject to change without notice,contact your sales representatives for the most recent information.
1/26
Ver 2.1 SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
Pin Configurations
1
2
3
T2/P1.0
T2EX/P1.1
SPWM/P1.2
VDD
40
39
P0.0/AD0/SEG13
38
37
P0.1/AD1/SEG12
P0.2/AD2/SEG11
P0.3/AD3/SEG10
P0.4/AD4/SEG9
4
5
P1.3
P1.4
36
35
33 32 31 30 29 28 27 26 25 24 23
22
SEG10/AD3/P0.3
SEG11/AD3/P0.2
34
35
P2.4/A12/SEG0
6
7
PWM/P1.5
P1.6
34
33
32
31
30
21
P2.3/A11/COM3
P2.2A10/COM2
P2.1/A9/COM1
P2.0A8/COM0
P4.0
P0.5/AD5/SEG8
P0.6/AD6/SEG7
36
37
20
19
18
SEG12/AD3/P0.1
SEG13/AD3/P0.0
VDD
8
SM79108 jhhQ
44L QFP
P1.7
P0.7/AD7/SEG6
#EA
38
39
40
41
42
43
44
9
RES
17
10
P4.2
T2/P1.0
T2EX/P1.1
RXD/P3.0
16
15
14
13
12
VSS
(Top View)
ALE/SEG5
#PSEN/SEG4
11
TXD/P3.1
XTAL1
XTAL2
P3.7/#RD/ADC3
P3.6/#WR/ADC2
29
28
12
13
#INT/P3.2
SPWM/P1.2
P1.3
P2.7/A15/SEG3
P2.6/A14/SEG2
P2.5/A13/SEG1
P2.4/A12/SEG0
P2.3/A11/COM3
P2.2/A10/COM2
#INT1/P3.3
P1.4
27
26
25
24
23
14
15
1
11
10
2
3
4
5
6
7
9
8
ADC0/T0/P3.4
ADC1/T1/P3.5
16
17
ADC2/#WR/P3.6
ADC3/#RD/P3.7
18
19
20
XTAL2
XTAL1
VSS
22
21
P2.1/A9/COM1
P2.0/A8/COM0
42
41 40
1
44 43
6
3
2
5
4
39
P0.4/AD4/SEG9
7
8
9
PWM/P1.5
P1.6
P1.7
RES
RXD/P3.0
P4.3
38
37
36
P0.5/AD5/SEG8
P0.6/AD6/SEG7
P0.7/AD7/SEG6
SM79108 jhhJ
10
11
12
13
35
#EA
34
33
P4.1
44L PLCC
(Top View)
ALE/SEG5
#PSEN/SEG4
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
ADC0/T0/P3.4
ADC1/T1/P3.5
32
31
14
15
16
17
P2.7/A15/SEG3
P2.6/A14/SEG2
30
29
P2.5/A13/SEG1
27 28
25 26
23
24
18 19
22
20 21
Specifications subject to change without notice,contact your sales representatives for the most recent information.
2/26
Ver 2.1 SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
Block Diagram
Decoder &
Register
256
Stack
Pointer
Timer 1
Timer 2
Timer 0
bytes RAM
Buffer
DPTR
WDT
to pertinent blocks
to whole chip
RES
Reset
Circuit
Acc
Vdd
Vss
PC
Incrementer
Power
Circuit
Buffer2
Buffer1
to pertinent blocks
Program
Counter
Interrupt
Circuit
ALU
Register
PSW
XTAL2
XTAL1
#EA
Timing
to whole system
Generator
ALE/SEG5
#PSENSEG4
Instruction
Register
8 K
bytes
ADC
Flash
Memory
Port 1
Latch
Port 3
Latch
Port 2
Latch
Port 0
Latch
SPWM
PWM
LCD
Driver
Port 1
Port 0
Port 2
Driver & Mux
Port 3
Driver & Mux
Driver & Mux
Driver & Mux
(14 x 4)
8
8
8
8
Specifications subject to change without notice,contact your sales representatives for the most recent information.
3/26
Ver 2.1 SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
Pin Descriptions
40L
44L
44L
PDIP QFP PLCC
Pin# Pin# Pin#
Symbol
P1.0/T2
Active I/O
(GPIO)
Names
1
40
41
42
43
44
1
2
i/o bit 0 of port 1 & timer 2 clock out
i/o bit 1 of port 1 & timer 2 control
i/o bit 2 of port 1 & SPWM channel
i/o bit 3 of port 1
2
3
P1.1/T2EX
P1.2/SPWM
P1.3
3
4
4
5
5
6
P1.4
i/o bit 4 of port 1
6
7
P1.5/PWM
i/o bit 5 of port 1 & PWM channel
i/o bit 6 of port 1
7
2
8
P1.6
8
3
9
P1.7
i/o bit 7 of port 1
9
4
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
RES
H
i
Reset
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
5
P3.0/RXD
i/o bit 0 of port 3 & receive data
7
P3.1/TXD
i/o bit 1 of port 3 & transmit data
8
P3.2/#INT0
P3.3/#INT1
P3.4/T0/ADC0
P3.5/T1/ADC1
P3.6/#WR/ADC2
P3.7/#RD/ADC3
XTAL2
-/L
-/L
i/o bit 2 of port 3 & low true interrupt 0
9
i/o bit 3 of port 3 & low true interrupt 1
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
17
28
39
6
i/o bit 4 of port 3 & ADC channel 0 & Timer 0
i/o bit 5 of port 3 & ADC channel 1 &Timer 1
i/o bit 6 of port 3 & ADC channel 2 & external memory write
i/o bit 7 of port 3 & ADC channel 3 & external memory read
o
i
Crystal out
XTAL1
Crystal in
VSS
Sink Voltage, Ground
P2.0/A8/COM0
P2.1/A9/COM1
P2.2/A10/COM2
P2.3/A11/COM3
P2.4/A12/SEG0
P2.5/SEG1
P2.6/SEG2
P2.7/SEG3
#PSEN/SEG4
ALE/SEG5
#EA
i/o bit 0 of port 2 & bit 8 of external memory address & LCCD common 0 output
i/o bit 1 of port 2 & bit 9 of external memory address & LCCD common 1 output
i/o bit 2 of port 2 & bit 10 of external memory address & LCCD common 2 output
i/o bit 3 of port 2 & bit 11 of external memory address & LCCD common 3 output
i/o bit 4 of port 2 & bit 12 of external memory address & LCCD seg 0 output
i/o bit 5 of port 2 & LCCD seg 1 output
i/o bit 6 of port 2 & LCCD seg 2 output
i/o bit 7 of port 2 & LCCD seg 3 output
o
o
i
program storage enable & LCCD seg 4 output
address latch enable & LCCD seg 5 output
external access
L
P0.7/AD7/SEG6
P0.6/AD6/SEG7
P0.5/AD5/SEG8
P0.4/AD4/SEG9
P0.3/AD3/SEG10
P0.2/AD2/SEG11
P0.1/AD1/SEG12
P0.0/AD0/SEG13
VDD
i/o bit 7 of port 0 & data/address bit 7 of external memory & LCCD seg 6 output
i/o bit 6 of port 0 & data/address bit 6 of external memory & LCCD seg7 output
i/o bit 5 of port 0 & data/address bit 5 of external memory & LCCD seg 8 output
i/o bit 4 of port 0 & data/address bit 4 of external memory & LCCD seg 9 output
i/o bit 3 of port 0 & data/address bit 3 of external memory & LCCD seg 10 output
i/o bit 2 of port 0 & data/address bit 2 of external memory & LCCD seg 11 output
i/o bit 1 of port 0 & data/address bit 1 of external memory & LCCD seg 12 output
i/o bit 0 of port 0 & data/address bit 0 of external memory & LCCD seg 13 output
i
Drive Voltage, Vcc
23 P4.0
34 P4.1
P4.2
12 P4.3
i/o bit 0 of Port 4
i/o bit 1 of Port 4
i/o bit 2 of Port 4
i/o bit 3 of Port 4
1
Specifications subject to change without notice,contact your sales representatives for the most recent information.
4/26
Ver 2.1 SM79108 08/2006
SFR Memory MAP
SyncMOS Technologies International. Inc.
SM79108
SFR Memory MAP
0F8H
0F0H
0E8H
0FFH
0F7H
0EFH
B
ACC
P4
LCDB0
LCDB1
LCDB2
LCDB3
TL2
LCDB4
TH2
LCDB5
LCDB6
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
0E7H
0DFH
LCDCON
PSW
PWMC0
RCAP2H
0D7H
0CFH
T2CON
RCAP2L
T2MOD
IP1
0C7H
0BFH
0B7H
IP
SCONF
P3
PWMD0
0B0H
0A8H
0A0H
98H
IE
P2
IE1
IFR
0AFH
0A7H
9FH
SPWMC
P1CON
SPWMD0
P2CON
SCON
P1
SBUF
P0CON
P3CON
TH1
WDTC
WDTKEY
90H
97H
TCON
P0
TMOD
SP
TL0
TL1
TH0
ADSCR
ADCD
PCON
8FH
88H
80H
DPL
DPH
(Reserved)
87H
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM79108
Addr
SFR
Reset
7
6
5
4
3
2
1
0
8EH
8FH
97H
9AH
9BH
9CH
9DH
9FH
ADSCR 0000_00**
COM
AD7
CON
AD6
ADCSS1
AD5
ADCSS0
AD4
CH1
AD3
CH0
AD2
Reserved Reserved
AD1 AD0
ADCD
WDTKEY
P0CON
00H
00H
00H
WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEY0
SEG6
SEG7
SEG8
PWME0
SEG1
SEG9
SEG10
SEG11
SPWME0
COME2
SGE12
SEG13
P1CON **0*_*0**
P2CON
P3CON
00H
00H
SEG3
ADCE3
WDTE
SEG2
ADCE2
R
SEG0
COME3
COME1
COME0
ADCE1
CLEAR
ADCE0
WDTC 000*_*000
PS2
PS1
PS0
0A3H SPWMC0 ****_**00
SPFS1
BRM01
SPFS0
BRM00
0A4H SPWMD0
00H
SPWMD04 SPWMD03 SPWMD02 SPWMD01 SPWMD00 BRM02
0A9H
0AAH
0B3H
0B9H
0BFH
IE1
IFR
****_0***
****_0***
00H
EADC
ADCIF
PWMD0
IP1
PWMD07 PWMD06 PWMD05 PWMD04 PWMD03 PWMD02 PWMD01 PWMD00
PADC
****_0***
SCONF 0***_***0
WDR
Reserved
PBS
ALEI
PFS0
P4.1
0D3H PWMC0 ****_*000
0D8H P4 ****_1111
0DFH LCDCON 000*_*000 Lout_en
0E1H LCDB0 00H SEG0
PFS1
P4.1
P4.3
P4.2
Lcd_en
SEG0
SEG
LS2
LS1
LS0
SEG0
SEG0
SEG1
SEG1
SEG1
SEG1
5/26
Ver 2.1
SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
Addr
0E2H
0E3H
0E4H
0E5H
0E6H
0E7H
SFR
Reset
00H
00H
00H
00H
00H
00H
7
6
5
4
3
2
1
0
LCDB1
LCDB2
LCDB3
LCDB4
LCDB5
LCDB6
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
1. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is
useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different
from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the
WDT counter. User should check WDR bit of SCONF register whenever unpracticed reset happened
The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway.
There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is inde-
pendent to the system frequency.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count
with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when
SM79108 been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of
the 16-bit counter and let the counter re-start to count from the beginning.
1.1 Watch Dog Timer Registers:
Watch Dog Key Register - (WDTKEY, 97H)
bit-7
WDT
KEY7
W
bit-0
WDT
KEY0
W
WDT
KEY6
W
WDT
KEY5
W
WDT
KEY4
W
WDT
KEY3
W
WDT
KEY2
W
WDT
KEY1
W
Read / Write:
Reset value:
0
0
0
0
0
0
0
0
By default, the WDTC is read only. User need to write values 1EH, 0E1H sequentially to the WDTKEY(97H) register to
enable the WDTC write attribute, That is
MOV WDTKEY, # 1EH
MOV WDTKEY, # E1H
When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY(97H) register to disable the
WDTC write attribute, That is
MOV WDTKEY, # E1H
MOV WDTKEY, # 1EH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/26
Ver 2.1 SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
Watch Dog Timer Registers - WDT Control Register (WDTC, 9FH)
bit-7
bit-0
PS0
R/W
0
WDTE
R/W
0
R
-
CLEAR
R/W
0
Unused
Unused
PS2
R/W
0
PS1
R/W
0
Read / Write:
Reset value:
-
-
0
*
*
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer reset bit
PS[2:0] : Overflow period select bits
PS [2:0]
000
Overflow Period (ms)
2.048
001
4.096
010
8.192
011
16.384
100
32.768
101
65.536
110
131.072
262.144
111
System Control Register (SCONF, 0BFH)
bit-7
bit-0
ALEI
R/W
0
WDR
R/W
0
Unused
Unused
Unused
Unused
Reserved
Unused
Read / Write:
Reset value:
-
-
-
-
-
-
*
*
*
*
*
*
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1
ALEI : ALE output inhibit bit, to reduce EMI
Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin.
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow.
User should check WDR bit whenever unpredicted reset happened.
2. Reduce EMI Function
The SM79108 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will
inhibit the clock signal in Fosc/6Hz output to the ALE pin.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
7/26
Ver 2.1 SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
3. Port 4 for PLCC or QFP package:
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is
located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Port4 (P4, 0D8H)
bit-7
bit-0
P4.0
R/W
1
Unused
Unused
Unused
Unused
P4.3
R/W
1
P4.2
R/W
1
P4.1
R/W
1
Read / Write:
Reset value:
-
-
-
-
*
*
*
*
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.
4. SPWM Function Description:
The 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary
rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of
the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The
number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to
generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock
speed. The SPFS[1:0] settings of SPWMC (0A3H) register are divided of Fosc to be SPWM clock, Fosc/
2^(SPFS[1:0]+1). The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/
2^(SPFS[1:0]+1)]/32.
4.1 SPWM Registers - P1CON, SPWMC0, SPWMD0
SPWM Registers - Port1 Configuration Register (P1CON, 9BH)
bit-7
bit-0
Unused
Unused
PWME0
R/W
0
Unused
Unused
SPWME0
Unused
Unused
Read / Write:
Reset value:
-
-
-
-
R/W
0
-
-
*
*
*
*
*
*
SPWME0 : When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset
to zero, the corresponding SPWM pin is active as I/O pin. Four bits are cleared upon reset.
PWME0 : When the bit set to one, the corresponding PWM pin is active as PWM function. When the bit reset
to zero, the corresponding PWM pin is active as I/O pin. Four bits are cleared upon reset.
SPWM Registers - SPWM Control Register (SPWMC, 0A3H)
bit-7
bit-0
SPFS0
R/W
0
Unused
Unused
Unused
Unused
Unused
Unused
SPFS1
R/W
0
Read / Write:
Reset value:
-
-
-
-
-
-
*
*
*
*
*
*
Specifications subject to change without notice,contact your sales representatives for the most recent information.
8/26
Ver 2.1 SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
SPFS[1:0]: These two bits is 2’s power parameter to form a frequency divider for input clock.
SPFS1
SPFS0
Divider
SPWM clock, Fosc=20MHz
SPWM clock, Fosc=24MHz
0
0
1
1
0
1
0
1
2
4
10MHz
5MHz
12MHz
6MHz
8
2.5MHz
1.25MHz
3MHz
16
1.5MHz
SPWM Registers - SPWM Data Register (SPWMD0, 0A4H)
bit-7
bit-0
SPWMD04 SPWMD03 SPWMD02 SPWMD01 SPWMD00 BRM02 BRM01 BRM00
Read/Write:
Reset value:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SPWMD0[4:0]: content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[2:0]: will insert certain narrow pulses among an 8-SPWM-cycle frame
N = BRM[2:0]
Number of SPWM cycles inserted in an 8-cycle frame
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Example of SPWM timing diagram:
MOV SPWMD0 , #83H
MOV P1CON , #04H
; SPWMD0[4:0]=10h (=16T high, 16T low), BRM0[2:0] = 3
; Enable P1.2 as SPWM output pin
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1st cycle frame 2nd cycle frame 3rd cycle frame 4th cycle frame 5th cycle frame
6th cycle frame 7th cycle frame 8th cycle frame
32T
32T
32T
32T
32T
32T
32T
32T
16T
16T
16T
16T
16T
16T
16T
16T
1T
1T
1T
(narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)
SPWM clock = 1 / T = Fosc / 2^(SPFS[1:0]+1)
The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(SPFS[1:0]+1)]/32
If user use Fosc=20MHz, SPFS[1:0] of SPWMC=#03H, then
SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz
SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz
5. PWM Function Description:
Each PWM channel contains a 8-bit wide PWM data register (PWMDR) to decide number of continuous pulses within a
PWM frame cycle. The value programmed in the register will determine the pulse length of the output. The PWM channel
can be configured as 5-bit or 8-bit resolution. If a channel is configured as 5-bit resolution, only LSB 5 bits are available.
The value of each PWM Data Register (PWMDR) is continuously compared with the content of an internal counter to deter-
mine the state of each PWM channel output pin.
5.1 PWM Registers - PWMC0, PWMD0
PWM Registers - PWM Control Register (PWMC0, 0D3H)
bit-7
bit-0
PFS0
R/W
0
Unused
Unused
Unused
Unused
Unused
PBS
R/W
0
PFS1
R/W
0
Read / Write:
Reset value:
-
-
-
-
-
*
*
*
*
*
PFS[1:0]: These two bits is 2’s power parameter to form a frequency divider for input clock.
PBS: This bit decides channel bit resolution. If PBS is set, the channel is 5-bit resolution.
PFS1
PFS0
Divider
16
PWM clock, Fosc=12MHz
750KHz
PWM clock, Fosc=24MHz
1.5MHz
0
0
1
1
0
1
0
1
32
375KHz
750KHz
64
187.5KHz
375KHz
128
93.75KHz
187.5KHz
Example : If user use Fosc = 20MHz, PFS[1:0] of PWMC = #03H, PBS = 0, then
PWM Clock = 20MHz / 128 = 156.25KHz
PWM Output cycle frame frequency = 156.25KHz / 256 = 610 Hz
Note : For bzzer application
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PWM Registers - PWM Data Register (PWMD0, 0B3H)
bit-7
bit-0
PWMD07 PWMD06 PWMD05 PWMD04 PWMD03 PWMD02 PWMD01 PWMD00
Read /Write:
Reset value:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PWM[7:0]: content of PWM Data Register. If PBS is set, only PWM[4:0] are available.
Example of PWM timing diagram:
For 5-bit resolution channel, M = content of PWMD0:
32T
M = 00H
M = 01H
M = 0FH
M = 1FH
For 8-bit resolution channel:
M = 00H
M = 01H
256T
M = 7FH
M = 0FFH
PWM clock = 1/T = Fosc / 2^ ( PFS [1:0] + 1 )
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6. Analog-to-Digital Converter (ADC)
The SM79108 equips with 4-channels, 8-bit ADC which is available at P3.4~P3.7. S/W can select one of the 4 ADC chan-
nels by setting SFR ADC Status and Control Register (ADSCR, 8EH) bit CH0~CH1. The ADC can do single conversion or
continuously conversion. When the conversion is completed, ADC puts the result in the ADC Data Register (ADCD, 8FH)
and sets COM bit of ADSCR (ADSCR.7). After channel selection bit CH[1:0] of ADSCR and P3CON been set, the selected
pin of P3.4~P3.7 will function as ADC input pin instead of general purpose I/O pin which is due to priority of ADC function is
higher than I/O function. The rest of the P3.4~P3.7 pin will still function as general purpose I/O pin. Writes to the port register
will have no affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return the
value in the port which is been read.
6.1 Straight line conversion
The ADC conversion relationship of input analog signal to digital output value is a linear straight line conversion relationship.
It will convert input signal in +Vdd V or above to 0FFH (full scale) and convert input signal +0V or below to 00H. The +Vdd is
the voltage applied to the IC.
6.2 ADC input clock frequency range
ADC input clock frequency range = 500KHz ~ 2.5MHz. User need to be aware of this frequency range limitation when using
ADC function. The frequency range limitation was induced by the sample-and-hold and DAC converter circuits inside of the
ADC submodule. If the ADC input clock frequency resides outside of the range then ADC function may not work.
ADC input clock frequency = oscillator frequency / divider. Divider elected by ADCSS[1:0] setting of ADSCR
One conversion time = 20 ADC clock cycles / ADC input clock frequency
Maximum sample rate of ADC = ADC input clock frequency / 20
6.3 ADC registers - ADSCR, ADR
ADC Registers - ADSCR, 8EH)
bit-7
COM
R
bit-0
CON
R/W
0
ADCSS1 ADCSS0
CH1
R/W
0
CH0
R/W
0
R
-
R
-
Read /Write:
Reset value:
R/W
0
R/W
0
0
*
*
COM: ADC conversion complete bit. This bit is a read only bit which is set each time conversion is completed. It is
cleared whenever ADSCR is written or ADCD is read. Reset clears this bit.
COM = 1 means conversion completed
COM = 0 means conversion not completed
CON: ADC continuous conversion bit. When set, the ADC will convert samples continuously and update the ADCD
register at the end of each conversion. When reset, only one conversion is allowed. Reset clears this bit.
CON = 1 means continuous mode
CON = 0 means signal mode
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ADCSS[1:0]: ADCSS channel select bit.
ADCSS1
ADCSS0
ADC_CLK
Fosc / 8 (below 20MHz)
Fosc / 16
0
0
1
1
0
1
0
1
Fosc / 32
Fosc / 64
CH[1:0] : ADC channel select bit. These bits are used to select one of the ADC channels.
CH1
CH0
Input select
CH0
0
0
1
1
0
1
0
1
CH1
CH2
CH3
Note: ADC_CLK frequency range 500KHz ~ 2.5MHz
ADC registers - ADC Data Register (ADCD, 8FH)
bit-7
AD7
R
bit-0
AD0
R
AD6
R
AD5
R
AD4
R
AD3
R
AD2
R
AD1
R
Read /Write:
Reset value:
0
0
0
0
0
0
0
0
ADC puts the result in the ADC Data Register (ADCD, 8FH) after each conversion. The ADCD register is read only regis-
ter. The content of the ADCD will be 00H after reset.
Ex : Osc = 20MHz ADCSS[1:0] = 00
ADC input clock = 20/8 = 2.5MHz (Max)
One conversion time = 20 / 2.5MHz = 8us
ADC Max sample reta = 2.5MHz / 20 = 125KHz
Port 3 Configuration Register (P3CON, 9DH)
bit-7
ADCE3
R/W
0
bit-0
ADCE2
R/W
0
ADCE1
R/W
0
ADCE0
R/W
0
Unused Unused
Unused
Unused
Read /Write:
Reset value:
-
-
-
-
*
*
*
*
Set ADCE3
ADCE3
= 1 enables the ADC function on pin P3.7/A15/ADC3,
= 0 disables the ADC function on pin P3.7/A15/ADC3,
= 1 enables the ADC function on pin P3.6/A14/ADC2,
= 0 disables the ADC function on pin P3.6/A14/ADC2,
Set ADCE2
ADCE2
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Set ADCE1
= 1 enables the ADC function on pin P3.5/A13/ADC1,
= 0 disables the ADC function on pin P3.5/A13/ADC1,
= 1 enables the ADC function on pin P3.4/A12/ADC0,
= 0 disables the ADC function on pin P3.4/A12/ADC0,
ADCE1
Set ADCE0
ADCE0
User may compare bits ADCE[3:0] of P3CON with bits CH[1:0] of ADSCR. User may consider P3CON as register for dis-
tinguish general purpose I/O function from other specific functions. After bit ADCE[3:0] been set, the corresponding I/O pin
will be assigned as high impedance input pins for signal input. On the other hand, the setting of CH[1:0] will select ADC
channels accordingly.
6.4 ADC Interrupt
The ADC module will generate one interrupt once one analog-to-digital conversion is completed. The ADC interrupt vector
locates at 4BH. There are three SFRs for configuring ADC interrupt: IP1, IE1 and IFR. To use ADC interrupt is the same
as to use other generic 8052 interrupts. That means using EADC of IE1 for enable/disable ADC interrupt, using PADC for
assign ADC interrupt priority. Whenever ADC interrupt occurs, ADCIF will be set to 1. After ADC interrupt subroutine (vec-
tor) been executed, ADCIF will be cleared to 0.
Interrupt Priority I Register (IP1, 0B9H)
bit-7
bit-0
Unused
Unused
Unused
Unused
PADC
R/W
0
Unused
Unused
Unused
Read /Write:
Reset value:
-
-
-
-
-
-
-
*
*
*
*
*
*
*
Interrupt priority bit PADC = 1 assigns high interrupt priority of ADC interrupt
Interrupt priority bit PADC = 0 assigns low interrupt priority of ADC interrupt
Interrupt Enable I Register (IE1, 0A9H)
bit-7
bit-0
Unused
Unused
Unused
Unused
EADC
R/W
0
Unused
Unused
Unused
Read /Write:
Reset value:
-
-
-
-
-
-
-
*
*
*
*
*
*
*
Interrupt enable bit EADC = 1 enables the ADC interrupt
Interrupt priority bit EADC = 0 disables the ADC interrupt
Interrupt Flag Register (IFR, 0AAH)
bit-7
bit-0
Unused
Unused
Unused
Unused
ADCIF
R/W
0
Unused
Unused
Unused
Read /Write:
Reset value:
-
-
-
-
-
-
-
*
*
*
*
*
*
*
Interrupt flag bit ADCIF will be set to 1 when ADC interrupt occurs. Interrupt flag bit ADCIF will be clear to 0 if ADC
Interrupt subroutine executed.
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7. LCD Driver
SM79108 incorporates an on-chip LCD driver which generates segment and common signals output according to the dis-
play data saved in LCD buffer registers (0E1H~0E7H) and incorporates segment and common drivers which can drive the
LCD panel directly.
The on chip LCD Driver has the following features:
1/4 duty (time multiplexing by 4) and 1/3 bias LCD segment driver
0.88 mA operation current (1.2 uA in power down mode)
56 bits of display data buffer
14 segment driver and 4 common driver outputs
A frames frequency can be selected
7.1 LCD Control register (LCDCON, 0DFH)
bit-7
LCD_ON
R/W
bit-0
LS0
R/W
0
LCD_EN
R/W
SEG
R/W
0
Unused
Unused
LS2
R/W
0
LS1
R/W
0
Read /Write:
Reset value:
-
-
0
0
*
*
LCDCON7~LCDCON0: LCD control register is used to control LCD driver operation
LCD_ON: LCD display bit
= 1:LCD display ON
= 0:LCD display OFF
LCD_EN: LCD enable bit
SEG: = 1:enables the LCD function on pin #PSEN/SEG4 and ALE/SEG5
= 0:no operation
LS[2:0]: Frequency prescaler select, determine the clock frequency of LCD driver, Fclk_lcd
LS2
0
LS1
0
LS0
0
PRESCALER SELECT
1
2
0
0
1
1
0
4
0
1
1
1
1
1
1
8
0
0
16
32
64
128
0
1
1
0
1
1
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The clock frequency of LCD driver is obtained using the following formula:
Fclk_lcd = { [Fosc / 2 ] / 32 x PRESCALER }
The frame of LCD driver is determined as follows:
Frame = Fclk_lcd / 256
The typical range of Fframe is:
1026HZ ~ 8HZ at 16MHz (Fosc = 8MHz)
7.2 LCD Buffer Registers (LCDB0 ~ LCDB6, 0E1H ~ 0E7H)
Addressing Map of the LCD buffer registers is shown as following:
com3
Bit7
com2
Bit6
com1
Bit5
com0
Bit4
com3
Bit3
com2
Bit2
com1
Bit1
com0
Bit0
Mnemonic address
LCDB0
LCDB1
LCDB2
LCDB3
LCDB4
LCDB5
LCDB6
E1H
E2H
E3H
E4H
E5H
E6H
E7H
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
7.3 Timing chart of LCD driver output
The 14 segment drivers and the 4 common drivers are 4-level outputs that switch between Vcc and the V1, V2
and Vss LCD driver voltages levels.
The output states are determined by the display data values which stored in the LCD buffer registers (0E1H
~0E7H).
The LCD driver's outputs are used to drive a 1/3-bias, 1/4-duty LCD panel.
7.4 The Output Control of Segments and Commons
Port 2 Configuration Register (P2CON) control COM0 ~ COM3 and SEG0 ~ SEG3 output; Port 0 Configuration
Register (P0CON) controls SEG6 ~ SEG13 outputs.
The bit 5 of LCD Control Register control the SEG4 and SEG5 outputs.
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Figure 6.1 Output states determination
Frame period
Vcc
V1
COM0 V2
VSS
Vcc
V1
COM1 V2
VSS
Vcc
V1
COM2 V2
VSS
Vcc
V1
COM3 V2
VSS
Vcc
V1
COM0 COM1 COM2 COM3
SEG0 V2
VSS
0
0
0
0
Vcc
V1
All segments are OFF
SEG1 V2
VSS
1
0
0
0
Segments connected to COM0
are ON
Vcc
V1
SEG2 V2
VSS
0
1
0
0
Vcc
V1
Segments connected to COM1
are ON
SEG3 V2
VSS
1
1
1
1
All segments are ON
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Operating Conditions
Symbol
TA
Description
Min.
-40
Typ. Max. Unit. Remarks
oC
V
Operating temperature
25
85
Ambient temperature under bias
VCC5
VCC3
Supply voltage
4.5
3
5.0
3.3
25
5.5
3.6
25
Supply voltage
V
Fosc 25
Fosc 40
Oscillator Frequency
Oscillator Frequency
3.0
3.0
MHz For 5V, 3.3V application
MHz For 5V application
40
40
DC Characteristics
(TA = -40 oC to 85 oC, Vcc = 5V)
Symbol
VIL1
Parameter
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Output High Voltage
Valid
port 0,1,2,3,4,#EA
Min.
-0.5
0
Max.
1.0
Unit
V
Test Conditions
Vcc = 5V
VIL2
RES, XTAL1
port 0,1,2,3,4,#EA
RES, XTAL1
port 12,3,4
0.8
V
“
“
“
VIH1
2.0
Vcc+0.5
V
VIH2
70%Vcc Vcc+0.5
V
VOL1
VOL2
VOH1
0.4
V
IOL = 1.6mA
IOL = 3.2mA
IOH = -60uA
IOH = -10uA
IOH = -800uA
IOH = -80uA
Vin = 0.45V
Vin = 2.0V
port 0,2,port 3.0~port 3.3, ALE, #PSEN
port 1, 2, 3, ALE, #PSEN
0.4
V
2.4
90%Vcc
2.4
V
V
VOH2
Output High Voltage
port 0
V
90%Vcc
-50
V
IIL
ITL
ILI
Logical 0 Input Current
Logical Transition Current
Input Leakage Current
port 1,2,4, port 3.0~port 3.3
port 1,2,4, port 3.0~ port3.3
port 0, #EA
uA
uA
uA
uA
Kohm
pF
-650
10
Vin = 0.45V
Vin = 5V
10
R RST
C IO
Reset Pulldown Resistor
Pin Capacitance
18
90
10
Freq=1MHz, Ta=25oC
I CC
Power Supply Current
Vdd
20
10
mA Active mode, 16MHz
mA Idle mode, 16MHz
100
uA
down mode, 16MHz
Note1: Under steady state (non-transient) conditions, IOL must be externally
Limited as follows: Maximum IOL per port pin : 10mA
Maximum IOL per 8-bit port : port 0
:26mA
port 1,2,3 :15mA
Maximum total IOL for all output pins : 71mA
If IOL exceeds the condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
Note2 : Minimum VCC for Power-down is 2V.
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AC Characteristics
(16/25/40MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=150pF; CL for all Other Output=80pF)
Valid
Cycle
fosc=16MHz
Min. Typ. Max
Variable fosc
Typ. Max
Unit Remarks
Symbol
T LHLL
T AVLL
T LLAX
T LLIV
Parameter
Min.
ALE pulse width
RD/WRT 115
2xT - 10
T - 20
nS
nS
nS
Address Valid to ALE low
Address Hold after ALE low
ALE low to Valid Instruction In
ALE low to #PSEN low
#PSEN pulse width
RD/WRT
RD/WRT
RD
43
53
T - 10
240
177
4xT - 10 nS
T LLPL
T PLPH
T PLIV
RD
53
T - 10
nS
nS
RD
173
3xT - 15
#PSEN low to Valid Instruction In
Instruction Hold after #PSEN
Instruction Float after #PSEN
Address to Valid Instruction In
#PSEN low to Address Float
#RD pulse width
RD
3xT - 10 nS
nS
T PXIX
RD
0
0
T PXIZ
RD
87
292
10
T + 25 nS
5xT - 20 nS
10 nS
nS
T AVIV
RD
T PLAZ
T RLRH
T WLWH
T RLDV
T RHDX
T RHDZ
T LLDV
T AVDV
T LLYL
RD
RD
365
365
6xT - 10
6xT - 10
#WR pulse width
WRT
RD
nS
#RD low to Valid Data In
Data Hold after #RD
302
5xT - 10 nS
nS
RD
0
0
Data Float after #RD
RD
145
590
542
2xT + 20 nS
8xT - 10 nS
9xT - 20 nS
3xT + 10 nS
nS
ALE low to Valid Data In
Address to Valid Data In
ALE low to #WR High or #RD low
Address Valid to #WR or #RD low
Data Valid to #WR High
Data Valid to #WR transition
Data hold after #WR
RD
RD
RD/WRT
RD/WRT
WRT
WRT
WRT
RD
178
230
403
38
197 3xT - 10
4xT - 20
7xT - 35
T - 25
T AVYL
T QVWH
T QVWX
T WHQX
T RLAZ
T YALH
T CHCL
T CLCX
T CLCH
T CHCX
T, TCLCL
nS
nS
73
T + 10
nS
#RD low to Address Float
#WR or #RD high to ALE high
clock fall time
5
nS
RD/WRT
53
72
T -10
T + 10 nS
nS
nS
nS
nS
nS
clock low time
clock rise time
clock high time
clock period
63
1/fosc
Vcc
ICC Active mode test circuit
ICC
Vcc
VCC
8
RST
PO
EA
SM79108
XTAL2
XTAL1
VSS
(NC)
Clock Signal
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Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
0.45V
70%Vdd
20%Vdd-0.1V
TCLCX
TCHCX
TCHCL
TCLCH
Tm.I External Program Memory Read Cycle
TPLPH
#PSEN
TLHLL
TAVLL
TLLPL
TPXIZ
TPXIX
ALE
TPLAZ
TLLAX
TPLIV
Instruction. IN
A0 - A7
A0 - A7
PORT 0
TAVIV
A8 - A15
A8 - A15
PORT 2
Tm.II External Data Memory Read Cycle
#PSEN
TYHLH
ALE
TLLDV
TRLRH
TLLYL
#RD
PORT 0
PORT 2
TAVLL
TRHDZ
TRHDX
DATA IN
TLLAX
TRLDV
TRLAZ
A0 - A7
from Ri or DPL
A0 - A7
from PCL
INSTRL
IN
TAVYL
TAVDV
A8 - A15 from PCH
P2.0 - P2.7 or A8 - A15 from DPH
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Tm.III External Data Memory Write Cycle
#PSEN
TYHLH
TLHLL
ALE
TLLYL
TWLWH
TQVWH
TAVLL
#WR
TQVWX
TLLAX
TWHQX
A0-A7
from Ri or DPL
A0-A7
From PCL
INSTRL
IN
DATA OUT
PORT 0
TAVYL
A8-A15 from PCH
P2.0-P2.7 or A8-A15 from DPH
PORT 2
Application Reference
Valid for SM79108
X’tal
C1
C2
R
3MHz
6MHz
30pF
30pF
open
12MHz
16MHz
30pF
30pF
open
30pF
30pF
open
30pF
30pF
open
X’tal
C1
C2
R
20MHz
22pF
22pF
open
25MHz
15pF
33MHz
5pF
40MHz
2pF
15pF
5pF
2pF
62KΩ
6.8KΩ
4.7KΩ
XI
NOTE: Oscillation circuit may differs with different crystal or ceramic
resonator in higher oscillation frequency which was due to each
X'tal
SM79108
crystal or ceramic resonator has its own characteristics.
User should check with the crystal or ceramic resonator manufacturer
for appropriate value of external components.
R
X2
C2
C1
21/26
Ver 2.1
SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
PD IP 40L (600m il) Package Inform ation：
Dim ension in m m
Dim ension in MIL
Sym bol
M in
0.254
3.683
0.356
0.356
1.016
1.016
0.203
0.203
52.07
14.99
13.69
－
Nom
M ax
M in
10
Nom
M ax
－
－
－
－
A1
A2
b
3.810
0.500
0.457
1.270
1.321
0.254
0.254
52.2
3.937
0.660
0.508
1.524
1.626
0.432
0.356
52.32
15.49
13.94
－
145
14
150
20
155
26
14
18
22
b1
b2
b3
c
40
50
60
40
52
64
8
10
17
8
10
14
c1
D
2050
590
539
－
2055
600
546
100
640
130
78
2060
610
549
－
15.24
13.87
2.540
16.26
3.302
1.981
1.778
－
E
E1
e
Note:
1. Refer to JEDEC STD.M S-011(AC).
2. Dim ension D and E1 do not include
m old protrusion. Allow able protrusion
is 0.25 m m per side. D and E1 are
m axim um plastic body size dim ension
include m old m ism atch.
15.75
2.921
1.727
1.651
0°
16.76
3.683
2.235
1.905
10°
620
115
68
660
145
88
eB
L
S
65
70
75
Q 1
θ
3. Dim ension b3 does not include
－
0°
10°
22/26
Ver 2.1
SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
P L C C 4 4 L P a c k a g e I n f o r m a tio n ：
UNIT
INCH(REF)
MM(BASE)
SYMBOL
0.180(MAX)
0.024 ±0.005
0.105 ±0.005
0.018 + 0.004
- 0.002
4.572(MAX)
0.52 ±0.14
A
A1
A2
2.667 ±0.127
0.457 + 0.102
- 0.051
B
0.028 + 0.004
- 0.002
0.711 + 0.102
- 0.051
B1
0.010(TYP)
0.690 ±0.010
0.653 ±0.003
0.610 ±0.020
0.690 ±0.010
0.653 ±0.003
0.610 ±0.010
0.050(TYP)
0.003(MAX)
0~5°
0.254(TYP)
17.526 ±0.254
16.586 ±0.076
15.494 ±0.508
17.526 ±0.254
16.586 ±0.076
15.494 ±0.254
1.270(TYP)
0.076(MAX)
0~5°
c
D
D1
D2
E
E1
E2
e
y
θ
23/26
Ver 2.1
SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
Q FP 44L (10x10x2.0m m ) Package Inform ation：
Dim ension in m m
Dim ension in MIL
Sym bol
M in
Nom
M ax
2.45
0.25
2.10
0.45
0.41
0.23
0.19
13.40
10.10
－
M in
Nom
M ax
964
9.6
－
－
－
－
A
A1
A2
b
0.05
1.90
0.29
0.29
0.11
0.11
13.00
9.90
－
0.15
2.00
0.32
0.30
0.17
0.15
13.20
10.00
0.800
0.88
1.60
－
2.1
74.8
11.4
11.4
4.3
6.0
78.7
12.6
11.8
6.7
82.7
17.7
16.1
9.1
b1
c
Note:
4.3
5.9
7.5
c1
E
1. Refer to JEDC STD.MS-022(AB).
2. Dim ension E1 do not include m old protrusion.
Allowable protrusion is 0.25mm per side.E1 are
m axim um plastic body size dim ension include
m old m ism atch .
512
390
－
520
394
31.5
34.6
63.0
－
528
398
－
E1
【 e】
L
0.73
1.50
－
1.03
1.70
0.076
28.7
59.1
－
40.6
66.9
3
3. Dim ension b does not include dam bar
protrusion .Allowable dam bar protrusion shall not
cause the lead width to exceed the m axim um b3
L1
y
Specifications subject to change without notice,contact your sales representatives for the most recent information.
24/26
Ver 2.1 SM79108 08/2006
SyncMOS Technologies International. Inc.
SM79108
eMCU Writer List
Contact info
Company
Programmer Model Number
Advantech
Tel:02-22182325
LabTool - 48 (1 * 1)
7F, No.98, Ming-Chung Rd.,
Shin-Tien City, Taipei, Taiwan,
ROC
Fax:02-22182435
E-mail:
aecwebmaster@advantech.com.tw
LabTool - 848 (1*8)
* Note: Not yet, about 3/E’03
Web site:
http://www.aec.com.tw
Hi-Lo
Tel:02-87923301
Fax:02-87923285
E-mail:
All - 11 (1*1)
Gang - 08 (1*8)
* Note: Not yet, about 3/E’03
4F, No. 20, 22, LN, 76,
Rui Guang Rd., Nei Hu, Taipei,
Taiwan, ROC.
support@hilosystems.com.tw
Web site:
http://www.hilosystems.com.tw
Leap
Tel:02-29991860
Fax:02-29990015
E-mail:
SU - 2000 (1*8)
* Note: Not yet, about 3/E’03
6th F1-4, Lane 609,
Chunghsin Rd., Sec. 5, Sanchung,
Taipei Hsien, Taiwan, ROC
Web site:
service@leap.com.tw
http://www.leap.com.tw
Xeltek Electronic Co., Ltd
338 Hongwu Road, Nanjing, China
210002
Tel:+86-25-4408399, 4543153-206
E-mail:
xelclw@jlonline.com,
xelgbw@jlonline.com
Superpro/2000 (1*1)
Superpro/680 (1*1)
Superpro/280 (1*1)
Superpro/L+(1*1)
Web site:
http://www.xeltek-cn.com
* Note: Not yet, about 3/E’03
25/26
Ver 2.1
SM79108 08/2006
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