Each address and data transmission uses 9-clock pulses. The ninth pulse is the acknowledge bit (ACK). After the
START condition, the master sends 7-slave address bits and an R/ W bit during the next 8-clock pulses. During the
ninth clock pulse, the device that recognizes its own address holds the data line low to acknowledge. The
acknowledge bit is also used by both the master and the slave to acknowledge receipt of register addresses and data.
C master device. The control byte begins with a START
condition, followed by 7-bits of slave address (1000001x for the SYR828, this address can be changed if necessary)
followed by the 8 bit, R/ W bit. The R/ W bit is 0 for a write or 1 for a read. If any slave devices on the I
recognize their address, they will acknowledge by pulling the SDA line low for the last clock cycle in the control
byte. If no slaves exist at that address or are not ready to communicate, the data line will be 1, indicating a Not
Acknowledge condition. Once the control byte is sent, and SYR828 acknowledges it, the 2nd byte sent by the master
must be a register address byte. The register address byte tells the SYR828 which register the master will write or
read. Once the SYR828 receives a register address byte it responds with an acknowledge.
SYR828 Rev. 0.1
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