TSL3301-LF [TAOS]
102 】 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG-TO-DIGITAL CONVERTER; 与模拟数字转换器102 】 1非线性光学传感器阵列
| 型号： | TSL3301-LF |
| 厂家： | 
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
| 描述： | 102 】 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总16页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
r
r
TAOS0078C − APRIL 2007
DIP PACKAGE
(TOP VIEW)
D 102 × 1 Sensor Element Organization
D 300 Dots-per-Inch Pixel Pitch
D High Sensitivity
SCLK 1
VDD
8 NC
D On-Chip 8-Bit Analog-to-Digital Conversion
D Three-Zone Programmable Offset (Dark Level) and Gain
D High Speed Serial Interface
D 1 MHz Pixel Rate
2
7 GND
6 GND
5 NC
SDIN 3
D Single 3-V to 5.5-V Supply
D Replacement for TSL3301
SDOUT 4
D RoHS Compliant
NC − No internal connection
Description
The TSL3301−LF is a high-sensitivity 300-dpi, linear optical sensor array with integrated 8-bit analog-to-digital
converters. The array consists of 102 pixels, each measuring 85 μm (H) by 77 μm (W) and spaced on 85 μm
centers. Associated with each pixel is a charge integrator/amplifier and sample-hold circuit. All pixels have
concurrent integration periods and sampling times. The array is split into three 34-pixel zones, with each zone
having programmable gain and offset levels. Data communication is accomplished through a three-wire serial
interface.
Intended for use in high performance, cost-sensitive scanner applications, the TSL3301−LF is based on a linear
sensor array die that has expanded capability, including multi-die addressing and cascade options. Please
contact TAOS for additional information on die and multi-die package availability.
Copyright E 2007, TAOS Inc.
The LUMENOLOGY r Company
Texas Advarnced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972) 673-0759
www.taosinc.com
1
TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
Functional Block Diagram
PIXEL ARRAY WITH INTEGRATORS AND S−H
(51-bit shift register)
PIXCLK
SI
HOLD
ZERO
LEFT ODD
LEFT EVEN
RIGHT ODD
RIGHT EVEN IREF
8
5
DB<7:0>
SCLK
SDIN
ADDR<4:0>
READ
VREF
IREF
OUTPUT CHARGE-TO-
VOLTAGE CONVERTER
WITH PROGRAMMABLE
GAINS AND OFFSETS
DIGITAL I/O
AND
CONTROL
WRITE
3
SDOUT
SECTOR
BIAS
BLOCK
VREF
IREF
RESET/SAMPLE
START
DUAL 8−BIT
SA ADC
ADCLK
Copyright E 2007, TAOS Inc.
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TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
6, 7
1
GND
Ground
SCLK
SDIN
I
I
System clock input for serial I/O and all internal logic.
Serial data input. Data is clocked in on the rising edge of SCLK.
Serial data output. Data is clocked out on the falling edge of SCLK.
Positive supply voltage.
3
SDOUT
4
O
V
2
DD
Detailed Description
The TSL3301−LF is a 102 × 1 linear optical array with onboard A/D conversion. It communicates over a serial
digital interface and operates over a 3 V to 5.5 V range. The array is divided into three 34-pixel zones (left, center,
and right), with each zone having programmable gain and offset (dark signal) correction.
The sensor consists of 102 photodiodes, also called pixels, arranged in a linear array. Light energy impinging
on a pixel generates a photocurrent, which is then integrated by the active integration circuitry associated with
that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through
an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity
(E ) on that pixel and to the integration time (t ). At maximum programmed gain, one LSB corresponds to
e
int
approximately 300 electrons.
Integration, sampling, output, and reset of the integrators are performed by the control logic in response to
commands input via the SDIN pin. Data is read out on the SDOUT pin. A normal sequence of operation consists
of a pixel reset (RESET), start of integration (STARTInt), integration period, sampling of integrators
(SAMPLEInt), and pixel output (READPixel). Reset sets all the integrators to zero. Start of integration releases
the integrators from the reset state and defines the beginning of the integration period. Sampling the integrators
ends the integration period and stores the charge accumulated in each pixel in a sample and hold circuit.
Reading the pixels causes the sampled value of each pixel to be converted to 8-bit digital format and output on
the SDOUT pin. All 102 pixels are output sequentially unless interrupted by an abort (ABORTPixel) command
or reset by a RESET command.
Gain adjustment is controlled by three 5-bit DACs, one for each of the the three zones. Table 1 lists the gain
settings and the corresponding pixel values. Offset is affected by the gain setting and may have to be adjusted
after gain changes are made.
†
Offset correction is controlled by three 8-bit sign-magnitude DACs and is performed in the analog domain prior
to the digital conversion. There is a separate offset DAC for each of the three zones. Codes 0h − 7Fh correspond
to positive offset values and codes 80h – FFh correspond to negative offset values.
The offset correction is proportional to the gain setting. At minimal gain, one LSB of the offset DAC corresponds
to approximately 1/3 LSB of the device output, and at maximum gain, to about 1 LSB of the device output.
Note that the gain and offset registers are in indeterminate states after power up and must be set by the controller
as required.
†
Sign-magnitude is a binary representation in which the most significant bit (MSB) is used to represent the sign of the number, with the
remaining bits representing the magnitude. An MSB of 1 indicates a negative number.
Copyright E 2007, TAOS Inc.
The LUMENOLOGY r Company
r
r
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3
TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
Table 1. Gain Settings and Results
GAIN CODE
RELATIVE GAIN
1
% INCREASE
GAIN CODE
RELATIVE GAIN
1.52
% INCREASE
3.23
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1.02
2.17
2.22
2.27
2.33
2.38
2.44
2.50
2.56
2.63
2.70
2.78
2.86
2.94
3.03
3.13
1.57
3.33
2
1.05
1.62
3.45
3
1.07
1.68
3.57
4
1.09
1.74
3.70
5
1.12
1.81
3.85
6
1.15
1.88
4.00
7
1.18
1.96
4.17
8
1.21
2.05
4.35
9
1.24
2.14
4.55
10
11
12
13
14
15
1.27
2.24
4.76
1.31
2.35
5.00
1.34
2.48
5.26
1.38
2.61
5.56
1.43
2.77
5.88
1.47
2.94
6.25
Serial interface
The serial interface follows a USART format, with start bit, 8 data bits, and one or more stop bits. Data is clocked
in synchronously on the rising edge of SCLK and clocked out on the falling edge of SCLK. Stop bits are not
required on the input. When clocking data out continuously (i.e., reading out pixels) there will be one stop bit
between data words.
The receive and transmit state machines are independent, which means commands can be issued while
reading data. This feature allows starting new integration cycles while reading data. Note that this allows
undefined conditions so care must be taken not to issue commands that will cause outputs (such as register
read) while reading out data. For instance, issuing a register read command while reading out image data will
result in garbage out. Likewise, it is possible to change offset and gain registers during a readout, which can
give unpredictable results.
It is not necessary to have a continuously active clock, but a minimum of 5 clocks after the stop bit is required
after any command has been issued to ensure that the corresponding internal logic actions have been
completed. When reading register contents, there will be a 4-clock delay from the completion of the REGRead
command before the register contents are output (see Figure 5). When reading out pixel values, there will be
a 44-clock delay from completion of the READPixel command until the first pixel data is output. When starting
integration (STARTInt), it is necessary to have 22 clocks to complete the pixel reset cycle (see Imaging below).
Copyright E 2007, TAOS Inc.
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TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
Register address map
The TSL3301−LF contains seven registers as defined in Table 2. Data in these registers may be written to or
read from using the REGWrite and REGRead commands. Three registers control the gain of the
analog-to-digital converters (ADC). Three other registers allow the offset of the system to be adjusted. Together
the gain and offset registers are used to maximize the achievable dynamic range.
Table 2. Register Address Map
ADDRESS REGISTER DESCRIPTION REGISTER WIDTH
0x00
0x01
0x02
0x03
0x04
0x05
0x1F
Left (pixels 0−33) offset
Left (pixels 0−33) gain
Center (pixels 34−67) offset
Center (pixels 34−67) gain
Right (pixels 68−101) offset
Right (pixels 68−101) gain
Mode
8
5
8
5
8
5
8
The offset registers are 8-bit sign-magnitude values and the gain registers are 5-bit values. The programmed
offset correction is applied to the sampled energy, and then the gain is applied. (i.e., the gain will affect the offset
correction.) These registers allow the user to maximize the dynamic range achievable in the given system.
The last register is the mode register. Bits in this register select the sleep mode as well as options for multichip
arrays and production testing. Note that test and multichip options do not apply to the 8-pin packaged device.
Users should always write zeros into the production test and multichip control bits.
7
6
0
5
0
4
3
2
1
0
0x1F
P2
SLP
P1
P0
C1
C0
MODE
SLP = Sleep Mode:
C1, C0 are Reserved (should be written 0)
1 places device into sleep mode
0 places device in normal operating mode
P2 to P0 are factory test bits (should be written 0)
Figure 1. Mode Register Bit Assignments
Copyright E 2007, TAOS Inc.
The LUMENOLOGY r Company
r
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5
TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
Command description
The TSL3301−LF is a slave device that reacts strictly to commands received from the digital controller. These
commands cause the device to perform functions such as reset, integrate, sample, etc. Table 3 summarizes
the command types and formats and Table 4 lists the command set for the TSL3301−LF. Each command is
described in more detail below.
Table 3. Command Type and Format Summary
COMMAND TYPE
Action command
Register write
FORMAT
< Command byte >
< Command byte > < Data byte >
Table 4. TSL3301−LF Command Set
COMMAND
HEX CODE
DESCRIPTION
SDIN held low for 30
clocks
IRESET
Interface Reset
RESET
0x1B
0x08
Reset Integration and read blocks
STARTInt
Start pixel integration
SAMPLEInt
READPixel
ABORTPixel
READHold
READHoldNStart
REGWrite
0x10
Stop light integration and sample results
Dump serial the contents of each sampled integrator
Abort any READPixel operation in progress
Combination of SAMPLEInt and READPixel commands
Combination of SAMPLEInt, READPixel and STARTInt commands
Write a gain, offset, or mode register
0x02
0x19
0x12
0x16
0x40 + address
0x60 + address
REGRead
Read a gain, offset, or mode register
Copyright E 2007, TAOS Inc.
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TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
PROGRAMMING INFORMATION
A minimum of 5 clock cycles after the stop bit is required after any command to ensure that the internal logic
actions have been completed.
Reset Commands
Reset commands are used to put the TSL3301−LF into a known state.
IRESET — Interface Initialization
Encoding: Break Character (10 or more consecutive start bits, or zeros)
The commands vary in length from one to three bytes. IRESET initializes the internal state machine that keeps
track of which command bytes have been received. This command should be first and given only once after
power-up to synchronize the TSL3301−LF internal command interpreter.
An alternative is to issue three successive RESET commands.
RESET — Main Reset
Encoding: 0x1b: <0001_1011>
RESET resets most of the internal control logic of the TSL3301−LF and any READPixel command currently in
progress is aborted. RESET puts the pixel integrators into the auto-zero/reset state. Any values that were being
held in the array’s sample/hold circuits are lost.
NOTE:
The value on the SDOUT pin is not guaranteed from the time power is applied until 30 clocks after
the first RESET command is issued.
Pixel Action Commands
Pixel action commands allow the user to control pixel integration and reading of pixel data.
STARTInt — Start Integration
Encoding: 0x08: <0000_1000>
STARTInt causes each pixel to leave the reset state and to start integrating light. The actual execution
of STARTInt is delayed 22 clock cycles until the pixel reset cycle has been completed. (See imaging below.)
SAMPLEInt — Stop Integration
Encoding: 0x10: <0001_0000>
SAMPLEInt causes each pixel to store its integrator’s contents into a sample and hold circuit. Also, the Integrator
is returned to the reset state.
READPixel — Read Pixel Data
Encoding: 0x02: <0000_0010>
READPixel causes the sampled value of each pixel to be converted to an 8-bit digital value that is clocked out
on the SDOUT pin. The LSB is the first data bit, which is preceded by a START bit (logic 0) and followed by a
STOP bit (logic 1). Each pixel in the device is presented on SDOUT starting from pixel 00 and completes with
pixel 101. There is a 44-clock cycle delay from the completion of the READPixel command until the first pixel
data is output.
Gain and offset registers are used to adjust the ADC converter to maximize dynamic range and should be
programmed prior to invoking the READPixel command.
Copyright E 2007, TAOS Inc.
The LUMENOLOGY r Company
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7
TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
ABORTPixel — Abort Pixel Data Read
Encoding: 0x19: <0001_1001>
ABORTPixel is an optional command that stops a READPixel command during its execution. It also causes pixel
integration to terminate and the device to enter the auto-zero/reset state. Any values that were being held in
the array’s sample/hold circuits are lost.
READHold — Sample and Read Combination
Encoding: 0x12: <0001_0010>
READHold is a macro command that combines both the SAMPLEInt and READPixel commands into a single
command.
READHoldNStart Combination
Encoding: 0x16: <0001_0110>
READHold is a macro command that combines the SAMPLEInt, READPixel, and StartInt commands into a
single command. 22 clock cycles are necessary to complete the pixel reset cycle.
Register Commands
The register commands provide the user the capability of setting gain and offset corrections for each of the three
zones of pixels. a4−a0 refer to the register address as given in Table 2.
REGWrite — Write a Gain/Offset/Mode Register
Encoding (2 bytes): 0x40 <data>: <010a4_a3a2a1a0> <d7d6d5d4_d3d2d1d0>
REGWrite writes a value into either a gain, offset, or mode register. The 5-bit address of the register is encoded
into the lower 5 bits of the command byte (the first byte). A second byte, which contains the data to be written,
follows the command byte.
REGRead — Read a Gain/Offset/Mode Register
Encoding: 0x60: <011a4_a3a2a1a0>
REGRead reads the value previously stored in a gain, offset, or mode register. The 5-bit address of the register
is encoded into the lower 5 bits of the command byte. Following receipt of the REGRead command, the device
places the contents of the selected register onto the SDOUT pin, LSB first.
There is a 4-clock cycle delay from the completion of the REGRead command until the register contents are
output.
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TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
OPERATION
Initialization Sequence
After powering on the device, a minimum of 10 clocks with SDIN held high must be received by the TSL3301−LF
to clear the receiver logic so that a start bit will be detected correctly. The control logic may then be cleared by
either issuing an IRESET command (break character) or 3 RESET (0x1b) commands. An additional 30 clocks
must be received by the device to assure the state of SDOUT.
Sleep Mode
The device can be put into a power down or sleep mode by writing a 0x10 to the mode register. This turns off
all the analog circuitry on the chip. Normal operation is restored by writing a 0x00 to the mode register. The
†
analog circuitry will require a minimum of 1 millisecond to recover from the sleep mode.
Note that putting the device in the sleep mode does not affect the logic states of the machine. If, for example,
a READPixel command is issued, the device will respond but the resulting data will be meaningless. Also note
that 0x00 and 0x10 are the only two legitimate user programmable values for the single-chip version of the
TSL3301−LF. Other values may put the device into a non-operational mode.
†
For minimum sleep mode current consumption, voltage levels on logic inputs must be at either V or ground.
DD
Imaging
After powering up the device and completing the initialization sequence, it is necessary to allow a minimum of
1 millisecond for the internal analog circuitry to settle. This delay is also required when coming out of the sleep
mode.
Issuing a STARInt (0x08) command will release the pixel integrators from the reset state. After an appropriate
delay to integrate the image, the pixel data may be sampled by issuing a SAMPLEInt (0x10) command and then
read out by issuing a READPixel (0x02) command.
A STARTInt command can be issued anytime after the SAMPLEInt command is issued to start another cycle.
Thus, it is possible to be reading out one sample while integrating the next. However, the sampled data from
the previous SAMPLEInt must be completely read out before the next SAMPLEInt command is issued.
The compound commands READHold (0x12) and READHoldNStart ((0x16) are shortcut commands to simplify
the imaging sequence.
It is important to note that a pixel reset sequence is initiated with the receipt of a STARTInt or READHoldNStart
command. The next integration sequence cannot start until the pixel reset sequence has been completed, which
requires 22 clocks AFTER the receipt of one of these commands. These clocks can also be used to clock
commands or data into or out of the device.
Copyright E 2007, TAOS Inc.
The LUMENOLOGY r Company
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9
TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
DD
Digital output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V
O
DD
Digital output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 to +10 mA
Digital input current range, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA to 20 mA
I
Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25_C to 85_C
‡
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Not recommended for solder reflow.
Recommended Operating Conditions
MIN NOM
MAX
UNIT
Supply voltage, V
3
2
5
5.5
V
V
V
DD
High-level input voltage at SCLK, SDIN, V
V
DD
IH
Low-level input voltage at SCLK, SDIN, V
0.8
IL
Power supply ripple, 100 kHz sawtooth waveform
Input clock (SCLK) rise time, 10% to 90%
60 mVp-p
30
70
10
ns
°C
Operating junction temperature, T
0
J
Maximum clock frequency, f
MHz
SCLK
Electrical Characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
4.95
4.6
2.9
2.7
0.01
0.4
11
MAX
UNIT
I
I
I
I
= 50 μA
= 4 mA
= 50 μA
= 4 mA
4.5
O
O
O
O
V
V
= 5 V
DD
DD
V
V
High-level output voltage, SDOUT
V
OH
OL
= 3.3 V
I
I
= 50 μA
0.1
O
O
Low-level output voltage, SDOUT
Supply current
V
= 4 mA
A/D active
17
11
mA
A/D inactive
Sleep mode
6
I
DD
10
μΑ
V
V
V
Low-level input voltage (SCLK, SDIN)
High-level input voltage (SCLK, SDIN)
High-level input current (SCLK, SDIN)
Low-level input current (SCLK, SDIN)
0.8
IL
2
V
IH
I
I
V = V
DD
±10
±10
μΑ
μΑ
IH
IL
I
V = 0
I
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TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
Light-to-Digital Transfer Characteristics at VDD = 5 V, TJ = 25°C, λp = 660 nm, tint = 250 μs (unless
otherwise noted)
PARAMETER
A-to-D converter resolution
TEST CONDITIONS
MIN
TYP
8
MAX
UNIT
Bits
Gain register = 00000b
Gain register = 11111b
3.6
1.24
2
nJ/cm
Full-scale reference
For converter only, does not include
photodiode characteristics
Full-scale reference temperature sensitivity
±150
ppm/°C
Gain register = 00000b
0
7
20
5
30
Average dark-level offset
Offset register = 00000000b
LSB
LSB
Gain register = 11111b
Gain register = 00000b, see Note 1
Gain register = 11111b, see Note 1
Gain register = 00000b
10
14
Dark signal nonuniformity (DSNU)
160
200
200
240
2
Ee = 11.3 μW/cm
Offset register =
00000000b
Average white level output
LSB
Gain register = 11111b
2
Ee = 3.77 μW/cm
2
Pixel-response non-uniformity (PRNU)
Programmable offset steps
Ee = 11.3 μW/cm , See Notes 2 and 3
±8% ±10%
±128
0.5
1.5
2
Gain register = 00000b
Gain register = 11111b
Programmable offset step size
LSB
Dark-level change with temperature
Differential nonlinearity
0°C < T < 70°C
LSB
LSB
LSB
J
±0.5
±1
Integral nonlinearity
Gain register = 00000b
Gain register = 11111b
0.5
1.5
Dark level noise
LSB
NOTES: 1. DSNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is not
illuminated.
2. PRNU does not include DSNU.
3. PRNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is uniformly
illuminated at nominal white level (typical average output level = 200).
Timing Requirements over recommended operating range (unless otherwise noted) (Figure 2)
MIN NOM
MAX
UNIT
MHz
ns
f
t
t
t
t
Maximum clock frequency
Clock high pulse duration
Clock low pulse duration
Input setup time
10
30
30
20
20
max
w(CLKH)
w(CLKL)
su
ns
ns
Input hold time
ns
h
Switching Characteristics over recommended operating range (unless otherwise noted) (Figure 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX
UNIT
ns
t
t
t
Rise time, output
Fall time, output
r
C = 20 pF
L
10
ns
f
Delay from clock edge to data-out stable
Input pin capacitance
20
ns
d
C
10
pF
i
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TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
TYPICAL CHARACTERISTICS
V
IH
t
w(CLKH)
SCLK
SDIN
t
w(CLKL)
V
V
IL
t
h
t
su
IH
V
IL
Figure 2. TSL3301−LF Input Timing Requirements
V
IH
SCLK
V
V
IL
t
d
OH
SDOUT
V
OL
Figure 3. TSL3301−LF Output Switching Characteristics
SCLK
SDIN
Start
B4
B0
B2
B3
B6
B7
B1
B5
Stop
Serial Input Data Format
SCLK
Start
B4
B0
B2
B3
B6
B7
B1
B5
Stop
SDOUT
Serial Output Data Format
Figure 4. TSL3301−LF Serial I/O
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TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
TYPICAL CHARACTERISTICS
SCLK
SDIN
1
2
3
4
B7
Stop
END of REGRead Command
SDOUT
Start
B0
Beginning of Output Response
Figure 5. TSL3301−LF REGRead Output Response Timing
PHOTODIODE SPECTRAL RESPONSIVITY
1.2
Normalized to
660 nm
T
A
= 25°C
1.0
0.8
0.6
0.4
0.2
0
300
500
700
900
1100
λ − Wavelength − nm
Figure 6. TSL3301−LF Photodiode Spectral Response
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TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
APPLICATION INFORMATION
Normal Sequence
A typical programming sequence for the TSL3301−LF device appears below:
Send(IRESET);
Send(RESET);
Calibration Cycle
*
*
while(1) {
for(i=0;i<=2;i++) {/* for each pixel page */
Write page gain register
Write page offset register
Read page gain register and verify (optional)
Read page offset register and verify (optional)
}
}
Send(STARTInt);
DelayIntegrationTime(); /* wait for appropriate time interval to elapse */
Send(SAMPLEInt);
Send(READPixel);
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TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
MECHANICAL INFORMATION
This dual-in-line package consists of an integrated circuit mounted on a lead frame and encapsulated in an electrically
nonconductive clear plastic compound.
0.440 (11,18)
0.420 (10,67)
C
Centerline of Pin 1 Nominally
Lies Between Pixels 5 and 6.
0.017 (0,43)
L
8
7
6
5
4
ꢁ 0.004 (0,1)
Pixel Coverage
(Note C)
0.260 (6,60)
0.240 (6,10)
450 ꢀm Typical
C
Package
L
C
L
C
L
Pixel 1
Pin 1
1
2
3
ꢀ 0.03 (0,76) NOM
C
Pin 1
0.310 (7,87)
0.290 (7,37)
L
0.260 (6,60)
0.240 (6,10)
0.016 (0,41)
0.014 (0,36)
Die Thickness
0.10 (2,54)
0.053 (1,35)
0.043 (1,09)
0.075 (1,91)
0.060 (1,52)
8°
10°
0.130 (3,30)
0.120 (3,05)
0.175 (4,45)
0.155 (3,94)
Seating Plane
8°
100°
90°
8°
0.012 (0,30)
0.008 (0,20)
0.060 (1,52)
0.040 (1,02)
0.025 (0,64)
0.015 (0,38)
0.150 (3,81)
0.125 (3,18)
Pb
NOTES: A. All linear dimensions are in inches and (millimeters).
B. Index of refraction of clear plastic is 1.55.
C. Center of pixel active areas typically located under this line.
D. Lead finish is NiPd.
E. This drawing is subject to change without notice.
Figure 7. Packaging Configuration
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TSL3301−LF
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C − APRIL 2007
PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
LEAD-FREE (Pb-FREE) and GREEN STATEMENT
Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current
RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous
materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified
lead-free processes.
Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and
Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information and Disclaimer The information provided in this statement represents TAOS’ knowledge and
belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties,
and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate
information from third parties. TAOS has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and
chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thus CAS numbers and other
limited information may not be available for release.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorporated.
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