5503-CGT [TDK]
Consumer Circuit, PQFP48, TQFP-48;
| 型号： | 5503-CGT |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | Consumer Circuit, PQFP48, TQFP-48 商用集成电路 |
| 文件： | 总11页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
5503 DCR
TDK SEMICONDUCTOR CORP.
Direct Conversion Receiver
Advanced Information
February 2001
FEATURES
DESCRIPTION
The 5503 is a low cost, high performance direct
conversion receiver (DCR) specifically designed for
digital wireless applications. The DCR architecture
provides a receiver design with fewer external
components than the conventional dual conversion
approach. The 5503 is designed to operate over an
input frequency range of 950 to 1450 MHz. The
device accepts an input signal in this frequency
range and down converts directly to baseband. The
local oscillator signal is generated by a completely
integrated phase lock loop that is fully
• Wideband I/Q demodulator
– RF input 950 to 1450 MHz
– External lowpass filter
- Integrated post-filter baseband drivers
• Integrated VCO and frequency synthesizer
• AGC Amplifier
APPLICATIONS
• Digital Satellite
• VSAT Receivers
programmable through
interface.
a
standard serial port
BLOCK DIAGRAM
1
5503 DCR
Direct Conversion Receiver
FUNCTIONAL DESCRIPTION
AGC Amplifier
The 5503 RF input can be driven differentially or
single ended. The RFp and RFn inputs are self-
biasing and are designed to be driven from a 50
Ohm source. For single-ended operation, the RFn
pin should be AC coupled to analog ground. A gain
control input, AGC, provides a 22 dB gain variation
with 0V providing minimum gain and 4V providing
maximum gain.
Ω
Ω
Ω
Ω
I/Q Mixer
The AGC amplifier drives the RF port of two identical
double balanced mixers. The LO ports of these
mixers are driven from an on-chip quadrature
network.
Note: A separate resonator circuit is required for
each oscillator
PLL Synthesizer
The synthesizer derives its reference from a source
which can be either an externally derived clock or an
external crystal coupled to the internal oscillator.
This source drives a programmable reference divider
with 15 preset divide ratios from 2 to 320. This
output provides the PLL reference by driving one
input of a phase/frequency detector. The VCO
Low Pass Filtering and Buffering
Following each mixer is a buffer amplifier for driving
an external passive low-pass filter. An external
series resistor connected to the IO1 or QO1 output
is used to provide the source match for the filter. A
second high impedance buffer amplifier is provided
(IIN or QIN) for additional gain and isolation after the
filter. The figure below shows a typical filter
designed for 20 Megasymbol per second operation:
output drives
a divider chain incorporating a
selectable divide by two prescaler followed by a
variable modulus prescaler and divider. The divider
is programmed by a 17-bit control word. This divider
chain output drives the other input of the
phase/frequency detector.
Loop Filter
The phase/frequency detector provides two output
pairs, FILN/EON and FILP/EOP. The FILN/EON
outputs are used when the VCO has a positive gain
characteristic (increasing voltage yields increasing
frequency). The FILP/EOP outputs are used for a
negative VCO gain characteristic. Below is shown a
typical loop filter:
Dual VCO
The 5503 uses two VCOs to cover the entire
specified tuning range. Both VCOs use nearly
identical architecture with the only difference being
slight design modifications to optimize the range of
operation.
The lower range VCO requires an
external resonator that supports a tuning range of
950 to 1150 MHz. The higher range VCO requires a
similar resonator with inductor values designed to
support the range of 1100 to 1475 MHz. A typical
lumped-element resonator circuit incorporating
varactor tuning is shown in the following figure:
2
5503 DCR
Direct Conversion Receiver
DCR Application Drawing
3
5503 DCR
Direct Conversion Receiver
PIN DESCRIPTIONS
ANALOG PINS
NAME
RFP, RFN
TYPE DESCRIPTION
I
RF inputs: balanced differential inputs to the receiver. The input signals placed on this
line are amplified with a variable gain amplifier before being passed to the I/Q
demodulator.
AGC
I
Automatic gain control input. A voltage from 0 to 4 volts on this pin varies the input
amplifier gain from minimum to maximum. The gain increase is 22 dB typical
Eop, Filp
I/O
External loop filter interface. Eop drives the base of an external common emitter
transistor. Filp is the feedback input from the loop filter capacitor. This output is used
for a negative VCO gain characteristic.
External loop filter interface. Eon drives the base of an external common emitter
transistor. Filn is the feedback input from the loop filter capacitor. This output is used
for a positive VCO gain characteristic.
Eon, Filn
I/O
I
XTLP, XTLN
Reference crystal input.
An external crystal connected between these pins
establishes the reference frequency for the PLL synthesizer. The crystal frequency
must be 8 MHz and have an ESR of less than 100 Ohms. Following this oscillator is a
programmable divider which establishes the synthesizer step size.
IO2, QO2
IO1, QO1
IIN, QIN
O
O
I
Baseband outputs.
These typically drive an A/D converter prior to digital
demodulation and processing.
I and Q channel outputs to external low pass filter. An external series resistor is
connected between this output and the filter to provide the source match.
I and Q channel inputs from external low pass filter. These are high impedance inputs
( >1000Ω). The low pass filter must be designed for a low input and high output
impedance.
Rxt
I
External reference resistor. This resistor is connected to ground and must be 7.68k
±1% . It is used as a reference for internal bias currents.
RSHP, RSHN
RSLP, RSLN
I
I
High range VCO resonator inputs
Low range VCO resonator inputs
DIGITAL PINS
Din
I/O
I
I2C data. This signal is connected to the I2C internal block. An external resistor
(typically 2.2 kΩ) is connected between Din and Vcc for proper operation
Dclk
I2C clock Input: Dclk should nominally be a square wave with a maximum frequency
of 400kHz. SCL is generated by the system I2C master
4
5503 DCR
Direct Conversion Receiver
POWER PINS
VPA1, VPA2,
VPA3a,
I
Analog Vcc pins
VPA3b, VPA4,
VPA5a,
VPA5b, VPA6
VPD1, VPD2
I
I
Digital Vcc pin.
Analog ground pins.
VNA1, VNA2,
VNA3a,
VNA3b, VNA4,
VNA6, VNA7
VND1
VNS
I
I
Digital ground pin.
Substrate ground pin.
MICROCONTROLLER SERIAL INTERFACE
I2C REGISTERS: WRITE MODE
S
1
address
0
A
reg0
0
A
reg1
A
reg2
A
reg3
5503 address
1
0
0
0
1
S : start bit
A : acknowledge bit
P : stop bit
TABLE 1: MICROCONTROLLER INTERFACE REGISTER
REGISTER 7(MSB)
6
2
2
2
5
4
2
2
3
2
2
2
1
0 (LSB)
14
6
13
12
11
3
10
9
8
0
1
2
3
0
2
2
2
2
7
5
4
2
1
0
2
1
2
2
2
2
16
15
PE
R3
R2
R1
R0
2
C1
C0
test1
test0
test2
vco1 vco0
x
5
5503 DCR
Direct Conversion Receiver
DESCRIPTION OF INTERNAL REGISTERS
Register 0
VCO divide ratio, bits 14 thru 8, msb always set to 0
Register 1
Register 2
VCO divide ratio, bits 7 thru 0
msb
Not Used. Always set to 1
VCO divide ratio, bits 16 and 15
PE, Prescaler enable. PE=1 enables divide by two prescaler
R3,R2,R1,R0 Reference division ratio, as shown in following table:
Reference
R3 R2 R1 R0 division ratio
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
2
4
8
16
32
64
128
256
Undefined
5
10
20
40
80
160
320
Register 3
C1, C0
Phase detector current control, as shown in following table:
ipump word
C1 C0
Phase Detector
charge current µA
0 0
0 1
1 0
1 1
100
200
300
400
6
5503 DCR
Direct Conversion Receiver
test0, test1
Test point select as shown in following table:
test1
test0
tp1
tp2
0
0
1
1
0
1
0
1
disabled
pump up
M cnt
disabled
pump down
N cnt
prescaler
modulus
test2 Phase detector disable (1 = disable, 0 = enable)
(vco0, vco1) Vco select word as shown in following table:
vco1 vco0 Low band VCO High band VCO
0
0
1
1
0
1
0
1
disabled
enabled
disabled
undefined
disabled
disabled
enabled
undefined
7
5503 DCR
Direct Conversion Receiver
ABSOLUTE MAXIMUM RATINGS
Operation beyond maximum rating may permanently damage the device.
PARAMETER
RATING
-55 to 150 °C
+110 °C
-0.3 to 6V
-0.3V to VCCn+0.3V
Storage temperature
Junction operating temperature
Positive supply voltage (Vp)
Voltage applied to any pin
TARGET SPECIFICATIONS
Unless otherwise specified: 0° < Ta < 70 °C; positive power supply (VCCn) = +5.0 V ±5%.
OPERATING CHARACTERISTICS
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Supply current
All outputs loaded
120
150
mA
Digital I/O Characteristics (Din, Dclk)
High level input voltage
Low level input voltage
Vcc+0.3
0.8
2
V
V
Gnd - 0.3
High level input current
Low level input current
Vin = Vcc - 1.0V
Vin = 1.0V
100
- 400
uA
uA
Receiver Characteristics Unless otherwise noted, input source impedance is 75 Ω
RFn bypassed to ground with 100 pf
Ω
Input impedance, RFp
50
22
Input signal range
Input frequency range
AGC Range
-58
950
20
-38
1450
dBm
MHz
dB
0V < VAGC < 4V
Fin = 950 MHz
DCR Gain, Lower Band
42
62
62
dB
Range
DCR Gain, Upper Band
Range
Fin = 1450 MHz
42
dB
Noise figure
Measured at maximum gain
Vrf_in = -38 dBm/tone
Vrf_in = -38 dBm/tone
Measured at RFp
15
0
-10
-60
dB
2nd order IIP
dBm
dBm
dBm
3rd order IIP
Lo Leakage
-12
VCO Characteristics
Tuning range, Low OSC
Tuning range, High OSC
Phase Noise
L1 = 8.2nH L2 = 27nH C1 = 1pF
L1 = 3.9nH L2 = 22nH C1 = .6pF
10kHz offset
950
1100
1150
1475
MHz
MHz
dBc/Hz
-78
8
5503 DCR
Direct Conversion Receiver
OPERATING CHARACTERISTICS (continued)
Low Pass Filter Interface
IOLPF, QOLPF output imped.
Filter Loss
Ω
Ω
10
6db
Filter Input Impedance
source match is by external R
50
I and Q Buffer Amplifier (each output loaded with 4pF in parallel with 20kΩ)
Ω
dB
Input impedance
Voltage Gain
1000
Freq = 30 MHz
23
Ω
Output impedance
I/Q output amplitude
-3dB frequency, Frf-Flo
Buffer THD
10
1.2
1.0
75
1%
Vpp
MHz
2%
Amplitude and Phase Characteristics
I/Q quadrature accuracy
I/Q amplitude matching
-3
-1
+3
+1
degree
dB
9
5503 DCR
Direct Conversion Receiver
PACKAGE PIN DESIGNATIONS
(Top View)
48-TQFP
5503-CGT
10
5503 DCR
Direct Conversion Receiver
MECHANICAL DRAWING
8.7 (0.343)
9.3 (0.366)
INDEX
1
6.8 (0.267)
7.2 (0.283)
0.0 (0)
0.20 (0.008)
0.60 (0.024) Typ.
0.2 (0.008) Typ.
1.40 (0.055)
1.60 (0.063)
0.50 (0.0197) Typ.
48-Lead Thin Quad Flatpack
Note: Controlling dimensions are in mm
PART DESCRIPTION
5503 DCR Direct Conversion Receiver
ORDER NO.
5503-CGT
PACKAGE MARK
5503-CGT
Advanced Information: The Advanced Information data sheet is to be approved for Beta Site and advanced customer information purposes
only. It is not intended to replace the electrical specification for the specific device it represents. This document will be updated and converted
into a Final (Preliminary Data Sheet) upon completion of Design Engineering Validation. Design Engineering should review this documentation
for its accuracy to the definition and the design goals for the product it represents.
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks
or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of
TDK Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice.
Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders.
2
2
Purchase of I C components of TDK Corporation or one of its sublicensed Associated Companies conveys a license under the Philips I C
2
2
Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by
Philips.
TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877, http://www.tsc.tdk.com
TDK Semiconductor Corporation
02/22/01- rev. G
11
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