78P2342JAT-IEL/A07R [TDK]

Digital Transmission Interface, E-3, PQFP100;
78P2342JAT-IEL/A07R
型号: 78P2342JAT-IEL/A07R
厂家: TDK ELECTRONICS    TDK ELECTRONICS
描述:

Digital Transmission Interface, E-3, PQFP100

文件: 总37页 (文件大小:458K)
中文:  中文翻译
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78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
FEBRUARY 2004  
DESCRIPTION  
FEATURES  
The 78P2342JAT is  
a
low-power, 2-port  
Transmit and receive interfaces for E3, DS3 and  
STS-1 applications  
DS3/E3/STS1 Line Interface Unit (LIU) with  
integrated Jitter Attenuator (JAT). It includes all the  
required clock recovery and transmitter pulse  
shaping functions for applications using 75-ohm  
coaxial cable at distances up to 1350 feet. These  
applications include DSLAMs, T1,3/E1,3 digital  
multiplexers, SONET Add/Drop multiplexers, PDH  
equipment, DS3 to Fiber optic and microwave  
modems and ATM WAN access for routers and  
switches.  
Designed for use with 75 ohm coaxial cable  
lengths up to 1350 ft  
Receives DS3-high and DSX3 monitor signals  
Local and Remote loopbacks  
Selectable B3ZS/HDB3 ENDEC with line code  
violation detector  
Standards-based LOS detector  
Optional serial-port based mode selection and  
channel status monitoring  
The receiver recovers clock and data from a B3ZS  
or HDB3 coded AMI signal. It can compensate for  
over 12dB of cable and 6dB of flat loss. The  
transmitter generates a signal that meets the  
Adaptive digital clock recovery (uses line-rate  
reference clock input)  
Receive output clock maintains nominal line-rate  
frequency at all times  
standard pulse shape requirements.  
The  
Fully integrated Jitter Attenuation function  
provided for all line rates (no external VCXO  
required)  
78P2342JAT includes optional B3ZS/HDB3 ENDEC  
with a receive line code violation detector, loop-back  
modes, Loss of Signal detector, clock polarity  
selection, and the ability to receive a DSX3 monitor  
signal.  
Jitter Attenuator configurable for transmit or  
receive path  
Transmit line fault monitor  
Requires no external current-setting resistor or  
loop filter components  
STANDARDS  
Telcordia GR-499-CORE and GR-253-CORE  
ITU-T G.823, G.824, G.775, and G.703  
ETSI TBR-24, ETS 300 686, ETS 300 687, and  
ETS EN 300 689  
ANSI T1.102-1993, T1.231-1997, T1.404-1994,  
and T1.105.03b  
Single 3.3V supply operation  
Available in 100-pin Exposed Pad JEDEC LQFP  
BLOCK DIAGRAM  
Controls Flags  
RLBK  
LBO E3 DS3  
Transmit  
TXNW  
TXEN  
Monitor  
TPOS  
TNEG  
TCLK  
B3ZS /  
HDB3  
LOUTP  
LOUTN  
Pulse  
Shaper  
Encoder  
Attenuator  
Jitter  
Attenuator  
ENDEC  
RPOS  
LINP  
LINN  
B3ZS /  
HDB3  
AGC  
Data  
Detector  
Adaptive  
Equalizer  
RNEG  
RCLK  
Decoder  
MON  
TCLKP  
RCLKP  
Power  
Distribution  
Signal  
Detector  
Clock  
Recovery  
LOS  
LLBKA  
LLBKB  
PDTX PDRX  
CKREF  
Signals from  
Adjacent Port  
Each Channel  
CS  
SCK  
SDI  
Master  
Control  
Registers  
Bias  
CKREF  
Generator  
SDO  
- 1 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
FUNCTIONAL DESCRIPTION  
The jitter tolerance of 78P2342JAT meets the  
requirements of ITU-T G.823 for E3 rates; the  
requirements of ITU-T G.824 and Telcordia GR-499  
(Cat I and II) for DS3 rates; and the requirements of  
Telcordia GR-253 for STS1 rates.  
With the Jitter Attenuator disabled, the jitter transfer  
function meets the requirements of GR-499 for  
Category II DS3 interfaces.  
The 78P2342JAT contains all the necessary  
transmit and receive circuitry for connection  
between E3, DS3, or STS-1 line interfaces and  
digital Framer/Mapper ICs.  
OPERATING RATE  
The Master Control Register (MSCR) determines  
which mode the device operates in according to the  
table below. The MSL0 pin is also provided for  
mode selection in applications without a serial  
control interface. Upon power-up or reset, the state  
of the MSL0 pin is sensed and mapped into the DS3  
and E3 register bits representing the appropriate  
mode of operation. After power-up/reset, the state of  
the MSL0 pin is ignored.  
When the Jitter Attenuator is enabled, the  
78P2342JAT meets the requirements of GR-499  
and GR-253 for all categories of DS3/STS1  
equipment and the ETSI TBR-24 requirements for  
E3 rates.  
standards,  
To check conformance with other  
please  
refer  
to  
the  
JITTER  
ATTENUATOR TRANSFER FUNCTION section for  
more detailed info.  
Standard  
MSL0 pin  
DS3 bit  
E3 bit  
RECEIVER MONITOR MODE  
E3  
L
H
Z
Z
0
1
0
1
1
0
0
1
DS3  
When in monitor mode, 20dB of flat gain is applied  
to the incoming signal before it is fed to the receive  
equalizer. This mode is controlled by the MON bit in  
the Mode Control Register.  
STS-1  
STS-1  
RECEIVER OPERATION  
SIGNAL DETECT  
The receiver input is either transformer-coupled or  
capacitor-coupled to the line signal. In applications  
where the highest performance and isolation are  
required, a 1:1 transformer is used in the receive  
path. In applications where isolation is provided  
elsewhere in the circuit, capacitor coupling can be  
used. The receiver input should be line terminated  
externally with a termination resistor.  
When the received signal is below a minimum  
threshold, the corresponding LOS signal (bit) is  
asserted. A time delay is provided before this output  
is active so that transient interruptions do not cause  
false indications. The LOS signal can also be used  
to trigger an interrupt on the INTRx pin when serial  
interface control is not available. This is controlled  
by setting the RXER bit in the Interrupt Control  
Register (INTC).  
Note: In DS3 or STS-1 mode, when LBO is not  
enabled, the transmitters have to be properly  
terminated to ensure reliable LOS detection. If a  
transmitter is not terminated, the resultant 2x signal  
is large enough to couple to the neighboring  
receivers through the ESD diodes, causing false  
Signal Detect indication.  
The AMI signal first enters an AGC, which has a  
selectable gain range setting. In normal operation,  
the AGC can compensate for signals with up to 6dB  
of flat loss. When Receiver Monitor Mode is  
enabled, the AGC can compensate for a DSX3  
monitor signal with 16 to 20 dB of flat loss. The  
signal then enters a high performance adaptive  
equalizer. The equalizer is designed to overcome  
inter-symbol interference caused by long cable  
lengths. Because the equalizer is adaptive, the  
circuit will work with all square-shaped signals such  
as DS3-high or 34.368 Mbit/s E3. The variable gain  
differential amplifier automatically controls the gain  
to maintain  
a
constant voltage level output  
regardless of the input voltage level.  
- 2 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
LOCAL LOOPBACK AND REDUNDANCY MUX  
Transmitter  
#1  
Each receiver has a 4-input MUX as shown in the  
adjacent figure. In multiport applications where  
redundant channels are required, the receiver MUX  
can be configured to provide the necessary  
multiplexing functions. This allows the user to use  
one port as a redundant monitor for the other port.  
The tables below show the register settings for  
selecting the desired receiver input source.  
LOUTP1, LOUTN1  
LINP1, LINN1  
00  
Receiver  
01  
10  
11  
#1  
LLBKA,B(1)  
Transmitter  
#2  
LOUTP2, LOUTN2  
LINP2, LINN2  
LLBKA  
LLBKB  
Receiver #1 Input  
Source  
(Port 1)  
(Port 1)  
00  
01  
10  
11  
Receiver  
0
0
1
1
0
1
0
1
LINP1/LINN1  
#2  
LOUTP1/LOUTN1  
LINP2/LINN2  
LLBKA,B(2)  
LOUTP2/LOUTN2  
When serial interface control is not available, the  
respective LPBKx pin for each of the channels can  
also be used to activate local loopback mode as  
shown below. Note that redundant channel modes  
can only be activated using the serial interface.  
LLBKA  
LLBKB  
Receiver #2 Input  
Source  
(Port 2)  
(Port 2)  
0
0
1
1
0
1
0
1
LINP2/LINN2  
LOUTP2/LOUTN2  
LINP1/LINN1  
LPBKx  
Loopback Mode  
pin  
LOUTP1/LOUTN1  
Normal Operation  
L
Note: The LLBKA and LLBKB bits are located in the  
Same as LLBKA,B = ‘00’  
Mode Control Register (MDCR).  
The Register  
Remote (Digital) Loopback  
Z
Control bit, REGEN, should be enabled when using  
the register settings to avoid conflict with external  
loopback setting pins.  
Same as RLBK = ‘1’  
Local (Analog) Loopback  
H
Same as LLBKA,B = ‘01’  
- 3 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
On the transmit side, when the ENDEC is enabled,  
NRZ input data is encoded to Positive and Negative  
AMI logic data following the B3ZS (for DS3/STS-1)  
or HDB3 (for E3) substitution codes. The NRZ data  
is input to the TPOS pin as shown below:  
B3ZS/HDB3 ENDEC WITH LINE CODE VIOLATION  
DETECT  
The 78P2342JAT includes a selectable B3ZS/HDB3  
Encoder/Decoder (ENDEC). The ENDEC function  
can be enabled or disabled through pin selection or  
register setting as shown below.  
ENDECB  
TPOSx  
TNEGx  
bit/pin  
0 / L  
ENDECB  
RPOSx  
RNEGx  
NRZ data  
‘Don’t Care’  
bit/pin  
1 / H  
Positive AMI  
Negative AMI  
Receive Line Code  
Violation Indicator  
0 / L  
NRZ data  
TRANSMITTER OPERATION  
1 / H  
Positive AMI  
Negative AMI  
Both transmitters are enabled by their corresponding  
TXEN bit. When enabled, each transmitter accepts  
logic level clock and data signals and generates  
current pulses on the LOUTPx and LOUTNx pins.  
When properly connected to a 1:2CT center-tapped  
transformer, a standards compliant AMI pulse is  
When the ENDEC is enabled, the decoder  
generates a composite NRZ logic data stream  
following the B3ZS (for DS3/STS-1) or HDB3 (for E3)  
substitution codes via the RPOSx pins:  
generated which can drive a 75  
coaxial cable.  
The decoder also detects Receive Line Code  
Violations (RLCV) and outputs a pulse via the  
RNEG pin. Three different classes of line code  
violations are detected.  
When the recommended transformer is used and  
when DS3 mode is selected, the transmitted pulse  
shape at the end of the 75  
terminated cable of 0 to  
450 feet will fit the DS3 template in ANSI T1.102-  
1993 and Telcordia GR-499-CORE. For STS-1  
applications, the transmitted pulse for a short cable  
meets the requirements of Telcordia GR-253-CORE.  
For E3 applications, the transmitted pulse for a short  
cable meets the requirements of ITU-T G.703.  
In either DS3 and STS-1 modes, the LBOx pin or  
LBO bit should be set high for short cable (< 225 ft),  
and should be set low for long cable (> 225 ft). The  
LBO settings are ignored in E3 mode.  
1) Too many zeros:  
More than two (three)  
consecutive zeros in B3ZS (HDB3) mode.  
2) Not enough zeros between bipolar pulse (B)  
and bipolar violation pulse (V): (B,V) for B3ZS.  
(B,V) or (B,0,V) for HDB3.  
3) Code violation: Even number of bipolar pulses  
(B) detected between bipolar violation pulses  
(V).  
When the ENDEC is disabled, the 78P2342JAT  
outputs a dual rail data stream via the RPOSx and  
RNEGx pins. In this mode, the Framer/Mapper  
providing the ENDEC function typically detects Line  
Code Violations.  
RCLK/TCLK POLARITY REVERSAL  
To simplify the interface with various framer circuitry,  
TCLK polarity can be internally inverted by setting  
the TCLKP bit, and RCLK polarity can be inverted  
by setting the RCLKP bit. Both bits are located in  
the Master Control Register (MSCR).  
REMOTE (DIGITAL) LOOPBACK  
When the Register Control bit, REGEN, is disabled  
and the LPBKx pin is floating; or when the Register  
Control bit, REGEN, is enabled and the RLBK bit is  
set, RCLKx, RNEGx, and RPOSx outputs are  
internally looped back to the TCLKx, TNEGx, and  
TPOSx inputs respectively.  
- 4 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
LINE BUILD-OUT  
The Jitter  
Attenuator  
can be configured  
The Line Build-Out (LBO) function controls the  
transmit amplitude and pulse shape in DS3 and  
STS-1 modes. The selection of LBO depends on  
the amount of cable the transmitter is connected to.  
When less than 225 ft of cable is used, the  
corresponding LBOx pin or LBO bit should be high.  
When 225ft or more cable is used the corresponding  
LBO setting (LBOx pin or LBO bit) should be low.  
LBO can be controlled either from pins or from  
register settings, depending on the status of the  
Register Control bit, REGEN.  
independently for each channel by writing to the  
Jitter Attenuator Control Register (JACR) as follows:  
JAEN  
bit  
JASL  
bit  
Jitter Attenuator Mode  
0
1
X
0
Jitter Attenuator disabled  
Jitter Attenuator configured  
to be in the receive path  
1
1
Jitter Attenuator configured  
to be in the transmit path  
TRANSMIT ENABLE  
When serial interface control is not available, the  
MSL1 pin is provided for global Jitter Attenuator  
mode selection. Upon power-up or reset, the state  
of the MSL1 pin is sensed and mapped into the  
JAEN and JASL register bits for all channels,  
representing the appropriate mode of operation.  
After power-up or reset, the state of the MSL1 pin is  
ignored. The state of the MSL1 pin, and the  
corresponding Jitter Attenuator configuration is  
shown below.  
The TXEN bit in the Mode Control Register controls  
the transmitter output.  
When logic zero, the  
transmitter output is disabled. This feature is used to  
disable ports as well as to multiplex two or more  
transceivers to one port. The transmitter of any port  
can also be disabled by floating the respective LBOx  
pin, in which case it will also power-down the entire  
transmitter.  
See section on the Power-Down  
Function for more info.  
TRANSMIT MONITOR  
MSL1 pin  
Jitter Attenuator Mode  
Jitter Attenuator in receive path  
Jitter Attenuator in transmit path  
Jitter Attenuator disabled  
The transmit monitor function detects activity on the  
transmitter output at the LOUTPx and LOUTNx pins.  
When there is a transmitter fault, in the case of an  
open or short on the chip, the transformer, or the  
circuit board, the transmit signal amplitude will be  
altered. The transmit monitor detects the amplitude  
of the driven signal. The TXNW signal (bit) goes  
high when the amplitude of the transmit signal is  
outside a valid amplitude range. When the signal  
amplitude is either too high or too low for longer than  
a specified duration, the TXNW bit goes high (See  
Transmit Monitor Specifications, pg.28). The TXNW  
signal can be also used to trigger an interrupt on the  
INTRx pin when serial interface control is not  
available.  
L
H
Z
PLL Bandwidth  
A PLL response with effectively one pole below 27  
Hz is adequate to meet the ETSI TBR24 E3  
standards. A PLL response with one pole below 40  
Hz is adequate to meet the GR-499 (Cat I) DS3  
standards. One of two bandwidths can be selected  
via register settings.  
The PLL bandwidth is  
proportional to the data rate as follows:  
Line Rate  
JABW bit  
PLL Bandwidth (Hz)  
JITTER ATTENUATOR  
0
1
0
1
0
1
*13  
188  
*17  
245  
20  
Jitter Attenuation function is provided on-chip. The  
Jitter Attenuator can be configured to be in the  
transmit or the receive path. When configured in the  
transmit path, the input clock at TCLK pin is passed  
through a very low bandwidth digital PLL. The  
corresponding transmit data is buffered into a FIFO  
and clocked out using the de-jittered output clock of  
the PLL. When configured in the receive path, the  
recovered clock is passed through the low  
bandwidth digital PLL, and the corresponding  
receive data is buffered into the FIFO and clocked  
out using the de-jittered clock.  
E3  
DS3  
STS1  
*283  
*The default state of the JABW bit depends on  
which line-rate is selected through the MSL0 pin. If  
E3 or DS3 mode is selected, the default state is ‘0’.  
If STS1 mode is selected, the default state is ‘1’.  
- 5 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
Elastic Store Depth  
SERIAL CONTROL INTERFACE  
To optimize the trade-off between data latency and  
clock wander tolerance, the FIFO elastic store depth  
can be selected through the serial port by writing to  
the Jitter Attenuator Control Register (JACR) as  
follows:  
The serial port controlled register allows a generic  
controller to interface with the 78P2342JAT. It is  
used for mode settings, diagnostics and test, and  
the retrieval of status and performance information.  
The serial interface consists of four pins: Chip Select  
(CS), Serial Clock (SCK), Serial Data In (SDI), and  
Serial Data Out (SDO). The CS pin initiates the  
read and write operations. It can also be used to  
select a particular device allowing SCK, SDI and  
SDO to be bussed together. SCK is the clock input  
that times the data on SDI and SDO. Data on SDI is  
latched in on the rising-edge of SCK, and data on  
SDO is clocked out using the falling edge of SCK.  
ESP[1:0]  
Elastic Store Depth  
bits  
00  
01  
10  
11  
Pass-Through mode  
16 UI  
32 UI  
64 UI (default)  
SDI is used to insert mode, address, and register  
data into the chip. Address and Data information  
are input least significant bit (LSB) first.  
The Elastic Store Depth selects the nominal FIFO  
read pointer address. The total or maximum elastic  
store depth is set to be twice as deep as the nominal  
pointer address. The circular buffer length is always  
twice as long as the nominal pointer address.  
SDO is a tristate capable output. It is used to output  
register data during a read operation. SDO output is  
normally high impedance, and is enabled only  
during the duration when register data is being  
POWER-DOWN FUNCTION  
clocked out.  
Read data is clocked out least  
Power-down control is provided to allow the  
transceivers to be shut off individually. Transmit and  
receive power-down can be set independently via  
the PDTX and PDRX bits in the Mode Control  
Register. Floating the respective LBOx pin can also  
set PDTX for each channel. The Serial Control  
Interface and Configuration Registers are not  
affected by power-down.  
significant bit (LSB) first.  
If SDI coming out of the micro-controller chip is also  
tristate capable, SDI and SDO can be connected  
together to simplify connections.  
The maximum clock frequency for register access is  
20MHz.  
Note: To allow equipment to power up in a known  
state, some register defaults are set by their  
corresponding pin control at power-up.  
INTERNAL POWER-ON RESET  
The 78P2342JAT includes on-chip Power-On Reset  
(POR) function to ensure the serial-port registers are  
initialized to known default states upon power-up.  
Roughly 50us after Vcc reaches 2.4V at power up,  
reset is released. This reset signal also sets all state  
machines within the LIU to nominal operational  
states. The internal reset signal is also brought out  
to the PORB pin. This pin is a multi-function pin that  
allows for the following:  
1) Override the internal POR signal by driving in an  
external active-low reset signal;  
2) Monitor the state of the internal PORB signal  
(for test and debug only);  
3) Add external capacitor to delay the release of  
the internal power-on reset signal to allow the  
MSL0 pin to stabilize prior to release of reset  
(approximately 8µs per nF added).  
The internal resistance of the PORB pin is  
approximately 5k.  
- 6 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
REGISTER DESCRIPTION  
REGISTER ADDRESSING  
Address Bits  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Sub-Address  
SA[1]  
Bit 1  
Bit 0  
Read/  
Write  
Port Address  
Assignment  
PA[3]  
PA[2]  
PA[1]  
PA[0]  
SA[2]  
SA[0]  
R/W*  
REGISTER TABLE  
a) PA[3:0] = 0 : Global Registers  
Reg.  
Sub  
Description  
Master Control  
Interrupt Control  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Addr  
Name  
REGEN  
<0>  
INPOL  
<0>  
E3  
<X>  
ENDECB RCLKP  
TCLKP  
<0>  
JAER  
<0>  
SRST  
<0>  
TXER  
<1>  
MSCR  
DS3  
<X>  
0
1
--  
(R/W)  
<0>  
<0>  
INTC  
(R/W)  
RXER  
<1>  
--  
--  
--  
--  
2
3
4
5
6
7
RSVD  
RSVD  
RSVD  
RSVD  
RSVD  
RSVD  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
--  
<0>  
--  
--  
<0>  
--  
--  
<0>  
--  
--  
<0>  
--  
--  
<0>  
--  
--  
<0>  
--  
--  
<0>  
--  
--  
<0>  
--  
--  
--  
--  
--  
--  
--  
--  
--  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
b) PA[3:0] = 1-2 : Port-Specific Registers  
Reg.  
Name  
Sub  
Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Addr  
MDCR  
PDTX  
<0>  
PDRX  
<0>  
LBO  
<1>  
LLBKA  
<0>  
LLBKB  
<0>  
RLBK  
<0>  
MON  
<0>  
TXEN  
<1>  
0
Mode Control  
(R/W)  
STAT  
(R/O)  
RSVD  
JACR  
(R/W)  
--  
--  
--  
1
2
3
Status Monitor  
Reserved  
FERR  
LOS  
TXNW  
--  
SGLO  
<1>  
JAEN  
<X>  
<1>  
<0>  
<1>  
<0>  
<0>  
ESP[1]  
<1>  
<1>  
ESP[0]  
<1>  
<0>  
<0>  
<0>  
JABW  
<X>  
Jitter Attenuator  
JASL  
JLBK  
<X>  
<0>  
Control  
4
5
6
7
RSVD  
RSVD  
RSVD  
RSVD  
Reserved  
Reserved  
Reserved  
Reserved  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
<0>  
--  
<0>  
--  
<0>  
--  
<0>  
--  
<0>  
--  
<0>  
--  
--  
--  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
<0>  
Note: Shaded registers in Register Table are reserved for TDK internal use only. Accessing reserved or  
undefined registers may cause undesirable operation.  
- 7 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
REGISTER DESCRIPTION (continued)  
LEGEND  
TYPE DESCRIPTION  
TYPE DESCRIPTION  
R/W Read or Write  
R/O  
Read only  
GLOBAL REGISTERS  
ADDRESS 0-0: MASTER CONTROL REGISTER  
DFLT  
BIT  
NAME  
TYPE  
DESCRIPTION  
VALUE  
Register Control Enable:  
0 : Pin selection overrides register settings  
1 : Device is controlled via register set.  
7
REGEN  
R/W  
0
NOTE: Pin 15 (ENDECB) must be tied low when REGEN is enabled.  
Line Speed Selection:  
Selects the line speed of all channels as well as the input clock frequency  
6
5
DS3  
E3  
R/W  
R/W  
X
X
at the CKREF pin.  
[DS3 E3] = 00 : STS-1 (51.840MHz)  
01 : E3 (34.368MHz)  
10 : DS3 (44.736MHz)  
11 : STS-1 (51.840MHz)  
NOTE: The default values of these register bits depend on the state of  
the MSL0 pin upon power-up or reset.  
Encoder/Decoder Disable:  
0 : selects NRZ digital data interface  
1 : selects AMI digital data interface  
4
3
ENDECB  
RCLKP  
R/W  
R/W  
0
0
NOTE: Relevant only when the REGEN bit is set. Otherwise, ENDECB  
pin selection prevails.  
RCLK Polarity Selection:  
0 : Receive Data clocked out on the falling-edge of RCLK  
1 : Receive Data clocked out on the rising-edge of RCLK  
TCLK Polarity Selection:  
2
1
TCLKP  
RSVD  
R/W  
R/O  
0
0 : Transmit Data clocked in on the rising-edge of TCLK  
1 : Transmit Data clocked in on the falling-edge of TCLK  
--  
Reserved  
Register Soft-Reset:  
When this bit is set, all registers are reset to their default values. Also  
resets Jitter Attenuator to “centered” states. This register bit is self-  
clearing.  
0
SRST  
R/W  
0
- 8 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
REGISTER DESCRIPTION (continued)  
ADDRESS 0-1: INTERRUPT CONTROL REGISTER  
This register selects the events that would cause the respective interrupt pin (INTRx) for each of the ports to be  
activated. User may set as many bits as required.  
DFLT  
BIT  
7
NAME  
INPOL  
RSVD  
JAER  
TYPE  
R/W  
R/O  
DESCRIPTION  
Interrupt Pin Polarity Selection:  
0 : Interrupt output is active-low  
1 : Interrupt output is active-high  
VALUE  
0
6:3  
2
--  
0
Reserved  
Jitter Attenuator Error Event:  
R/W  
When set, JAT FIFO overflow or underflow (as indicated by the FERR bit)  
will cause an interrupt to be flagged.  
Receiver Error Event:  
1
0
RXER  
TXER  
R/W  
R/W  
1
1
When set, loss of receive signal (as indicated by the LOS bit) will cause  
an interrupt to be flagged.  
Transmitter Error Event:  
When set, transmitter fault (as indicated by the TXNW bit) will cause an  
interrupt to be flagged.  
- 9 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
REGISTER DESCRIPTION (continued)  
PORT-SPECIFIC REGISTERS  
For PA[3:0] = N = 1-2 only. Accessing a register with port address greater than 2 constitutes an invalid  
command, and the read/write operation will be ignored.  
ADDRESS N-0: MODE CONTROL REGISTER  
DFLT  
BIT  
NAME  
TYPE  
DESCRIPTION  
VALUE  
Transmitter Power-Down:  
0 : Normal Operation  
1 : Power-Down  
7
PDTX  
R/W  
0
NOTE: Relevant only when the REGEN bit is set. Otherwise, LBOx pin  
selection prevails.  
Receiver Power-Down:  
6
5
PDRX  
LBO  
R/W  
R/W  
0
1
0 : Normal Operation  
1 : Power-Down  
Transmitter Line Build-Out (DS3 and STS-1 only):  
0 : 225ft of cable attached to the cross-connect  
1 : < 225ft of cable attached to the cross-connect  
NOTE: Relevant only when the REGEN bit is set. Otherwise, LBOx pin  
selection prevails.  
Local (Analog) Loopback Mode Selection:  
[LLBKA : LLBKB] = 00 : Normal operation  
01 : Local (Analog) Loopback  
4
3
LLBKA  
LLBKB  
R/W  
R/W  
0
0
10 : Adjacent receiver input (see page 3)  
11 : Adjacent transmitter loopback (see page 3)  
NOTE: Relevant only when the REGEN bit is set. Otherwise, LPBKx pin  
selection prevails.  
Remote (Digital) Loopback Enable:  
0 : Normal Operation  
1 : Loops RCLK, RPOS, and RNEG back onto TCLK, TPOS, and TNEG  
2
1
0
RLBK  
MON  
TXEN  
R/W  
R/W  
R/W  
0
0
1
NOTE: Relevant only when the REGEN bit is set. Otherwise, LPBKx pin  
selection prevails.  
Monitor Mode Enable:  
Used for reception of split-off signals that are flat attenuated by at least  
16dB but no more than 20dB.  
0 : Disable  
1 : Enable  
Transmitter Output Enable:  
0 : Transmit driver is disabled. Output is tri-stated.  
1 : Normal Operation  
NOTE: Relevant only when the REGEN bit is set. Otherwise, LBOx pin  
selection prevails.  
- 10 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
REGISTER DESCRIPTION (continued)  
ADDRESS N-1: STATUS MONITOR REGISTER  
DFLT  
BIT  
NAME  
TYPE  
DESCRIPTION  
VALUE  
Jitter Attenuator FIFO Error Flag:  
This bit is set whenever a FIFO overflow or underflow occurred. It is  
reset after a read operation to this register.  
7
6:4  
3
FERR  
RSVD  
LOS  
R/O  
R/O  
R/O  
X
0 : Proper Operation  
1 : FIFO Overflow/Underflow  
X
X
Reserved  
Loss-of-Signal Indication:  
0 : Signal Detector detecting a valid receive input signal  
1 : Standards-based Loss-of-Signal indication  
NOTE: RPOSx and RNEGx are forced low when LOS=’1’. RCLK will  
continue to output a line rate clock  
Transmitter Not-Working Indication:  
0 : Transmitter OK  
2
1
0
TXNW  
RSVD  
SGLO  
R/O  
R/O  
R/O  
X
X
X
1 : Transmitter not working  
Reserved  
Signal Low Indication:  
0 : Receive signal level OK  
1 : Receive signal level too low / Loss of signal  
- 11 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
REGISTER DESCRIPTION (continued)  
ADDRESS N-3: JITTER ATTENUATOR CONTROL REGISTER  
DFLT  
BIT  
NAME  
TYPE  
DESCRIPTION  
VALUE  
Jitter Attenuator Enable:  
0 : Disables jitter attenuation function  
1 : Enables jitter attenuation function  
7
JAEN  
R/W  
X
NOTE: The default values of these register bits depend on the state of  
the MSL1 pin upon power-up or reset.  
Jitter Attenuation Selection:  
0 : Jitter Attenuator on the receive path  
1 : Jitter Attenuator on the transmit path  
6
JASL  
R/W  
X
NOTE: The default values of these register bits depend on the state of  
the MSL1 pin upon power-up or reset.  
Jitter Attenuator Local Loopback Enable:  
0 : Normal Operation  
1 : TCLKx, TPOSx, TNEGx connected to JAT input and  
5
4
JLBK  
R/W  
R/W  
R/W  
0
0
RCLKx, RPOSx, RNEGx connected to JAT output  
NOTE: If both RLBK and JLBK bits are set, RLBK mode takes priority.  
RSVD  
Reserved. Must be set to zero.  
FIFO Elastic Store Pointer Selection:  
ESP[1:0] = 00 : Pass-through  
01 : 8 UI  
ESP  
[1:0]  
3:2  
11  
10 : 16 UI  
11 : 32 UI (default)  
1
0
RSVD  
JABW  
R/W  
R/W  
0
Reserved. Must be set to zero.  
Jitter Attenuator Bandwidth Selection:  
0 : Low bandwidth  
1 : High bandwidth  
(see JAT Bandwidth Selection Table on page 5)  
X
NOTE: The default values of these register bits depend on the state of  
the MSL0 pin upon power-up or reset. If the state of the MSL0 pin  
selects E3 or DS3 mode, the default value of JABW is ‘0’. If the state of  
the MSL0 pin selects STS1 mode, the default value of JABW is ‘1’.  
- 12 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
PIN DESCRIPTION  
LEGEND  
TYPE  
A
DESCRIPTION  
Analog Pin  
CMOS Digital Input  
CMOS Digital Input w/ Pull-up  
CMOS Digital Input w/ Pull-down  
CMOS Schmitt Trigger Input  
TYPE DESCRIPTION  
CIT  
CO  
COZ  
S
CMOS 3-State Input  
CMOS Digital Output  
CMOS Tristate Digital Output  
Supply  
CI  
CIU  
CID  
CIS  
G
Ground  
TRANSMITTER PINS  
NAME  
PIN  
TYPE  
DESCRIPTION  
Transmit Positive Data/Transmit NRZ:  
When ENDECB =’1’, a logic one on this pin generates a positive AMI  
pulse on the coax. This pin should not be high at the same time that  
corresponding TNEGx is high.  
23, 31  
CI  
TPOSx  
When ENDECB =’0’, data on this pin is encoded and converted into  
positive and negative AMI pulses.  
Transmit Negative Data:  
When ENDECB =’1’, a logic one on this pin generates a negative AMI  
pulse on the coax. This pin should not be high at the same time that  
corresponding TPOSx is high.  
24, 32  
CI  
TNEGx  
TCLKx  
When ENDECB =’0’, this pin is ignored.  
Transmitter Clock Input:  
This signal is used to latch the respective TPOSx and TNEGx signals  
into the 78P2342JAT.  
25, 33  
98, 92  
99, 93  
CIS  
A
Line Out:  
LOUTPx  
LOUTNx  
Differential AMI Outputs. Requires a 1:2CT center-tapped  
transformer and a shunt termination resistor. See APPLICATION  
INFORMATION section for more info.  
- 13 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
PIN DESCRIPTION (continued)  
RECEIVER PINS  
NAME  
PIN  
TYPE  
DESCRIPTION  
Reference Clock Input:  
This clock should be from a clean source ( 20 ppm) and match the  
selected line-rate frequency as follows:  
57  
CIS  
CKREF  
E3 : 34.368 MHz  
DS3: 44.736 MHz  
STS-1: 51.840 MHz  
Receive Clock:  
Recovered receive clock output.  
NOTE: During LOS conditions, RCLKx will continue to output a line  
rate clock  
27, 35  
28, 36  
CO  
CO  
RCLKx  
RNEGx  
Receive Negative Data:  
When ENDECB =’1’, this pin indicates reception of a negative AMI pulse  
on the coax.  
When ENDECB =’0’, this pin outputs a one when a Receive Line  
Code Violation (RLCV) is detected.  
NOTE: During LOS conditions, RNEGx output is squelched  
Receive Positive Data/NRZ Data:  
When ENDECB =’1’, this pin indicates reception of a positive AMI  
pulse on the coax cable.  
When ENDECB =’0’, it outputs decoded NRZ data.  
NOTE: During LOS conditions, RPOSx output is squelched  
Line In:  
Differential AMI Inputs. Should be 1:1 transformer-coupled and  
terminated with a shunt resistor. See APPLICATION INFORMATION  
section for more info.  
29, 37  
CO  
A
RPOSx  
96, 90  
95, 89  
LINPx  
LINNx  
- 14 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
PIN DESCRIPTION (continued)  
CONTROL AND STATUS PINS  
NAME  
PIN  
TYPE  
DESCRIPTION  
Data-Rate Mode Selection:  
Low = E3 mode  
High = DS3 mode  
19  
CIT  
MSL0  
Float = STS-1 mode  
NOTE: Pin state is latched-in on rising-edge of PORB signal. Pin  
state is ignored after reset.  
Jitter Attenuator Mode Selection:  
Low = JAT in Receive path  
High = JAT in Transmit path  
Float = JAT is bypassed  
20  
14  
CIT  
A
MSL1  
PORB  
NOTE: Pin state is latched-in on rising-edge of PORB signal. Pin  
state is ignored after reset.  
Chip Reset (active-low):  
Forces hardware reset on device. See description on Internal Power-  
on Reset for complete use of this pin.  
ENDEC Enable (active-low):  
Set high to disable internal ENDEC function. See description on  
B3ZS/HDB3 ENDEC with Line Code Violation Detect for complete  
use of this pin.  
15  
CID  
CIT  
ENDECB  
LBOx  
NOTE: Relevant only when the REGEN bit is ‘0’. Pin must be held  
low when the REGEN bit is set.  
Line Build-Out:  
Low = Used with 225ft or more of cable.  
High = Used with less than 225ft of cable.  
Float = Disable and power down transmitter. [TXEN=0; PDTX=1]  
5, 6  
NOTE: LBO control relevant only when the REGEN bit is ‘0’. Pin  
state sampled approximately once every 0.5ms.  
Loopback Enable:  
Low = Normal Operation  
High = Local Loopback. Transmitter looped back to Receiver  
Float = Remote Loopback. Receiver looped back to Transmitter  
10, 11  
64, 63  
CIT  
CO  
LPBKx  
INTRx  
NOTE: Relevant only when the REGEN bit is ‘0’. Pin state sampled  
approximately once every 0.5ms.  
Interrupt Flag:  
This pin is normally high when the INPOL bit is ‘0’ (default), and  
normally low when the INPOL bit is ‘1’. When an interrupt event  
occurs (as defined in the Interrupt Control Register description), the  
respective INTRx pin will change state.  
- 15 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
PIN DESCRIPTION (continued)  
CONTROL AND STATUS PINS (continued)  
SERIAL-PORT PINS  
NAME  
PIN  
TYPE  
DESCRIPTION  
Chip Select:  
High during write and read operations. Low disables the serial port.  
While CS is low, SDO remains in high impedance state, and SDI and  
SCK activities are ignored.  
CS  
65  
CI  
Serial Clock:  
Controls the timing of SDI and SDO.  
Serial Data Input:  
Inputs mode and address information. Also inputs register data during  
a Write operation. Both address and data are input least significant bit  
first.  
SCK  
SDI  
66  
68  
CIS  
CI  
Serial Data Output:  
Outputs register information during a Read operation. Data is output  
least significant bit first.  
SDO  
67  
COZ  
POWER AND GROUND PINS  
It is recommended that all supply pins be connected to a single power supply plane and all ground pins be  
connected to a single ground plane.  
NAME  
PINS  
TYPE DESCRIPTION  
1, 2, 3, 4, 17, 59,  
72, 73, 74, 75  
18, 60, 78, 81, 84,  
87, 91, 94, 97, 100  
16, 22, 30, 38, 46,  
54, 55, 58  
9, 21, 26, 34, 42,  
50, 56, 69  
VCC  
S
S
S
S
Analog Power Supply  
GND  
Analog Ground  
VCCD  
GNDD  
Digital Power Supply  
Digital Ground  
- 16 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS  
ABSOLUTE MAXIMUM RATINGS  
Operation beyond these limits may permanently damage the device.  
PARAMETER  
RATING  
Supply Voltage (VCC/VCCD)  
Storage Temperature  
Junction Temperature  
Pin Voltage (LOUTPx, LOUTNx)  
Pin Voltage (all other pins)  
Pin Current  
-0.5 to 4.0 VDC  
-65 to 150 °C  
-40 to 125 °C  
VCC + 1.5 VDC  
-0.3 to (VCC+0.6) VDC  
100 mA  
RECOMMENDED OPERATING CONDITIONS  
Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges.  
PARAMETER  
RATING  
DC Voltage Supply (VCC/VCCD)  
Ambient Operating Temperature  
3.0 to 3.6 V  
-40 to 85°C  
DC CHARACTERISTICS:  
PARAMETER  
SYMBOL CONDITIONS  
DS3/E3 mode  
JAT Enabled:  
JAT Disabled  
DS3/E3 mode  
JAT Enabled:  
JAT Disabled  
MIN  
NOM  
MAX  
UNIT  
Supply Current  
All channels enabled; LBO=0  
180  
172  
196  
187  
mA  
Idd  
:
Receive-only Supply Current  
All channels PDTX = 1  
83  
75  
90  
82  
mA  
mA  
Iddr  
:
Transmit-only Supply Current  
DS3/E3 mode  
137  
118  
JAT Enabled:  
JAT Disabled:  
Iddt  
All channels PDRX = 1;  
LBO=0  
Supply Current per Port  
DS3/E3 mode  
82  
76  
mA  
mA  
Iddx  
Iddq  
JAT Enabled:  
JAT Disabled:  
(including transmitter current  
through transformer)  
PDTX = 1, PDRX = 1  
Power-Down Current  
20  
30  
- 17 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
ANALOG PINS CHARACTERISTICS:  
The following table is provided for informative purpose only. Not tested in production.  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
NOM  
MAX  
UNIT  
LINPx and LINNx  
Ground reference  
Vblin  
1.9  
2.25  
2.6  
V
Common-Mode Bias Voltage  
LINPx and LINNx Differential  
Input Impedance  
Rilin  
10  
5
kΩ  
kΩ  
PORB Input Impedance  
Ripor  
DIGITAL I/O CHARACTERISTICS:  
Pins of type CI, CIU, CID:  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
NOM  
MAX  
0.8  
UNIT  
V
V
Input Voltage Low  
Input Voltage High  
Input Current  
Vil  
Vih  
Iil, Iih  
Rpu  
Rpd  
Cin  
2.0  
-1  
1
µA  
kΩ  
kΩ  
pF  
Pull-up Resistance  
Pull-down Resistance  
Input Capacitance  
Type CIU only  
Type CID only  
32  
32  
56  
56  
8
84  
84  
Pins of type CIS:  
PARAMETER  
SYMBOL  
Vt+  
Vt-  
Iil, Iih  
Cin  
CONDITIONS  
MIN  
1.3  
0.8  
-1  
NOM  
MAX  
1.7  
1.2  
1
UNIT  
V
V
µA  
pF  
Low-to-High Threshold  
High-to-Low Threshold  
Input Current  
Input Capacitance  
8
- 18 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
Pins of type CIT:  
PARAMETER  
Input Voltage Low  
Input Voltage High  
Minimum impedance to be  
considered as “float” state  
SYMBOL  
Vtil  
CONDITIONS  
MIN  
NOM  
MAX  
0.8  
UNIT  
V
V
Vtih  
2.0  
30  
Rtiz  
kΩ  
Pins of type CO and COZ:  
PARAMETER  
SYMBOL  
Vol  
CONDITIONS  
Iol = 8mA  
Ioh = -8mA  
MIN  
NOM  
MAX  
0.4  
UNIT  
V
V
ns  
pF  
Output Voltage Low  
Output Voltage High  
Output Transition Time  
Pin Capacitance  
Effective Source Impedance  
Tristate Output Leakage  
Current  
Voh  
Tt  
Cout  
Rsrc  
2.4  
C
L
= 20pF; (20-80%)  
6
1
8
30  
Iz  
Type COZ only  
-1  
µA  
- 19 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
SERIAL-PORT TIMING CHARACTERISTICS:  
PARAMETER  
CS or SDI to SCK setup time  
SYMBOL  
CONDITION  
MIN  
4
TYP  
MAX  
UNIT  
ns  
t
su  
CS or SDI to SCK hold time  
4
ns  
t
h
SCK to SDO propagation  
delay  
5
12  
20  
ns  
t
prop  
SCK Frequency  
SCK  
MHz  
SEN  
tsu  
th  
SCK  
tsu th  
tprop  
X
1
SA0  
SA1  
SA2  
PA0  
PA1  
PA2  
PA3  
X or Z  
D4  
SDI  
Z
D0  
D1  
D2  
D3  
D5  
D6  
D7  
Z
SDO  
Read Operation  
SEN  
SCK  
tsu  
th  
tsu th  
X
0
SA0  
SA1  
SA2  
PA0  
PA1  
PA2  
PA3  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
X
SDI  
Z
SDO  
Write Operation  
- 20 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
TRANSMIT TIMING CHARACTERISTICS:  
PARAMETER  
Clock Duty Cycle  
Setup Time  
SYMBOL  
TTC/TTCF  
TTDxS  
CONDITIONS  
MIN  
40  
2.5  
2.5  
NOM  
MAX  
60  
UNIT  
%
ns  
Hold Time  
TTDxH  
ns  
TIMING DIAGRAM: Transmitter Waveforms (E3/DS3/STS-1)  
TTCF  
TTC  
TCLK  
TCLKP=LOW  
TCLK  
TCLKP=HIGH  
TTDPH  
TTDPS  
TPOS  
TTDNH  
TTDNS  
TNEG  
- 21 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
RECEIVE TIMING CHARACTERISTICS:  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
NOM  
MAX  
UNIT  
CKREF Duty Cycle  
--  
40  
60  
%
w.r.t. line-rate  
frequency  
CKREF Frequency Stability  
--  
-20  
+20  
ppm  
RCLK Duty Cycle  
Data Propagation Delay  
TRC/TRCF  
TPROP  
40  
-0.3  
10  
100  
2.3  
10  
60  
3
%
ns  
UI  
UI  
µS  
UI  
UI  
µS  
E3 mode  
DS3 mode  
STS1 mode  
140  
150  
3
130  
130  
3
255  
250  
100  
255  
250  
250  
Receive Loss of Signal  
Assert Timing  
--  
E3 mode  
DS3 mode  
Receive Loss of Signal  
De-assert Timing  
100  
2.3  
--  
STS1 mode, see  
Note 1  
Note 1: At least a 100µS of software delay must be added after STS-1 LOS de-assertion to be compliant with  
the ANSI T1.231 requirement of 100 to 250µS.  
TIMING DIAGRAM  
:
Receive Waveforms (E3/DS3/STS-1)  
RECEIVE LINE  
INPUT (REF)  
(LINP,LINN)  
TRCF  
TRC  
RCLK  
RCLKP=LOW  
RCLK  
RCLKP=HIGH  
TPROP  
RPOS  
RNEG  
TPROP  
- 22 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
E3 – TRANSMITTER SPECIFICATIONS  
PARAMETER  
CONDITION (see timing diagram)  
MIN  
TYP  
MAX  
UNIT  
Transmitter Amplitude  
Measured at 0ft of terminated  
75ohm cable.  
900  
1000  
1100  
mVpk  
Ratio of amplitudes of positive and  
negative pulses measured at pulse  
centers  
Transmitter Amplitude Mismatch  
0.95  
1.05  
Ratio of widths of positive and  
negative pulses measured at pulse  
half amplitude  
Measured at 0ft of terminated  
75ohm cable.  
Transmitter Pulsewidth Mismatch  
Transmitter Pulsewidth  
0.95  
12.1  
1.05  
17  
14.8  
ns  
DS3 – TRANSMITTER SPECIFICATIONS  
PARAMETER  
CONDITION  
MIN  
TYP  
MAX  
UNIT  
Measured at 0ft of terminated  
75ohm cable with LBO pin held  
high (enabled).  
Transmitter Amplitude  
700  
800  
850  
mVpk  
Ratio of amplitudes of positive  
and negative pulses measured at  
pulse peaks.  
Transmitter Amplitude Mismatch  
0.9  
1.1  
+5.7  
-20  
Transmitter Power  
at 22.368 MHz  
Harmonic Power  
at 44.736 MHz  
All ones pattern, 3kHz bandwidth  
-1.8  
dBm  
dBm  
All ones pattern  
Power below fundamental at  
22.368MHz  
STS-1 – TRANSMITTER SPECIFICATIONS  
PARAMETER  
CONDITION  
MIN  
TYP  
MAX  
UNIT  
Transmitter Amplitude  
Measured at 0ft of terminated  
75ohm cable with LBO pin held  
high (enabled).  
700  
825  
950  
mVpk  
Transmitter Amplitude Mismatch  
Transmitter Power  
Ratio of amplitudes of positive and  
negative pulses measured at pulse  
peaks.  
PRBS15 pattern band-limited to  
207.36MHz.  
0.9  
1.1  
-2.7  
+4.7  
dBm  
- 23 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
E3 TRANSMIT PULSE TEMPLATE  
17 ns  
0.2  
0.1  
1.0  
8.65 ns  
0.1  
0.2  
14.55 ns  
0.5  
12.1 ns  
24.5 ns  
0.1  
0
0.1  
0.1  
0.1  
0.2  
29.1 ns  
- 24 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
DS3 TRANSMIT PULSE TEMPLATE  
1.2  
1
0.8  
0.6  
0.4  
0.2  
0
-0.2  
-1  
-0.5  
0
0.5  
1
1.5  
Time, Unit Intervals  
Time axis range (UI)  
Normalized amplitude equation  
UPPER CURVE  
-0.85 < T < -0.68  
-0.68 < T < 0.36  
0.36 < T < 1.4  
0.03  
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}  
-1.84(T-0.36)  
0.08+0.407 e  
LOWER CURVE  
-0.85 < T < -0.36  
-0.36 < T < 0.36  
0.36 < T < 1.4  
-0.03  
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}  
-0.03  
- 25 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
STS-1 TRANSMIT PULSE TEMPLATE  
1.2  
1
0.8  
0.6  
0.4  
0.2  
0
-0.2  
-1  
-0.5  
0
0.5  
1
1.5  
Time, Unit Intervals  
STS-1 (Transmit template specs)  
Time axis range (T)  
Normalized amplitude equation (A)  
UPPER CURVE  
-0.85 < T < -0.68  
-0.68 < T < 0.26  
0.26 < T < 1.4  
0.03  
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}  
-2.4(T-0.26)  
0.1+0.61 e  
LOWER CURVE  
-0.85 < T < -0.38  
-0.38 < T < 0.36  
0.36 < T < 1.4  
-0.03  
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}  
-0.03  
- 26 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
TRANSMITTER OUTPUT JITTER  
The transmit jitter specification ensures compliance with ITU-T G.823 and G.824, Telcordia GR-499 CORE(I)  
and GR-253-CORE, and ANSI T1.102-1993 for all supported rates. Transmit output jitter is guaranteed only if a  
clean SONET quality transmit clock source is used.  
Measured Jitter  
Amplitude  
Jitter  
Detector  
20dB/decade  
Transmitter  
Output  
f1  
f2  
PARAMETER  
Transmitter Output Jitter  
CONDITION  
10 Hz to 800 kHz  
10 kHz to 800 kHz  
MIN  
NOM  
MAX  
0.15  
0.08  
UNIT  
UIpp  
UIpp  
Note: Filters defined by standards are used for all testing  
- 27 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
TRANSMIT MONITOR  
The transmit monitor function looks at the signals on the LOUTPx and LOUTNx pins and checks for the  
existence of a valid signal. The monitor detects the peak of the transmitted signal at the LOUTPx and LOUTNx  
pins and checks that it is between VUNDER and VOVER at all times. If the peak level is within the voltage threshold  
window, the TXNW signal is low. If the peak level falls outside of the threshold limits for more than  
approximately 25 bit times, the TXNW signal goes high.  
VTPOS - VTNEG  
VOVER  
VPEAK  
VUNDER  
Time  
PARAMETER  
CONDITION  
MIN  
TYP  
MAX  
UNIT  
DS3/STS-1 mode with LBOx=1  
450  
mVpk  
VUNDER  
E3 mode;  
DS3/STS-1 mode with LBOx=0  
550  
1050  
1480  
mVpk  
mVpk  
mVpk  
DS3/STS-1 mode with LBOx=1  
VOVER  
E3 mode;  
DS3/STS-1 mode with LBOx=0  
- 28 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
DS3/STS-1 -- RECEIVER SPECIFICATIONS (Transformer-coupled)  
PARAMETER  
CONDITION  
MIN  
TYP  
MAX  
UNIT  
MON=0;  
Signal at DSX is 360-850 mVpk.  
90  
850  
mVpk  
(see Note 2)  
Peak Differential Input  
Amplitude, LINPx and LINNx  
MON=1  
(see Note 3)  
25  
90  
0
80  
1200  
6
mVpk  
mVpk  
dB  
(see Note 1)  
MON=0; DS3-HIGH  
(see Note 4)  
MON=0.  
Flat-loss Tolerance  
Receive Clock Jitter  
All valid cable lengths.  
DS3 mode with 10 Hz – 400 kHz  
a) Normal receive mode  
b) Remote loopback mode  
0.1  
0.06  
UIpp  
UIpp  
Interfering Tone Tolerance  
(see Note 5)  
Maximum ratio of Interference Power  
to Signal Power for BER < 10-8  
a) With 0ft cable from DSX  
-9  
dB  
dB  
-10  
b) With 450ft cable from DSX  
Note 1: Signal source should meet DS3 template of ANSI-T102.1993 Figure 4 and STS-1 template of ANSI-  
T102.1993 Figure 5. Loss characteristics of the WE728A or RG59B cable should be better than Figure  
C2 of ANSI-T102.1993.  
Note 2: Min spec corresponds to minimum DSX amplitude, 5.5dB of cable loss (450ft) and 6dB of flat  
attenuation. Error-free receiver performance is guaranteed for up to 600ft of cable from DSX cross-  
connect. Typical part can handle up to 900ft.  
Note 3: Min spec corresponds to amplitude of 425mVpk at DSX, 5.5dB of cable loss (450ft) and 20dB of flat  
attenuation. In monitor mode, interfering tone performance is not guaranteed.  
Note 4: In this mode, no noise, jitter, or interfering tone impairments should be added for guaranteed receiver  
performance.  
Note 5: Interfering signal is a non-synchronous sinusoidal tone of 22.368MHz for DS3 or 25.92MHz for STS-1.  
Data is a PRBS15 (215-1) pattern.  
- 29 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
E3 – RECEIVER SPECIFICATIONS (Transformer-coupled)  
PARAMETER  
CONDITION  
MIN  
TYP  
MAX  
UNIT  
MON=0  
(See Note 1)  
MON=1  
(See Note 2)  
MON=0.  
All valid cable lengths.  
With 100Hz-800kHz filter:  
a) Normal receive mode  
b) Remote loopback mode  
120  
1200  
mVpk  
Peak Differential Input  
Amplitude, LINPx and LINNx  
25  
0
100  
6
mVpk  
dB  
Flat-loss Tolerance  
Receive Clock Jitter  
0.1  
0.06  
UIpp  
UIpp  
Interfering Tone Tolerance  
(see Note 3)  
Maximum ratio of Interference Power  
to Signal Power for BER < 10-8  
a) With 0ft cable  
-9  
dB  
dB  
-10  
b) With 900ft cable  
Note 1: Min spec corresponds to signal amplitude of 950mVpk at source, 12dB of cable loss (1100ft) and 6dB  
of flat attenuation. Error-free receiver performance is guaranteed for all cable less than 1100ft. Typical  
part can handle up to 1350ft.  
Note 2: Min spec corresponds to signal amplitude of 1000mVpk at source, 12dB of cable loss (1100ft) and  
20dB of flat attenuation. In monitor mode, interfering tone performance is not guaranteed.  
Note 3: Interfering signal is a non-synchronous E3 signal of the specified power level below the desired E3  
signal. Both data and interfering signals are PRBS23 (223-1) pattern.  
- 30 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
RECEIVER JITTER TOLERANCE  
The 78P2342JAT receive jitter tolerance exceeds all specifications as shown on the graph below.  
PARAMETER  
CONDITION  
MIN  
NOM  
MAX  
UNIT  
Receiver High Frequency Jitter  
Tolerance  
> 60 kHz  
0.75  
UIpp  
Jitter Tolerance: 78P234x vs. Standards  
104  
103  
102  
101  
100  
10-1  
10-2  
78P234x  
GR-499-CORE(I) [DS3]  
GR-499-CORE(II) [DS3]  
GR-253-CORE(II) [STS1]  
-
ITU T G.823 [E3]  
-
ITU T G.824 [DS3]  
JAT enabled  
101  
102  
103  
104  
105  
106  
107  
Jitter Frequency (Hz)  
- 31 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
ELECTRICAL SPECIFICATIONS (continued)  
RECEIVER JITTER TRANSFER FUNCTION  
The receiver clock recovery loop characteristics are such that the receiver has the following transfer function.  
When the Jitter Attenuator (JAT) is enabled in the receive or transmit path, the receiver or transmitter will  
exhibit a jitter transfer as shown in the graph and table below. Jitter Attenuator operation is guaranteed through  
digital scan testing. The actual jitter transfer is guaranteed by logic design and is not tested during production  
testing.  
PARAMETER  
CONDITION  
MIN  
NOM  
MAX  
UNIT  
Receiver Jitter transfer function  
Below Fc  
At –3dB point  
JABW= 0, E3 mode (default)  
JABW= 1, E3 mode  
0.1  
dB  
13  
188  
JABW= 0, DS3 mode (default)  
JABW= 1, DS3 mode  
17  
245  
Hz  
Receiver Jitter Bandwidth, Fc  
JABW= 0, STS1 mode  
JABW= 1, STS1 mode (default)  
20  
283  
JAEN= 0, JAT disabled  
After Fc  
55  
kHz  
dB per  
Jitter transfer function roll-off  
20  
decade  
10  
27Hz  
40kHz  
40Hz  
1kHz  
59.6kHz  
0
-10  
-20  
-30  
-40  
ETSI TBR 24 (E3)  
E3 JAT  
STS1 JAT  
JAT Disabled  
DS3 JAT  
-50  
10  
100  
1k  
10k  
100k  
1M  
Jitter Frequency  
- 32 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
APPLICATION INFORMATION  
EXTERNAL COMPONENTS:  
COMPONENT  
PIN(S)  
VALUE  
UNITS  
TOLERANCE  
LINPx  
Receiver Termination Resistor  
Transmitter Termination Resistor  
84.5  
1%  
LINNx  
LOUTPx  
LOUTNx  
402  
1%  
TRANSFORMER SPECIFICATIONS:  
COMPONENT  
Turns Ratio for the Receiver  
VALUE  
UNITS  
1:1  
TOLERANCE  
Turns Ratio for the Transmitter (center-tapped)  
Suggested Manufacturer: Pulse, Tamura, Halo  
1:2CT  
THERMAL INFORMATION  
PACKAGE  
CONDITIONS  
No forced air;  
4-layer JEDEC test board  
No forced air;  
Θ ( ˚C/W)  
ja  
Standard 100-pin JEDEC LQFP (78P2342JAT-IGT)  
46  
Exposed Pad 100-pin JEDEC LQFP (78P2342JAT-IEL)  
4-layer JEDEC test board;  
Die attach pad soldered to PCB  
24.8  
SCHEMATICS  
For schematics, recommended transformer part numbers, etc. please check TDK Semiconductor's website or  
contact your local sales representative for the latest application note(s) and/or demo board manuals.  
- 33 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
MECHANICAL SPECIFICATIONS  
(Top View)  
15.7 (0.618)  
16.3 (0.641)  
15.7 (0.618)  
16.3 (0.641)  
PIN No. 1  
Indicator  
13.8 (0.543) SQ  
14.2 (0.559)  
0.50 TYP.  
(0.0197)  
0.00(0)  
0.20 (0.008)  
0.60 (0.024) TYP.  
1.40 (0.055)  
1.60 (0.063)  
0.18( 0.007)  
0.27 (0.011)  
78P2342JAT-IGT Mechanical Specification  
100-pin TQFP (JEDEC LQFP)  
- 34 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
MECHANICAL SPECIFICATIONS  
(Bottom View)  
16.000 +/- 0.200  
14.000 +/- 0.100  
12.000 REF.  
100  
1
MAX. EXPOSED  
PAD AREA  
10.000 MAX.  
13.950 +/- 0.100  
MAX. 1.600  
1.400 +/- 0.050  
0.220 +/- 0.050  
0.500  
0.100 +/- 0.050  
0.600 +/- 0.150  
78P2342JAT-IEL Mechanical Specification  
100-pin Exposed Pad LQFP (JEDEC LQFP)  
- 35 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
PACKAGE INFORMATION  
Pin-Out  
(Top View)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
N/C  
VCC  
VCC  
LBO1  
LBO2  
N/C  
N/C  
GNDD  
SDI  
N/C  
GNDD  
LPBK1  
LPBK2  
N/C  
SDO  
SCK  
CS  
INTR1  
INTR2  
N/C  
78P2342JAT  
N/C  
PORB  
ENDECB  
VCCD  
VCC  
N/C  
GND  
VCC  
VCCD  
CKREF  
GNDD  
VCCD  
VCCD  
N/C  
GND  
MSL0  
MSL1  
GNDD  
VCCD  
TPOS1  
TNEG1  
TCLK1  
N/C  
N/C  
100-pin TQFP (JEDEC LQFP)  
ORDERING INFORMATION  
PART DESCRIPTION  
ORDER NUMBER  
PACKAGE MARK  
78P2342JAT-IGT  
xxxxxxxxxxP7  
100-pin JEDEC LQFP  
78P2342JAT-IGT /A07  
100-pin JEDEC LQFP,  
78P2342-IGT  
xxxxxxxxxxP7  
78P2342-IGT /A07  
No Jitter Attenuator  
78P2342JAT-IEL  
xxxxxxxxxxP7  
100-pin JEDEC LQFP w/ Exposed Solder Pad  
78P2342JAT-IEL /A07  
78P2342-IEL /A07  
100-pin JEDEC LQFP w/ Exposed Solder Pad,  
78P2342-IEL  
xxxxxxxxxxP7  
No Jitter Attenuator  
Tape & Reel option  
append ‘R’  
append ‘/F’  
n/a  
Lead-free option  
78Pxxxxxxx-xxx  
xxxxxxxxxxP7F  
- 36 -  
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
REVISION HISTORY  
Revision Date:  
Revision Description:  
ENDEC pin addition (pin 15) and default change to ENDEC bit  
Changed LBOx pin functionality by adding TXEN & PDTX control  
Corrected LPBKx pin description and Intrinsic Transmit Jitter spec.  
June 24, 2002  
Changed to Preliminary Status  
Added Exposed Pad package option (-IEL) and Lead-free option (/ F)  
Updated Receive Jitter Tolerance and Jitter Transfer graphs  
Removed SGHI bit definition  
Updated Internal Power on Reset description  
Added pin type CIT  
Updated timing diagrams & e-spec table values  
Changed recommended Rx / Tx termination resistor values to 84.5 / 402 ohm respectively  
Added Thermal Information section  
July 10, 2003  
Changed to Final Status  
Updated ENDEC description (pg.4)  
Updated RNEGx and RPOSx pin descriptions (pg.14)  
Updated DC Characteristics (pg.17)  
Updated pull-up & pull-down resistances (pg.18)  
Added Loss of Signal timing specs (pg.22)  
Updated Transmitter Specification conditions (pg.23)  
Updated Transmit Monitor Specifications (pg.28)  
Corrected Jitter Transfer BW for JAT disabled (pg.32)  
Updated ordering numbers and IC markings (pg.36)  
February 9, 2004  
This product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to  
warranty, patent infringement and limitation of liability. TDK Semiconductor Corporation (TSC) reserves the right to make changes in  
specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders.  
TSC assumes no liability for applications assistance.  
TDK Semiconductor Corp., 6440 Oak Canyon Rd., Irvine, CA 92618  
TEL (714) 508-8800, FAX (714) 508-8877, http://www.tdksemiconductor.com  
02/09/04 – rev 2.1  
©
2004 TDK Semiconductor Corporation  
- 37 -  

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