9402AVK_技术文档

VSP 94x2A

DATA SHEET

Contents

Page

Section

Title

4

1.

Introduction

5

1.1.

Features

7

2.

Functional Description

CVBS Front-end

7

2.1.

7

2.1.1.

2.1.2.

2.1.3.

2.1.4.

2.1.5.

2.1.6.

2.2.

Source Select

7

Signal Levels and Gain Control

Clamping

8

9

Synchronization

9

Chroma Decoder

12

13

14

15

16

17

19

21

22

24

25

26

27

28

29

30

32

Luminance Processing

RGB Front-end

2.2.1.

2.2.2.

2.2.3.

2.2.4.

2.2.5.

2.2.6.

2.2.7.

2.2.8.

2.2.9.

2.2.10.

2.2.11.

2.3.

Source Select

Signal Magnitudes and Gain Control

Clamping

Digital Prefiltering

RGB → YUV Matrix

Contrast, Brightness and Saturation Control of Input Signal

Soft Mix

Static Switch mode

Static Mixer mode

Dynamic Mixer mode

FBL Activity and Overflow Detection

Input Processing

2.3.1.

2.3.2.

2.3.3.

2.3.4.

2.4.

Horizontal Prescaler

Noise Reduction

Noise Measurement

Letterbox Detection

Output Processing

2.4.1.

2.4.1.1.

2.4.2.

2.5.

Horizontal Postscaler

Panorama Mode

Operation Modes

Display Processing

Peaking

2.5.1.

2.5.2.

2.5.3.

2.5.4.

2.5.5.

2.5.5.1.

2.5.5.2.

2.5.5.3.

2.5.5.4.

2.5.5.5.

2.5.6.

2.5.7.

2.6.

Digital Color Transition Improvement (DCTI)

Coarse and Fine Delay

Oversampling and DAC

Output-Sync Controller

HOUT Generator

VOUT Generator

BLANK Generator

Background Generator

Window Function

Digital 656 Input

Digital 656 Output

Clock Concept

2.6.1.

Line-locked Clock Generator

2

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DATA SHEET

VSP 94x2A

Contents, continued

Page

Section

Title

2

34

40

46

52

3.

I C Bus Interface

2

3.1.

I C Bus Slave Address

2

3.1.1.

3.1.2.

3.1.3.

3.1.4.

I C Bus Format

2

I C Bus List in Alphabetical Order

2

I C Bus Command Table

2

I C Bus Command Description

105

106

109

110

112

114

117

119

121

4.

Specifications

4.1.

Outline Dimensions

1)

4.2.

Pin Connections and Short Descriptions for VSP 9402 and VSP 9412

Differing Pin Connections and Short Descriptions for VSP 9412

Pin Configurations

4.3.

4.4.

4.5.

Pin Circuits

4.6.

Electrical Characteristics

4.6.1.

4.6.2.

4.6.3.

4.6.3.1.

4.6.3.2.

Absolute Maximum Ratings

Recommended Operating Conditions

Characteristics

General Characteristics

2

I C Bus Characteristics

123

5.

Application Circuit

125

5.1.

Application Overview

126

6.

Data Sheet History

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Aug. 16, 2004; 6251-552-1DS

3

VSP 94x2A

DATA SHEET

Powerful Scan-Rate Converter

The family is ideally suited to work in conjunction with

the deflection processors SDA 9380 (9402/32) and

DDP 3315C (9412/42). In combination with the ’digital

TV decoder’ MDE 9500, double-scan iDTV is possible.

including Multistandard Color Decoder

Release Note: Revision bars indicate significant

changes to the previous edition.

The package is upward pin-compatible to other

medium-range and high-end devices of the VSP 94xy

family. A 50/60 Hz derivative is also available (9432,

9442). The device comprises a digital multistandard

color decoder, an RGB interface with fast-blank capa-

bility (SCART), digital ITU656 input, scaling units

including panorama, embedded DRAM for upconver-

sion, picture improvements, temporal noise reduction,

as well as A/D and D/A converters.

1. Introduction

The VSP 94x2A (PRIMUS) is a new component of the

Micronas MEGAVISION IC set in a CMOS embed-

®

ded DRAM technology. The VSP 94x2A comprises all

main functions of a digital featurebox in one monolithic

IC. The number of features is limited in favor of a low-

cost solution, but no trade-off has been made concern-

ing picture quality.

Table 1–1: PRIMUS’ versions

Version

Scan Rate

Digital Input

Digital Output

Analog Output

Conversion

1)

9402A (B13)

100i/120i

(✓)

✓

9412A (B14)

✓

1)

Input and output cannot be used at same time (pin sharing)

Table 1–2: Hardware Compatibility and Suited Backend ICs

1)

Hardware Compatible

Suited Backend IC

DDP 3315C

SDA 9380

✓

VSP 9402A,

✓

VSP 9405B, VSP 9435B

VSP 9407B, VSP 9437B

(No ITU656 input possible)

VSP 9412A,

✓

VSP 9415B, VSP 9445B

VSP 9417B, VSP 9447B

VSP 9425B, VSP 9427B

✓

1)

With some restrictions. Please refer to pin description and/or respective application note

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VSP 94x2A

1.1. Features

– Scan-rate-conversion

• Simple interlaced modes (100/120 Hz): AABB,

AAAA, BBBB (9402A/9412A only)

– Integrated video matrix switch

• Up to seven CVBS inputs, up to two Y/C inputs,

• No scan-rate-conversion modes (50/60 Hz): AB,

AA, BB (9432A/9442A only)

• Three CVBS outputs (Y/C inputs signals are com-

bined to CVBS output format)

– Flexible output sync controller

• 9 bit amplitude resolution for CVBS, Y/C A/D con-

verter

• Flexible positioning of the output signal

• Flexible programming of the output sync raster

• ‘Blank signal’ generation

• AGC (Automatic Gain Control)

– Multi-standard color decoder

• PAL/NTSC/SECAM including all substandards

• Automatic recognition of chroma standard

• Only one crystal necessary for all standards

– Signal manipulations

• Still field

• Insertion of colored background

• Windowing

– RGB-FBL or YUV-H-V input

• Vertical chrominance shift for improved VCR pic-

ture quality

• 8 bit amplitude resolution for RGB or YUV

• 8 bit amplitude resolution for FBL or H

– Sharpness improvement

– ITU656 support (version dependent, refer to next

chapter)

• Digital color transition improvement (DCTI)

• Peaking (luminance)

• ITU656 input/output

• DS656 output (double-scan ‘656-like’ output)

– Three D/A converters

• 9 bit amplitude resolution for Y, -(R-Y), -(B-Y) out-

put

– Letterbox detection

– Noise reduction

• 72 MHz clock frequency

• Temporal noise reduction

• Two-fold oversampling for anti-imaging

• Simplification of external analog postfiltering

• Field-based temporal noise reduction for lumi-

nance and chrominance

– 1920 active pixel/per line in default configuration

• Different motion detectors for luminance and

chrominance or identical

2

– I C-bus control (400 kHz)

2

• Flexible programming of the temporal noise

reduction parameters

• Selectable I C address

– 1.8 V ±5% and 3.3 V ±5% supply voltages

• Automatic measurement of the noise level

– PMQFP80-1 package

– Horizontal scaling of the 1f signal

H

• Split-screen possible with additional PiP or Text

processor

– Flexible digital horizontal scaling of the 2f signal

H

• Scaling factors: 3, ..., 0.75 including 16:9 compat-

ibility

• 5 zone panorama generator

– Embedded memory

• On-chip memory controller

• Embedded DRAM core for field memory

• SRAM for PAL/SECAM delay line

– Data format 4:2:2

– Flexible clock and synchronization concept

• Horizontal line-locked or free-running mode

• Vertical locked or free-running mode

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VSP 94x2A

DATA SHEET

e r u f f

d a t a b

ked

F

L

Y

BLAN

AD

CLKF2

Fig. 1–1: Block Diagram

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DATA SHEET

VSP 94x2A

2. Functional Description

can be looped back to output CVBSO1-3

(CVBOSEL1, CVBOSEL2, CVBOSEL3). A signal

addition is performed to output a CVBS signal even

when separate Y/C signals are used at input. Inputs

that are not used are roughly clamped to fit in the

allowed voltage region. For stand-by operation (power-

down mode), A/D and D/A converter are switched off

by STANDBY keeping the source-selector operational.

2

All I C bus registers mentioned are printed in bold and

italics (e.g. YCDEL).

2.1. CVBS Front-end

The CVBS front-end consists of the color decoding cir-

cuit itself, a sync processing circuit for generation of H/

V signals out of the CVBS signal, and the luminance

processing. The main task of the luminance process-

ing is to remove the color carrier by means of a notch

filter. For PAL and SECAM operation a baseband delay

line is used for U and V signals. This can be used as

comb filter in NTSC operation (only for chrominance).

The RGB input can either be used as an overlay for the

CVBS channel (RGB+FBL) or as a full master channel

(RGB+H/V). The overlay is done by means of a soft-

mix and can be used e.g. for ‘SCART’ connector. This

block contains a matrix (for RGB signals) which is

switched off for YUV (e.g. YPbPr) input signals. A CBS

(contrast, brightness, saturation) control makes the

input signal adjustable.

2.1.2. Signal Levels and Gain Control

To adjust to different CVBS input voltages a digitally

working automatic gain control is implemented. Input

voltages in the range between 0.6 to 1.8 V can be

pp

applied to the CVBS inputs.

For best signal-to-noise ratio the maximum available

CVBS amplitude is recommended.

The AGC behavior can be chosen from four possible

modes (AGCMD) (see Table 2–1).

Table 2–1: AGC Modes

2.1.1. Source Select

AGCMD AGC Operation Mode

Fig. 2–1 shows the analog front-end. The analog

CVBS signal can be fed to the inputs CVBS1...7 of

00

AGC uses the height of the sync pulse

as a reference and additionally reduces

amplification when ADC overflows

VSP 94x2A (amplitude 0.5...1.5 V ). One signal is

pp

selected via CVBSEL1 and fed to the first ADC. A sec-

ond signal is selected via CVBSEL2 and fed to the

other ADC. CVBS4&5 or CVBS6&7 are intended to be

use as separate Y/C inputs (YCSEL). After clamping

to the back porch both signals are AD-converted with

an amplitude resolution of 9 bit. The AD conversion is

done using a 20.25 MHz freerunning stable crystal

clock. Before the A to D conversion the signals are

lowpass filtered to avoid antialias effects. Three inputs

01

AGC uses the height of the sync pulse

as a reference

10

11

AGC uses only ADC overflows

AGC is disabled and the ADC fits to the

values given in AGCADJ1

C

CVBS 1

CVBS 2

CVBS 3

C

CVBS 4 / Y1

1

/

1

/

1

/

1

/

1

/

CVBS 5 / C1

CVBS 6 / Y2

CVBS 7 / C2

9

Clamping pulse of ADC_CVBS1

or ADC_CVBS2.

Shifting of signal to required

input voltage range for

CVBSO1..3

Buffer

C

Filter

CVBSO1

CVBSO3

CVBSO2

ADC_CVBS2

ADC_CVBS1

Fig. 2–1: Input Selection

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VSP 94x2A

DATA SHEET

511

446

upper headroom

442

white

black

256

144

64

0

16

0

lower headroom

Fig. 2–2: CVBS, Y and C Amplitude Characteristics.

When using the sync height based AGC mode, the A/D

gain increases or decreases depending on the incom-

ing signal. When using overflow detection only, the

gain is set to maximum and is reduced whenever an

’overflow’ occurs.

2.1.3. Clamping

The timing of the clamping (pulse) control signals for

the analog inputs are derived from its corresponding

CVBS input signal. The clamping algorithm works with

a split measurement pulse and a clamping pulse. The

measurement pulse is used to detect the clamping

error. The clamping pulse is used to enable current

sources for reducing the detected clamping errors. The

start and length of the measurement signals are inde-

pendently adjustable for both channels (CLMPST1,

CLMPD1, CLMPST2, CLMPD2).

The signal is low pass filtered so that chrominance and

noise are not used for detection. The threshold can be

adjusted by PWTHD. A setting of ’11’ equals 511 and

means an overflow of the ADC. Other settings react for

a lower level. The gain only becomes higher when a

change of the channel is detected or is manually reset

by AGCRES. AGCFRZE holds the current AGC value.

The same applies for the clamping signals

(CLMPST1S, CLMPD1S, CLMPST2S, CLMPD2S).

Clamping and measurement signals for RGB channel

are not separate. Clamping for these ADC are con-

trolled by CLMPST2S and CLMPD2S only. Clamping

can be suppressed for some lines by CLMPLOW and

CLMPHIGH to ignore copyprotection information. No

external sync signals are required.

A manual setting of the ADCs gain control is possible

using the parameters AGCADJ1 and AGCADJ2.

The conversion range (CR) is bigger than the signal

range (SRY, SRC) leaving a headroom for overshoots

(see Fig. 2–2).

.

Gain Control Characteristic

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

CLMPST1

CLMPD1

Measurement ADC1

Clamping ADC1

CLMPST1S

CLMPD1S

0.9

0.8

0.7

0.6

0.5

CLMPST2

CLMPD2S

CLMPD2

Measurement ADC2

CLMPST1S

Measurement and Clamping RGBF

Clamping ADC2

0

8

16

24

32

40

48

56

64

AGCADJ1, AGCADJ2 (I²C)

Fig. 2–3: CVBS ADC Characteristic

Fig. 2–4: Clamping Signals

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DATA SHEET

VSP 94x2A

Table 2–2: Clamping Adjustment

Signal

Description

CLMPST1

CLMPD1

Measurement pulse start for ADC1

Measurement pulse duration for ADC1

Clamping pulse start for ADC1

Clamping pulse duration for ADC1

(Measurement pulse start for ADC2)

(Measurement pulse duration for ADC2)

CLMPST1S

CLMPD1S

CLMPST2

CLMPD2

CLMPST2S

CLMPD2S

Measure and clamp start for RGBF-ADC (clamping start for ADC2)

Measure and clamp duration for RGBF-ADC (clamping duration for ADC2

2.1.4. Synchronization

2.1.5. Chroma Decoder

After elimination of the high frequent components of

the CVBS signal by a low pass filter, horizontal and

vertical sync pulses are separated. Horizontal sync

pulses are generated by a digital phase locked loop.

The time constant can be adjusted between fast and

slow behavior in four steps (PLLTC) to accommodate

different input sources (e.g. VCR). The time-constant

can be changed during normal operation without visi-

ble picture degradation. A fine tuning of the PLL time

constant can be done by NSRED.

The digital multistandard chroma decoder is able to

decode NTSC and PAL signals with a subcarrier fre-

*

quency of 3.58 MHz and 4.43 MHz (PAL B /N/

†

60 ,NTSC M/4.4) as well as SECAM signals with auto-

matic standard detection. Alternatively a standard can

be forced. The demodulation is done with a regener-

ated color-carrier. To enable a factory adjustment of

the crystal frequency, the frequency of the regenerated

subcarrier can be adjusted via SCADJ. For this pur-

pose the crystal deviation (SCDEV) can be read out

2

via I C after chroma PLL locking (indicated by

Additional weak input signals from a satellite dish

(’fish’) become more stable when SATNR is enabled.

Vertical sync pulses are separated by integration of

equalizing pulses. A vertical flywheel mode improves

vertical sync separation for weak signals (VFLYWHL,

VFLYWHLMD).

SCOUTEN) and can be stored in µC ROM for SCADJ.

For test purposes, CPLLOF allows the opening of the

chroma PLL loop.

For adjustment to the specific operational area an

automatic norm detection is selectable. Available

50 Hz color standards are PAL B, PAL N and SECAM.

Available 60 Hz color standards are NTSC M, PAL M,

PAL60 and NTSC44. For each line standard, one or

more color standards can be enabled for automatic

chroma standard detection. Please refer to Table 2–

3: and Table 2–4: for allowed combinations.

Additionally, v-syncs may be gated by VTHRL and

VTHRH to reject invalid v-syncs (independently adjust-

able for 50 and 60 Hz sources) if no input signal is con-

nected the device switches to a freeruning mode. The

device can be configured to switch-on background

color when no or only a weak signal is applied (NOS-

IGB). 50 Hz or 60 Hz operation for sync separation

may be forced separately or selected to work automat-

ically (FLNSTRD).

The standard detection process can be set to slow or

fast behavior (LOCKSP). In slow behavior, 25 fields

are used to detect the standard, whereas 15 fields are

used in fast behavior. If the detection was not success-

ful during this time frame, the system will switch to the

next enabled TV Standard.

*

PAL B is representative for PAL B/G/H/I/N

† PAL60 and NTSC44 are nonstandard signals which

are generated by some VCR or DVD player

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VSP 94x2A

DATA SHEET

Table 2–3: Allowed combinations for color-standard

search (50 Hz)

ACCFRZ holds the current ACC value. The maximum

amplification of the ACC can be limited by ACCLIM.

This results a smooth attenuation of color intensity for

weak color carrier (see Fig. 2–5).

Standard

(50 Hz)

None

CSTAND

D2

0

D1

0

D0

0

U,V

PAL N

0

1

+0dB

CON

PAL B

0

1

0

SECAM

1

0

Automatic

PAL BG / SECAM

1

0

color off

+6dB

-4dB

Table 2–4: Allowed combinations for color-standard

search (60 Hz)

CKILL

attenuation of

color-carrier

ACCLIM

Standard

(60 Hz)

CSTAND

PAL, NTSC operation

CONS

D6

0

D5

D4

1

D3

0

U,V

PAL M

0

1

0

1

+0dB

NTSC M

NTSC44

0

1

0

Automatic

0

1

0

PAL M / NTSC M

color off

Automatic

1

0

0(!)

NTSC M /

+6dB

-4dB

NTSC44/PAL60

attenuation of

color-carrier

CKILLS

In addition, a standard can be forced as well.

AMSTD50 selects whether PAL B or SECAM is tried

first in the automatic routine. AMSTD60 selects

whether NTSC44/PAL60 or NTSC M is tried first. Both

bits can also be set for automatic detection, then the

last detected chroma standard will be used. For

SECAM detection, a choice between different recogni-

tion levels is possible (SCMIDL, SCMREL) and the

evaluated burst position is shiftable (BGPOS).

SECAM operation

Fig. 2–5: Color Killer Adjustment

Color standard (STDET), line standard (LNSTDRD)

and color killer status (CKSTAT) can be read out.

An Automatic Chroma Control (ACC) produces a sta-

ble output for input chroma variations from (approxi-

mately) -30 dB to +6 dB compared to nominal burst

value. The ACC reference value is programmable for NTSC

and PAL independently (NTSCREF, PALREF) to ensure

correct color saturation. With ACCFIX, the ACC is dis-

abled and a constant value (dependent on NTSCREF

and PALREF) is used instead.

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DATA SHEET

VSP 94x2A

If the chrominance signal is below an adjustable

threshold (CKILL (PAL; NTSC) or CKILLS (SECAM))

the color is switched off. To prevent on / off switching, a

hysteresis is given by CON or CONS which is the

value of switching on the color. COLON switches on

the color under any circumstance.

Chroma filter

5

0

5

10

15

20

25

30

35

40

CHRF=’001000’

CHRF=’001100’

The output of the color decoder can be set to UV or

CrCb data by CRCB. For NTSC only, the color impres-

sion (tint) can be adjusted by the Hue Control between

-88° and 90° in steps of 0.7° (HUE). Low chrominance

values (+/- 1...3 LSB) may be deleted by UV-coring

(UVCOR). The Chroma bandwidth can be adjusted by

CHRF. The setting value of CHRF has no linear

impact to the chroma bandwidth. The frequency

response of the Chroma bandfilter are shown in Figure

2-7. Also a filter with asymmetrical characteristic

around the color carrier is available (IFCOMP)

(Figure 2–7). For SECAM mode, the de-emphasis filter

can be adjusted by DEEMPFIR and DEEMPIIR. The

bell filter can be adjusted by BELLFIR and BELLIIR.

CHRF=’001001’

CHRF=’001110’

CHRF=’111001’

0.5

0

1

1.5

2

2.5

3

3.5

4

Frequency (MHz)

Fig. 2–6: Chroma Filter Characteristics

IF Prefilter

10

3.58

4.433

5

0

5

IFCOMP=’100’

IFCOMP=’000’

IFCOMP=’011’

The delay between Y and C is well aligned and can

also be adjusted in steps of 50 ns (YCDEL). No picture

shifting occurs when switching between different color

standards (e.g. SECAM -> PAL). A delay-line is imple-

mented for PAL and SECAM signals. It acts as a sim-

ple chrominance comb-filter for NTSC and can be dis-

abled by COMB. This improves the vertical chroma

resolution, but cross-color remains.

10

15

20

25

30

IFCOMP=’001’

IFCOMP=’010’

0

1

2

3

4

5

6

Frequency (MHz)

Fig. 2–7: IF Prefilter

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VSP 94x2A

DATA SHEET

2.1.6. Luminance Processing

characteristic for SECAM (4.25 MHz)

A luminance notch filter is implemented to separate

the chroma information from the luminance. Depend-

ing on the color standard, one out of three different

notch characteristics is chosen (‘PAL’, ‘NTSC’,

‘SECAM’) automatically.

5

0

NTCHSEL=

4.25

5

’100’

’001’

’000’

10

15

20

25

30

’010’

For PAL and Secam the respective notch filters have 5

different characteristics each. The luminance notch fil-

ter for NTSC can be set to 4 different filter response

curves. They can be selected by NTCHSEL. Alterna-

tively, no notch should be used for Y/C input

(NOTCHOFF). The filter characteristics can be found

in Figure 2–8. In SECAM operation, the notch filter can

be fixed to one frequency or toggle between 4.4 MHz

and 4.25 MHz depending on the transmitted color (Dr,

Db) (SECNTCH).

’011’

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

frequency [MHz]

Fig. 2–10: Filter Characteristics for SECAM

(SECNTCH=’01’, 4.25 MHz)

A simple lowpass-filter can be enabled by LPPOST to

further reduce high-frequency noise component from

the CVBS signal.

characteristic for Y/C

5

LPPOST=0

0

LPPOST=1

5

10

15

20

25

30

characteristic for NTSC

5

NTCHSEL=

3.58

’x00’

0

’x01’

’x10’

5

’x11’

10

15

20

25

30

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

frequency [MHz]

Fig. 2–11: Filter Characteristics for Y/C mode.

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

The black level can be shifted by the parameter

LMOFST. This is required to compensate 7.5 IRE off-

sets in some input signals (e.g. NTSC) The positive or

negative offset is added to the Y signal before scaling.

frequency [MHz]

Fig. 2–8: Filter Characteristics for NTSC, PAL M and

PAL N

BLACK

BLANKING BLACK

BLANKING

LMOFST='10'

LMOFST='00'

LMOFST='11'

LMOFST='10'

LMOFST='00'

LMOFST='11'

characteristic for PAL

5

NTCHSEL=

4.43

LMOFST='01'

0

5

’000’

’100’

LMOFST='01'

Input signals without 7.5IRE offset

Input signals with 7.5IRE offset

10

15

20

25

30

’010’

Fig. 2–12: Adjustment of ‘Black’ to ‘Blankingvalue’ at

Analog Output.

’011’

’001’

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

frequency [MHz]

Fig. 2–9: Filter Characteristics for PAL B/G, NTSC44,

PAL60

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DATA SHEET

VSP 94x2A

2.2. RGB Front-end

YUV including sync or H/V signals. This can be used,

for example, for a DVD player or set-top-box. When

using H sync from a non CVBS input (e.g. separate H-

sync) this must be indicated by HINP. The usage of

separate V sync must be set by VINP.

An analog RGB input port for an external RGB or YUV

source is available. The incoming signal is clamped to

the back porch by a clamping pulse. As the memory is

only able to store a 4:2:2 picture, the YUV input signal

is downconverted to 4:2:2. There are two operation

modes available. The first one uses this input as an

overlay input (soft mix). The RGB or YUV signal must

then be synchronized to the main CVBS/YC signal.

The second so called independent mode uses RGB /

The delay of luminance and fast-blank can be adjusted

by YFDEL, and chrominance can be delay adjusted by

UVDEL. If necessary, a fine adjustment of the fast

blank can be set by the parameter FBLDEL.

Table 2–5: Possible input signals for RGB Front-end

Input Signal

RGB

FBL

V

Sync Separation

Sync on CVBS

Sync on H

Remark

Hinp Vinp

IN

1)

CVBS

1

0

1

0

1

0

1)

YUV

1)

RGB

H

V

E.g. set-top-box

Soft mix

1)

YUV

H

Sync on H

RGB

FBL

Synchron to CVBS/YC

YUV

Soft mix

RGB (incl. sync)

Sync on G (maybe on R/B) No external sync

Sync on Y No external sync e.g. DVD

YUV (incl. sync)

1)

Instead of FBL input, CVBS input can be used when Hinp=0

from VINP pin

AGCADJ2

Data 2

from CVBS

Source select

ADC2

ADC1

AGCADJ1

AGCMD

HINP

256

0

1

Sync

processing

from CVBS

Source select

CLMPV1

CLAMPSIGNALS

1

VINP

ADCSEL

0

1

AGCADJR

CLMPVRB

from RGB

Source select

DATAR

to soft-mix

ADCR

ADCG

ADCB

ADCF

R Processing

G Processing

B Processing

F Processing

RBOFFSET

CLAMPSIGNALS2

DATAG

AGCADJG

CLMPVG

from RGB

Source select

to soft-mix

GOFFSET

AGCADJB

CLMPVRB

from RGB

Source select

DATAB

DATAF

to soft-mix

RBOFFSET

AGCADJF

DCLMPF

from RGB

Source select

to soft-mix

Fig. 2–13: Signal and Clamping Organization

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VSP 94x2A

DATA SHEET

2.2.1. Source Select

2.2.2. Signal Magnitudes and Gain Control

Two inputs are available. The choice between the first

or second input is made by RGBSEL.

The gain adjustment of the four ADCs can be done

with the parameters AGCADJR, AGCADJG, AGC-

ADJB, AGCADJF

255

229

255

229

upper headroom

80

16

0

16

0

lower headroom

Fig. 2–14: Y/RGBF Amplitude Characteristics (with or without sync)

255

240

255

240

upper headroom

100% U

100% V

212

128

44

212

128

44

75% V

75% U

16

lower headroom

0

Fig. 2–15: UV Amplitude Characteristics

Gain Control Characteristic

DC Gain Control Characteristic

ADC output=255

1.6

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1.5

1.4

1.3

1.2

1.1

1

conversion range

0.9

0.8

0.7

0.6

0.5

0.4

ADC output=0

0.1

0.2

0

8

16

24

32

40

48

56

64

0

8

16

24

32

40

48

56

64

AGCADJR, AGCADJG, AGCADJB, AGCADJF (I²C)

AGCADJF (I²C)

Fig. 2–16: RGB ADC Characteristic, Fast-blank ADC

with Clamping (DCLMPF=0)

Fig. 2–17: Fast-blank ADC Characteristic without

Clamping (DCLMPF=1)

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DATA SHEET

VSP 94x2A

Table 2–6: Configurations of input signals

Mode

CLMPVG

CLMPVRB GOFST

RBOFST

DCLMPF

YUV, sync on Y

YUV, sync on H,V

RGB, sync on G

RGB, sync on RGB

RGB, sync on H,V

80

16

80

16

128

16

64

0

128

0

Don’t care

0 (clamping enabled)

Don’t care

64

0

80

64

0

Don’t care

16

0 (clamping enabled)

1 (clamping disabled)

RGB with fast-blank, synchron to CVBS 16

16

0

YUV with fast-blank, synchron to CVBS

16

128

0

128

2.2.3. Clamping

RGB-prefiltering

10

0

When using the dynamic softmix-mode with fast-blank,

clamping of fast-blank input must be disabled by

DCLMPF. The analog clamping value of red and blue

input (V and U resp.) can be adjusted by CLMPVRB.

The analog clamping value of green input (Y resp.) can

be adjusted by CLMPVG. Depending on the input sig-

nal format (YUV, RGB, sync signal or not) these bits

must be set accordingly. On the digital side, a correc-

tion of the analog clamping value must be performed

to reconstruct the blacklevel. This is achieved by RBO-

FST and GOFST. (see Table 2–6 on page 15)

3

10

20

30

40

0

5

10

Frequency [MHz]

15

20

2.2.4. Digital Prefiltering

Fig. 2–18: Digital Prefiltering of RGB Input

2.2.5. RGB → YUV Matrix

A digital prefiltering can be enabled. A band limitation

is required, because the following deskewing filter per-

forms best at frequencies of below 14 MHz. The filter-

ing is performed in all four channels and can be dis-

abled by AABYP. For signal conversion to 4:2:2, an

additional chrominance lowpass can be enabled by

CHRSF. The deskewing filter can be disabled by

SKEWSEL. This is necessary when using the H50-pin

in connection with a Micronas picture-in-picture device

(e.g. SDA 938x, SDA 948x, SDA 958x). In this applica-

tion, the RGB input (in1, in2, in3) of the PiP can not be

used for other RGB/YUV signals (e.g. ‘SCART’ is not

possible). As there is a pixel skew on H50, this pin is

NOT suited to synchronize any IC, except for the

above mentioned PiP ICs

RGB or YUV signals are selected by YUVSEL. The

matrix coefficients are set according to ITU recommen-

dations.

Y

U

V

R

G

B

0,299 0,587 0,114

–0,147 –0,289 0,436

0,615 –0,515 –0,100

=

⋅

Fig. 2–19: RGB to YUV Matrix

Micronas

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VSP 94x2A

DATA SHEET

2.2.6. Contrast, Brightness and Saturation Control

of Input Signal

k = MIXGAIN ⋅ (31 – FBLOFFST) + 32

The YUV signal can be manipulated in order to fit to

the main channel. The contrast can be adjusted

between 0 and 1.97 in 64 steps (CONADJ). The

brightness is adjustable in 255 steps (BRTADJ). Due

to the independent chroma adjustment of U and V (64

steps each, USATADJ, VSATADJ), UV as well as

CrCb input signals can both be displayed correctly.

All necessary limitation and rounding operations are

built-in to fit the range: 0 ≤ k ≤ 128

Considering MIXGAIN=3, k is obtained by

k = 158 – 3 ⋅ FBLOFFST

[κ limited to 0 and 128]

2.2.7. Soft Mix

The soft-mixer circuit consists of a Fast Blank (FB)

processing block supplying a mixing factor k (0... 128)

achieving the output function:

The mixing is only controlled by FBLOFFST.

In the static mixer mode as well as in the previously

mentioned static switch mode, the softmixer operates

independently of the analog fast blank input.

YUV_main⋅ (128 – k) + YUV_inserted⋅ k

YUVmix= --------------------------------------------------------------------------------------------

128

2.2.10. Dynamic Mixer mode

In the dynamic mixer mode, the mixer is controlled by

the Fast Blank signal. The VSPA provides a linear mix-

ing coefficient

k= ‘0’ means that only the main signal is fed through to

the output. k= ‘128’ means that only the inserted signal

becomes visible. The soft mixer supports four modes

that are selected by MIXOP and SMOP.

MIXGAIN(FB – FBLOFFST ⋅ 2)

Table 2–7: RGB operation modes

k = ----------------------------------------------------------------------------------- + 64

2

MIXOP

SMOP

Soft Mix mode

The dynamic mode is used for mixing which is depen-

dent on FB input. FB is the preprocessed digitized fast-

blank input in the range from 0...127. FBL manipulation

is done both for luminance and chrominance FBL sig-

nal.

00

0

Dynamic Soft Mix

(DECTWO must be set to ’1’)

00

1

Static Soft Mix

(DECTWO must be set to ’1’)

Fast blank is delay adjustable by FBLDEL in the range

of -2...4 clock cycles.

01

10

11

x

Only RGB/YUV path visible

Only CVBS path visible

(Reserved)

2.2.11. FBL Activity and Overflow Detection

It is important to know whether the FBL input is used

or not. Therefore a detection circuit gives information

via the I C bus to the microcontroller. The circuit uses

2.2.8. Static Switch mode

2

the FBL value as input. If it is greater than a threshold

for one or five clock cycles (FBLCONF), the I C regis-

ter FBLACTIVE is set. This register is reset after a

read access by the microcontroller. PFBL, PG, PR, PB

indicate an overflow of the corresponding ADC (upper

limit: ADC= 255) exceeding 5 clock cycles duration.

In its simplest and most common application the soft-

mixer is used as a static switch between YUVmain and

YUVinsert. This for instance the adequate way to han-

dle a DVD component signal. By using MIXOP, k is

internally set to 0 or 128 respectively.

2

2.2.9. Static Mixer mode

The signal YUVmain and the component signal YUVin-

sert may also be statically mixed. In this environment,

k is manually controlled via FBLOFFSET and MIX-

GAIN.

16

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DATA SHEET

VSP 94x2A

2.3. Input Processing

UV decimation filter

5

0

3

HSYNC

5

NALPFIP

(not active

lines input)

10

15

20

25

30

35

40

Complete picture area

ALPFIP

(Active lines

input)

Active picture

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Frequency (MHz)

Fig. 2–22: UV-decimation Filter Characteristic for

Standard Operation (Decimation=1.5)

NAPPLIP

(not active

pixel per

APPLIP

(active

pixel per

line input)

2.3.2. Noise Reduction

Fig. 2–20: Image Format before Memory

The Fig. 2–23 shows a block diagram of the temporal

noise reduction. The structure of the temporal motion

adaptive noise reduction is the same for luminance as

for chrominance signal. Noise reduction is enabled by

NRON.

2.3.1. Horizontal Prescaler

The main application of the horizontal prescaler is the

conversion of the number of pixels coming form the

40.5/20.25 MHz pixel clock domain down to the num-

ber of pixels stored in the memory (factor 2/3). Gener-

ally the number of incoming pixels can be decimated

by a factor between 1 and 64 in a granularity of 2 out-

put pixels. The horizontal scaler reduces the number of

incoming pixels by subsampling. To prevent the intro-

duction of alias distortion low pass filters are used for

luminance and chrominance processing (Fig. 2–22). In

case of ITU656 input, the lowpass filter must be dis-

abled by HAAPRESC.

The output of the motion detector is weighted using the

parameters TNRCLC and TNRCLY. The look-up table

input value range is separated into 8 segments. It is

possible to freely program different behavior of the

noise reduction by using predefined curve characteris-

tic for each segment. The curve characteristics can be

programmed by the parameters TNRSxY for lumi-

nance and TNRSxC for chrominance. The curve-start

is defined by TNRSSY (TNRSSC) at the end of the last

segment (Figure 2–24). The overall curve is now con-

structed by connecting the end of segment 6 to the

beginning of segment 7 and so on. Negative values of

Ky (Kc) are not possible and clipped to zero.

The horizontal prescaler consists of two main subsam-

pling stages. The first stage is a scaler for rational dec-

imation factors in a range of 1 to 2, controlled by

HSCPRESC. The second stage decimates in integer

steps (1,2,3,4...32), controlled by HDCPRESC.

For chrominance, the result of the luminance motion

detector or a separate chorminance motion detector

can be used (TNRSEL).

Y-decimation filter

5

0

5

10

15

20

25

30

35

40

0

1.25

2.5

3.75

5

6.25

7.5

8.75

10

Frequency [MHz]

Fig. 2–21: Y-decimation Filter Characteristics for

Standard Operation (Decimation=1.5)

Micronas

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VSP 94x2A

DATA SHEET

Y_in

Ky

Motion

Noise

LUTY

Y_out

DetectionY

Y_delay

ReductionY

Y_delay

TNRCLY

TNRCLC

TNRSxY

TNRSxC

TNRABS

NRON

UV_in

TNRSEL

UV_in

Motion

Noise

Kuv

LUT C

UV_out

Detection C

UV_delay

Reduction C

Kc

UV_delay

Fig. 2–23: Temporal Noise Reduction

TNRSx=0000

TNRSx=0100

TNRSx=1000

TNRSx=1100

TNRSx=0001

TNRSx=0010

TNRSx=0011

TNRSx=0101

TNRSx=1001

TNRSx=1101

TNRSx=0110

TNRSx=1010

TNRSx=1110

TNRSx=0111

TNRSx=1011

TNRSx=1111

Fig. 2–24: Segments of LUT

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DATA SHEET

VSP 94x2A

segment 0 segment 1

segment 2 segment 3

segment 4 segment 5 segment 6 segment 7

Ky/Kc

15

14

13

12

11

10

9

TNRSSY,

TNRSSC

8

7

6

5

4

3

2

1

0

TNRSY

,

TNRSC

0001

1111

0100

0000

0

4

8

12

20

28

36

48

64 motion

Fig. 2–25: Predefined Curve Characteristics for LUT

2.3.3. Noise Measurement

black bars at the top and bottom exist. With the help of

an expansion algorithm it is possible to expand the let-

terbox picture vertically and horizontally in such a way,

that the letterbox picture will fill the complete screen

without loosing information. To do so, the information

about the active part of the letterbox picture is neces-

sary. Active part means the information about the first

active line and the last active line of the letterbox pic-

ture. The figure below shows the principle of this idea.

The noise measurement algorithm can be used to

change the parameters of the temporal noise reduction

processing depending on the actual noise level of the

input signal. This is done by the TV- microcontroller

which reads the noise level (NOISEME), and sends

different parameter sets to the temporal noise reduc-

tion registers of the VSP 94x2A depending on this

value (0 = no noise, 126 = strong noise). Value 127

indicates an overflow status which means that the

measurement failed. The value is determined by aver-

aging over several fields. The line taken for noise mea-

surement is selected by NMLINE. When NOISEME

contains updated data which were not read so far,

NMSTATUS is set. NMSTATUS is reset when read.

The measurement position can be adjusted (NMPOS)

as well as the sensitivity (NMSENSE).

The WSS (Wide Screen Signal) signal contains some

information about the picture format (4:3 or 14:9 or

16:9), but not all existing formats are covered and not

all signals contain WSS. Therefore a separate algo-

rithm is necessary which delivers the necessary infor-

mation. The figure below shows the concept of the let-

terbox detection algorithm. One part of the algorithm is

dedicated hardware and located in the VSP 94x2A

another part is software and located in the RAM of the

TV microcontroller. The part located in VSP 94x2A is

called measurement part. The measurement part

delivers 5 signals to the controller part.Based on the

delivered information the controller part calculates an

expansion and a vertical pan factor and sends these

values back to the VSP 94x2A for manipulation of the

video signal.

2.3.4. Letterbox Detection

A drawback of wide screen 16:9 TV sets are the black

bars at the left and the right side on the screen, if dis-

playing a 4:3 source on a 16:9 screen with correct

aspect ratio. In case of letterbox source material also

4:3 Letterbox Picture

Expanded Letterbox Picture

Fig. 2–26: Handling of Letterbox Pictures on 16:9 Tubes

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VSP 94x2A

DATA SHEET

Software

Hardware (940x)

LBSLAA

LBELAA

Controller

part

Measurement

Part

Y

LBFORMAT

LBSUBTITLE

LBTOPTITLE

zooming parameters

Horizontal and/or

Vertical

YUVin

YUVout

Resizing

Fig. 2–27: HW/SW Partitioning

The letterbox detection block works only at a data rate

of 13.5 MHz. Due to the fact, that the input data rate at

channel-mux output can be 13.5 MHz, 20.25 MHz or

40.5 MHz, the input signal has to be downsampled.

P

2

Depending on the I C bus register LBSUB different

LBVWSTU

modes are possible (Downsample 1, 1.5, 3). As digital

656input data are already in 13.5 MHz format, no

downsampling should be used (LBSUB=0). For CVBS,

YUV and RGB signals (if DECTWO=1) a downsam-

pling of 1.5 (LBSUB=2) is required.

L

LBVWST

LBVWEND

In principle the input picture is separated in one upper

and one lower part. The measurement windows are

defined by the parameters LBVWSTUP, LBV-

WENDUP (upper vertical measurement window),

LBVWSTLO, LBVWENDLO (lower measurement win-

dow) and LBHWST, LBHWEND (horizontal measure-

ment window).

4*LBHWST

4* LBHWEND

Fig. 2–28: Measurement Windows

A controller software and its description is available

upon request.

20

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DATA SHEET

VSP 94x2A

2.4. Output Processing

2.4.1.1. Panorama Mode

2.4.1. Horizontal Postscaler

The picture can be geometrically distorted in horizontal

direction for an improved impression in the case of

expansions of 4:3 pictures to a 16:9 ratio tube. It is

enabled by HPANON. The idea behind this panorama

mode is to keep the middle part of the picture in a 4:3

ratio and to stretch the left and the right to fill the entire

width of the 16:9 screen. For the adjustment of the

expansion process, the picture is divided into 5 seg-

ments. For each of these segments the increment

value for the expansion factor can be defined sepa-

rately. Each end of a segment can be defined individu-

ally in a granularity of two output pixels. For every seg-

ment an increment value can be defined

(HINC0...HINC4) which indicates the amount of deci-

mation/expansion. One LSB is equivalent to an offset

of 0.125 to HSCPRESC per double pixel. This means

that with HINC, HSCPRESC is altered in the range

from −32...31.875 per double pixel. The segments are

distributed among the maximum number of pixels,

which is adjusted by PPLOP. The first four segments

are defined by (HSEG1...HSEG4). The last one goes

from HSEG4 to PPLOP.

After main memory, the display processing is per-

formed using a different clock. In this way a decoupling

of input and output clocks is achieved. The conversion

to the display clock is done by an interpolation filter.

This can be used for horizontal expansion in the range

of 1...4 in steps of 2 pixels (HSCPOSC). Due to

increased clock frequency in the backend part, the

realized horizontal scaling factor depends on backend

clock frequency. Usually (36 MHz operation), the hori-

zontal expansion factors result as 0.75...16. This

ensures that the factor 0.75 gives no loss of resolution

(to show a 4:3 picture on a 16:9 tube). When using

DS656 output, neither horizontal compression nor hor-

izontal panorama is possible due to 27 MHz clock.

Table 2–8: Horizontal expansion factors

HSCPOSC

Horizontal

Filter

Overall Expansion

Expansion

CLKB36=

27 MHz

CLKB36=

36 MHz

INC_VAL

31.875

1024 (min.)

3072

4

3

HINC0

HINC1

1.33

1

1.33

1

HINC2

output

pixels

0

4095

0.75

HINC3

HINC4

-32

Because of the nonlinear characteristic and integer

number of pixel, sometimes different HSCPOSC val-

ues result in the same decimation factors.

HSEG2

HSEG3

HSEG4

max.

0

HSEG1

HSCALE

4095

Horizontal Postscaler

3.5

compression

3

1024

4095

3072

3

2.5

2

expansion

HSCPOSC

(I²C)

1024

output

pixels

1.5

1

HSEG2

HSEG3

HSEG4

max.

0

HSEG1

0.75

Fig. 2–30: Visualization of Panorama Segments

0.5

0

1000

2000

3000

4000

HSCPOSC(I²C)

Fig. 2–29: Expansion Factor of Horizontal Postscaler

Dependent on HSCPOSC

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VSP 94x2A

DATA SHEET

Table 2–9: Examples of Panorama Mode

Table 2–9 on page 22) describes the different scan

rate conversion algorithms of VSP 94x2A and the cor-

responding raster sequences.

Function

Panorama Extreme Pan. Lens

Fig. 2–32 on page 23 explains the 50/60 Hz interlaced

to the 100/120 Hz interlaced conversion including the

field signal, the raster organization and the memory

timing for AABB.

HSCPOSC 2099

1023

3999

d

HSEG1

HSEG2

HSEG3

HSEG4

HINC0

HINC1

HINC2

HINC3

HINC4

APPLOP

96

d

192

288

384

192

288

384

192

288

384

472

492

000

d

A still field can be displayed using FREEZE command.

For the improvement of VCR signals, the chrominance

can be shifted one line upwards by CHRSHFT

40

20

85

43

d

FRAME/FIELD

FRAME

FIELD A

odd lines

000

492

472

960

000

469

427

960

d

FIELD B

20

40

d

even lines

960

Content of picture

d

DISPLAY LINE-SCANNING PATTERN

2.4.2. Operation Modes

Display line-scanning

pattern

TV

Display raster

odd lines

There are four operation modes defined. The first

mode is simple AABB, where each stored field in the

memory is displayed double times on the TV screen.

The second and third mode are AAAA and BBBB, in

which only one field phase will be displayed on the TV

screen. There is also a fourth mode AAAA mode with

αβαβ raster possible. Fig. 2–31 explains the picture

and the display raster.

even lines

Display line-scanning

pattern

Tube, Display raster

The interlaced input signal (e.g. 50 Hz PAL or 60 Hz

NTSC) is composed of a field A (odd lines) and a field

B (even lines).

Fig. 2–31: Explanation of Field and Display Line-

scanning Pattern

n

A - Input signal, field A at time n,

n

B - Input signal, field B at time n

The field information describes the picture content.

The output signal, which could contain different picture

contents (e.g. field A, field B), can be displayed with

the display raster α or β.

n

(A ,α) - Output signal, field A at time n, displayed as

raster α,

n

(A ,β) - Output signal, field A at time n, displayed as

raster β,

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DATA SHEET

VSP 94x2A

Table 2–10: Operation modes for scan-rate conversion

Input Field A

Input Field B

STOPMODE

Scan-Rate

Conversion

Output Field

Phase 0

Output Field

Phase 1

Output Field

Phase 2/0

Output Field

Phase 3/1

n

00

01

10

11

AABB mode

AAAA mode

BBBB mode

A ,α

B ,β

n

A ,α

n

A ,α

A ,β

A ,α

A ,β

n-1

n

B

,β

B

,β

B ,β

Aⁿ

Bⁿ

Aⁿ⁺¹

Line number

of memory

Write

Read

time

Aⁿ⁺¹

Aⁿ

Bⁿ

Aⁿ⁺¹

OPDEL

raster_org

n

n+1

field

Fig. 2–32: 50/60 Hz Interlaced to 100/120 Hz Interlaced Conversion (AABB)

Micronas

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VSP 94x2A

DATA SHEET

2.5. Display Processing

The peaking filter clock frequency is CLKB36=36 MHz

(27 MHz). The maximum signal frequency of the pic-

ture stored in the memory is 6.75 MHz. Due to a peak-

ing after postscaler, the frequency range of the peak-

ing filter varies with the expansion factor of the

postscaler.

The display processing part contains an integrated tri-

ple 9-bit DAC and performs digital enhancements and

manipulations of the digital video component signal.

Fig. 2–35 shows the block diagram of the display pro-

cessing part.

Peaking filter characteristic

15

2.5.1. Peaking

The luminance peaking filter improves the overall fre-

quency response of the luminance channel. It consists

of two filters working in parallel. They have high pass

(HP) and band pass (BP) characteristics. Their gain

factors are programmable separately (BCOF, HCOF).

Values greater than 4 peak the signal, whereas values

less than 4 attenuate the signal. The high pass and the

band pass filters are equipped with a common coring

algorithm. It is optimized to achieve a smooth display

of grey scales, not to improve the signal-to-noise ratio.

Therefore no artifacts are produced. Coring can be

switched off (YCOR). The Fig. 2–34 shows the block

diagram of the peaking block.

BCOF

HCOF

10

5

0

5

0

0.1

0.2

0.3

0.4

0.5

normalized Frequency (B)

Fig. 2–33: Peaking Filter: Bandpass and Highpass

filter

BP

GAINB

GAINH

coring

HP

AP

Peak_in

Peak_out

Fig. 2–34: Block Diagram Peaking

9402/9432 only

YCOR,

HCOF,

BCOF

PKLY,

PKLU,

PKLV,

COARSEDEL

CHROMAMP FINEDEL

Y

Fine

Delay

Peaking

DCTI

Delay

4:4:4

DAC

Yin

Cin

ayout

Coarse

Delay

8:8:8

DAC

U

auout

DAC

avout

V

THRESHC,

ASCENTCTI

8

656out

ITU656

Encoder

656clk

SHIFTUV,

DPOUT656

Fig. 2–35: Block Diagram of Display Processing

24

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DATA SHEET

VSP 94x2A

2.5.2. Digital Color Transition Improvement (DCTI)

Table 2–11: Conversion table between HCOF/BCOF

and GAINHP/GAINBP

A digital algorithm is implemented to improve horizon-

tal transitions of the chrominance signals resulting in a

better picture sharpness. A correction signal propor-

tional to the slope of the detected horizontal transition

of the input signal is added to the original input signal.

The amplitude of the correction signal is adjustable by

BCOF

0

GAINBP

−1

HCOF

0

GAINHP

−1

2

1

−0.75

−0.50

−0.25

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.50

3.00

4.00

1

−0.75

−0.50

−0.25

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.50

3.00

4.00

the I C bus parameter ASCENTCTI.

2

The I²C bus parameter THRESHC modifies the sensi-

tivity of the DCTI circuit. High values of THRESHC

result in an improvement of significant color transitions

only.

3

4

5

6

7

8

9

10

11

12

13

14

15

10

11

12

13

14

15

Table 2–12: Peaking filter adaption for 36 MHz or 27 MHz operation

Expansion Factor of

Postscaler

Corresponding Frequency of Input

Signal for Center Frequency

Bandpass (B=0.25)

Corresponding Frequency of Input

Signal for Center Frequency Highpass

(B=0.5)

CLKB36=36 MHz/27 MHZ

3.375 MHz / 2.5 MHz

...

CLKB36=36 MHz/27 MHZ

6.75 MHz / 5.06 MHz

...

0.75

...

1

4.5 MHz / 3.375 MHz

...

9 MHz / 6.75 MHz

...

3

13.5 MHz / 10.125 MHz

27 MHz / 20.25 MHz

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VSP 94x2A

DATA SHEET

2.5.3. Coarse and Fine Delay

PKLY

Before digital-to-analog conversion an adjustment of

the phase of the luminance is performed. A coarse

delay from −8 to +7 in steps of 1 pixel CLKB36

(~28 ns) is possible (COARSEDEL). FINEDEL shifts

the luminance one CLKB72 (~14 ns) pixel. This can be

used to compensate delays, if the external processing

of Y and UV produces different delays (e.g. external

lowpass filtering).

128 LSB upper headroom for peaking

240 LSB normal

signal range

'black'

16 LSB

2.5.4. Oversampling and DAC

128 LSB lower headroom for peaking

After conversion into 8:8:8 format (CLKB72=72 MHz),

three 9-bit digital-to-analog converters are used for

analog YUV output. This twofold-oversampling gener-

ates 1920 active pixels per line (when using recom-

mended settings) and simplifies the external postfilter-

ing. The output voltage is determined by PKLY, PKLU

and PKLV and can be set in a range of 0.4 V ...1.9 V

(fullscale).

0 V

PKLU

PLLV

CHROMAMP=1

CHROMAMP=0

'no color'

8 bits of the luminance D/A converter are used for the

entire signal. The 9th bit is used for over- and under-

shoots caused by the peaking to prevent or reduce

clipping artifacts. As the CTI block seldomly produces

such overshoots, a full-scale operation can be acti-

vated by CHROMAMP. The output voltages may be

calculated by:

Fig. 2–36: DAC Output Signals

PKLY

256







+ 0.36V ⋅ signalY

---------------

VoltageY = 1.56V ⋅



2.5.5. Output-Sync Controller

The output sync controller generates horizontal and

vertical synchronization signals for the scanrate-con-

verted output signal.

160....400

-----------------------

signalY =

512

The number of pixels per line is 4*PPLOP. The default

value of 288 results in 1152 pixels/line. With

CLKB= 36 MHz, the horizontal output frequency is

31.25 kHz, which is twice the PAL horizontal fre-

quency. Out of these pixels, 16*APPLOP are displayed

as active picture area, which are 960 by default. The

position on the screen depends on the NAPPLOP. It

marks the picture area not active in horizontal direction

and moves the active picture in horizontal direction.

The number of lines per field is 2*LPFOP. This value is

only used in the vertical freeruning mode. In vertical

locked mode, the number of lines per field is derived

from the CVBS signal itself and not adjustable. The

active and non-active picture areas are marked by

ALPFOP and NALPFOP, respectively.

[for unpeaked signals max.]

0....511

signalY = -----------------

512

[for peaked signals max.]

PKLU, V

256









----------------------

VoltageU, V = 1.56V ⋅

+ 0.36V ⋅ CHROMAMP ⋅ signalUV

Both generators have a so called ‘locked-mode’ and

‘freeruning-mode’. Not all combinations of these

modes make sense. Table 2–13 on page 27 shows

ingenious configurations.

128....384

512

signalUV = -----------------------

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DATA SHEET

VSP 94x2A

derived from the CVBS signal, to enable a soft transi-

tion to locked mode (PDGSR, LPFOPFF). This syn-

chronization is only possible when the number of

CVBS input lines corresponds to the programmed

value of LPFOP.

HSYNC

NALPFOP

(not active

lines output)

Complete picture area

LPFOP

(lines

output)

When no or very weak signal is connected to the

CVBS input, the IC can be configured to automatically

switch into freerunning mode. This stabilizes the dis-

play which may contain OSD information, e.g. during

channel-tune. The configuration, whether the IC

switches to H-freerun, V-freerun or both can be config-

ured by AUTOFRRN

ALPFOP

(Active lines

output)

Active picture

APPLOP

(active

pixel per

line output)

2.5.5.1. HOUT Generator

PPLOP

(pixel per line output)

The HOUT generator has two operation modes, which

can be selected by the parameter HOUTFR. The

HOUT signal is active high for 64 clock cycles

(CLKB36). In the freerunning-mode the HOUT signal is

generated depending on the PPLOP parameter. In the

locked-mode the HOUT signal is locked on the incom-

ing H-Sync signal derived from CVBS. The polarity of

the HOUT signal is programmable by the parameter

HOUTPOL.

Fig. 2–37: Image Format behind Memory

For freerun mode the backend part works stand alone

without analyzing the input signals. The clock domains,

input data part and output data part of the IC, are not

synchronized to each other. If the output processing

works in the freerun mode, the output signals of the

2

OSC are generated depending on I C-bus settings.

For locked mode the backend part works with a line

locked clock. This means that the front-end and the

backend of the IC are synchronized to each other. The

generation of the controlling signals depends on output

signals from the front-end. This mode will be the

default and the most used mode for standard TV appli-

cations.

2.5.5.2. VOUT Generator

The VOUT generator has two operation modes, which

can be selected by the parameter VOUTFR. In the fre-

erunning-mode (VOUTFR=1) the VOUT signal is gen-

erated depending on the LPFOP parameter.

With activated vertical freerun mode the phase of the

generated vsync signal has no correlation to the

incoming vsync signal. A hard switch from freerun

mode to locked mode would therefore cause visible

synchronization problems in the deflection unit of the

TV set concerning the vertical picture positioning. To

avoid these problems a circuit is implemented which

synchronizes the freerunning vsync signal to the vsync

In the locked-mode the VOUT signal is synchronized

by the incoming V-Sync signal derived from CVBS,

delayed by some lines (OPDEL). During one incoming

V-Sync signal, two VOUT pulses have to be generated.

The polarity of the VOUT signal is programmable by

the parameter VOUTPOL. The VOUT signal is active

high for two output lines..

Table 2–13: Ingenious configurations of the HOUT and VOUT generator

Mode

HOUTFR

VOUTFR

‘H-and-V-locked’ mode

‘H-freerunning / V-locked’ mode

‘H-and V freerunning’ mode

0

1

0

1

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VSP 94x2A

DATA SHEET

2.5.5.3. BLANK Generator

be replaced by the background values and vice versa.

There is also the possibility to realize a fixed border via

the I²C bus (BORDPOSH and BORDPOSV). 4096 dif-

ferent colors are available.

The BLANK signal is used to horizontally and vertically

mark active picture area. It is enabled by BLANEN and

its polarity can be chosen by BLANPOL and VBLAN-

POL. Referred to hsync, the start is given by BLAN-

DEL and its length is given by BLANLEN, both adjust-

able with 4 pixel resolution. Referred to vsync, the start

is given by VBLANDEL and its length is given by

VBLANLEN, both adjustable in 1 lines resolution.

BORDPOSH and BORDPOSV also influence the win-

dow generation. This means the automatic opening

and closing of the picture will start or end at the posi-

tion which is defined with these values. The border is

calculated with the following formula: The horizontal

border on the left side of the TV screen is 2*BORD-

POSH and 2*BORDPOSH on the right side of the TV

screen. This means, that 4*BORDPOSH pixels are

overwritten with border values. The same applies to

the vertical direction. 4*BORDPOSV lines in total are

overwritten with background values. BORDERV

decides whether upper or lower or both borders are

displayed. BORDERH decides whether left or right or

both borders are displayed.

2.5.5.4. Background Generator

This generator is able to realize an automatic closing

and opening of the displayed picture. This means that

with every picture the displayed colored background,

defined by UBORDER, VBORDER and YBORDER

will get bigger or smaller. The original picture data will

Table 2–14: Display line scanning pattern sequence

Display Line Scanning Pattern Sequence

1. to 2.

2. to 3.

313

3. to 4.

312

4. to 5.(1.)

313

a a a a

b b b b

a a b b

a b a b

312

313

312

313

312

312.5

313

312.5

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DATA SHEET

VSP 94x2A

2.5.5.5. Window Function

WINDHDR. To change from „close“ to „open“ or vice

versa only the WINDHDR parameter has to be tog-

gled. The speed of the window can be defined by the

WINDHSP parameter. Fig. 2–39 shows the functional-

ity of the vertical window function.

Fig. 2–38 shows the functionality of the horizontal win-

dow function. The window can be closed or opened.

The windowing feature can be enabled by the WIND-

HON parameter. The WINDHST and the WINDHDR

parameter determine, what status (opened or closed)

the window has, and what can be done with the win-

dow (open or close). With each enabling of the window

function by the WINDHON parameter, the status of the

window will be as defined by WINDHST and

All settings are also available in vertical direction. All

I C parameters exist for both directions (e.g. WIND-

HON and WINDVON for horizontal and vertical window

enabling). Combinations of both window functions

(horizontal and vertical) are also possible.

2

Fig. 2–38: Horizontal Windowing

close window

open window

Fig. 2–39: Vertical Windowing

close window

open window

Fig. 2–40: Horizontal and Vertical Windowing

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VSP 94x2A

DATA SHEET

2.5.6. Digital 656 Input

2.5.7. Digital 656 Output

The IC decodes a digital 8 bit@27 MHz data stream

according to ITU.BT656 standard. The configuration is

set by EN_656. and DPOUT656.

Dependent on version (single- or double-scan), the

output data format corresponds to CCIR 656 (8-bit bus

at a data rate of 27 MHz) or has double-scan format

(8-bit bus at a data rate of 54 MHz). There all frequen-

cies and data-rates are doubled compared to standard

CCIR656 specification. Double scan format is intended

to be used with a suited backend device, e.g.

DDP3315C. Timing reference codes (SAV, EAV) are

inserted according to the specification. The output can

be enabled by DPOUT656. The output should be set

to 720 pixels per line (APPLOP) and the display clock

should be set to 27/54 MHz (refer to Chapter 2.6.).

The chrominance information can be inverted by

CHRMSIG656. HOUT and VOUT pins may be used in

parallel.

Table 2–15: 656 input / output selection

EN_656

DPOUT656

656 Operation

0

Input disabled/

output disabled

0

1

0

1

Input disabled/

output enabled

Input enabled/

output disabled

2.6. Clock Concept

Input enabled/

output disabled

(9412A only)

A single 20.25 MHz crystal at fundamental mode is

used as clock reference. All other clocks are derived

from this source. The CVBS front-end works with

20.25 MHz, the RGB front-end works with 40.5 MHz,

the oversampling DACs use CLKB72 and the memory

and all parts behind the memory are clocked with

CLKB36. The frequency of CLKB36 and CLKB72 is

adjustable and depends on application. With analog

output, CLKB72 is usually 72 MHz and with digital out-

put, CLKB72 is usually 54 MHz. CLKB72 is always

twice of CLKB36.

Four input modes are supported:

Table 2–16: 656 modes

IMODE

656 Operation

00

Full ITU mode (automatic)

Three different clock concepts are supported. The dif-

ference is the behavior in clocking the memory output.

The front-end part of the VSP 94x2A uses a freeruning

but crystal-stable clock (CLKF). After deskewing, an

orthogonal picture is written into the memory. The read

out is done using the (CLKB) clock.

Information about active picture is taken

from data-stream

01

Full ITU mode (manual)

Information about active picture is taken

from APPLIPI, NAPPLIPI, ALPFIPI,

NALPFIPI

The horizontal sync-signal output (HOUT) is derived

from a counter running with CLKB. The VOUT is

directly derived from the input vertical signal, which is

generated by the sync-separation block. This ‘H-fre-

erunning-V-locked mode’ is only possible together with

a DC coupled deflection controller.

10

11

ITU656 only data, H/V-sync according

PAL/NTSC

ITU656 only data, H/V-sync according

ITU656

In ‘H-and-V-locked mode’ CLKB is line-locked to the

incoming signal. The freerunning YUV picture data

and the internal H signal are converted to the line-

locked domain. Now HOUT and the sync signal in the

To adjust the input to sources, which deviate from the

standard, the field information may be inverted

(F_POL) and the chrominance format can be chosen

between unsigned and 2’s complement format (CFOR-

MAT). The polarity of H an V can be inverted by

H_POL and V_POL respectively. Dependent on ver-

sion, the digital input must be selected by ITUPRTSEL

(pins i656i or 656io).

1f domain are directly coupled.

H

In case of ‘H-and-V-freerunning mode’ the HOUT and

VOUT signals are derived from counters running with

CLKB. There is no connection to the incoming signal.

This mode can be used for stable pictures when no

signal is applied (e.g. channel search with OSD inser-

tion).

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DATA SHEET

VSP 94x2A

The selection between freerunning and locked clocks

may be forced or selected to be dependent on PLL

conditions. Please refer to Fig. 2–41

with this sampling clock. The clock output can be dis-

abled by CLKOUTON. Additionally a 20.25 MHz clock

can be output to pin 74 (656hin/clkf20) to supply other

ICs (e.g. PiP) with the same clock (CLKF2PAD). When

enabled, 656-input with separate H/V-sync is not pos-

sible. For 656-output operation, CLKB36 is given to pin

9 (656clk).

A

clock

output

of

27 MHz

(single-scan

version:13.5 MHz) is possible (pin 27:clkout). This

clock is 3/4 of CLKB36. HOUT and VOUT are in line

Table 2–17: Clock system

Name

Clock

Nominal Frequency

‘H-/V-

‘H-freerunning- ‘H-/V-

locked’

Mode

V-locked’

Mode

freerunning’

Mode

CLKF20

CLKF40

CVBS front-end

20.25 MHz

40.5 MHz

FR

RGB front-end,

input processing

FR

CLKB36

CLKB72

CLKB27

Output and dis-

play processing

9402: 36 MHz (analog out)

9412: 27 MHz (digital out)

LL

FR

Oversampling,

DAC

9402: 72 MHz

9412: 54 MHz

CLKOUT-pin

9402: 27 MHz

9412: 20.25 MHz

Front-end

PLL

STAB=0 and

AUTOFREERUN=1x

CVBS

Freerun

Generator

freerunning

clocks

SETSTABLL

HOUTFR

0

1

0

1

CLKBxx

1

0

yes

no

locked

clocks

LL-PLL

STABLL

(indicates PLL stability)

Fig. 2–41: Conditions for Freerunning/Locked Switching

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VSP 94x2A

DATA SHEET

2.6.1. Line-locked Clock Generator

A freerunning frequency is also generated which may

be selected alternatively. The freerunning frequency

for the 100/120 Hz version dependent on FRINC is

The clock generation system derives all clocks from

one 20.25 MHz crystal oscillator clock source. An

internal PLL multiplies this oscillator frequency by 32,

generating a clock of 648 MHz which is used as refer-

ence for all clocks needed.

f

= FRINC ⋅ 103Hz

displayfr

Line-locked horizontal sync pulses are generated by a

digital phase locked loop. The time constant can be

adjusted between fast and slow behavior (KPL, KIL) to

accommodate different backend ICs. The PLL control

can be frozen up to 15 lines before V-sync (FION) for a

duration up to 15 lines (FILE). This may be used to

reduce disturbances by h-phase errors which are pro-

duced by VCR’s. The output frequency for the 100/120

Hz version dependent on IICINCR is

Normally, IICINCR and FRINC are equal or nearly the

same. The value is internally divided by two for the 50/

60 Hz versions.

The number of pixels generated by the PLL is given by

PPLIP. For line-locked clock generation the following

equation must be fulfilled:

PPLIP = 2 ⋅ PPLOP

f

= IICINCR ⋅ 103Hz

displayll

20.25 MHz

CLKF40

CLKF20

xtal

oscillator

frequency

divider

FRINC

PLL

648MHz

frequency

divider

FR-DTO

M

U

X

CLKB27

CLKB36

CLKB72

inter-

polation

sync-

separation

phase

detector

loop

filter

frequency

divider

ADC

LL-DTO

IICINCR

analog

CVBS

locked or

freerunning

selection

line-locked

Fig. 2–42: Line-locked Clock Ceneration

nominal 50Hz

operation (analog out)

13.5 / 18

27 / 36 MHz

nominal 50Hz

operation (digital out)

nominal 100Hz

operation (analog out)

nominal 100Hz

operation (digital out)

Fig. 2–43: Allowed Operation Area for Clock Generation

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The PLL settings for different operation modes can be

seen in Table 2–18.

Dependent on input signal (50 Hz or 60 Hz), the line-

locked clock is changing slightly (e.g. from 27 MHz to

27.18 MHz). To have no artifacts when switching

between locked and freerun operation, it is possible to

change the FRINC parameter, after the input TV stan-

dard has been detected safely. In case the IC is oper-

ating in horizontal locked OR freerunning mode only,

this adaptivity is not required.

Table 2–18: Recommended LL-PLL settings for normal TV-application

Operation

Input

50 Hz

60 Hz

50 Hz

60 Hz

PPLIP*4

PPLOP*4

IICINCR

FRINCR

349525

351953

262144

263892

349525

351953

262144

263892

CLKB36 [MHz]

f [kHz]

H

100/120 Hz

(analog out)

2304

1152

349525

36

31.250

31.468

31.250

31.468

15.625

15.734

15.625

15.734

36.25

27

100/120 Hz

(digital out)

1728

2304

1728

864

262144

349525

262144

27.18

18

50/60 Hz (ana- 50 Hz

log out)

1152

864

60 Hz

18.125

13.5

13.59

50/60 Hz (digi- 50 Hz

tal out)

60 Hz

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VSP 94x2A

DATA SHEET

2

3. I C Bus Interface

The transmitted data is internally stored in registers.

The registers are located in four different clock

domains. The Table 3–5 on page 35 shows the four

different clock domains of the VSP 94x2A. The clock

domains are called CP - CVBS processing block

(20.25 MHz domain, clkf20), FP - Front end processing

block (40.5 MHz domain, clkf40), BP - Back end pro-

cessing block (36.0 MHz domain, clkb36) and PP -

PLL processing block (36.0 MHz domain, clkf36).

2

3.1. I C Bus Slave Address

When pin 19 (adr/tdi) is connected to Vss, the

VSP 94x2A reacts on the first I C address (B0h for

write access and B1h for read access). The second

address (B2h and B3h) is active, when pin 19 is con-

nected to Vdd.

2

The registers themselves are grouped in an I C bus

2

Table 3–1: I C bus slave addresses B0h and B1h

interface block, one in each domain. The transmitted

2

data is received by the I C bus kernel. The I C bus ker-

nel itself is located in the CP domain. This means that

the working frequency is 20.25 MHz. The data is trans-

Write Address1: B0h

Read Address1: B1h

2

mitted to the I C bus interface blocks via an internal

1 0 1 1 0 0 0 0

1 0 1 1 0 0 0 1

serial bus.

For the write process, the I2C bus master has to write

a ‘don’t care’ byte to the subaddress FFh (store com-

mand). This makes the register values available to the

four I2C bus interface blocks (except for the not-take-

over registers, which are used immediately).

2

Table 3–2: I C bus slave addresses B2h and B3h

Write Address2: B2h

Read Address2: B3h

1 0 1 1 0 0 1 0

1 0 1 1 0 0 1 1

In order to have a defined time step for the several

blocks in the different domains, the data are made

valid with internal V-syncs, depending on the different

clock domains.

2

3.1.1. I C Bus Format

2

The subaddresses, where the data are made valid with

the V-sync signal of the 20.25 MHz domain are indi-

cated in the overview of the subaddresses with “V20“.

The others are called “V40”, “V36F” and “V36B”

accordingly.

The VSP 94x2A I C bus interface acts as a slave

receiver and a slave transmitter and provides two dif-

ferent access modes (write, read). All modes run with

a subaddress auto increment. The interface supports

the normal 100 kHz transmission speed as well as the

high speed 400 kHz transmission.

Table 3–3: Write

S

1

0

1

0

x

0

A

Subaddress

A

Data Byte

A

*****

A

P

S: Start condition

SR: Repeated Start condition

A: Acknowledge

P: Stop condition

NA: Not Acknowledge

Table 3–4: Read

NA

S

1

0

1

0

x

0

A

SR

1

0

1

0

x

1

A

P

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VSP 94x2A

ferent blocks, the data is made valid with the same V-

Sync related signals mentioned above for the write

process.

2

Table 3–5: I C bus clock domains

Domain

CP-CD

CP-PP

Description

CVBS frontend

LL-PLL

Clock

The VSP 94x2A distinguishes between two different

types of read-registers. The behavior of the “normal”

read registers does not differ from the behavior of the

write registers. Only the direction of the data flow is

opposite.

CP

FP

CLKF20

CLKF40

CP-I2C

FP-PRE

FP-MC

FP-RGB

FP-TNR

I²C read

The “rs typ” read registers behave differently. They can

be only set (means value 1) by the internal blocks

using the rising edge of a corresponding signal. After

Prescaler

Memory-controller

RGB Frontend

2

reading by the I C bus master, the registers will be

2

automatically reset (means value 0) by the I C bus ker-

nel/interface. For example the register NMSTATUS

belongs to the “rs typ” read registers. NMSTATUS sig-

nalizes a new value for NOISEME. So if NMSTATUS is

read as ‘0’ the current noise measurement has not

been updated. If the NMSTATUS is read as ‘1’ a new

noise measurement value can be read. All other “rs

typ” read registers work in the same way. The “rs typ”

read registers will be marked in the overview with the

short cut “rstyp” or will have the additional hint “Note:

Temporal noise

reduction

FP-I2C

PP

I²C read

CLKF40

CLKF36

CLKB36

PP

BP

LL-PLL

PP-I2C

BP-DP

I²C read

Display processing

Pixel-Mixer

2

reset automatically when read/write” in the detailed I C

bus command description.

BP-PM

BP-ODC

BP-ODC/MC

Output data control

By default all registers are made valid by the internal V-

Sync related signals and, in addition, a store command

has to be sent for write registers. The registers, which

should also be made available immediately as for writ-

ing and reading, are marked with the short cut NTO

(No take over mechanism).

Output data control/

memory-controller

BP-POS

BP-DAC

BP-I2C

Postscaler

CLKB36

CLKB72

CLKB36

DAC processing

I²C read

Registers which need a hand-shake mechanism

2

between the I C bus interface and the different blocks

are marked with the shortcut HS (Hand shake mecha-

nism). This means that all bits of the registers are used

when the last register is written. After PPLIP9-2 is writ-

ten, PPLIP1-0 must be written to allow these bits to

have effect.

The I2C parameter V20STAT, V40STAT and V36BSTAT

reflect the state of the register values.

The registers for the write parameter STOPMODE are

If these bits are read as ‘1’, then the store command

was sent, but the data is not made available yet.

directly connected to the read registers of the parame-

ter SMMIRROR. So it is possible to check the I C bus

2

protocol by writing and reading to the register STOP-

MODE and SMMIRROR, respectively.

If these bits are ‘0’ then the data was made valid and a

new write or read cycle can start.

The transmitted data is internally stored in registers.

Writing to or reading from a non-existant register is

permitted and does not generate a fault by the IC.

The bits V20STAT, V40STAT and V36BSTAT may be

checked before writing or reading new data, otherwise

data can be lost by overwriting. No V36FSTAT register

exist. To make the register values available to the four

I C bus interface immediately after sending, the I C

bus master has to write a ‘don’t care’ byte to the sub-

address FEh (store command).

After switching on the IC, all bits of the VSP 94x2A are

set to defined states, (refer to Table 3–6). POR is set

after reset to pin 24. It stays ‘1’, until it is cancled via

software PORCNCL. This can be used to decide dur-

ing TV operation, whether to program all registers (e.g.

after power failure reset) or only altered ones (normal

TV operation).

2

For the read process, the I C bus master must not

send a store command. In order to have a defined time

2

step for the I C bus interface blocks in the different

domains, where the data will be available from the dif-

Micronas

Aug. 16, 2004; 6251-552-1DS

35

VSP 94x2A

DATA SHEET

xin

sda scl

xout

S

o

u

r

c

e

cvbs1

cvbs2

cvbs3

cvbs4

36.0F MHz

72,0 MHz

PP

(PLL

27,0 MHz

ADC

AGC

processing

block)

vout

hout

36,0B MHz

cvbs5

S

e

l

e

c

t

cvbs6

ADC

40,5 MHz

20,25 MHz

cvbs7

cvbso1

cvbso2

cvbso3

OUT 27.0

ODC

I²C

CP

OSC

HPRESCALE

TNR

DAC

(CVBS

processing block)

O

u

t

7

2

ayout

auout

avout

M

C

-

M

C

-

CD

S

o

u

r

c

e

b/u1

g/y1

r/v1

FP

BP

(Front end processing block)

(Back end processing block)

1

2

HPOSTSCALE

RGB

fbl/hin1

DELAY

PICIMPROVE

ADC

b/u2

g/y2

r/v2

S

e

l

e

c

t

VSP 94x2A

fbl/hin2

ADC

vin

hout50

vout50

2

Fig. 3–1: I C Bus Clock Domains

2

Table 3–6: I C bus characterization

Subaddress

00h

Default

AAh

CAh

B0h

C8h

16h

10h

20h

01h

F0h

3Eh

00h

A0h

00h

90h

80h

00h

20h

R/W

W

Take-over Subaddress

Default

44h

00h

FFh

1Fh

F4h

44h

00h

FFh

AAh

05h

00h

60h

90h

00h

04h

R/W

Take-over

V40

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

W

01h

V40

02h

V40

03h

V40

04h

V40

05h

V40

06h

V40

07h

V40

08h

NTO

09h

NTO

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

NTO/HS

NTO/rstyp

NTO

NTO/HS

NTO

10h

36

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–6: I C bus characterization, continued

Subaddress

11h

Default

20h

00h

16h

00h

03h

1Fh

F4h

00h

26h

3Ch

01h

00h

04h

40h

20h

9Ch

AAh

00h

18h

0Bh

00h

R/W

W

Take-over Subaddress

Default

00h

2Dh

44h

94h

20h

00h

01h

00h

E0h

01h

80h

44h

40h

C0h

5Ch

66h

40h

00h

A5h

5Fh

0Fh

00h

3Ch

03h

R/W

W

Take-over

NTO

V36B

V20

V40

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

65h

66h

67h

68h

69h

6Ah

12h

V40

13h

V40

14h

V40

15h

V40

16h

V40

17h

V40

18h

V40

19h

V40

1Ah

1Bh

1Ch

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

V40

V36B

V20

41h

V20

42h

V20

43h

V20

44h

V20

45h

V20

46h

V20

47h

V20

48h

V36B

V20

49h

V20

4Ah

4Bh

4Ch

V20

Micronas

Aug. 16, 2004; 6251-552-1DS

37

VSP 94x2A

DATA SHEET

2

Table 3–6: I C bus characterization, continued

Subaddress

4Dh

Default

00h

55h

0Bh

00h

3Fh

00h

1Ch

FCh

77h

02h

6Ch

00h

15h

00h

R/W

W

R

Take-over Subaddress

Default

07h

R/W

W

Take-over

V20

V36B

V20

6Bh

6Ch

6Dh

6Eh

6Fh

4Eh

07h

4Fh

1Ch

5Ch

00h

V20

50h

V20

51h

52h

70h

00h

53h

71h

E4h

00h

54h

72h

55h

73h

00h

56h

74h

00h

57h

75h

7Fh

40h

V20

76h

B2h

B3h

B4h

B5h_{(no autoincrement)}

B6h

B7h

B8h

B9h

BAh

BBh

BCh

BDh

BEh

BFh

C0h

C1h

D0h

D1h

D2h

E0h

V20

77h

V20

00h

V20

78h

V20

FFh

43h

V20

79h

V20

7Ah

V20

(spare)

00h

7Bh

V20

W

V40

7Ch

V20

00h

7Dh

V20

00h

7Eh

V20

00h

7Fh

V20

(spare)

AAh

05h

80h

V20

W

NTO

81h

V20

82h_{(no autoincrement)}

83h

84h_{(no autoincrement)}

85h

V20

NTO

no/rstyp

NTO

(spare)

00h

R

W

V40

V36

V40

R

00h

86-93h

94h-95h

96h

R

00h

(spare)

00h

R

V40

00h

97h

00h

38

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–6: I C bus characterization, continued

Subaddress

98h

Default

R/W

R

Take-over Subaddress

Default

00h

R/W

W

Take-over

V40

V36B

V20

NTO

V20

V40

NTO

E1h

E2h

E3h

E4h

E5h

E6h

E7h

E8h

E9h

99h

R

00h

W

V40

A0h

00h

FFh

00h

10h

00h

W

R

00h

W

V40

A1h

00h

W

V40

A2h

00h

W

V40

A3h

00h

W

V40

A4h

00h

W

V40

B0h

00h

W

V40

B1h

00h

W

V40

EAh

EBh

ECh

EDh

EEh

EFh

F0-F6h

F7h-FDh

FEh

(spare)

W

FFh

Take-over mechanism

Register types

NTO

V20

No take-over mechanism

W

R

Write register

Read register

Take-over with V-sync

in 20 MHz domain

V40

V36B

HS

Take-over with V-sync

in 40 MHz domain

Rrstyp

Reset register

after reading

Take-over with V-sync

in back-end 36.0 MHz domain

Handshake mechanism required

Micronas

Aug. 16, 2004; 6251-552-1DS

39

VSP 94x2A

DATA SHEET

2

3.1.2. I C Bus List in Alphabetical Order

Name

Subaddress

31h

BCOF

Name

Subaddress

BELLFIR

7Dh

47h

AABYP

0Ch

5Bh

7Ah

0Ch

81h

4Dh

67h

68h

16h

90h

17h

15h

14h

68h

67h

68h

B0h

05h

B8h

32h

90h

B1h

05h

01h

B9h

3Dh

30h

32h

BELLIIR

ACCFIX

BGPOS

ACCFRZ

ACCLIM

BLANDEL

BLANEN

07h

36h

ADCSEL

ADLCK

BLANLEN

BLANPOL

BORDERH

BORDERV

BORDPOSH

BORDPOSV

BRTADJ

08h

36h

ADLCKCC

ADLCKSEL

AFPROC

AGCADJ1

AGCADJ2

AGCADJB

AGCADJCV

AGCADJF

AGCADJG

AGCADJR

AGCFRZE

AGCMD

45h

35h

34h

0Ah

4Fh

18h

CDELHPOS

CFORMAT

CHRF

5Eh

55h

CHRMSIG656

CHROMAMP

CHROMSIGN

CHRSF

57h

0Bh

3Dh

60h

AGCRES

AGCTHD

ALPFIP

CHRSHFT

CKILL

CKILLS

61h

ALPFIPI

CKSTAT

88h

ALPFOP

AM50O

CLKF2PAD

CLKOUTINV

CLKOUTON

CLKOUTSEL

CLKOUTSEL72

CLKT

16h

4Fh

30h

AM60O

AMSTD50

AMSTD60

APENSEL

APPLIP

4Fh

4Dh

2Eh

6Bh

7Bh

6Ch

7Bh

CLMPD1

APPLIPI

CLMPD1S

CLMPD2

APPLOP

ASCENTCTI

AUTOFRRN

CLMPD2S

40

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

Name

Subaddress

69h

Name

Subaddress

27h

CLMPHIGH

CLMPLOW

CLMPST1

CLMPST1S

CLMPST2

CLMPST2S

CLMPVG

CLMPVRB

CLPSTGY

CLRANGE

COARSEDEL

COLON

DISRES

DPOUT656

EIA770

6Ah

6Dh

78h

56h

7Ch

18h

EN_656

ENLIM

6Eh

79h

7Eh

18h

F_POL

10h

FBLACTIVE

FBLCONF

FBLDEL

FBLOFFST

FEMAG

83h

0Dh

6Bh

5Dh

32h

0Dh

0Ch

B1h

6Ch

71h

5Bh

5Fh

5Ch

0Bh

5Bh

82h

FHDET

COMB

FHFRRN

FIELDBINV

FILE

CON

54h

CONADJ

CONS

2Eh

32h

FINEDEL

FIOFFOFF

FION

CPLLOF

54h

CPLLRES

CRCB

80h

2Dh

2Ch

6Bh

7Eh

29h

5Bh

5Fh

6Ah

70h

FKOI

CSTAND

FKOIHYS

FLDINV

FLINE

CVBOSEL1

CVBOSEL2

CVBOSEL3

CVBSEL1

CVBSEL2

DCLMPF

DECTWO

DEEMPFIR

DEEMPIIR

DEEMPSTD

DETHPOL

DETVPOL

DISALLRES

DISCHCH

70h

FLNSTRD

FMOD

6Fh

10h

FOFFST

FREEZE

FREQSEL

FRFIX

C1h

3Fh

7Ch

1Ah

BCh

D0h

0Eh

F3h

F2h

18h

0Bh

B5h

82h

FRINC

FSWFTL

GOFST

88h

GRADELAA

GRADISSTABLE

H_POL

80h

6Ch

Micronas

Aug. 16, 2004; 6251-552-1DS

41

VSP 94x2A

DATA SHEET

Name

Subaddress

09h

Name

Subaddress

89h

HAAPRESC

HCOF

INT

31h

ISHFT

7Eh

16h

HDCPRESC

HDTOTEST

HINC0

05h

ITUPRTSEL

KD2

2Eh

48h

29h

KIL

A1h

2Ah

A0h

E9h

ECh

EFh

F0h

HINC1

49h

KINL

HINC2

4Ah

4Bh

4Ch

29h

KOIH

HINC3

KOIWID

HINC4

KPL

HINCREXT

HINP

KPNL

6Dh

3Ah

38h

LB43SENS

LBACTIVITY

LBASDEL

LBELAA

HORPOS

HORWIDTH

HOUTDEL

HOUTFR

HOUTPOL

HPANON

HPOL

3Eh

41h

LBFORMAT

LBFS

F2h

41h

E6h

EDh

E0h

EAh

EEh

E4h

E3h

EAh

E2h

E7h

E9h

F0h

4Fh

6Ch

28h

LBGFBDEL

LBGRADDET

LBGRADRST

LBGSDEL

LBHISTBLA

LBHIWHITE

LBHSDEL

LBHWEND

LBHWST

LBNGFEN

LBSLAA

HRES

HSCPOSC

HSCPRESC

HSEG1

4Eh

01h

50h

HSEG2

51h

HSEG3

52h

HSEG4

53h

HSPPL

C0h

29h

HSWIN

HTESTW

HUE

2Ah

63h

LBSTABILITY

LBSTATUS

LBSUB

E9h

85h

HWID

2Eh

7Ah

82h

EAh

F2h

IFCOMP

IFCOMSTR

IICINCR

IMODE

LBSUBTITLE

LBTHDNBNG

LBTHDNBNHA

LBTOPTITLE

E9h

EBh

F2h

25h

18h

42

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

Name

Subaddress

E1h

E6h

E5h

E8h

2Ch

A3h

A2h

A4h

29h

Name

Subaddress

19h

LBVWENDLO

LBVWENDUP

LBVWSTLO

LBVWSTUP

LIMEN

NMLINE

NMPOS

NMSENSE

NMSTATUS

NOGRADFOUND

NOISEME

NOSIGB

NOSYNC

NOTCHOFF

NRON

1Ah

85h

F2h

LIMII

84h

LIMIP

6Dh

3Ch

5Ch

1Ah

8Bh

72h/7Eh

80h

LIMLR

LMOD

LMOFST

LNL

5Dh

2Dh

89h

NRPIXEL

NSRED

NTCHSEL

NTSCREF

OPDEL

OSCPD

PALDEL

PALDET

PALID

LNSTDRD

LOCKSP

LPBLACK

LPCDEL

LPFIPMD

LPFLD

47h

F5h

72h

64h

44h

2Fh

8Ah

43h

7Ch

47h

LPFOP

8Ch

88h

LPFOPFF

LPPOST

LPWHITE

MINV

3Ch

62h

PALIDL0

PALIDL1

PALIDL2

PALINC1

PALINC2

PALREF

PB

75h

F5h

92h

74h

82h

MIXGAIN

MIXOP

0Fh

0Dh

09h

82h

MLL

65h

MVP

B2h

04h

85h

MVPG

PDGSR

PFBL

3Fh

NALPFIP

NALPFIPI

NALPFOP

NAPIPPHI

NAPPLIP

NAPPLIPI

NAPPLOP

85h

BAh

45h

PG

85h

PKLU

59h

17h

PKLV

5Ah

58h

02h

PKLY

B7h

3Fh

PLLTC

6Eh

8Ch

POR

Micronas

Aug. 16, 2004; 6251-552-1DS

43

VSP 94x2A

DATA SHEET

Name

Subaddress

80h

Name

Subaddress

2Ch

7Ch

56h

PORCNCL

PPLIP

SETSTABLL

SHAPERDIS

SHIFTUV

SKEWSEL

SLLTHD

2Bh

3Ch

41h

PPLOFF

PPLOP

0Eh

66h

PR

85h

PWADJCNT

PWTHD

93h

SLLTHDV

SLLTHDVP

SLS

B1h

78h

5Dh

0Eh

45h

RBOFST

RDCTRLDIS

REFRON

REFRPER

REFTRIM

REFTRIMCV

REFTRIMCVRD

REFTRIMEN

REFTRIMRD

REFTRIMRGB

REFTRIMRGBRD

REV

8Fh/F6h

87h

SMMIRROR

SMOP

41h

0Eh

8Ch

86h

41h

STAB

76h

STABLL

77h

STANDBY

STDET

11h

8Eh

72h

88h

STOPMODE

SUBTITLE

SWITCHTO43

SYNFTHD

THRESHC

THRSEL

TNRABS

TNRCLC

TNRCLY

TNRS0C

TNRS0Y

TNRS1C

TNRS1Y

TNRS2C

TNRS2Y

TNRS3C

TNRS3Y

TNRS4C

TNRS4Y

TNRS5C

3Fh

8Dh

77h

F2h

8Eh

F6h

0Fh

72h

82h

30h

RGBSEL

SATNR

78h

1Ah

24h

SCADJ

66h

SCDEV

89h

24h

SCMIDL

79h

20h

SCMREL

SCOUTEN

SDB

7Fh

88h

1Bh

20h

B2h

5Eh

7Fh

81h

1Bh

21h

SDR

SECACC

SECACCL

SECDIV

1Ch

21h

7Fh

5Ch

1Ch

22h

SECINC1

SECINC2

SECNTCH

1Dh

22h

44

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

Name

Subaddress

1Dh

23h

Name

Subaddress

81h

TNRS5Y

VFLYWHLMD

VINMTHD

VINP

TNRS6C

TNRS6Y

2Fh

72h

1Eh

23h

TNRS7C

TNRS7Y

VLENGTH

VLP

91h

1Eh

1Ah

1Fh

7Eh

41h

TNRSEL

VOUTFR

VOUTPOL

VPOL

TNRSSC

TNRSSY

TOPTITLE

TRAPBLU

TRAPRED

TSTSHAPERI

UBORDER

UPBLACK

UPWHITE

USATADJ

UVCOR

41h

1Fh

62h

F2h

VSATADJ

VSHIFT

11h

80h

73h

80h

VSIGNAL

VSLPF

18h

7Ch

37h

C1h

75h

VTHRH50

VTHRH60

VTHRL50

VTHRL60

WINDHDR

WINDHON

WINDHSP

WINDHST

WINDVDR

WINDVON

WINDVSP

WINDVST

WRCTRLDIS

Y2RGB

F5h

B4h

74h

F5h

10h

B3h

3Bh

39h

5Ch

13h

UVDEL

V_POL

18h

V20STAT

V36BSTAT

V40STAT

V656DEL

VBLANDEL

VBLANLEN

VBLANPOL

VBORDER

VDEL_EN

VDELF_EN

VDETIFS

VDETITC

VERSION

VFLYMD

99h

98h

96h

39h

4Dh

D0h

37h

39h

09h

12h

YBORDER

YCDEL

36h

55h

62h

03h

YCOR

30h

5Dh

B2h

8Fh/F6h

8Ch

7Dh

YCSEL

6Bh

12h

YFDEL

YUVSEL

0Eh

VFLYWHL

Micronas

Aug. 16, 2004; 6251-552-1DS

45

VSP 94x2A

DATA SHEET

2

3.1.3. I C Bus Command Table

2

Table 3–7: I C register overview

Sub

add

(Hex)

Data Byte

D3

D7

D6

D5

D4

D2

D1

D0

Input Processing

00h

01h

02h

03h

04h

05h

06h

APPLIP[8:1]

APPLIP[0]

HSCPRESC [11:5]

NAPPLIP6[6:0]

NALPFIP8

HSCPRESC[4:0]

VDELF_EN

NALPFIP

NAPPLIP[9:7]

APENSEL

ALPFIP[9:8]

HDCPRESC

ALPFIP[7:0]

07h

08h

09h

BLANDEL

BLANLEN

WRCTRLDIS

HAAPRESC

MLL

RGB Front-end

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

BRTADJ

DECTWO

ADCSEL

CLMPVRB1

YUVSEL

RGBSEL

CLMPVG

STANDBY1

Y2RGB

CHRSF

CONADJ

FBLOFFST

FBLDEL

AABYP

CLMPVRB0

SMOP

MIXOP

FBLCONF

SKEWSEL

RBOFST

GOFST

MIXGAIN

DCLMPF

STANDBY0

USATADJ

VSATADJ

YFDEL

UVDEL

AGCADJR

AGCADJG

AGCADJB

AGCADJF

VSIGNAL

ITUPRTSEL

NAPIPPHI1

IMODE

CLKF2PAD

NAPIPPHI0

CFORMAT

F_POL

H_POL

V_POL

NRON

EN_656

TNRSEL

Noise Reduction

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

NMLINE [7:0]

NMPOS

NMSENSE

NMLINE [8]

TNRS1Y

TNRS3Y

TNRS5Y

TNRS7Y

TNRSSC

TNRABS

TNRS0Y

TNRS2Y

TNRS4Y

TNRS6Y

TNRSSY

46

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–7: I C register overview, continued

Sub

add

Data Byte

D3

(Hex)

D7

TNRS0C

D6

D5

D4

D2

D1

D0

20h

21h

22h

23h

24h

TNRS1C

TNRS2C

TNRS4C

TNRS6C

TNRCLY

TNRS3C

TNRS5C

TNRS7C

TNRCLC

Line-locked Clock PLL

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

IICINCR[18:11]

IICINCR[10:3]

DISRES

IICINCR[2:0]

HINCREXT

HRES

FMOD

HSWIN

KD2

LMOD

KOIWID

PPLIP[9:2]

SETSTABLL

FION

KOIH

HTESTW

FRFIX

LIMEN

FKOI

FILE

FKOIHYS

PPLIP[1:0]

LNL

CLKT

HWID

HDTOTEST

LPFIPMD

VINMTHD

Display Processing

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

42h

43h

YCOR

CLKOUTON

ALPFOP[9:8]

THRESHC

ASCENTCTI

HCOF

BCOF

AUTOFRRN

ALPFOP[7:0]

BORDPOSV

BORDPOSH [7:0]

BLANPOL

UBORDER

HORWIDTH[7:0]

WINDVSP

HORPOS

FINEDEL

COARSEDEL

BLANEN

BORDPOSH[9:8]

YBORDER

VBORDER

WINDVST

WINDHST

WINDVDR

WINDHDR

WINDVON

HORWIDTH[10:8]

HORPOS[10:8]

WINDHSP1

NOSYNC

WINDHSP0

PPLOFF

WINDHON

LPFOPFF

CHRSHFT

HOUTDEL

NAPPLOP[9:8]

NAPPLOP

PPLOP[9:8]

PPLOP[7:0]

LPFOP

APPLOP

PDGSR

FREEZE

REFRON

STOPMODE

HOUTPOL

HOUTDEL[9:8]

HOUTFR

REFRPER

VOUTPOL

VOUTFR

Micronas

Aug. 16, 2004; 6251-552-1DS

47

VSP 94x2A

DATA SHEET

2

Table 3–7: I C register overview, continued

Sub

add

Data Byte

D3

(Hex)

D7

OPDEL[7:0]

BORDERV

NALPFOP

D6

D5

D4

D2

D1

D0

44h

45h

46h

BORDERH

RDCTRLDIS

LPFOP8

NALPFOP8

OPDEL[8]

Panorama Scaler

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

PALDEL.1

PALDEL.0

LOCKSP

BGPOS

HINC0 [7:0]

HINC1 [7:0]

HINC2 [7:0]

HINC3 [7:0]

HINC4 [7:0]

V656DEL

AFPROC

CLKOUTSEL272

CLKOUTINV

HINC4 [8]

HPANON

HINC3 [8]

HINC2 [8]

HINC1 [8]

HINC0 [8]

HSCPOSC [7:0]

CDELHPOS

HSEG1

CLKOUTSEL

HSCPOSC [11:8]

HSEG2

HSEG3

HSEG4

FIOFFOFF

CHRMSIG656

FIELDBINV

VDEL_EN

HSEG2 [10:8]

HSEG4 [10:8]

HSEG1 [10:8]

HSEG3 [10:8]

DAC Control

56h

57h

58h

59h

5Ah

SHIFTUV

CHROMSIGN

PKLY

DPOUT656

CHROMAMP

PKLU

PKLV

CVBS Front-end

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

65h

66h

CONS

CON

COLON

UVCOR

CRCB

ACCFIX

ACCFRZ

NOTCHOFF

SECNTCH

VDETIFS

PWTHD

SDR

CLRANGE

CHRF

LMOFST

COMB

CKILL

CSTAND

CKILLS

VPOL

LPPOST

YCDEL

HUE

NTSCREF

PALREF

SLLTHD

SCADJ

48

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–7: I C register overview, continued

Sub

add

Data Byte

D3

(Hex)

D7

AGCMD

D6

D5

D4

D2

D1

D0

67h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

70h

71h

72h

73h

74h

75h

76h

77h

78h

79h

7Ah

7Bh

7Ch

7Dh

7Eh

7Fh

80h

81h

82h

AGCADJ1

AGCADJ2

AGCRES

CLMPHIGH

CVBOSEL1

FLINE

AGCFRZE

CLMPLOW

FLDINV

HPOL0

HINP

CLPSTGY

FHDET

YCSEL

CLMPD1

CLMPD2

HPOL1

DISCHCH

NOSIGB

CLMPST1

CLMPST2

PLLTC

CVBSEL2

CVBOSEL2

FHFRRN

REFTRIMEN

VSHIFT

CVBSEL1

CVBOSEL3

SATNR

VINP

NSRED

LPCDEL

PALIDL1

VTHRL50

VTHRH50

PALIDL0

REFTRIM

REFTRIMCV

SLLTHDVP

SCMIDL

REFTRIMRGB

THRSEL

CLMPST1S

CLMPST2S

ACCLIM

IFCOMP

CLMPD2S

CLMPD1S

OSCPD

EIA770

SHAPERDIS

ISHFT

TSTSHAPERI

NSRED2

FREQSEL1

FREQSEL0

VFLYWHL

BELLFIR

BELLIIR

FLNSTRD

SECACC

PORCNCL

ADLCK

ENLIM

VLP

SECDIV

SECINC1

SECINC2

CPLLRES

SCMREL

TRAPBLU

NTCHSEL

ADLCKSEL

DISALLRES

SECACCL

TRAPRED

PALINC2

ADLCKCC

IFCOMSTR

VFLYWHLMD

PALIDL2

SYNFTHD

CPLLOF

DEEMPSTD

PALINC1

Read Register

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

FBLACTIVE

NOISEME

LBSTATUS

PFBL

PG

PB

PR

NMSTATUS

STABLL

SMMIRROR

PALID

DETHPOL

LNSTDRD

LPFLD

DETVPOL

INT

STDET

SCDEV

SCOUTEN

CKSTAT

NRPIXEL

Micronas

Aug. 16, 2004; 6251-552-1DS

49

VSP 94x2A

DATA SHEET

2

Table 3–7: I C register overview, continued

Sub

add

(Hex)

Data Byte

D3

D7

D6

D5

D4

D2

D1

D0

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

96h

97h

98h

99h

PP

POR

VFLYMD

STAB

PALDET

REFTRIMRD

REFTRIMCVRD

REFTRIMRGBRD

SLS

VERSION

AM50O

MINV

AM60O

AGCADJCV

VLENGTH

PWADJCNT

V40STAT

V36BSTAT

V20STAT

A0h

A1h

A2h

A3h

A4h

KPNL[3:0]

KINL[3:0]

LIMIP

KPL[3:0]

KIL[3:0]

LIMII

KPNL[4]

KPL[4]

KINL[4]

KIL[4]

LIMLR

CVBS Front-end

B0h

B1h

B2h

B3h

B4h

B5h

AGCTHD

SLLTHDV

FEMAG

AMSTD60

MVP

AMSTD50

SDB

MVPG

VDETITC

VTHRL60

VTHRH60

DEEMPIIR

DEEMPFIR

ITU Input

B7h

B8h

B9h

BAh

NAPPLIPI

ALPFIPI

APPLIPI [7:0]

APPLIPI[8]

NALPFIPI

LL-PLL

BCh

BDh

BEh

FRINC[18:11]

FRINC[10:3]

FRINC[2:0]

C0h

C1h

HSPPL

FOFFST

VSLPF

50

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–7: I C register overview, continued

Sub

add

(Hex)

Data Byte

D3

D7

D6

D5

D4

D2

D1

D0

D0h

D1h

D2h

VBLANDEL [9:8]

VBLANDEL [7:0]

VBLANLEN [7:0]

VBLANPOL

FSWFTL

VBLANLEN [9:8]

Letterbox Detection

E0h

E1h

E2h

E3h

E4h

E5h

E6h

E7h

E8h

E9h

EAh

EBh

ECh

EDh

EEh

EFh

LBGRADDET

LBVWENDLO

LBHWEND

LBHIWHITE

LBHISTBLA

LBMASLA

LBFS

LBVWSTLO

LBVWENDUP

LBHWST

LBVISUON

LBVWSTUP

LBNGFEN

LBSTABILITY

LBSUB1

LB43SENS

LBSUB0

LBTHDNBNG

LBHSDEL

LBGRADRST

LBTHDNBNHA

LBACTIVITY

LBGFBDEL

LBGSDEL

LBASDEL

Letterbox Read

F0h

F1h

F2h

F3h

F4h

F5h

LBSLAA

LBELAA

LBFORMAT

GRADELAA[8]

GRADELAA[7:0]

LBSUBTITLE

GRADSLAA

LBTOPTITLE

GRADISSTABLE

TOPTITLE

SUBTITLE

UPBLACK

NOGRADFOUND

SWITCHTO43

UPWHITE

LPBLACK

REV

LPWHITE

F6h

FEh

VERSION

SLS

take-over-indication (immediately)

FFh

take-over-indication (after V-pulse)

Micronas

Aug. 16, 2004; 6251-552-1DS

51

VSP 94x2A

DATA SHEET

2

3.1.4. I C Bus Command Description

Underlined values are initialized at power-on. Some

bits are intended to not be user adjustable. Mandatory

and recommended settings are available from Micro-

2

nas in a separate document (Application Note: I C

Settings).

2

Table 3–8: I C bus command description

Bit

Subaddress 00h

D7-D0 APPLIP8-1

Name

Description

Active Pixel Per Line

[FP-PRE]

Number of pixels to be stored in memory

Granularity: 2 pixel

‘000000000’: 0 pixel

‘101010101’: 682 pixel

‘111111111’: 1022 pixel

Subaddress 01h

D7

APPLIP0

Belongs to 00h

[FP-PRE]

D6-D0

HSCPRESC11-5

[FP-PRE]

Control Signal For HSCALE In Horizontal Pre-scaler

‘000000000000’: subsampling factor by scaler stage is 1

‘100000000000’: subsampling factor is 1.5 (720 pixel)

‘100101010110’: subsampling factor is 1.583 (682 pixel)

‘111111111111’: subsampling factor is 2 (540 pixel)

Subaddress 02h

D7-D3

HSCPRESC4-0

Belongs to 01h

[FP-PRE]

D2-D0

NAPPLIP9-7

[FP-PRE]

Not Active Pixel Per Line

Granularity: 2 clock cycles (~50 ns)

‘0000000000’: 0 clock cycles

‘0001001000’: 144 clock cycles (~7.2 µs)

‘1111111111’: 2046 clock cycles (~51 µs)

Subaddress 03h

D7

VDELF_EN

[FP-PRE]

Vertical pulse delay frontend

‘0’: no delay

‘1’: delayed

D6-D0

NAPPLIP6-0

[FP-PRE]

Belongs to 02h

Subaddress 04h

D7-D0 NALPFIP7-0

Not Active Lines Per Field (Input Processing)

‘000000000’: 0 lines

[FP-PRE]

‘000010110’: 22 lines

‘111111111’: 511 lines

52

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 05h

D7

APENSEL

Active Pixel Enable Select

[FP-PRE]

0: count clock cycles (recommended for CVBS/RGB input)

1: count active pixels (recommended for ITU656 input)

D6

NALPFIP8

[FP-PRE]

Belongs to 04h

D5-D4

ALPFIP9-8

[FP-PRE]

Active Lines Per Field

‘0000000000’: no active line

‘0100100000’: 288 active lines

‘1111111111’: 1023 active lines

D3-D0

HDCPRESC

Horizontal Pre-Scaler Decimates By

‘0000’: 1

‘0001’: 2

‘0010’: 3

‘0011’: 4

‘0100’: 6

‘0101’: 8

‘0110’: 12

‘0111’: 16

‘1000’: 24

‘1001’: 32

Subaddress 06h

D7-D0

ALPFIP7-0

Belongs to 05h

Subaddress 07h

D7-D0

BLANDEL

Blanking signal delay

Delay in pixels from hsync to active edge of blank signal:

Blank_start=4*BLANDEL

‘00000000’: no delay

‘00000001’: 4 pixel delay

‘11111111’: 1020 pixel delay

Subaddress 08h

D7-D0

BLANLEN

Blanking signal length

Length in pixels from start of active blank signal:

Blank_length=4*BLANLEN

‘00000000’: no pixel

‘11110000’: 960 pixel

‘11111111’: 1020 pixel length

Micronas

Aug. 16, 2004; 6251-552-1DS

53

VSP 94x2A

DATA SHEET

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 09h

D6

WRCTRLDIS

[FP-MC]

Memory Write Control Circuit Disable

‘0’: enabled

‘1’: disabled

D5-D4

HAAPRESC

[FP-MC]

Horizontal Anti Alias Filter

‘00’: filter bypassed

‘01’: force characteristic weak

‘10’: force characteristic strong

‘11’: automatic characteristic (weak or strong)

Note: For normal CVBS/RGB full-screen, filter should be set to weak or auto-

matic characteristic. For ITU656 full-screen input, filter should be bypassed.

Strong characteristic is for split-screen and PiP only.

D3-D0

MLL

Minimum Line Length

[FP-MC]

effective number of clock periods: 600 + MLL*128

1110: corresponds to 2392 clock periods

Subaddress 0Ah

D7-D0 BRTADJ

Brightness Adjustment of RGB/YUV input

‘10000000’: −128 LSB (darkest picture)

‘00000000’: 0

[FP-RGB]

‘01111111’: +127 LSB (brightest picture)

Subaddress 0Bh

D7

DECTWO

Decimation by 2

[FP-RGB]

decimation of RGB/YUV signal before soft-mix

‘0’: no decimation

‘1’: decimation by 2

D6

CHRSF

[FP-RGB]

Additional Chroma subsampling filter

‘0’: disabled

‘1’: enabled

D5-D0

CONADJ

[FP-RGB]

Contrast Adjustment of RGB/YUV input

‘000000’: 0

‘000001’: 1/32

‘100000’: 1

‘111111’: 63/32

Subaddress 0Ch

D7

ADCSEL

[FP-RGB]

Select ADC for sync signal conversion

‘0’: use ADC_G

‘1’: use ADC_FBL

D6

AABYP

[FP-RGB]

Bypass RGB/YUV Antialiasfilter

‘0’: use filter

‘1’: bypass

D5-D0

FBLOFFST

[FP-RGB]

Fast Blank Offset Correction

‘000000’: 0 LSB offset

‘111111’: 63 LSB offset

54

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 0Dh

D7-D6

D5-D3

CLMPVRB

[FP-RGB]

Clamping Value Red and Blue ADC

‘00’: 16 (B/R signal without sync)

‘01’: 80 (B/R signal with sync)

‘10’: 128 (U/V signal)

‘11’: (reserved)

FBLDEL

[FP-RGB]

Fast Blank Delay vs. RGB/YUV Input

granularity: 25 ns

‘000’: −50 ns delay

‘010’: no delay

‘110’: +100 ns delay

‘111’: (reserved)

D2-D1

D0

MIXOP

[FP-RGB]

Mixing Configuration

‘00’: enable Soft-Mix

‘01’: only RGB path visible

‘10’: only CVBS path visible

‘11’: (reserved)

FBLCONF

[FP-RGB]

Configuration of FBLACTIVE signal

‘0’: react after one clock (25 ns) active FBL input

‘1’: react after 5 clock (125 ns) active FBL input

Subaddress 0Eh

D7

YUVSEL

[FP-RGB]

YUV or RGB Input Selection

‘0’: YUV expected

‘1’: RGB expected

D6

SMOP

[FP-RGB]

Softmix Operation Mode

‘0’: dynamic

‘1’: static

D5

SKEWSEL

[FP-RGB]

SKEW Correction for RGB/YUV Channel

‘0’: SKEW correction enabled

‘1’: SKEW correction disabled (for PiP3, PiP4 only)

D4-D2

RBOFST

[FP-RGB]

Clamping Correction for R/B ADC

‘000’: 0 (R/B, no pedestal offset visible)

‘001’: 16

‘010’: 64 (R/B with sync, no pedestal offset visible)

‘011’: 80

‘100’: 127 (UV negative pedestal offset)

‘101’: 128 (UV)

‘110’: 129 (UV positive pedestal offset)

‘111’: (reserved)

D1-D0

GOFST

[FP-RGB]

Clamping correction for G ADC

‘00’: 0 (G/Y, no pedestal offset visible)

‘01’: 16

‘10’: 64 (G/Y with sync, no pedestal offset visible)

‘11’: 80

Micronas

Aug. 16, 2004; 6251-552-1DS

55

VSP 94x2A

DATA SHEET

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 0Fh

D7

RGBSEL

Input selection

[FP-RGB]

‘0’: use RGB/YUV input1

‘1’: use RGB/YUV input2

D6-D0

MIXGAIN

[FP-RGB]

Gain of Fast Blank Signal

‘1000000’: −64

‘0000000’: 0

‘0111111’: +63

Note: For proper operation in dynamic softmix mode, absolute value of MIX-

GAIN must be bigger than 2 (e.g. 3)

Subaddress 10h

D7

CLMPVG

Clamping Value G ADC

[FP-RGB]

‘0’: 16

‘1’: 80

D6

DCLMPF

[FP-RGB]

Clamping Fast Blank input

‘0’: enable clamping

‘1’: disable clamping (DC coupling)

D5-D0

USATADJ

[FP-RGB]

U Saturation Adjustment

‘000000’: 0

‘000001’: 1/32

‘100000’: 1

‘111111’: 63/32

Subaddress 11h

D7-D6

STANDBY

Standby Mode

[FP-RGB]

‘00’: all analog cores active

‘01’: RGB/FBL ADCs in Stand-By mode

‘10’: RGB/FBL and CVBS ADCs and DACs in Stand-By mode

‘11’: DACs in Stand-By mode

D5-D0

VSATADJ

[FP-RGB]

V Saturation Adjustment

‘000000’: 0

‘000001’: 1/32

‘100000’: 1

‘111111’: 63/32

Subaddress 12h

D7

Y2RGB

[FP-RGB]

Y to RGB (for YUV mode)

0: use Y from green ADC

1: use Y from CVBS ADC

D5-D0

YFDEL

[FP-RGB]

Y/FBL Delay Adjustment

Granularity: 50 ns

‘000000’: no delay

‘111111’: 3.15 µs

56

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Subaddress 13h

D5-D0 UVDEL

Name

Description

UV Delay Adjustment

Granularity: 50 ns

‘000000’: no delay

‘111111’: 3.15 µs

[FP-RGB]

Subaddress 14h

D5-D0 AGCADJR

Conversion Range Adjustment Red

‘000000’: 0.5 V input signal

[FP-RGB]

‘111111’: 1.5 V input signal

Subaddress 15h

D5-D0 AGCADJG

Conversion Range Adjustment Green

‘000000’: 0.5 V input signal

[FP-RGB]

‘111111’: 1.5 V input signal

Subaddress 16h

D7

ITUPRTSEL

[FP-RGB]

ITU port selection

0: first input (656io)

1: second input (i656i)

D6

CLKF2PAD

[FP-RGB]

Frontend clock is given to pin 74

‘0’ pin 74 is used as h-input for ITU656

‘1’: CLKF20 (20.25 MHz) is given to pin 74

D5-D0

AGCADJB

[FP-RGB]

Conversion Range Adjustment Blue

‘000000’: 0.5 V input signal

‘111111’: 1.5 V input signal

Subaddress 17h

D7-D6

NAPIPPHI

CbYCrY-phase shift

[FP-RGB]

‘0’: no phase shift

D5-D0

AGCADJF

[FP-RGB]

Conversion Range Adjustment Fast Blank

‘000000’: 0.5 V input signal

‘111111’: 1.5 V input signal

Micronas

Aug. 16, 2004; 6251-552-1DS

57

VSP 94x2A

DATA SHEET

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 18h

D7-D6

IMODE

Input format

[FP-RGB]

‘00’: full ITU mode (automatic)

‘01’: full ITU mode (manual)

‘10’: ITU656 only data, H/V-sync according PAL/NTSC

‘11’: ITU656 only data, H/V-sync according ITU656

D5

D4

D3

D2

D1

D0

VSIGNAL

[FP-RGB]

Input signal

‘0’: interlaced

‘1’: non interlaced

CFORMAT

[FP-RGB]

Chrominance data format

‘0’: unsigned

‘1’: 2s complement

F_POL

[FP-RGB]

Field polarity

‘0’: Field A=0, Field B=1

‘1’: Field A=1, Field B=0

H_POL

[FP-RGB]

H656 polarity

‘0’: H656 active low

‘1’: H656 active high

V_POL

[FP-RGB]

V656 polarity

‘0’: V656 active low

‘1’: V656 active high

EN_656

ITU656-Input Interface

[FP-RGB]

‘0’: analog input enabled (CVBS/RGB)

‘1’: ITUI enabled

Subaddress 19h

D7-D0 NMLINE7-0

Line For Noise Measurement

[FP-TNR]

0 : line 2

d

1 : line 3

d

311 : line 1 (PAL)

d

261 : line 1 (NTSC)

d

lines 3-260 are not standard dependent

58

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 1Ah

D7-D6

D5-D4

NMPOS

[FP-TNR]

Noise Measurement analyze window position

00: 6.3 µs

01: 12.6 µs

10: 18.9 µs

11: 23.7 µs

NMSENSE

[FP-TNR]

Noise Measurement sensitivity

00: *1

01: *2

10: *4

11: *8

D3

D2

NMLINE8

[FP-TNR]

Belongs to 19h

TNRABS

[FP-TNR]

Motion Detector Works on Absolute Values:

‘0’: absolute values not calculated

‘1’: absolute values calculated

D1

D0

NRON

[FP-TNR]

Temporal Noise Reduction

‘0’: disabled

‘1’: enabled

TNRSEL

[FP-TNR]

Chrominance Motion Values From:

‘0’: luminance motion detector

‘1’: separate chrominance motion detector

Subaddress 1Bh

D7-D4

TNRS0Y

TNR Curve Characteristic of Luma Segment 0

[FP-TNR]

default value: 0001

D3-D0

TNRS1Y

[FP-TNR]

TNR Curve Characteristic of Luma Segment 1

default value: 1111

Subaddress 1Ch

D7-D4

TNRS2Y

TNR Curve Characteristic of Luma Segment 2

[FP-TNR]

default value: 1111

D3-D0

TNRS3Y

[FP-TNR]

TNR Curve Characteristic of Luma Segment 3

default value: 0100

Subaddress 1Dh

D7-D4

TNRS4Y

TNR Curve Characteristic of Luma Segment 4

[FP-TNR]

default value: 0100

D3-D0

TNRS5Y

[FP-TNR]

TNR Curve Characteristic of Luma Segment 5

default value: 0100

Subaddress 1Eh

D7-D4

TNRS6Y

TNR Curve Characteristic of Luma Segment 6

[FP-TNR]

default value: 0000

D3-D0

TNRS7Y

[FP-TNR]

TNR Curve Characteristic of Luma Segment 7

default value: 0000

Micronas

Aug. 16, 2004; 6251-552-1DS

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 1Fh

D7-D4

D3-D0

TNRSSY

[FP-TNR]

TNR Start Value of Luma LUT

default value: 1111

TNRSSC

[FP-TNR]

TNR Start Value of Chroma LUT

default value: 1111

Subaddress 20h

D7-D4

TNRS0C

TNR Curve Characteristic of Chroma Segment 0

[FP-TNR]

default value: 0001

D3-D0

TNRS1C

[FP-TNR]

TNR Curve Characteristic of Chroma Segment 1

default value: 1111

Subaddress 21h

D7-D4

TNRS2C

TNR Curve Characteristic of Chroma Segment 2

[FP-TNR]

default value: 1111

D3-D0

TNRS3C

[FP-TNR]

TNR Curve Characteristic of Chroma Segment 3

default value: 0100

Subaddress 22h

D7-D4

TNRS4C

TNR Curve Characteristic of Chroma Segment 4

[FP-TNR]

default value: 0100

D3-D0

TNRS5C

[FP-TNR]

TNR Curve Characteristic of Chroma Segment 5

default value: 0100

Subaddress 23h

D7-D4

TNRS6C

TNR Curve Characteristic of Chroma Segment 6

[FP-TNR]

default value: 0000

D3-D0

TNRS7C

[FP-TNR]

TNR Curve Characteristic of Chroma Segment 7

default value: 0000

Subaddress 24h

D7-D4

TNRCLY

[FP-TNR]

TNR Luminance Classification

‘0000’: strong noise reduction

‘1111’: slight noise reduction

D3-D0

TNRCLC

[FP-TNR]

TNR Chrominance Classification

‘0000’: strong noise reduction

‘1111’: slight noise reduction

Subaddress 25h

D7-D0 IICINCR18-11

Set HDTO frequency

[PP]

Granularity=103 Hz

33981 (minimum: nominal pixel clock= 3.5 MHz)

d

349525 (nominal pixel clock= 36 MHz)

d

388362 (maximum: nominal pixel clock= 40 MHz)

d

60

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2

Table 3–8: I C bus command description, continued

Bit

Subaddress 26h

D7-D0 IICINCR10-3

Name

Description

Belongs to 25h

[PP]

Subaddress 27h

D3

DISRES

[PP]

Reset of LL-PLL watchdog

‘0’: reset disabled

‘1’: reset enabled

D2-D0

IICINCR2-0

[PP]

Belongs to 25h

Subaddress 28h

D0

HRES

[PP]

Reset of LL-HPLL

‘0’: no reset

‘1’: reset

Note: reset automatically when written

Subaddress 29h

D7-D4

HSWIN

[PP]

Width of Noise Suppression Window of LL-HPLL

‘0000’: ±28 µs

‘0001’: ±24 µs

‘0010’: ±20 µs

‘0011’: ±16 µs

‘0100’: ±12 µs

‘0101’: ±8 µs

‘0110’: ±4 µs

‘0111’: dynamic windowing.

‘1000’: ±30 µs

‘1001’: ±27 µs

‘1010’: ±26 µs

‘1011’: ±22 µs

‘1100’: ±18 µs

‘1101’: ±14 µs

‘1110’: ±10 µs

‘1111’: ±6 µs

D3

D2

D1

D0

KD2

[PP]

Phase Detector Steepness

‘0’: steepness for normal TV operation mode

‘1’: steepness for operations where PPLIP is less than 288

d

HINCREXT

[PP]

HDTO testmode

‘0’: normal mode

‘1’: line-locked-clocks derived from frontend line-length

LMOD

[PP]

Selects line locked mode

‘0’: line locked-clocks derived from HPLL

‘1’: line-locked-clocks derived from frontend line-length

FMOD

[PP]

Selects freerun mode

‘0’: freerun-clocks derived from crystal

‘1’: freerun-clocks derived from HDTO

Adjustable frequency is only possible when set to ‘1’. When set to ‘0’, Backend

clock is always 36 MHz (9432/42: 18 MHz)

Micronas

Aug. 16, 2004; 6251-552-1DS

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 2Ah

D7-D6

D5-D4

D3-D0

KOIWID

[PP]

Window-Width of coincidence detector

‘00’: ±32 pixel (= ±0.9 µs for TV application)

‘01’: ±64 pixel (= ±1.8 µs for TV application)

‘10’: ±128 pixel (= ±3.6 µµs for TV application)

‘11’: ±256 pixel (= ±7.2 µs for TV application)

KOIH

[PP]

Hysteresis of coincidence detector

‘00’: 0 lines

‘01’: 8 lines

‘10’: 16 lines

‘11’: 32 lines

HTESTW

[PP]

Test bits for HPLL

00: default

Subaddress 2Bh

D7-D0 PPLIP9-2

Pixel per Line Input (Input-Processing)

[PP]

Granularity=4 pixel

‘175 ’: 700 (minimum)

d

‘576 ’: 2304

d

‘963 ’: 3852 (maximum)

d

Subaddress 2Ch

D7

SETSTABLL

[PP]

Stability Signal of LL_HPLL

‘0’: STABLL is generated by the HPLL

‘1’: STABLL is forced to 1

D6

FRFIX

[PP]

Freerunning clocks

‘0’: from fixed clock divider

‘1’: from freerunning DTO (adjustable clocks)

D4

LIMEN

[PP]

Limiter enable

‘0’: A32 behavior for LIMIP and LIMII

‘1’: normal LIMII and LIMIP characteristic

D3

FKOI

[PP]

Force Coincidence Bit

‘0’: coincidence bit dynamically changed

‘1’: coincidence bit forced to 1

D2

FKOIHYS

[PP]

Force coincidence hysteresis bit

‘0’: coincidence hysteresis bit dynamically changed

‘1’: coincidence hysteresis bit forced to 1

D1-D0

PPLIP1-0

[PP]

Belongs to 2Bh

Subaddress 2Dh

D7-D4

FION

[PP]

Increment Freeze before V-sync

‘0’: no freeze

‘15’: freeze starts 15 lines before V-sync

D0

LNL

[PP]

Dynamic Time Constant Control

‘0’: linear mode

‘1’: non linear mode

62

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 2Eh

D7-D6

CLKT

[PP]

Switch clkf20 and clkf40 to pads cvbs1 or bin2 (test only)

‘00’: no clock

‘01’: cvbs1 is output of clkf40

‘10’: bin2 is output of clkf20

‘11’: cvbs1 is output of clkf40 and bin2 is output of clkf20

D5

HWID

[PP]

Minimum width of H-sync

‘0’: 60*T

‘1’: 15*T

clkllf36

D4

HDTOTEST

[PP]

Test-bit for HPLL

‘0’: normal mode

‘1’: test mode

D3-D0

FILE

[PP]

Increment Freeze duration

‘0’: no freeze

‘15’: increment is frozen for 15 lines

Subaddress 2F

D1

LPFIPMD

[BP-DP]

Lines per field method

0: backend

1: frontend

D0

VINMTHD

[BP-DP]

Vertical ODC line counting

0: field delay

1: frame delay

Subaddress 30h

D7-D6

YCOR

[BP-DP]

Luminance Coring

‘00’: off

‘01’: 2

‘10’: 4

‘11’: 8

D5

CLKOUTON

[BP-DP]

Clkout Pad:

‘0’: off (tristate)

‘1’: on

D4-D2

THRESHC

[BP-DP]

Slope of DCTI function

‘000’: 255 (DCTI off)

‘001’: 2

‘010’: 3

‘011’: 4

‘100’: 6

‘101’: 8

‘110’: 10

‘111’: 12

D1-D0

ASCENTCTI

[BP-DP]

Gain of DCTI function

‘00’: 1/4

‘01’: 1/2

‘10’: 1

‘11’: 2

Micronas

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 31h

D7-D4

HCOF

Peaking: High-Pass Filter Adjustments

[BP-DP]

‘0000’: 0

‘0001’: 1/4

...

‘0100’: 1

...

‘1100’: 12/4

‘1101’: 14/4

‘1110’: 16/4

‘1111’: 20/4

D3-D0

BCOF

Peaking: Band-Pass Filter Adjustments

[BP-DP]

‘0000’: 0

‘0001’: 1/4

...

‘0100’: 1

...

‘1100’: 12/4

‘1101’: 14/4

‘1110’: 16/4

‘1111’: 20/4

Subaddress 32h

D7-D6

AUTOFRRN

Automatic freerun

[BP-DP]

when sync-separartion not stable

‘00’: disabled (keep H/V locked, if selected)

‘01’: use vertical freerun

‘10’: use horizontal freerun

‘11’: use horizontal and vertical freerun

D5-D4

ALPFOP9-8

[BP-DP]

Active Lines Per Field Output

‘0000000000’: 0 (minimum)

‘0100100000’: 288 (default)

‘1111111111’: 1023 (maximum)

D3

FINEDEL

[BP-DP]

Luminance Fine Delay output

‘0’: no delay

‘1’: +1 CLKB72 (13.9 ns for TV signal)

D2-D0

COARSEDEL

[BP-DP]

Luminance Coarse Delay output

Granularity: 1 CLKB36 (27.8 ns for TV signal)

‘000’: −4 CLKB36

‘100’: no delay

‘111’: +3 CLKB36

Subaddress 33h

D7-D0 ALPFOP7-0

Belongs to 32h

[BP-PM]

Subaddress 34h

D7-D0 BORDPOSV

Borderposition Vertical

[BP-PM]

Granularity: 2 lines

‘00000000’: no border

‘11111111’: border at 512 lines at top and bottom

64

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VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Subaddress 35h

D7-D0 BORDPOSH7-0

Name

Description

Borderposition Horizontal

Granularity: 2 pixel

[BP-PM]

‘0000000000’: no border

‘1111111111’: border at 2048 pixel on left and right

Subaddress 36h

D7

BLANPOL

[BP-PM]

Blanking signal polarity

‘0’: active high

‘1’: active low

D6

BLANEN

[BP-PM]

Blanking signal enable

‘0’: disabled (pin 8 can be used as 656vin)

‘1’: enabled

D5-D4

D3-D0

BORDPOSH 9-8

[BP-PM]

Belongs to 35h

YBORDER

[BP-PM]

Luminance Value for Border

‘0000’: sub black

‘0001’: black

‘1111’: white

Subaddress 37h

D7-D4

UBORDER

Chrominance (U) Value for Border

[BP-PM]

‘1000’:

‘0000’: ‘no color’ U

‘0111’:

D3-D0

VBORDER

[BP-PM]

Chrominance (V) Value for Border

‘1000’:

‘0000’: ‘no color’ V

‘0111’:

Subaddress 38h

D7-D0

HORWIDTH7-0

[BP-PM]

Horizontal Picture Width

Granularity: 2 pixel

‘00000000000’: no display

‘00111100000’: 960 pixel

‘11111111111’: 4094 pixel

Note: Should be set equal to APPLOP (3Dh)

Micronas

Aug. 16, 2004; 6251-552-1DS

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 39h

D7-D6

WINDVSP

[BP-PM]

Vertical Windowing: Speed

‘00’: slow

‘01’: medium

‘10’: fast

‘11’: very fast

D5

WINDVST

[BP-PM]

Vertical Windowing: Start

‘0’: window is closed

‘1’: window is open

D4

WINDVDR

[BP-PM]

Vertical Windowing: Direction

‘0’: open the vertical window

‘1’: close the vertical window

D3

WINDVON

[BP-PM]

Vertical Windowing: Enable

‘0’: off

‘1’: on

D2-D0

HORWIDTH

10-8

Belongs to 38h

[BP-PM]

Subaddress 3Ah

D7-D0 HORPOS7-0

Horizontal Position inside active picture area

Granularity: 2 pixel

[BP-PM]

‘00000000000’: most left display position

‘11111111111’: most right display position

Subaddress 3Bh

D7-D6

WINDHSP

[BP-PM]

Horizontal Windowing: Speed

‘00’: slow

‘01’: medium

‘10’: fast

‘11’: very fast

D5

WINDHST

[BP-PM]

Horizontal Windowing: Start

‘0’: window is closed

‘1’: window is open

D4

WINDHDR

[BP-PM]

Horizontal Windowing: Direction

‘0’: open the horizontal window

‘1’: close the horizontal window

D3

WINDHON

[BP-PM]

Horizontal Windowing: Enable

‘0’: off

‘1’: on

D2-D0

HORPOS10-8

[BP-PM]

Belongs to 3Ah

66

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 3Ch

D7

NOSYNC

[BP-ODC]

No horizontal synchronization

‘0’: horizontal synchronization

‘1’: no horizontal synchronization

D6-D4

PPLOFF

Synchronization offset

[BP-ODC]

(for switching from hor. freerun mode to locked mode)

Granularity: 4 pixel

‘000’: 0 (disabled)

‘010’: 8

‘111’: 28

D3-D0

LPFOPFF

[BP-ODC]

Lines per field offset:

(for switching from vertical freerun mode to locked mode)

Granularity: 2 lines

‘0000’: 0 (disabled)

‘0110’:12

‘1111’: 31

Subaddress 3Dh

D7

CHRSHFT

[BP-O/M]

Chrominance Shift

shifts the chrominance signal

‘0’: no shift

‘1’: one line upward

D6-D0

APPLOP

[BP-O/M]

Active Pixel Per Line Output:

Granularity: 16 pixel

‘0000000’: 0 pixel

‘0111100’: 960 pixel

‘1111111’: 2032 pixel

Subaddress 3Eh

D7-D0

HOUTDEL7-0

[BP-ODC]

H Sync output Delay:

Granularity: 4 pixel

‘0000000000’: no delay

‘0000000001’: 4 pixel delay

‘1111111111’: 4092 pixel delay

Micronas

Aug. 16, 2004; 6251-552-1DS

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Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 3Fh

D7-D6

NAPPLOP9-8

[BP-O/M]

Not Active Pixel Per Line Output:

Granularity: 4 pixel

‘0000000100’: 16 not active pixel

‘1111111111’: 4092 not active pixel

D5

PDGSR

[BP-O/M]

Switch for Vsync transfer algorithm:

‘0’: Vsync transfer algorithm is enabled

‘1’: Vsync transfer algorithm is disabled

D4

FREEZE

[BP-O/M]

Freeze picture

‘0’: live

‘1’: frozen (data writing disabled)

D3-D2

STOPMODE

[BP-O/M]

Operation mode for scan rate conversion:

‘00’: AABB (Raster ααββ)

‘01’: AAAA (Raster αααα)

‘10’: AAAA (Raster αβαβ)

‘11’: BBBB (Raster ββββ)

D1-D0

HOUTDEL9-8

[BP-O/M]

Belongs to 3Eh

Belongs to 3Fh

Subaddress 40h

D7-D0 NAPPLOP7-0

[BP-ODC]

68

Aug. 16, 2004; 6251-552-1DS

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 41h

D7-D6

PPLOP9-8

[BP-O/M]

Pixel Per Line Output:

Granularity:4

‘0000000000’: 0 pixel

‘0100100000’: 1152 pixel

‘1111111111’: 4092 pixel

D5

D4

D3

D2

D1

D0

REFRPER

[BP-O/M]

Refresh period of the memory

‘0’: ~5 ms

‘1’: ~2,5 ms

REFRON

[BP-O/M]

Refresh on

‘0’: no memory refresh

‘1’: memory refresh active

HOUTPOL

[BP-O/M]

HOUT polarity:

‘0’: high active

‘1’: low active

VOUTPOL

[BP-O/M]

VOUT polarity:

‘0’: high active

‘1’: low active

HOUTFR

[BP-O/M]

HOUT freerun

‘0’: locked mode

‘1’: freerun mode

VOUTFR

[BP-O/M]

VOUT freerun

‘0’: locked mode

‘1’: freerun mode

Subaddress 42h

D7-D0 PPLOP7-0

Belongs to 41h

[BP-O/M]

Subaddress 43h

D7-D0 LPFOP7-0

Lines Per Field Output:

Only used for freerun mode

Granularity: 2 lines

[BP-ODC]

‘000000000’: no lines

‘010011100’: 312 lines

‘111111111:’ 1022 lines

Subaddress 44h

D7-D0

OPDEL7-0

[BP-ODC]

V delay for output operation:

‘000000000’: no delay

‘010101010’: 170 lines

‘111111111’: 511 lines

Micronas

Aug. 16, 2004; 6251-552-1DS

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 45h

D7-D6

D5-D4

D3

BORDERV

[BP-O/M]

Border V

‘00’: both borders are displayed

‘01’: only lower border is displayed

‘10’: only upper border is displayed

‘11’: (reserved)

BORDERH

[BP-O/M]

Border H

‘00’: both borders are displayed

‘01’: only right border is displayed

‘10’: only left border is displayed

‘11’: (reserved)

RDCTRLDIS

[BP-O/M]

Memory read control circuit disable

‘0’: enabled

‘1’: disabled

D2

D1

LPFOP8

[BP-O/M]

Belongs to 43h

NALPFOP8

[BP-O/M]

Not Active Lines Output

NALPFOP-1 lines are not active lines.

‘000000001’: all lines active

‘000011001’: 24 lines not active

‘111111111’: 510 lines not active

D0

OPDEL8

[BP-O/M]

Belongs to 44h

Belongs to 45h

Subaddress 46h

D7-D0 NALPFOP7-0

[BP-ODC]

Subaddress 47h

D6-D5

D4-D3

PALDEL

[CP-CD]

PAL/NTSC delay vs. SECAM (chrominance)

‘00’: PAL/NTSC most left

‘11’: PAL/NTSC most right

LOCKSP

[CP-CD]

Duration Of Chroma PLL Search

‘00’: 25 fields

‘01’: 20 fields

‘10’: 17 fields

‘11’: 15 fields

D2-D0

BGPOS

[CP-CD]

Burstgate Delay (SECAM only)

Granularity: 200 ns

‘000’: most left (−400 ns)

‘011’: 200 s delay

‘111’: most right (+1 us)

Subaddress 48h

D7-D0 HINC0_7-0

Horizontal Post-Scaler Increment 0

‘100000000’: −32 pixel

[BP-POS]

‘000000000’: 0 pixel

‘011111111’: 31.875 pixel

70

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2

Table 3–8: I C bus command description, continued

Bit

Subaddress 49h

D7-D0 HINC1_7-0

Name

Description

Horizontal Post-Scaler Increment 1

‘100000000’: −32 pixel

[BP-POS]

‘000000000’: 0 pixel

‘011111111’: 31.875 pixel

Subaddress 4Ah

D7-D0 HINC2_7-0

Horizontal Post-Scaler Increment 2

‘100000000’: −32 pixel

[BP-POS]

‘000000000’: 0 pixel

‘011111111’: 31.875 pixel

Subaddress 4Bh

D7-D0 HINC3_7-0

Horizontal Post-Scaler Increment 3

‘100000000’: −32 pixel

[BP-POS]

‘000000000’: 0 pixel

‘011111111’: 31.875 pixel

Subaddress 4Ch

D7-D0 HINC4_7-0

Horizontal Post-Scaler Increment 4

‘100000000’: -32 pixel

[BP-POS]

‘000000000’: 0 pixel

‘011111111’: 31.875 pixel

Subaddress 4Dh

D7

V656DEL

V656 delay

[BP-POS]

0: identical delay for modification

1: field 0 is one line shorter

Note: has only effect when AFPROC=1

D6

D5

AFPROC

[BP-POS]

Active Field Processing for 656V generation

0: inverted active field used as v-sync output

1: v-sync modifies end of active video

CLKOUTSEL72

[BP-POS]

Output clock select

0: CLKOUT depends on CLKOUTSEL

1: CLKOUT is identical to clkb72

D4

D3

D2

D1

D0

HINC4_8

[BP-POS]

Belongs to 4Ch

Belongs to 4Bh

Belongs to 4Ah

Belongs to 49h

Belongs to 48h

HINC3_8

[BP-POS]

HINC2_8

[BP-POS]

HINC1_8

[BP-POS]

HINC0_8

[BP-POS]

Micronas

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2

Table 3–8: I C bus command description, continued

Bit

Subaddress 4Eh

D7-D0 HSCPOSC7-0

Name

Description

Horizontal Scaling Factor For Post Scaler

‘010000000000’: factor is 4

[BP-POS]

‘101101010101’: factor is 1.407 (682 → 960)

‘110000000000’: factor is 4/3 (720 → 960)

‘111111111111’: factor is 1

Subaddress 4Fh

D7

CDELHPOS

[BP-POS]

Chrominance delay

0: no delay

1: half-pixel delay

D6

CLKOUTSEL

[BP-POS]

Output clock select

0: CLKOUT is identical to clkb27

1: CLKOUT is identical to clkb36

Note: HSYNC, VSYNC, BLANK are transferred to selected clock

D5

CLKOUTINV

[BP-POS]

CLKOUT inversion

0: no inverted CLKOUT

1: inverted CLKOUT

D4

HPANON

[BP-POS]

Panorama Mode enable

‘0’: panorama mode disabled

‘1’: panorama mode enabled

D3-D0

HSCPOSC

11-8

Belongs to 4Eh

[BP-POS]

Subaddress 50h

D7-D0 HSEG1_7-0

Beginning of Segment 1 for Panorama Mode

Granularity: 2 pixel

[BP-POS]

‘00000000000’: 0 pixel behind picture start

‘11111111111’: 4094 pixel behind picture start

Subaddress 51h

D7-D0 HSEG2_7-0

Beginning of Segment 2 for Panorama Mode

Granularity: 2 pixel

[BP-POS]

‘00000000000’: 0 pixel behind picture start

‘11111111111’: 4094 pixel behind picture start

Subaddress 52h

D7-D0 HSEG3_7-0

Beginning of Segment 3 for Panorama Mode

Granularity: 2 pixel

[BP-POS]

‘00000000000’: 0 pixel behind picture start

‘11111111111’: 4094 pixel behind picture start

Subaddress 53h

D7-D0 HSEG4_7-0

Beginning of Segment 4 for Panorama Mode

Granularity: 2 pixel

[BP-POS]

‘00000000000’: 0 pixel behind picture start

‘11111111111’: 4094 pixel behind picture start

72

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Micronas

DATA SHEET

VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 54h

D7

D6

FIOFFOFF

[BP-POS]

Fieldoffset for ITU656 NTSC signals

‘0’: disabled

‘1’: enabled

FIELDBINV

[BP-POS]

Backend field inversion

‘0’: no inversion

‘1’: inversion

D5-D3

D2-D0

HSEG2_10-8

[BP-POS]

Belongs to 51h

Belongs to 50h

HSEG1_10-8

[BP-POS]

Subaddress 55h

D7

CHRMSIG656

[BP-POS]

Chrominance format for 656 output

‘0’: (R−Y), (B−Y) output

‘1’: −(R−Y), −(B−Y) output

D6

VDEL_EN

[BP-POS]

Vertical pulse delay backend (test only)

‘0’: no delay

‘1’: delayed

D5-D3

D2-D0

HSEG4_10-8

[BP-POS]

Belongs to 53h

HSEG3_10-8

[BP-POS]

Belongs to 52h

Subaddress 56h

D7

D6

SHIFTUV

[BP-DAC]

Shift UV subsampling at digital output

‘0’: take first UV couple

‘1’: take second UV couple

VSP9432/42 only

DPOUT656

[BP-DAC]

Enable digital 656 Output

‘0’: disable output

‘1’: enable output

Subaddress 57h

D7

CHROMSIGN

Chrominance sign

[BP-DAC]

‘0’: (R−Y), (B−Y) output

‘1’: −(R−Y), −(B−Y) output

D6

CHROMAMP

[BP-DAC]

Chrominance amplification

‘0’: amplification=1

‘1’: amplification=2

Subaddress 58h

D7-D0

PKLY

[BP-DAC]

Voltage Level for Y DAC Output

‘00000000’: 0.4 V

‘10000000’: 1.0 V

‘11111111’: 1.9 V

including peaking overshoots. 0.9 V for white max.

Micronas

Aug. 16, 2004; 6251-552-1DS

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 59h

D7-D0

PKLU

[BP-DAC]

Voltage Level for U DAC Output

‘00000000’: 0.4 V

‘10000000’: 1.0 V

‘11111111’: 1.9 V

Subaddress 5Ah

D7-D0

PKLV

[BP-DAC]

Voltage Level for V DAC Output

‘00000000’: 0.4 V

‘10000000’: 1.0 V

‘11111111’: 1.9 V

Subaddress 5Bh

D7-D5

CONS

[CP-CD]

Color Switched On (SECAM)

at level=CKILLS+CONS

‘000’: min value

‘010’: default

‘111’: max value

D4

COLON

[CP-CD]

Force Color On

‘0’: color depends on color decoder status

‘1’: color always on

D3-D2

CRCB

[CP-CD]

Choice of UV or CrCb output

00: UV color space

01: CrCb color space

10: modified CrCb color space (SECAM only; PAL & NTSC: same as setting

‘01’)

D1

D0

ACCFIX

[CP-CD]

Fix ACC to Nominal Value

‘0’: ACC is working

‘1’: ACC is fixed

ACCFRZ

[CP-CD]

Freeze ACC

‘0’: ACC is working

‘1’: ACC is frozen

74

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 5Ch

D7-D5

D4-D3

CON

[CP-CD]

Color Switched On (PAL/NTSC)

at level=CKILL+CON

‘000’: min value

‘010’: default

‘111’: max value

UVCOR

[CP-CD]

Chrominance coring

‘00’: off

‘01’: ±1LSB

‘10’: ± 2LSB

‘11’: ± 3LSB

D2

NOTCHOFF

[CP-CD]

Luminance notch-filter

‘0’: notch-filter enabled

‘1’: notch-filter bypassed

D1-D0

SECNTCH

[CP-CD]

Selection of Notch filter behavior in SECAM mode

‘00’: 4.406 MHz

‘01’: 4.250 MHz

‘10’: 4.33 MHz

‘11’: 4.406 / 4.25 dependent on transmitted color

Subaddress 5Dh

D7-D6

D5-D4

D3-D2

PWTHD

[CP-CD]

Selection Of ‘Peak-White’ Threshold

‘00’: 448

‘01’: 470

‘10’: 500

‘11’: 511

CLRANGE

[CP-CD]

Chroma lock-range

‘00’: ± 425 Hz

‘01’: ± 463 Hz

‘10’: ± 505 Hz

‘11’: ± 550 Hz

LMOFST

[CP-CD]

Luminance Offset in color decoder during visible picture

‘00’: no offset

‘01’: −32 LSB ( −7.5 IRE)

‘10’:+32 LSB (+7.5 IRE)

‘11’: −16 LSB (−3.75 IRE)

Note: A 7.5 IRE offset is added during blanking in display processing. When

choosing ‘10’, the luminance offset is equal to the offset of the CVBS input as

in both picture and blanking the same 7.5 IRE offset is used.

D1

VDETIFS

[CP-CD]

Vertical Sync-Detection Slope

‘0’: normal

‘1’: slow

Micronas

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 5Eh

D7-D6

D5-D0

SDR

[CP-CD]

Secam Dr adjustment

00: 191

01: 194

10: 197

11: 200

CHRF

Chroma Bandwidth

[CP-CD]

selects chroma bandwidth

‘011100’: nominal bandwidth

Subaddress 5Fh

D7

COMB

Delay Line

[CP-CD]

‘0’: use delay line

‘1’: do not use delay line (only suited for NTSC)

D6-D0

CSTAND

[CP-CD]

Color Standard Assignment

‘0000000’: no color standard chosen

‘0000001’: PAL N

‘0000010’: PAL B

‘0000100’: SECAM

‘0001000’: PAL 60

‘0010000’: PAL M

‘0100000’: NTSC M

‘1000000’: NTSC 44

For allowed combinations please refer to chapter (see Section 2.1.5. on

page 9)

‘1100110’: PALB/SECAM/NTSCM/NTSC44/PAL60

Subaddress 60h

D7-D0

CKILL

[CP-CD]

Chroma Level For Color Off (PAL/NTSC)

‘00000000’: high burst amplitude

‘01000000’: default

‘11111111’: low burst amplitude

Subaddress 61h

D7-D0 CKILLS

Chroma Level For Color Off (SECAM)

‘00000000’: low burst amplitude

‘01000000’: default

[CP-CD]

‘11111111’: high burst amplitude

76

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 62h

D7-D6

VPOL

[CP-CD]

V Polarity at VINP

‘00’: use Vsync

‘01’: use inverted Vsync

‘10’: autodetect polarity

‘11’: (reserved)

D5

LPPOST

[CP-CD]

Additional Filtering of Luminance

‘0’: no filtering

‘1’: filtering

D4-D0

YCDEL

[CP-CD]

Luminance Delay

‘10000’: 800 ns

‘0000’: no delay

‘01111’: −700 ns

Subaddress 63h

D7-D0

HUE

Hue Control (Tint)

‘10000000’: −89°

‘00000000’: 0°

[CP-CD]

‘01111111’: +88°

Subaddress 64h

D7-D0 NTSCREF

[CP-CD]

ACC Reference Adjustment (NTSC)

‘00000000’: low reference value

‘10100101’: nominal value

‘11111111’: high reference value

Subaddress 65h

D7-D0 PALREF

ACC Reference Adjustment (PAL)

‘00000000’: low reference value

‘01011111’: nominal value

[CP-CD]

‘11111111’: high reference value

Subaddress 66h

D7-D6

SLLTHD

[CP-CD]

Slicing Level Threshold H

‘00’: no offset

‘01’: small negative

‘10’: small positive

‘11’: large positive (adaptive)

D5-D0

SCADJ

[CP-CD]

Subcarrier Adjustment

‘000000’: −262 ppm

‘001111’: 0 ppm

‘111111’: 840 ppm

Micronas

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Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 67h

D7-D6

D5-D0

AGCMD

[CP-CD]

AGC method

‘00’: sync amplitude and peak white

‘01’: sync amplitude only

‘10’: peak white only

‘11’: fixed to value AGCADJ1

AGCADJ1

[CP-CD]

Automatic Gain Adjustment ADC1

‘000000’: 0.6 V input signal

‘111111’: 1.8 V input signal

Subaddress 68h

D7

AGCRES

[CP-CD]

AGC reset

‘0’: no reset

‘1’: reset

D6

AGCFRZE

[CP-CD]

freeze AGC (ADC_CVBS)

‘0’: normal operation

‘1’: freeze AGC at current value

D5-D0

AGCADJ2

[CP-CD]

Automatic Gain Adjustment ADC2

‘000000’: 0.6 V input signal

‘111111’: 1.8 V input signal

Subaddress 69h

D7-D0 CLMPHIGH

Vertical End Of Clamping Pulse

Granularity: 2

[CP-CD]

‘00000000’: line 256

‘00111100’: line 376

‘11111111’: line 766

Subaddress 6Ah

D7-D4 CVBOSEL1

Output select 1 for pin cvbso1

‘0000’: CVBS1

[CP-CD]

‘0001’: CVBS2

‘0010’: CVBS3

‘0011’: CVBS4 or Y1

‘0100’: CVBS5 or C1

‘0101’: CVBS6 or Y2

‘0110’: CVBS7 or C2

‘0111’: Y1 + C1

‘1000’: Y2 + C2

D3-D0

CLMPLOW

[CP-CD]

Vertical Start Of Clamping Pulse

‘0000’: line 0

‘0011’: line 6

‘1111‘: line30

78

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 6Bh

D7

FLINE

Mode Selection

[CP-CD]

‘0’: interlace input

‘1’: progressive input

D6

FLDINV

[CP-CD]

Field Inversion

‘0’: no inversion

‘1’: inversion

D5

CLPSTGY

[CP-CD]

Clamping strategy

‘0’: back-porch clamping

‘1’: sync-tip-clamping

D4

YCSEL

Y/C select

[CP-CD]

‘0’: CVBS input

‘1’: Y/C input

D3-D0

CLMPD1

[CP-CD]

Measurement duration ADC1

Granularity: 200 ns

‘0000’: 0 µs

‘0111’: 1.4 µs

‘1111’: 3 µs

Subaddress 6Ch

D7-D6

HPOL

[CP-CD]

H Polarity at HINP

‘00’: use Hsync

‘01’: use inverted Hsync

‘10’: autodetect polarity

‘11’: (reserved)

D5

FHDET

[CP-CD]

Automatic Multisync capability

‘0’: disabled

‘1’: enabled

D4

DISCHCH

[CP-CD]

Channel-change signal for color decoder

‘0’: color-decoder not reset after channel-change

‘1’: color-decoder reset after channel-change

D3-D0

CLMPD2

[CP-CD]

Measurement duration ADC2

Granularity: 200 ns

‘0000’: 0 µs

‘0111’: 1.4 µs

‘1111’: 3 µs

Micronas

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Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 6Dh

D7

NOSIGB

No signal behavior

[CP-CD]

‘0’: noisy screen when out of sync

‘1’: colored background insertion instead

D6

HINP

[CP-CD]

Horizontal Pulse Detection

‘0’: from CVBS ADC1

‘1’: from RGBF ADC

D5-D0

CLMPST1

[CP-CD]

Measurement start ADC1

‘000000’: 0 µs

‘011100’: 5.6 µs

‘111111’: 12.8 µs

Subaddress 6Eh

D7-D6

PLLTC

[CP-CD]

Time constant HPLL (VCR...TV)

‘00’: very fast

‘01’: fast

‘10’: slow

‘11’: very slow

D5-D0

CLMPST2

[CP-CD]

Measurement start ADC2

‘000000’: 0 µs

‘011100’: 5.6 µs

‘111111’: 12.8 µs

Subaddress 6Fh

D7-D4 CVBSEL2

Input select for ADC2

‘0000’: CVBS1

[CP-CD]

‘0001’: CVBS2

‘0010’: CVBS3

‘0011’: CVBS4 or Y1

‘0100’: CVBS5 or C1

‘0101’: CVBS6 or Y2

‘0110’: CVBS7 or C2

‘0111’: Y1 + C1

‘1000’: Y2 + C2

‘1111’: disabled

D3-D0

CVBSEL1

[CP-CD]

Input select for ADC1

‘0000’: CVBS1

‘0001’: CVBS2

‘0010’: CVBS3

‘0011’: CVBS4 or Y1

‘0100’: CVBS5 or C1

‘0101’: CVBS6 or Y2

‘0110’: CVBS7 or C2

‘0111’: Y1 + C1

‘1000’: Y2 + C2

‘1111’: disabled

80

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2

Table 3–8: I C bus command description, continued

Bit

Subaddress 70h

D7-D4 CVBOSEL2

Name

Description

Output select for pin cvbso2

‘0000’: CVBS1

[CP-CD]

‘0001’: CVBS2

‘0010’: CVBS3

‘0011’: CVBS4 or Y1

‘0100’: CVBS5 or C1

‘0101’: CVBS6 or Y2

‘0110’: CVBS7 or C2

‘0111’: Y1 + C1

‘1000’: Y2 + C2

D3-D0

CVBOSEL3

[CP-CD]

Output select for pin cvbso3

‘0000’: CVBS1

‘0001’: CVBS2

‘0010’: CVBS3

‘0011’: CVBS4 or Y1

‘0100’: CVBS5 or C1

‘0101’: CVBS6 or Y2

‘0110’: CVBS7 or C2

‘0111’: Y1 + C1

‘1000’: Y2 + C2

Subaddress 71h

D7-D0

FHFRRN

[CP-CD]

Free Running Frequency Of Horizontal PLL

‘00000000’: 384 clocks (52.7 kHz)

‘11100100’: 1296 clocks (15.625 kHz)

‘11111111’: 1404 clocks (14.423 kHz)

Micronas

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 72h

D7

REFTRIMEN

[CP-CD]

Reference Value enable

‘0’: use fuses

‘1’: uses programmed value

D6

SATNR

[CP-CD]

Noise reduction for satellite signal

‘0’: disabled

‘1’: enabled

D5

VINP

[CP-CD]

Vertical Pulse Detection

‘0’: from CVBS signal

‘1’: from V-input pin

D4-D3

NSRED1-0

[CP-CD]

Noise Reduction For Horizontal PLL

‘000’: 1/16

‘001’: 1/8

‘010’: 1/4

‘011’: 1/2

‘100’: 1

‘101’: 2

‘110’: 4

‘111’: 8

MSB is at address 7Eh, D2

D2-D0

LPCDEL

[CP-CD]

Window Shift For Fine Error Calculation

‘100’: −4 clock cycles

‘000’: no offset

‘011’: +3 clock cycles

Subaddress 73h

D7-D0 VSHIFT

Field Detection Window Shift

‘00000000’: no shift

[CP-CD]

‘11111111’: shifted by 2048

Subaddress 74h

D7

PALIDL1

[CP-CD]

PAL/NTSC Identification Level 1

‘0’: less sensitive (192)

‘1’: more sensitive (64)

D6-D0

VTHRL50

[CP-CD]

Vertical Window Noise Suppression Opening

Opening= 4*VTHRL50

0000000: opening in first line

1111111: opening in line 508

Subaddress 75h

D7

PALIDL0

[CP-CD]

PAL/NTSC Identification Level 0

‘0’: less sensitive

‘1’: more sensitive

D6-D0

VTHRH50

[CP-CD]

Vertical Window Noise Suppression Closing

Closing= 312+4*VTHRH50

0000000: closing in line 312

1111111: closing in line 820

When VINP (72h) is set, 50 Hz values are taken for opening and closing val-

ues.

82

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2

Table 3–8: I C bus command description, continued

Bit

Subaddress 76h

D7-D0 REFTRIM

Name

Description

Reference Value Bandgap

[CP-CD]

‘01000000’: low reference

‘00000000’: medium reference

‘01111111’: high reference

‘1XXXXXXX’: reference disabled, resistor used

Subaddress 77h

D7-D4

REFTRIMCV

[CP-CD]

Reference Value ADC CVBS (antialiasfilter)

‘0000’: narrow

‘1111’: wide

D3-D0

REFTRIMRGB

[CP-CD]

Reference Value ADC RGBF (antialiasfilter)

‘0000’: narrow

‘1111’: wide

Subaddress 78h

D7

SLLTHDVP

Vertical Slicing Level Threshold Polarity

[CP-CD]

‘0’: positive

‘1’: negative

D6

THRSEL

[CP-CD]

H Slicing level threshold

‘0’: 50 %

‘1’: 37 %

D5-D0

CLMPST1S

[CP-CD]

Clamping start for ADC1

‘000000’: 0 µs

‘011100’: 5.6 µs

‘111111’: 12.8 µs

Subaddress 79h

D7-D6

SCMIDL

SECAM identification level

[CP-CD]

‘00’: 128

‘01’: 64

‘10’: 96

‘11’: 80

D5-D0

CLMPST2S

[CP-CD]

Clamping start ADC2

‘000000’: 0 µs

‘011100’: 5.6 µs

‘111111’: 12.8 µs

Micronas

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 7Ah

D7-D3

D2-D0

ACCLIM

[CP-CD]

ACC-limitation for weak signals

‘00000’: strong limitation

‘11111’: no limitation

IFCOMP

[CP-CD]

IF compensation filter

‘000’: pal prefiltering

‘001’: pal prefiltering + IF

‘010’: prefiltering

‘011’: IF 6dB

‘100’: flat

Note: ‘000’ or ‘001’ are not suited for 3.58 MHz subcarrier color standards

(PAL M, PAL N, NTSC M)

Subaddress 7Bh

D7-D4

CLMPD2S

[CP-CD]

Clamping duration for ADC2

Granularity: 200 ns

‘0000’: 0 µs

‘0111’: 1.4 µs

‘1111’: 3.0 µs

D3-D0

CLMPD1S

[CP-CD]

Clamping duration for ADC1

Granularity: 200 ns

‘0000’: 0 µs

‘0111’: 1.4 µs

‘1111’: 3.0 µs

Subaddress 7Ch

D5

EIA770

EIA 770 support

[CP-CD]

‘0’: standard TV signals expected

‘1’: progressive signals expected

timing according to EIA 770.1 or EIA 770.2 when ‘1’

D4

SHAPERDIS

[CP-PP]

Power Down Of Crystal Oscillator Shaper

‘0’: normal operation

‘1’: power down active

D3

OSCPD

[CP-PP]

Power Down Of Crystal Oscillator Amplifier

‘0’: normal mode

‘1’: power down mode

D2

TSTSHAPERI

[CP-PP]

Testmode Control Of Crystal Oscillator

‘0’: normal operation (shaper active)

‘1’: external clock input (shaper replaced)

D1-D0

FREQSEL

[CP-PP]

Amplifier Current Setting Of Oscillator Pad

‘00’: 100 µA

‘01’: 590 µA

‘10’: 235 µA

‘11’: 1730 µA

84

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DATA SHEET

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2

Table 3–8: I C bus command description, continued

Bit

Subaddress 7Dh

BELLFIR

Name

Description

D6-D4

D3-D1

D0

Bell filter FIR component

‘000’: −116

‘001’: −113

‘010’: −110

‘011’: −108

‘100’: −106

‘101’: −104

‘110’: −102

‘111’: −100

[CP-CD]

BELLIIR

[CP-CD]

Bell filter IIR component

‘000’: 8

‘001’: 9

‘010’: 10

‘011’: 11

‘100’: 12

‘101’: 13

‘110’: 14

‘111’: 16

VFLYWHL

[CP-CD]

Vertical Flywheel

‘0’: disabled

‘1’: enabled

Subaddress 7Eh

D7-D6

FLNSTRD

[CP-CD]

Force line standard at CVBS/RGB frontend

‘00’: automatic

‘01’: force 50 Hz

‘10’: force 60 Hz

‘11’: (reserved)

D5

ENLIM

[CP-CD]

Enable limiter

‘0’: disabled

‘1’: enabled

D4-D3

ISHFT

I-adjustment for horizontal PLL

[CP-CD]

‘00’: *1

‘01’: *2

‘10’: *4

‘11’: *8

D2

NSRED2

[CP-CD]

Belongs to 72h

D1-D0

VLP

Lowpass for vertical sync-separation

[CP-CD]

‘00’: none

‘01’: weak

‘10’: medium

‘11’: strong

Micronas

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 7Fh

D7

SECACC

[CP-CD]

Secam acceptance

‘0’: disabled

‘1’: enabled

D6

SECDIV

[CP-CD]

Secam Divider

‘0’: divide by 4

‘1’: divide by 2

D5-D4

SECINC1

[CP-CD]

Secam increment 1

‘00’: 2

‘01’: 3

‘10’: 4

‘11’: 5

D3-D2

D1-D0

SECINC2

[CP-CD]

Secam increment 2

‘00’: 1

‘01’: 2

‘10’: 3

‘11’: 4

SCMREL

[CP-CD]

Secam rejection level

‘00’: 320

‘01’: 384

‘10’: 352

‘11’: 1024

86

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 80h

D7

PORCNCL

[CP-CD]

Reset control bit cancel

‘0’: no operation

‘1’: reset POR bit (8Ch)

after use, PORCNCL must be set to ‘0’ again

D6-D4

NTCHSEL

[CP-CD]

Luminance Notch selection

‘000’: sharp notch

‘001’: medium 1

‘010’: medium 2

‘011’: broad notch

‘100’: broad steep notch (PAL, SECAM only)

D3

D2

D1

D0

CPLLRES

[CP-CD]

Force Chroma PLL reset

‘0’: no reset

‘1’: reset chroma PLL

after use, CPLLRES must be set to ‘0’ again

DISALLRES

[CP-CD]

Disable all chroma resets

‘0’: resets allowed

‘1’: resets disabled

may only be used if ONE color standard is selected

TRAPBLU

[CP-CD]

Notchfrequency for 4,250 MHz

‘0’: 4.25 MHz

‘1’: 4.2 MHz

has only effect in SECAM mode

TRAPRED

[CP-CD]

Notchfrequency for 4,406 MHz

‘0’: 4.406 MHz

‘1’: 4.356 MHz

has only effect in SECAM mode

Micronas

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Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 80h

D7

PORCNCL

[CP-CD]

Reset control bit cancel

‘0’: no operation

‘1’: reset POR bit (8Ch)

after use, PORCNCL must be set to ‘0’ again

D6-D4

NTCHSEL

[CP-CD]

Luminance Notch selection

‘000’: sharp notch

‘001’: medium 1

‘010’: medium 2

‘011’: broad notch

‘100’: broad steep notch (PAL, SECAM only)

D3

D2

D1

D0

CPLLRES

[CP-CD]

Force Chroma PLL reset

‘0’: no reset

‘1’: reset chroma PLL

after use, CPLLRES must be set to ‘0’ again

DISALLRES

[CP-CD]

Disable all chroma resets

‘0’: resets allowed

‘1’: resets disabled

may only be used if ONE color standard is selected

TRAPBLU

[CP-CD]

Notchfrequency for 4,250 MHz

‘0’: 4.25 MHz

‘1’: 4.2 MHz

Note: has only effect in SECAM mode

TRAPRED

[CP-CD]

Notchfrequency for 4,406 MHz

‘0’: 4.06 MHz

‘1’: 4.356 MHz

Note: has only effect in SECAM mode

88

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Micronas

DATA SHEET

VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 81h

D7

ADLCK

[CP-CD]

Additional lock-detection

‘0’: no used

‘1’: used

D6

ADLCKSEL

[CP-CD]

Additional lock-detection selection

‘0’: PALID

‘1’: PALDET

D5

ADLCKCC

[CP-CD]

Additional lock-detection color-killer

‘0’: do not use lock signal

‘1’: use lock-signal

D4-D3

VFLYWHLMD[CP-

CD]

Vertical Flywheel Mode

‘00’: CHECK FOR CORRECT STANDARD

‘01’: 3 lines deviation allowed

‘10’: 4 lines deviation allowed, no check for interlace

‘11’: 5 lines deviation allowed, no check for interlace

D2-D0

SECACCL

[CP-CD]

Secam Acceptance level

‘000’: 100

‘001’: 84

‘010’: 64

‘011’: 32

‘100’: 70

‘101’: 76

‘110’: 90

Note: must be enabled by SECACC (7Fh) to have an effect

Micronas

Aug. 16, 2004; 6251-552-1DS

89

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 82h (no auto-increment)

D7-D6

SYNCFTHD

[CP-CD]

SYNCF threshold

00: 4 lines

01: 3 lines

10: 2 lines

11: 1 line

D5

D4

D3

D2

D1

D0

IFCOMPSTR

[CP-CD]

2nd IF compensation filter

‘0’: disabled

‘1’: enabled

PALIDL2

[CP-CD]

PAL/NTSC identifikation level 2

‘0’: less sensitive

‘1’: more sensitive

CPLLOF

[CP-CD]

Chroma PLL Open

‘0’: normal operation

‘1’: chroma PLL opened

DEEMPSTD

[CP-CD]

Deemphase Filtering For Standard Detection

‘0’: weak

‘1’: strong

PALINC1

[CP-CD]

PAL/NTSC Detection: Increment 1

‘0’: +3

‘1’: +2

PALINC2

[CP-CD]

PAL/NTSC Detection: Increment 2

‘0’: −1

‘1’: −2

do not use PALINC2=1 in combination with PALINC1=1

Subaddress 83h (Read-only)

D0

FBLACTIVE

[CP-I2C]

Activity At FBL Input

‘0’: no activity

‘1’: activity

reset automatically when read

Subaddress 84h (Read-only, no auto-increment))

D6-D0

NOISEME

[FP-TNR]

Noise level of the input signal

0000000: no noise

1111110: strong noise

1111111: strong noise or measurement failed

Note: no autoincrement possible

90

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 85h (Read-only)

D5

D4

D3

D2

D1

D0

LBSTATUS

[FP-TNR]

Status bit for letter box detection:

0: No new value available

1: New value from Letter Box Detection available

Note: reset automatically when read

PFBL

[FP-TNR]

Indicates Overflow at FBL Input

‘0’: no overflow

‘1’: overflow

Note: reset automatically when read

PG

[FP-TNR]

Indicates Overflow at GREEN Input

‘0’: no overflow

‘1’: overflow

Note: reset automatically when read

PB

[FP-TNR]

Indicates Overflow at BLUE Input

‘0’: no overflow

‘1’: overflow

Note: reset automatically when read

PR

[FP-TNR]

Indicates Overflow at RED Input

‘0’: no overflow

‘1’: overflow

Note: reset automatically when read

NMSTATUS

[FP-TNR]

Indicates New Value of the Noise Measurement

0: NOISEME has not been updated

1: New value of NOISEME available

Note: reset automatically when read

Subaddress 86h (Read-only)

D0

STABLL

[PP]

Shows LL-HPLL Lock Status

‘0’: LL_HPLL is not locked

‘1’: LL_HPLL is locked

Subaddress 87h (Read-only)

D1-D0

SMMIRROR

[BP-O/M]

Operation mode for scan rate conversion:

‘00’: AABB (Raster ααββ)

‘01’: AAAA (Raster αααα)

‘10’: AAAA (Raster αβαβ)

‘11’: BBBB (Raster ββββ)

Micronas

Aug. 16, 2004; 6251-552-1DS

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 88h (Read-only)

D7

DETHPOL

[CP-CD]

Detected Polarity Of HSync

‘0’: negative

‘1’: positive

D6

DETVPOL

[CP-CD]

Detected Polarity Of V Sync

‘0’: negative

‘1’: positive

D5-D3

STDET

[CP-CD]

Detected Color Standard

‘000’: non standard or standard not detected

‘001’: NTSC M

‘010’: PAL M

‘011’: NTSC44

‘100’: PAL60

‘101’: PAL N

‘110’: SECAM

‘111’: PAL B/G

D2

D1

D0

SCOUTEN

[CP-CD]

SCDEV valid indication

‘0’: SCDEV not valid

‘1’: SCDEV valid

PALID

[CP-CD]

PAL identification (algorithm 1)

‘0’: not PAL

‘1’: PAL

CKSTAT

[CP-CD]

Colorkill status

‘0’: color off

‘1’: color on

Subaddress 89h (Read-only)

D7

LNSTDRD

[CP-CD]

Line Standard detection

‘0’: 60 Hz

‘1’: 50 Hz

D6

INT

[CP-CD]

Interlace Detection

‘0’: progressive input

‘1’: interlace input

D5-D0

SCDEV

[CP-CD]

Deviation Of Clock System or Color Carrier

‘100000’: max. negative deviation

‘000000’: no deviation

‘011111’: max. positive deviation

Subaddress 8Ah (Read-only)

D7-D0

LPFLD

[CP-CD]

Nr. of lines per field for input signal

lines= 256+LPFLD*2

‘00000000’: 256 lines or less

‘11111111’: 766 lines or more

92

Aug. 16, 2004; 6251-552-1DS

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DATA SHEET

VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 8Bh (Read-only)

D7-D0

NRPIXEL

[CP-CD]

Pixel number of input signal

Granularity: 4

‘00000000’: 384 or less

‘11111111’: 1404 or more

PIXEL=4*NRPIXEL+384

Subaddress 8Ch (Read-only)

D7

POR

Reset indication

[CP-CD]

a reset at pin 24 (reset) sets POR. POR is reset with PORCNCL (80h)

‘0’: no reset appeared

‘1’: reset appeared

D3

VFLYMD

[CP-CD]

Vertical Flywheel mode locked

0: unlocked

1: locked

VFLYWHL must be enabled to give a result

D2

D0

STAB

[CP-CD]

Status of horizontal synchronization

‘0’: sync separation not locked

‘1’: sync separation locked and stable

PALDET

[CP-CD]

PAL identification (algorithm 2)

‘0’: not PAL

‘1’: PAL

Subaddress 8Dh (Read-only)

D7-D0

REFTRIMRD

[CP-CD]

Reference Value Bandgap

‘01000000’: low reference

‘00000000’: medium reference

‘01111111’: high reference

‘1XXXXXXX’: reference disabled, resistor used

Note: contains fused value only when REFTRIMEN (72h)=0.

Subaddress 8Eh (Read-only)

D7-D4

REFTRIMCVRD

[CP-CD]

Reference Value CVBS ADC

‘0000’: narrow

‘1111’: wide

Note: contains fused value only when REFTRIMEN (72h)=0.

D3-D0

REFTRIMRGBRD

[CP-CD]

Reference Value RGB ADC

‘0000’: narrow

‘1111’: wide

Note: contains fused value only when REFTRIMEN (72h)=0.

Micronas

Aug. 16, 2004; 6251-552-1DS

93

VSP 94x2A

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 8Fh (Read-only, NOT compatible to 940X family)

D3

SLS

[CP-I2C]

Line Standard At Device Output

‘0’: 100 Hz (VSP 9402A, VSP 9412A)

‘1’: 50 Hz (VSP 9432A, VSP 9442A)

D2-D0

VERSION

[CP-I2C]

Version Of VSP 94XX Family

‘001’: VSP 94x5B

‘010’: VSP 94x2A

‘011’: VSP 94x7B

‘101’: VSP 94x9C

others: reserved

Subaddress 90h (Read-only)

D7

AM50O

[CP-I2C]

Last detected Standard 50 Hz

‘0’: PAL or none

‘1’: SECAM

D6

AM60O

[CP-I2C]

Last detected Standard 60 Hz

‘0’: NTSC M or none

‘1’: NTSC44 or PAL60

D5-D0

AGCADJCV

[CP-I2C]

AGC value for ADC1

000000: smallest input range

111111: biggest input range

Subaddress 91h (Read-only)

D6-D0

VLENGTH

[CP-I2C]

Length of vertical pulse

0000000: short v

1111111: long v

Subaddress 92h (Read-only)

D7-D0

MINV

[CP-I2C]

Measured sync amplitude

00000000: smallest sync

11111111: largest sync

Subaddress 93h (Read-only)

D4-D0

PWADJCNT

[CP-I2C]

Peak White adjust counter

00000: no PW reduction

11111: largest PW reduction

Subaddress 96h (Read-only)

D0

V40STAT

[FP-I2C]

V Status bit of 40.5 MHz domain

‘0’: New write or read cycle can start

‘1’: No new write or read cycle can start

Subaddress 98h (Read-only)

D0

V36BSTAT

[BP-I2C]

V Status bit of backend 36 MHz domain

‘0’: New write or read cycle can start

‘1’: No new write or read cycle can start

94

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VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress 99h (Read-only)

D0

V20STAT

[CP-I2C]

V Status bit of 20.25 MHz domain

‘0’: New write or read cycle can start

‘1’: No new write or read cycle can start

Subaddress A0h

D7-D4

KPNL

[PP]

Proportional factor for loop filter if HPLL is not locked

same values as in locked condition (KPL)

D3-D0

KPL

[PP]

Proportional factor for loop filter if HPLL is locked)

00000: 0

00001: 1

00010: 2

00011: 4

00100: 8

00101: 16

00110: 32

00111: 64

01000: 128

01001: 256

01010: 512

01011: 1024

01100: 2048

01101: 4096

01110: 8192

01111:16384

10000: 0.5

10001: 1.5

10010: 2.5

10011: 3

10100: 3.5

10101: 4.5

10110: 5

10111: 6

11000: 7

Micronas

Aug. 16, 2004; 6251-552-1DS

95

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress A1h

D7-D4

D3-D0

KINL

[PP]

Integrational factor for loop filter if HPLL is not locked

same values as in locked condition (KIL)

KIL

Integrational factor for loop filter if HPLL is locked

[PP]

00000: 0

00001: 1

00010: 2

00011: 4

00100: 8

00101: 16

00110: 32

00111: 64

01000: 128

01001: 256

01010: 512

01011: 1024

01100: 2048

01101: 4096

01110: 8192

01111:16384

10000: 0.5

10001: 1.5

10010: 2.5

10011: 3

10100: 3.5

10101: 4.5

10110: 5

10111: 6

11000: 7

Subaddress A2h

D7-D0

LIMIP

[PP]

Limiter Control for P-part for increased dynamic range

LIMIT_P= ±16*LIMIP

‘00000000’: ±0

‘11111110’: ±4064

‘11111111’: no limitation

Subaddress A3h

D7-D0

LIMII

[PP]

Limiter Control for I-part for increased dynamic range

LIMIT_I= ±16*LIMII

‘00000000’: ±0

‘11111110’: ±4064

‘11111111’: no limitation

96

Aug. 16, 2004; 6251-552-1DS

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DATA SHEET

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress A4h

D7

KPNL4

[PP]

Refer to A0h

Refer to A1h

D6

KPL4

[PP]

D5

KINL4

[PP]

D4

KIL4

[PP]

D3-D0

LIMLR

[PP]

Limit LL-PLL lock-in range

0000: full lock-in range of ±5.85 %

0001: lock in range limited to ±3.8 %

0010: lock in range limited to ±2.55 %

0011: lock in range limited to ±1.27 %

0100: ock in range limited to ±0.63 %

0101: lock in range limited to ±0.32 %

0110: lock in range limited to ±0.19 %

0111: lock in range limited to ±0.13 %

1000: lock in range limited to ±5 %

1001: lock in range limited to ±4.5 %

1010: lock in range limited to ±3.1 %

1011: lock in range limited to ±2.1 %

1100: lock in range limited to ±1.5 %

1101: lock in range limited to ±1 %

1110: (reserved)

1111: (reserved)

Subaddress B0

D6-D5

AGCTHD

[CP-CD]

AGC hysterisys

00: broad

01: medium 1

10: medium 2

11: small

D4-D0

FEMAG

[CP-CD]

Fine Error characteristic

00000: smallest gain

10000: default (equal to A32 version)

11111: largest gain

Micronas

Aug. 16, 2004; 6251-552-1DS

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress B1

D6-D4

SLLTHDV

[CP-CD]

Slicing Level Threshold V

‘000’: no offset

‘001’: 4

‘010’: 8

‘011’:12

‘101’: adaptive (limited to ±4)

‘110’: adaptive (limited to ±8)

‘111’: adaptive (limited to ±12)

polarity is selected by SLLTHDVP (78h)

D3-D2

D1-D0

AMSTD60

[CP-CD]

Automatic standard detection priority 60 Hz

00: NTSC M

01: NTSC44/PAL60

10: (reserved)

11: automatic

AMSTD50

[CP-CD]

Automatic standard detection priority 50 Hz

00: PAL B

01: SECAM

10: (reserved)

11: automatic

Subaddress B2

D7-D6

SDB

[CP-CD]

Secam Db adjustment

00: −55

01: −58

10: −61

11: −64

D4

MVPG

[CP-CD]

Vertical Pulse gating

0: disabled

1: enabled

D3

MVP

Vertical length measurement with vertical pulse detection

[CP-CD]

0: disabled

1: enabled

D2-D0

VDETITC

[CP-CD]

Vertical Detection Integration Time Constant

000: 400 clock cycles

001: 375 clock cycles

010: 350 clock cycles

011: 300 clock cycles

100: 250 clock cycles

101: 225 clock cycles

110: 200 clock cycles

111: automatic

Subaddress B3

D6-D0 VTHRL60

Vertical Window Noise Suppression Opening

Opening=4*VTHRL60M

[CP-CD]

0000000: opening in first line

1111111: opening in line 508

98

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Subaddress B4

D6-D0 VTHRH60

Name

Description

Vertical Window Noise Suppression Closing

Closing=262+4*VTHRH60M

[CP-CD]

0000000: closing in line 262

1111111: closing in line 770

Subaddress B5

D7-D5 DEEMPIIR

Deemphase filter IIR component

[CP-CD]

‘000’: 5

‘001’: 6

‘010’: 7

‘011’: 8

‘100’: 9

‘101’: 10

‘110’: (reserved)

‘111’: (reserved)

D3-D0

DEEMPFIR

[CP-CD]

Deemphase filter FIR component

‘0000’: 16

‘0101’: 21

‘1111’: 31

Subaddress B7

D7-D0 NAPPLIPI

Not active pixels from HSYNC to input data for ITU

[FP-RGB]

Subaddress B8

D7-D0 ALPFIPI

Delay=NAPPLIPI * 2 + NAPIPPHI

Active lines per field for ITU

Active lines=ALPFIPI * 2

(int) 144: 288 active lines

[FP-RGB]

Subaddress B9

D7-D0 APPLIPI

Active pixels per line for ITU

Active pixels=APPLIPI * 2

(int) 360=720 lines

[FP-RGB]

Subaddress BA

D7

APPLIPI[8]

[FP-RGB]

Active pixels per line for ITU

Active pixels=APPLIPI * 2

(int) 360=720 lines

D6

NALPFIPI

[FP-RGB]

Not active lines per field for ITU

(int) 20= 20 lines

Subaddress BCh

D7-D0

FRINC18-11

[PP]

Set HDTO freerunning frequency

Granularity=103 Hz

33981 (minimum: nominal pixel clock= 3.5 MHz)

d

349525 (nominal pixel clock= 36 MHz)

d

388362 (maximum: nominal pixel clock= 40 MHz)

d

Micronas

Aug. 16, 2004; 6251-552-1DS

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2

Table 3–8: I C bus command description, continued

Bit

Subaddress BD

D7-D0 FRINC10-3

Name

Description

Belongs to BCh

[PP]

Subaddress BE

D2-D0 FRINC2-0

Belongs to BCh

[PP]

Subaddress C0

D7-D0 HSPPL

Hsync shift

[FP-RGB]

shift=HSPPL * 4

00000000: default

Subaddress C1

D7

FOFST

[FP-RGB]

Offset of active field at interlaced mode (line offset):

0: NALPFIPI+1 at field A, NALPFIPI at field B

1: NALPFIPI at field A, NALPFIPI+1 at field B

D2-D0

VSLPF

Vsync shift

[FP-RGB]

shift=VSLPF * 4

0000000: default

Subaddress D0

D7-D6

VBLANDEL

Refer to D1h

[BP-PM]

D5

VBLANPOL

[BP-PM]

Vertikal Blank Signal Polarity

0: positive

1: negative

D2

FSWFTL

[BP-PM]

Stability Signal of LL_HPLL

‘0’: STABLL is generated accoding to SETSTABLL

‘1’: STABLL is forced to 1 (hout synchronization enabled)

D1-D0

VBLANLEN

[BP-PM]

Refer to D2h

Subaddress D1

D7-D0 VBLANDEL[7:0]

Vertical Delay in lines from vsync to active edge of blank signal:

Blank_start=1*VBLANDEL

[BP-PM]

‘0000000000’: no delay

‘1111111111’: 1023 lines delay

Subaddress D2

D7-D0 VBLANLEN

Vertical Length in lines from start of active blank signal:

Blank_length=4*VBLANLEN

[BP-PM]

‘00000000’: no line

‘11111111’: 1020 lines

Subaddress E0

D7-D0 LBGRADDET

Threshold for gradient detected

[FP-RGB]

(int) 50: default

100

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Subaddress E1

D7-D0 LBVWENDLO

Name

Description

Vertical measure window lower end

[FP-RGB]

Subaddress E2

D7-D0 LBHWEND

(int) 150: default, [in lines (*2) related to VSYNC]

Horizontal measure window end

(int) 180: default,

[FP-RGB]

[in active pixels (*4) related to HSYNC]

Subaddress E3

D7-D0 LBHIWHITE

Histogram white

[FP-RGB]

Subaddress E4

D7-D0 LBHISTBLA

(int) 50: default

Histogram black

[FP-RGB]

(int) 25: default

Subaddress E5

D7

LBMASLA

Set to 1

[FP-RGB]

D6-D0

LBVWSTLO

[FP-RGB]

Vertical measure window lower start

(int) 96: default], [in lines (*2) related to VSYNC]

Subaddress E6

D7

LBFS

[FP-RGB]

Field subsampling mode

0: A+B fields

1: only A field

D6-D0

LBVWENDUP

[FP-RGB]

Vertical measure window upper end

(int) 73: default], [in lines (*2) related to VSYNC]

Subaddress E7

D7

LBVISUON

[FP-RGB]

Visualisation of letter box results

0: disabled

1: enabled

D6-D0

LBHWST

[FP-RGB]

Horizontal measure window start

(int) 36: default, [in active pixels (*4) related to HSYNC]

Subaddress E8

D5-D0

LBVWSTUP

[FP-RGB]

Vertical measure window upper start

(int) 20: default], [in lines (*2) related to VSYNC]

Micronas

Aug. 16, 2004; 6251-552-1DS

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2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress E9

D7

LBSTABILITY

Stability flag

[FP-RGB]

0: continuous format update

1: Format update only once

D6

LB43SENS

[FP-RGB]

Sensitivity to 4:3 switch

0: off

1: on

D5

LBNGFEN

[FP-RGB]

No gradient found

0: disabled

1: enabled

D4-D0

LBTHDNBNG

[FP-RGB]

Threshold for darkness-brightness, gradient only

(int) 15: default]

Subaddress EA

D7-D6

LBSUB

Subsampling mode

[FP-RGB]

0x: 13.5 MHz (1, e.g. digital 656 input)

10: 20.25 MHz source (1.5, for CVBS, YUV and RGB)

11: 40.5 MHz source (3)

D5

LBGRADRST

[FP-RGB]

Reset of gradient method

0: no reset

1: reset

D4-D0

LBHSDEL

[FP-RGB]

Histogram stability delay

(int)10=default

Subaddress EB

D4-D0 LBTHDNBNHA

Threshold for darkness-brightness, histogram, activity

[FP-RGB]

Subaddress EC

D4-D0 LBACTIVITY

(int)30=default

Activity

[FP-RGB]

Subaddress ED

D4-D0 LBGFBDEL

(int) 5: default]

Gradient fall back delay value

[FP-RGB]

Subaddress EE

D4-D0 LBGSDEL

(int) 11: default]

Gradient stability delay value

[FP-RGB]

Subaddress EF

D4-D0 LBASDEL

(int) 10: default]

Activity stability delay

[FP-RGB]

(int) 10: default]

102

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress F0 (read only)

D7

LBELAA

Refer to F1h

[FP-RGB]

D6-D0

LBSLAA

Letter box detection: Start line of active area

[FP-RGB]

LBSLAA is measured in relation to VSYNC

Subaddress F1 (read only)

D7-D0

LBELAA

Letter box detection: End line of active area

[FP-RGB]

LBELAA is measured in relation to VSYNC

Subaddress F2 (read only)

D7

D6

D5

LBFORMAT

[FP-RGB]

Letter box detection: Format

0: 4:3 format

1: other format (letter box)

LBSUBTITLE

[FP-RGB]

Letter box detection: Subtitle flag

0: no subtitle

1: subtitle available

LBTOPTITLE

[FP-RGB]

Letter box detection: Toptitle flag

0: no toptitle

1: toptitle available

D4

D3

D2

D1

D0

GRADISSTABLE

[FP-RGB]

Letter box detection: gradient is stable

internal value, only for test purposes

TOPTITLE

[FP-RGB]

LBD: upper area contains high activity

internal value, only for test purposes

SUBTITLE

[FP-RGB]

LBD: lower area contains high activity

internal value, only for test purposes

NOGRADFOUND

[FP-RGB]

LBD: no gradient found

internal value, only for test purposes

SWITCHTO43

[FP-RGB]

LBD: switch to 4:3 format

internal value, only for test purposes

Subaddress F3 (read only)

D7

GRADELAA

[FP-RGB]

Refer to F4h

D6-D0

GRADSLAA

[FP-RGB]

LBD: Gradient start line of active area

internal value, only for test purposes

Subaddress F4 (read only)

D7-D0

GRADELAA

[FP-RGB]

LBD: Gradient end line of active area

internal value, only for test purposes

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VSP 94x2A

DATA SHEET

2

Table 3–8: I C bus command description, continued

Bit

Name

Description

Subaddress F5 (read only)

D3

D2

D1

D0

LPBLACK

[FP-RGB]

LBD: lower area contains medium brightness level

internal value, only for test purposes

UPBLACK

[FP-RGB]

LBD: upper area contains medium brightness level

internal value, only for test purposes

LPWHITE

[FP-RGB]

LBD: lower area contains high brightness level

internal value, only for test purposes

UPWHITE

[FP-RGB]

LBD: upper area contains high brightness level

internal value, only for test purposes

Subaddress F6h (Read-only, compatible to 940X family)

D7-D5

VERSION

[CP-I2C]

Version Of VSP 94xxX Family:

‘001’: VSP 94x5B

‘010’: VSP 94x2A

‘011’: VSP 94x7B

‘101’: VSP 94x9C

others: reserved

D4

SLS

[CP-I2C]

Line Standard At Device Output

‘0’: 100 Hz (VSP 9402A, VSP 9412A)

‘1’: 50 Hz (VSP 9432A, VSP 9442A)

D3-D1

REV

[CP-I2C]

Revision of VSP94x2A

‘000’: A23 or below

‘001’: A31 or A32

‘010’: B13 or B14

Subaddress FEh

2

FE

Subaddress FFh

FF

Any value to this subaddress executes previous I C protocolls immediately

2

Any value to this subaddress executes previous I C protocolls according to the

take-over-mechanism (dedicated v-pulse, V20, V40, V36)

104

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DATA SHEET

VSP 94x2A

4. Specifications

4.1. Outline Dimensions

Fig. 4–1:

3

PMQFP80-1: Plastic Metric Quad Flat Package, 80 leads, 14 × 14 × 2 mm

Ordering code: VK

Weight approximately 0.96 g

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VSP 94x2A

DATA SHEET

1)

4.2. Pin Connections and Short Descriptions for VSP 9402 and VSP 9412

1)

For VSP 9412, the pin connections differ for pins: 1, 2, 3, 75, 76, 77, 78, 79 ,80 (see Section 4.3. on page 109).

No.

Pin Name

Type

Connection

(If not used)

Short Description

1

2

3

4

5

6

7

8

VDDDACY

AYOUT

S/I

O/I

S/I

S

DAC (Y)

Y output

VSSDACY

VSSD2

DAC (Y)

Supply voltage for digital (0 V digital)

Supply voltage for digital (1.8 V digital)

VDDD2

S

2

SDA

I/O

I

I C-Bus data

TMS

Testmode select (Connected to vdd33)

Separate V input for 656 / BLANK output

1)

656VIN/BLANK

I/O

Connect to

Vss and dis-

able blank

9

656CLK

656IO7

VSSP2

VDDP2

SCL

I/O

S

Leave open

Digital input / output clock

10

11

12

13

14

Digital input / output (MSB)

Supply voltage for digital (0 V pad)

Supply voltage for digital (3.3 V pad)

S

2

I

I C-Bus clk

2)

V

I

Connect to

Vss

Vertical pulse for RGB input

15

16

17

656IO6

656IO5

HOUT

I/O

O

Leave open

Digital input / output

Horizontal output (Single or double scan, depen-

dent on version)

3)

18

19

20

21

22

23

H50

O

Leave open

Hout 50 Hz (with skew)

2

ADR / TDI

I

I C address / test data in

4)

V50

O

Leave open

Vout 50 Hz

656IO4

656IO3

VOUT

I/O

O

Digital input / output

Vertical output (Single or double scan, dependent

on version)

24

25

26

RESET

VDDP3

VSSP3

I

Reset input (Reset when low)

S

Supply voltage for digital (0 V pad)

Supply voltage for digital (3.3 V pad)

106

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DATA SHEET

VSP 94x2A

No.

Pin Name

Type

Connection

(If not used)

Short Description

27

28

29

30

31

32

33

34

35

36

37

CLKOUT

VDDD3

VSSD3

656IO2

656IO1

656IO0

VSSD4

VDDD4

VDDAFBL

VSSAFBL

FBL1

O

S

Leave open

Output clock (27 MHz nom.)

Supply voltage for DRAM (1.8 V digital)

Supply voltage for digital (0 V digital)

Digital input / output

S

I/O

S

Leave open

Digital input / output

Digital input / output (LSB)

Supply voltage for digital (0 V digital)

Supply voltage for digital 1.8 V digital

Supply voltage for FBL (1.8 V)

Supply voltage for FBL (0 V)

S

I

Connect to

Vss

Fast Blank input 1 (H1) (Analog input)

38

39

40

41

FBL2

RIN1

GIN1

BIN1

I

Connect to

Vss

Fast Blank input 2 (H2) (Analog input)

R or V in1 (Analog input)

Connect to

Vss

Connect to

Vss

G or Y in1 (Analog input)

Connect to

Vss

B of U in1 (Analog input)

42

43

44

45

46

VDDARGB

VSSARGB

VDD33RGB

VSS33RGB

RIN2

S

I

Supply voltage for RGB (1.8 V)

Supply voltage for RGB (0 V)

Supply voltage RGB (3.3 V)

Supply voltage RGB (0 V)

R or V in2 (Analog input)

Connect to

Vss

47

48

49

GIN2

BIN2

I

Connect to

Vss

G or Y in2 (Analog input)

B of U in2 (Analog inpu)

Supply voltage for digital (0 V)

I

Connect to

vss

5)

VSSD5

S

Connect to

Vss

50

51

52

VDDAC1

VSSAC1

CVBS1

S

I

Supply voltage CVBS1 (1.8 V)

Supply voltage CVBS1 (0 V)

CVBS input (Analog input)

Connect to

Vss

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VSP 94x2A

DATA SHEET

No.

Pin Name

CVBS2

CVBS3

CVBS4

CVBS5

CVBS6

CVBS7

Type

Connection

(If not used)

Short Description

53

54

55

56

57

58

I

Connect to

Vss

CVBS input (Analog input)

CVBS input or Y1 (Analog input)

CVBS input or C1 (Analog input)

CVBS input or Y2 (Analog input)

CVBS input or C2 (Analog input)

Connect to

Vss

Connect to

Vss

Connect to

Vss

Connect to

Vss

Connect to

Vss

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

VDD33C

VSS33C

CVBSO3

CVBSO2

CVBSO1

VDDAC2

VSSAC2

VDDD1

S

O

S

O

I

Supply voltage CVBS (3.3 V)

Supply voltage CVBS (0 V)

CVBS output 3 (Analog output)

CVBS output 2 (Analog output)

CVBS output 1 (Analog output)

Supply voltage CVBS2 (1.8 V)

Supply voltage CVBS2 (0 V)

Leave open

Supply voltage for digital (1.8 V digital)

Supply voltage for digital (0 V digital)

Supply voltage for PLL (1.8 V)

Crystal connection 2

VSSD1

VDDAPLL

XOUT

XIN

Crystal connection 1

TCLK

I

Testclock

VDDP1

S

I/O

Supply voltage for digital (3.3 V pad)

Supply voltage for digital (0 V pad)

Separate H input for 656 / 20.25 clock output

VSSP1

656HIN/CLKF20

Connect to

Vss and dis-

able clock

75

76

77

78

79

VDDDACV

AVOUT

S/I

O/I

S/I

O/I

Leave open

DAC (V) (27 MHz nom.)

V output

VSSDACV

VDDDACU

AUOUT

DAC (V)

DAC (U)

U output

108

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DATA SHEET

VSP 94x2A

No.

Pin Name

Type

Connection

(If not used)

Short Description

80

VSSDACU

S/I

DAC (U)

1)

In VSP 9402, A31 (and higher) and in VSP 94xxA/B/C, this pin is shared by 656vin and blank.

In VSP 94xxB and VSP 94xxC, this pin is shared by v and intr (C800 controller output).

In VSP 94xxB and VSP 94xxC, this pin is shared by h50 and irq (Data-slicer-interrupt).

In VSP 94xxB and VSP 94xxC, this pin is shared by v50 and blank.

2)

3)

4)

5)

This pin is not used and not bonded in VSP 9402A. The use of this pin in VSP 94xxB/C will be V

.

SS

For upgradability, it is recommended to not leave this pin open.

4.3. Differing Pin Connections and Short Descriptions for VSP 9412

Pin No.

Pin Name

Type

Connection

(If not used)

Short Description

1

I656I5

I656I6

I656I7

I656ICLK

I656I0

I656I1

I656I2

I656I3

I656I4

S/I

O/I

S/I

O/I

S/I

O/I

S/I

Leave open

656 input

2

656 input

3

656 input (MSB)

656 input clock

656 input (LBS)

656 input

75

76

77

78

79

80

656 input

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VSP 94x2A

DATA SHEET

4.4. Pin Configurations

VSSAC1

CVBS1

CVBS2

CVBS3

CVBS4

CVBS5

CVBS6

CVBS7

VDD33C

VSS33C

VDDAC1

VSSD5

BIN2

GIN2

RIN2

VSS33RGB

VDD33RGB

VSSARGB

VDDARGB

BIN1

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

CVBSO3 61

CVBSO2 62

CVBSO1 63

VDDAC2 64

VSSAC2 65

VDDD1 66

40 GIN1

39 RIN1

38 FBL2

37 FBL1

36 VSSAFBL

35 VDDAFBL

34 VDDD4

33 VSSD4

32 656IO0

31 656IO1

30 656IO2

29 VSSD3

28 VDDD3

27 CLKOUT

26 VSSP3

25 VDDP3

24 RESET

23 VOUT

22 656IO3

21 656IO4

VSSD1 67

VDDAPLL 68

XOUT 69

XIN 70

VSP 9402 A

TCLK 71

VDDP1 72

VSSP1 73

656HIN/CLKF20 74

VDDDACV 75

AVOUT 76

VSSDACV 77

VDDDACU 78

AUOUT 79

VSSDACU 80

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

VDDACY

V50

AYOUT

VSSDACY

VSSD2

VDDD2

SDA

TMS

656VIN/BLANK

656CLK

ADR/TDI

H50

HOUT

656IO5

656IO6

V

SCL

VDDP2

VSSP2

656IO7

Fig. 4–2: PMQFP80-1 Package (Version VSP 9402A)

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DATA SHEET

VSP 94x2A

VSSAC1

CVBS1

CVBS2

CVBS3

CVBS4

CVBS5

CVBS6

CVBS7

VDD33C

VDDAC1

VSSD5

BIN2

GIN2

RIN2

VSS33RGB

VDD33RGB

VSSARGB

VDDARGB

VSS33C

BIN1

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

CVBSO3 61

CVBSO2 62

CVBSO1 63

VDDAC2 64

VSSAC2 65

VDDD1 66

VSSD1 67

VDDAPLL 68

XOUT 69

40 GIN1

39 RIN1

38 FBL2

37 FBL1

36 VSSAFBL

35 VDDAFBL

34 VDDD4

33 VSSD4

32 656IO0

31 656IO1

30 656IO2

29 VSSD3

28 VDDD3

27 CLKOUT

26 VSSP3

25 VDDP3

24 RESET

23 VOUT

22 656IO3

21 656IO4

XIN 70

VSP 9412 A

TCLK 71

VDDP1 72

VSSP1 73

656HIN/CLKF20 74

I656ICLK 75

I656I0 76

I656I1 77

I656I2 78

I656I3 79

I656I4 80

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

I656I5

V50

I656I6

I656I7

VSSD2

VDDD2

SDA

TMS

656VIN/BLANK

656CLK

656IO7

ADR/TDI

H50

HOUT

656IO5

656IO6

V

SCL

VDDP2

VSSP2

Fig. 4–3: PMQFP80-1 Package (Version VSP 9412A)

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VSP 94x2A

DATA SHEET

4.5. Pin Circuits

VDDP

VSSP

OUT

VSSB

Fig. 4–4: Supply Pins (Ground): VSSDACY,

VSSDACU, VSSDACV, VSS33C, VSS33RGB,

VSSP1, VSSP2, VSSP3

Fig. 4–8: Digital Output Pins: H50, V50, CLKOUT,

HOUT, VOUT

VDDP

IN

VSSB

Fig. 4–5: Supply Pins (Power 3.3 V): VDDDACY,

VDDDACU, VDDACV, VDD33C, VDD33RGB,

VDDP1, VDDP2, VDDP3

Fig. 4–9: Digital Input Pins: V, TMS, ADR/TDI, RESET

VDDP

OSCCLK

REF

(int.)

IN

OUT

XIN

XOUT

Fig. 4–6: Input/Output Pins (Crystal connection): XIN,

XOUT

2

Fig. 4–10: I C bus Pins: SDA, SCL

VDD

VDDP

VSS

500

OUT

IN

VSSB

Fig. 4–7: Supply Pins (Power 1.8 V and Ground):

VDDAC1, VSSAC1, VDDAC2, VSSAC2,

VDDARGB,VSSARGB, VDDAFBL, VSSAFBL,

VDDAPLL, VDDD1, VSSS1, VDDD2, VSSS2,

VDDD3, VSSS3, VDDD4, VSSS4

Fig. 4–11: Digital Input/Output Pins: 656IOX,656CLK,

656HIN/CLKF20, 656VIN/BLANK

112

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DATA SHEET

VSP 94x2A

VDDDACx

VDD

display

DAC

500

150

1V

Fig. 4–14: Analog Input Pins: CVBS1...CVBS7

(if cvbsx is not connected to any ADC)

Fig. 4–12: Analog Output Pins: AYOUT, AUOUT,

AVOUT

VDD

OUT

500

IN

Fig. 4–15: Analog Output Pins: CVBSO1...CVBSO3

Fig. 4–13: Analog Input Pins: RIN1, RIN2, GIN1,

GIN2, BIN1, BIN2, FBL1, FBL2, CVBS1...CVBS7

(if cvbsx is connected to any ADC)

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VSP 94x2A

DATA SHEET

4.6. Electrical Characteristics

Abbreviations

tbd = to be defined

vacant= not applicable

positive current values means current flowing into the chip

4.6.1. Absolute Maximum Ratings

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only. Functional operations of the device at these conditions in not implied Exposure to absolute

maximum rating conditions for extended periods will affect device reliability.

This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric

fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than abso-

lute maximum-rated voltages to this high-impedance circuit.

All voltages listed are referenced to ground except where noted.

All GND pins must be connected to a low-resistive ground plane close to the IC.

Table 4–1: Absolute Maximum Ratings

Symbol

Parameter

Pin Name

Limit Values

Max

Unit

Min

1)

T

Ambient Temperature

PMQFP80-1

A

2)

−10

70

°C

T

Case Temperature

PMQFP80-1

C

S

−10

−65

105

125

°C

T

Storage Temperature

3)

P

Maximum Power Dissipation

PMQFP80-1

MAX

DD1

1500

mW

V

4) 5)

V

Supply Voltages1

Supply Voltages2

VDDDx,

-0.3

2

VDDAFBL

VDDARGB

VDDAC1

VDDAC2

VDDAPLL

4) 5)

L

VDDPx,

3.6

V

DD2

VDD33C,

VDD33RGB,

VDDACU,

VDDACV

∆V

Internally Conected Power Supplies Groups of inter-

SUP

have to be connected externally

with an impedance of less than

0.05 Ω

nally conected

power supply

pins:

{VSSDx,

VSSPx},

{VDDDx},

{VDDPx},

{VDDACU/V}

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DATA SHEET

VSP 94x2A

Table 4–1: Absolute Maximum Ratings

Symbol

Parameter

Pin Name

Limit Values

Unit

Min

Max

∆V

Voltage Differences between not

internally connected supply pins of

the same nominal supply voltage

Groups of inde-

pendant

grounds:

-0.3

0.3

V

SUP

{VSSDx;

VSSPx},

{VSSARGB,

VSSAFBL,

VSS33RGB},

{VSSAC1,

VSSAC2,

VSS33C},

{VSSDACx},

Groups of inde-

pendant 1.8 V

supply voltages:

{VDDDx},

{VDDAC1,

VDDAC2},

{VDDARGB,

VDDAFBL},

{VDDAPLL}

Groups of inde-

pendant 3.3 V

supply voltages

{VDDPx},

{VDDACU/V},

{VDD33C},

{VDD33RGB}

2)

V

Input Voltage

All input pins

with reference to

their relevant

VDD

-0.3

V

+0.3

DD

V

I

Input Current at 0.4 V

Input Current at 2.4 V

All digital inputs

with pull-up

55

157

230

µA

V

I_low

All digital inputs

with pull-down

57

I_high

3)

V

Output Voltage

All output pins

with reference to

their relevant

VDD

-0.3

V

+0.3

DD2

O

2

I

Output Sink Current (at 0.4 V)

Output Source Current (at 2.4 V)

Output Sink Current (at 0.4 V)

I C pads

10.3

30.1

36

mA

O_low (I2C)

O_high(I2C)

O_low

2

I C pads

(open drain)

58.8

Digital outputs

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VSP 94x2A

DATA SHEET

Table 4–1: Absolute Maximum Ratings

Symbol

Parameter

Pin Name

Limit Values

Max

Unit

Min

I

Output Source Current (at 2.4 V)

Digital outputs

31.7

97.1

mA

O_high

¹⁾Measured on Micronas typical 2-layer (1s1p) board based on JESD - 51.2 Standard with maximum power consumption

allowed for this package

²⁾A power-optimized board layout is recommended. The case temperature mentioned in the “Absolute Maximum Ratings”

must not be exceeded at worst case conditions of the application.

³⁾Package limit

4)

V

(3.3 V nom.) must always be higher than V_DD1(1.8 V nom.) −0.3 V (even during power-up)

DD2

⁵⁾The deviation among all V_DD1or V_DD2supplies may never exceed 0.3 V.

116

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VSP 94x2A

4.6.2. Recommended Operating Conditions

Functional operation of the device beyond those indicated in the “Recommended Operating Conditions/Characteris-

tics” is not implied and may result in unpredictable behaivior, reduce reliability and lifetime of the device.

All voltage listed are referenced to ground except where noted.

Do not insert the device into a live socket. Instead, apply power by switching on the external power supply.

Symbol

Parameter

Pin Name

Limit Values

Typ

Unit

Min

Max

T

Ambient Operating Temperature

PMQFP80-1

A

1)

0

25

35

70

°C

T

Case Operating Temperature

PMQFP80-1

C

85

P

V

Maximum Power Dissipation

PMQFP80-1

MAX

700

mW

V

Supply voltages (3.3 V)

VDDP1,

VDDP2,

3.14

3.3

3.47

DDxx

VDDP3,

VDDACY,

VDDACU,

VDDACV,

VDD33C,

VDD33RGB

V

Supply voltages (1.8 V)

VDDAC1,

VDDAC2,

1.71

1.8

1.89

V

DDxx

VDDARGB,

VDDAFBL,

VDDAPLL;

VDDD1;

VDDD2;VDDD3;

VDDD4

V

Input voltage low

Input voltage high

TMS, ADR/TDI,

V, TCLK,

RESET,

1.0

V

in,L

1.7

in,H

656VIN/BLANK,

656HIN/,

656IOX,

656CLK,

I656IX,

I656ICLK

t

Active time reset

Load resistance

Load capacitance

RESET

1.3

10

µs

kΩ

pF

RES

R

C

AYOUT,

AUOUT,

AVOUT

L

tbd

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VSP 94x2A

DATA SHEET

Symbol

Parameter

Pin Name

Limit Values

Unit

Min

0.6

0.5

Typ

1.2

0.3

100

47

Max

V

Analog CVBS input voltage

Analog RGB input voltage

Analog FBL input voltage

CVBS1,

CVBS2,

CVBS3,

CVBS4,

CVBS5,

CVBS6,

CVBS7,

RIN1, RIN2,

GIN1, GIN2,

BIN1, BIN2,

FBL1, FBL2

1.8

1.5

V

i,CVBS

i,RGB

i,FBL

V

Analog chroma input voltage (burst)

Input coupling capacitors CVBS

Input coupling capacitors RGB/FBL

Source resistance

V

nF

kΩ

0.1

Crystal Specification

Frequency (fundamental)

3)

f

XIN,

20.248 20.25

20.252 MHz

xtal

XOUT

∆f

/f

Maximum permissible frequency

deviation

−100

100

ppm

max

xtal

3)

∆f/f

Recommended permissible frequency

deviation

−40

0

40

ppm

xtal

4)

C

R

C

Load capacitance

13

pF

W

L

S

1

0

Series resistance

tbd

25

30

Motional capacitance

Parallel capacitance

20

fF

7

pF

C

External load capacitance to ground

13

L,EXT

1)

A power-optimized board layout is recommended. The Case Operating Temperature mentioned in the Recom-

mended Operating Conditions must not be exceeded at worst case conditions of the application

2)

3)

4)

P

variation: User-determined by application circuit for I/O’s

MAX

Values outside this range may cause color decoding failures.

After (subcarrier) adjustment // including temperature and aging deviations

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DATA SHEET

VSP 94x2A

4.6.3. Characteristics

For Min./Max. values:

at T = 0 to 70°C,

A

f

=20.25MHz,

CLOCK

V

= 3.14 to 3.47 V,

= 1.71 to 1.89V

SUP3.3V

SUP1.8V

For typical values:

at T = 25°C,

A

f

= 20.25MHz,

CLOCK

V

= 3.14 to 3.47 V,

= 1.71 to 1.89V

SUP3.3V

SUP1.8V

4.6.3.1. General Characteristics

Symbol

Parameter

Pin Name

Unit

Test Conditions

LImit Values

Min.

Typ.

220

65

Max.

I

Average total supply current

mA

DDtot 1.8 V

I

DDtot 3.3 V

I

Average supply current in

power-down-mode

74

STANDBY= ‘10’

DDPD

1.8 V

I

Average supply current in

power-down-mode

36

mA

DDPD

3.3 v

P_tot

Total power dissipation

0.61

0.27

0.8

W

P_totPD

Total power dissipation in

power-down-mode

STANDBY= ‘10’

Digital Inputs

C

I

Input capacitance

TMS,ADR/TDI,

V, TCLK,

RESET,

7

pF

µA

Input leakage current

−10

10

Incl. leakage current of

SDA output stage

656VIN/

BLANK,

656HIN/,

656IOX,

656CLK,

I656IX,

I656ICLK

Digital Outputs

V_OH

V_OL

I_OH

I_OL

Output voltage high

H50, V50,

CLKOUT,

HOUT,

2.5

V_dd2

0.6

V

Output voltage low

Output current high

Output current low

V

VOUT

mA

Clock Outputs

t

CLKOUT cycle time

CLKOUT

656CLK

37

ns

%

ns

%

CLKOUT duty cycle

656CLK cycle time

656CLK duty cycle

40

60

Micronas

Aug. 16, 2004; 6251-552-1DS

119

VSP 94x2A

DATA SHEET

Symbol

Parameter

Pin Name

Unit

Test Conditions

LImit Values

Min.

−100

−1

Typ.

Max.

Analog CVBS Front-end

Input leakage current

CVBS1,

CVBS2,

CVBS3,

CVBS4,

CVBS5,

CVBS6,

CVBS7

100

1

nA

Clamping inactive

Settled state

C

Input capacitance

7

pF

I

Input clamping error

Input clamping current

LSB

µA

|I

|

Dependent on clamping

error

CLP

DNL

INL

CT

Differential nonlinearity

Integral nonlinearity

-0.5

-1

0.5

1

LSB

dB

Nominal conditions

Crosstalk between CVBS

inputs

-50

f_sig<5 MHz

BW

V_in

Bandwidth

7

MHz

V

-3 dB

Input voltage

0.6

0.9

1.2

1.8

1.1

A_cvbso

CVBS output amplification

CVBSO1,

CVBSO2,

CVBSO3

Analog RGBF Front-end

Input leakage current

RIN1, RIN2,

BIN1, BIN2,

GIN1, GIN2,

FBL1, FBL2

−100

−1

100

1

nA

Clamping inactive

Settled state

C

CVBS input capacitance

Input clamping error

7

pF

I

LSB

µA

|I

|

Input clamping current

Dependent on clamping

error

CLP

DNL

INL

CT

Differential nonlinearity

Integral nonlinearity

−0.5

−1

0.5

1

LSB

dB

Nominal conditions

Crosstalk between RGB

inputs

-50

BW

V_in

Bandwidth

10

MHz

V

−3 dB

Input voltage

0.5

1.2

1.5

Digital To Analog Converters

DNL

INL

Differential nonlinearity

AUOUT,

AVOUT

−1

−2

1

2

LSB

V

Nominal conditions

Integral nonlinearity

U_OL

Full range output voltage

0.4

1.9

Nominal conditions PKLY/

U/V=min

U_OH

Full range output voltage

Output matching

V

Nominal conditions PKLY/

U/V=max

−3

3

%

120

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

Symbol

Parameter

Pin Name

Unit

Test Conditions

LImit Values

Min.

Typ.

Max.

Color Decoder/Synchronization and Luminance Processing

∆f_Hf

Horizontal PLL pull-in-range

ACC range

±4.9

%

Based on 15625 kHz

Nominal crystal frequency

−30

+6

+2

dB

Hz

AGC range

−7.5

∆f_SC

Chroma PLL pull-in-range

±500

The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics spec-

ify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at

T = 25 °C and the given supply voltage.

A

2

4.6.3.2. I C Bus Characteristics

Symbol

2

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Fast I C Bus (All Values are Referred to Min(V ) and Max(V ))

IH

IL

C

Capacitive load/bus line

SDA/SCL rise/fall times

SDA/SCL

400

300

pF

ns

b

t , t

20+$

1300

$=0.1 C /pF

b

R

F

t

Inactive time before start

of transmission

BUF

2

f

t

I C clock frequency

SCL

0

400

kHz

ns

SCL

SCL low time

SCL high time

1300

600

100

0

LOW

HIGH

Set-up time start condition SDA

Hold time start condition

Set-up time DATA

SU;STA

HD;STA

SU;DAT

HD;DAT

Hold time DATA

900

Set-up time stop condition

600

SU;STO

2

I C Bus pins

V

Threshold rise

Threshold fall

SDA, SCL

2.08

1.8

V

IHr

IL

Micronas

Aug. 16, 2004; 6251-552-1DS

121

VSP 94x2A

DATA SHEET

t

R

f

t

HIGH

t

LOW

t

SU;STO

SU;STA

SDA

t

HD;DAT

SU;DAT

t

HD;STA

t

IN

SP

t

BUF

t

AA

SDA

OUT

2

Fig. 4–16: I C bus timing data

I²C selectable

VSP 940xA

VSP 940xB

VSP 943xB

VSP 940xB

VSP 943xB

analog

output

analog

output

single-scan

656 output (943x)

or

single-scan

656 input

(port 1)

double-scan

656 output (940x)

Fig. 4–17: Signal Flow 940x

VSP 941xA

VSP 941xB

VSP 944xB

single-scan

656 input

(port 2)

single-scan

656 output (944x)

or

double-scan

656 output (941x)

Fig. 4–18: Signal flow 941x, 944x, 942x

122

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

5. Application Circuit

L1 10

H

L3 10

H

34

33

28

29

5

25

26

12

11

72

73

59

60

44

45

1

+1V8

vddd4

vssd4

vddd3

vssd3

vddd2

vssd2

vddd1

vssd1

vddargb

vssargb

vddapll

vddac2

vssac2

vddac1

vssac1

vddafbl

vssafbl

tclk

vddp3

vssp3

+3.3 V

C37

100nF

C36

C47

100nF

C46

C49

10

C39

10

F

vddp2

L2 10

H

100nF

vssp2

100nF

vddp1

C35

100nF

C45

100nF

4

C38

10

vssp1

L4 10

F

66

67

42

43

68

64

65

50

51

35

36

71

19

7

C34

100nF

vdd33c

vss33c

+3.3 V

C44

100nF

C48

10

F

vdd33rgb

vss33rgb

vdddacy

vssdacy

vdddacu

vssdacu

vdddacv

vssdacv

(reserved)

C43

100nF

C33

100nF

C42

100nF

3

C32

100nF

20.25MHz

656HIN

656ICLK

656IN7

656IN6

656IN5

656IN4

656IN3

656IN2

656IN1

656IN0

78

80

75

77

49

C41

100nF

J1

C31

100nF

C40

100nF

IC1

+3.3V

C30

100nF

BLANK

J2

B2h

B0h

I2C

Address

J3

VSP

adr/tdi

tms

656VIN

9402A

74

8

656hin/clkf20

656vin/blank

R21...R27: 8x 75

9

656clk

656io7

656io6

656io5

656io4

656io3

656io2

656io1

656io0

clkout

hout

656OCLK

656OUT7

656OUT6

656OUT5

656OUT4

656OUT3

656OUT2

656OUT1

C29 47nF

C28 47nF

C27 47nF

46

47

48

38

39

40

41

37

14

58

57

56

55

54

53

52

13

6

10

15

16

21

22

30

31

32

27

17

23

2

RIN2

GIN2

BIN2

FBL2

rin2

MQFP80

gin2

bin2

fbl2

C25 47nF

C24 47nF

C23 47nF

rin1

RIN1

GIN1

stepping

gin1

bin1

fbl1

BIN1

B13

-- / 47 nF

C22

656OUT0

CLKOUT

HOUT

HIN1/FBL1

VIN1

v

C21 100 nF

C20 100 nF

C19 100 nF

C18 100 nF

C17 100 nF

C16 100 nF

C15 100 nF

cvbs7

cvbs6

cvbs5

cvbs4

cvbs3

cvbs2

cvbs1

scl

CVBS7

CVBS6

CVBS5

CVBS4

CVBS3

CVBS2

CVBS1

vout

VOUT

ayout

79

76

61

62

63

18

20

auout

avout

cvbso3

cvbso2

cbbso1

h50

CVBSO3

CVBSO2

CVBSO1

H50

sda

24

reset

v50

R1...R7: 7x 75

V50

xin

70

xout

69

+3V3

+5V

Q1

20M25

R20

51

R21

51

C52

F

C5

22pF*

C6

22pF*

R8

3k3

R9

3k3

T1

33

R19

Y100

U100

V100

SCL

SDA

C53

33

SN7002

51

*values are PCB and

crystal dependent

F

T2

C54

33

F

only for 5V I²C master

RESET

T3 T4 T5

3*BC807

buffer not necessary when short

connection to backend-processor

Fig. 5–1: VSP 9402A

Micronas

Aug. 16, 2004; 6251-552-1DS

123

VSP 94x2A

DATA SHEET

L1 10

H

L3 10

H

34

33

28

29

5

25

26

12

11

72

73

59

60

44

45

1

+1V8

vddd4

vssd4

vddp3

vssp3

+3.3 V

C37

100nF

C36

C47

100nF

C46

C49

10

C39

10

F

vddd3

vssd3

vddp2

L2 10

H

100nF

vssp2

100nF

vddd2

vssd2

vddp1

C35

100nF

C45

100nF

4

C38

10

vssp1

L4 10

F

66

67

42

43

68

64

65

50

51

35

36

71

19

7

C34

100nF

vddd1

vssd1

vdd33c

vss33c

+3.3 V

C44

100nF

C48

10

F

vddargb

vssargb

vddapll

vddac2

vssac2

vddac1

vssac1

vddafbl

vssafbl

tclk

vdd33rgb

vss33rgb

vdddacy

vssdacy

vdddacu

vssdacu

vdddacv

vssdacv

(reserved)

C43

100nF

C33

100nF

C42

100nF

3

C32

100nF

20.25MHz

656HIN

78

80

75

77

49

C41

100nF

J1

C31

100nF

C40

100nF

IC1

+3.3V

C30

100nF

BLANK

J2

B2h

B0h

I2C

Address

J3

VSP

adr/tdi

656VIN

9

9412A _656clk

tms

656OCLK

656OUT7

74

8

10

15

16

21

22

30

31

32

27

17

23

656hin/clkf20

656vin/blank

R21...R27: 8x 75

656io7

656io6

656io5

656io4

656io3

656io2

656io1

656io0

656OUT6

656OUT5

656OUT4

656OUT3

656OUT2

656OUT1

656OUT0

C29 47nF

C28 47nF

C27 47nF

46

47

48

38

39

40

41

37

14

58

RIN2

GIN2

BIN2

FBL2

rin2

MQFP80

gin2

bin2

fbl2

C25 47nF

C24 47nF

C23 47nF

rin1

RIN1

GIN1

stepping

gin1

bin1

fbl1

BIN1

B14 clkout

CLKOUT

HOUT

-- / 47 nF

C22

HIN1/FBL1

VIN1

hout

vout

v

VOUT

C21 100 nF

cvbs7

cvbs6

cvbs5

cvbs4

cvbs3

cvbs2

cvbs1

scl

CVBS7

CVBS6

CVBS5

CVBS4

CVBS3

CVBS2

CVBS1

75

3

i656iclk

i656i7

i656i6

i656i5

i656i4

i656i3

i656i2

i656i1

i656i0

656ICLK

C20 100 nF 57

656IN7

656IN6

656IN5

656IN4

656IN3

656IN2

656IN1

656IN0

C19 100 nF

56

55

54

53

52

13

6

2

C18 100 nF

C17 100 nF

C16 100 nF

C15 100 nF

1

80

79

78

77

76

sda

24

reset

R1...R7: 7x 75

xin

70

xout

69

+3V3

Q1

20M25

C5

22pF*

C6

22pF*

R8

3k3

R9

3k3

T1

SCL

SDA

SN7002

*values are PCB and

crystal dependent

T2

only for 5V I²C master

RESET

Fig. 5–2: VSP 9412A

124

Aug. 16, 2004; 6251-552-1DS

Micronas

DATA SHEET

VSP 94x2A

5.1. Application Overview

RGB

H, V

RGB

YUV

DVD

YC

SDA 9402

PRIMUS

Camcorder

CLK

CVBS

VCR

RGB

YUV

H, V

SDA 9380

EDDC

CVBS

Tuner

IF

HD, VD,

EW

M

U

X

CVBS, YC

CVBS

SDA 6000

M2

RGB, FBL, COR

SDA 5550

TVTPro

Fig. 5–3: Application Overview with SDA 9380

RGB

H, V

digital656

MPEG

RGB

YUV

DVD

VSP 9412A

PRIMUS

YC

Camcorder

CLK

CVBS

VCR

RGB

DS656

H, V

CVBS

DDP 3315C/

DDP 3316C

Tuner

IF

HD, VD,

EW

CVBS, YC

CVBS

SDA 6000

M2

RGB, FBL, COR

SDA 5550

TVTPro

Fig. 5–4: Application Overview with DDP 3315C/DDP 3316C

Micronas

Aug. 16, 2004; 6251-552-1DS

125

VSP 94x2A

DATA SHEET

6. Data Sheet History

1. Preliminary Data Sheet: “VSP 94x2A-B13/B14

Powerful Scan-Rate Converter including Multistan-

dard Color Decoder”, July 26, 2002, 6251-552-4PD.

Fourth release of the preliminary data sheet.

Mayor changes:

2

– New I C registers added

2. Data Sheet: “VSP 94x2A-B13/B14

Powerful Scan-Rate Converter including Multistan-

dard Color Decoder”, Aug. 16, 2004,

6251-552-1DS. First release of the data sheet.

Major changes:

– Version VSP 9432A and VSP 9442A omitted

– Section 4. Specification updated

– Application diagrams updated

– Subadress 7Bh updated

All information and data contained in this data sheet are without any

commitment, are not to be considered as an offer for conclusion of a

contract, nor shall they be construed as to create any liability. Any new

issue of this data sheet invalidates previous issues. Product availability

and delivery are exclusively subject to our respective order confirmation

form; the same applies to orders based on development samples deliv-

ered. By this publication, Micronas GmbH does not assume responsibil-

ity for patent infringements or other rights of third parties which may

result from its use.

Further, Micronas GmbH reserves the right to revise this publication and

to make changes to its content, at any time, without obligation to notify

any person or entity of such revisions or changes.

No part of this publication may be reproduced, photocopied, stored on a

retrieval system, or transmitted without the express written consent of

Micronas GmbH.

Micronas GmbH

Hans-Bunte-Strasse 19

D-79108 Freiburg (Germany)

P.O. Box 840

D-79008 Freiburg (Germany)

Tel. +49-761-517-0

Fax +49-761-517-2174

E-mail: docservice@micronas.com

Internet: www.micronas.com

Printed in Germany

Order No. 6251-552-1DS

126

Aug. 16, 2004; 6251-552-1DS

Micronas


型号：	9402AVK
厂家：	TDK ELECTRONICS
描述：	Consumer Circuit, CMOS, PQFP80, 14 X 14 MM, 2 MM HEIGHT, PLASTIC, MS-022, MQFP-80 商用集成电路
文件：	总126页 (文件大小：1673K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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