BSP3505DPP [TDK]
Consumer Circuit, CMOS, PDIP64, SHRINK, PLASTIC, DIP-64;
| 型号： | BSP3505DPP |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | Consumer Circuit, CMOS, PDIP64, SHRINK, PLASTIC, DIP-64 光电二极管 |
| 文件： | 总40页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
BSP 3505D
Baseband
Sound Processor
MICRONAS
Edition Oct. 21, 1998
6251-481-1PD
BSP 3505D
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
4
4
4
4
1.
Introduction
1.1.
1.2.
1.3.
BSP 3505D Integrated Functions
Features of the DSP-Section
Features of the Analog Section
5
5
5
6
6
6
2.
Architecture of the BSP 3505D
Analog Section and SCART Switching Facilities
Standby Mode
2.1.
2.1.1.
2.2.
2.3.
2.4.
BSP 3505DAudio Baseband Processing
Clock and Crystal Specifications
Digital Control Output Pins
2
7
3.
I C Bus Interface: Device and Subaddresses
8
3.1.
Protocol Description
2
9
3.2.
Proposal for BSP 3505D I C Telegrams
9
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.3.
Symbols
9
Write Telegrams
Read Telegrams
Examples
9
9
2
10
Start Up Sequence: Power Up and I C-Controlling
11
11
12
12
13
13
14
14
15
15
16
17
17
17
17
18
18
18
19
19
19
20
20
20
20
4.
Programming the BSP 3505D
Register ‘MODE_REG’
4.1.
4.2.
DSP Write Registers: Table and Addresses
DSP Read Registers: Table and Addresses
DSP Write Registers: Functions and Values
Volume Loudspeaker Channel
Balance Loudspeaker Channel
Bass Loudspeaker Channel
Treble Loudspeaker Channel
Loudness Loudspeaker Channel
Spatial Effects Loudspeaker Channel
Volume SCART1
4.3.
4.4.
4.4.1.
4.4.2.
4.4.3.
4.4.4.
4.4.5.
4.4.6.
4.4.7.
4.4.8.
4.4.9.
4.4.10.
4.4.11.
4.4.12.
4.4.13.
4.4.14.
4.5.
Channel Source Modes
Channel Matrix Modes
SCART Prescale
Definition of Digital Control Output Pins
Definition of SCART-Switching Facilities
Beeper
Automatic Volume Correction (AVC)
DSP Read Registers: Functions and Values
Quasi-Peak Detector
4.5.1.
4.5.2.
4.5.3.
4.5.4.
4.5.5.
BSP Hardware Version Code
BSP Major Revision Code
BSP Product Code
BSP ROM Version Code
2
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
Contents, continued
Page
Section
Title
21
21
23
26
30
31
31
32
34
5.
Specifications
5.1.
Outline Dimensions
5.2.
Pin Connections and Short Descriptions
Pin Configurations
5.3.
5.4.
Pin Circuits
5.5.
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Characteristics
5.5.1.
5.5.2.
5.5.3.
37
40
40
6.
7.
8.
Application Circuit
Appendix A: BSP 3505D Version History
Data Sheet History
MICRONAS INTERMETALL
3
BSP 3505D
PRELIMINARY DATA SHEET
Baseband Sound Processor
1.2. Features of the DSP-Section
– flexible selection of audio sources to be processed
Release Notes: The hardware description in this
document is valid for the BSP 3505D version A2.
– digital baseband processing: volume, bass, treble,
loudness, and spatial effects
1. Introduction
– simple controlling of volume, bass, treble, loudness,
and spatial effects
The BSP 3505D is designed as a single-chip Baseband
Sound Processor for applications in analog and digital
TV sets, video recorders, and satellite receivers.
1.3. Features of the Analog Section
– two selectable analog stereo audio baseband inputs
(= two SCART inputs)
input level: ≤2 V RMS,
The IC is produced in submicron CMOS technology, and
is fully pin and software compatible to the MSP 34xx
family. The BSP 3505D is available in a PLCC68,
PSDIP64, PSDIP52, PQFP80, and in a PQFP44 pack-
age.
input impedance: ≥25 kΩ
– one selectable analog mono input:
input level: ≤2 V RMS,
Note: The BSP 3505D version has reduced control reg-
isters and less functional pins. The remaining registers
are software compatible to the MSP 34xxD. The pinning
is compatible to the MSP 34xxD.
input impedance: ≥15 kΩ
– stereo high-quality A/D converter, S/N-Ratio: ≥85 dB
– 20 Hz to 20 kHz bandwidth for SCART-to-SCART-
copy facilities
– loudspeaker: stereo four-fold oversampled D/A-con-
verter
output level per channel: max. 1.4 VRMS
output resistance: max. 5 kΩ
S/N-ratio: ≥85 dB at maximum volume
max. noise voltage in mute mode: ≤10 µV
(BW: 20 Hz ...16 kHz)
1.1. BSP 3505D Integrated Functions
– Stereo baseband input via integrated A/D converters
– Two stereo D/A converters
– AVC: Automatic Volume Correction
– Bass, treble, volume, loudness processing
– Full SCART in/out matrix without restrictions
– spatial effect (pseudostereo / basewidth enlargement)
– Digital control output pins D_CTR_OUT0/1
– Reduction of necessary controlling
– stereo four-fold oversampled D/A converter supplying
a stereo SCART-output
output level per channel: max. 2 V RMS,
output resistance: max. 0.5 kΩ,
S/N-Ratio: ≥85 dB (20 Hz...16 kHz)
2
– Less external components
2
I C
2
2
Loudspeaker
OUT
MONO IN
BSP 3505D
2
2
SCART1 IN
SCART2 IN
SCART
OUT
Fig. 1–2: Main I/O Signals BSP 3505D
FM/AM Mono
SIF
Loudspeaker
Tuner
VIF
BSP 3505D
2
2
2
SCART
SCART1
SCART2
SCART1
Output
SCART
Inputs
Fig. 1–1: Typical BSP 3505D application
4
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
SCART_IN
2. Architecture of the BSP 3505D
SC1_IN_L/R
Fig. 2–2 shows a simplified block diagram of the IC. Its
architecture is split into two main functional blocks:
to Audio Baseband
Processing (DSP_IN)
SC2_IN_L/R
A
D
1. DSP (digital signal processing) section performing
audio baseband processing
SCARTL/R
2. analog section containing two A/D-converters,
four D/A-converters, and SCART-switching facilities.
MONO_IN
S1
2.1. Analog Section and SCART Switching Facilities
intern. Sig-
nal Lines
SCART_OUT
The analog input and output sections include full matrix
switching facilities, which are shown in Fig. 2–1.
Pins
The switches are controlled by the ACB bits defined in
the audio processing interface (see section 4. Program-
ming the BSP 3505D).
SC1_OUT_L/R
from Audio Baseband
Processing (DSP_OUT)
D
SCART1_L/R
A
S2
2.1.1. Standby Mode
Fig. 2–1: SCART-Switching Facilities (see 4.4.12.)
positions show the default configuration after Power
On Reset.
If the BSP 3505D is switched off by first pulling STAND-
BYQ low, and then disconnecting the 5 V, but keeping
the 8 V power supply (‘Standby’-mode), the switches
S1 and S2 (see Fig. 2–1) maintain their position and
function. This facilitates the copying from selected
SCART-inputs to SCART-output in the TV-set’s standby
mode.
Note: SCART_OUT is undefined after RESET!
In case of power-on start or starting from standby, the IC
switches automatically to the default configuration,
shown in Fig. 2–1. This action takes place after the first
2
I C transmission into the DSP part. By transmitting the
ACB register first, the individual default setting mode of
the TV set can be defined.
XTAL_OUT
XTAL_IN
Clock
D_CTR_OUT0/1
DSP
LOUD-
SPEAKER L
DACM_L
D/A
Loudspeaker
DACM_R
LOUD-
SPEAKER R
D/A
Mono
MONO_IN
SC1_IN_L
A/D
A/D
D/A
D/A
SC1_OUT_L
SCARTL
SCARTR
SCART1_L
SCART1_R
SCART1
SCART
SC1_OUT_R
SC1_IN_R
SC2_IN_L
SCART2
SCART Switching Facilities
SC2_IN_R
Fig. 2–2: Architecture of the BSP 3505D
MICRONAS INTERMETALL
5
BSP 3505D
PRELIMINARY DATA SHEET
2.2. BSP 3505D Audio Baseband Processing
All audio baseband functions are performed by digital
signal processing (DSP). The DSP functions are
grouped into three processing parts: input preproces-
sing, channel source selection, and channel postpro-
cessing (see Fig. 2–3).
The input preprocessing is intended to form a standard-
ized signal level.
All input and output signals can be processed simulta-
neously.
2.3. Clock and Crystal Specifications
Remark on using the crystal: External capacitors at
each crystal pin to ground are required. The higher the
capacitors, the lower the clock frequency results.
The nominal free running frequency should match the
center of the tolerance range between 18.433 and
18.431 MHz as closely as possible.
2.4. Digital Control Output Pins
The static level of two output pins of the BSP 3505D
(D_CTR_OUT0/1) is switchable between HIGH and
2
LOW by means of the I C-bus. This enables the control-
ling of external hardware controlled switches or other
2
devices via I C-bus (see section 4.4.11.)
SCARTL
SCARTR
Loudspeaker L
Volume
SCART
Loudspeaker
Channel
Matrix
Analog
Inputs
Bass
Treble
Loudspeaker
Outputs
ȍ
Loudness
AVC
Prescale
Balance
Loudspeaker R
Beeper
SCART1_L
SCART1_R
Volume
SCART1
Channel
Matrix
SCART
Output
Quasi peak readout L
Quasi peak readout R
Quasi-Peak
Detector
SCART
Internal signal lines (see Fig. 2–1)
Fig. 2–3: Audio Baseband Processing (DSP-Firmware)
6
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
2
3. I C Bus Interface: Device and Subaddresses
Due to the internal architecture of the BSP 3505D the IC
cannot react immediately to an I C request. The typical
2
Asaslavereceiver, theBSP3505Dcanbecontrolledvia
I C bus. Access to internal memory locations is
achieved by subaddressing. The DSP processor part
has its own subaddressing register bank.
response time is about 0.3 ms for the DSP processor
part. If the receiver (BSP) can’t receive another com-
plete byte of data until it has performed some other func-
tion; for example, servicing an internal interrupt, it can
2
2
hold the clock line I C_CL LOW to force the transmitter
In order to allow for more BSP or MSP ICs to be con-
nected to the control bus, an ADR_SEL pin has been im-
plemented. With ADR_SEL pulled to high, low, or left
open, the BSP 3505D responds to changed device ad-
dresses. Thus, three identical devices can be selected.
into a wait state. The positions within a transmission
where this may happen are indicated by ’Wait’ in section
3.1. ThemaximumWait-periodoftheBSPduringnormal
operation mode is less than 1 ms.
2
I C-Bus conditions caused by BSP hardware problems:
By means of the RESET bit in the CONTROL register,
all devices with the same device address are reset.
In case of any internal error, the BSPs wait-period is ex-
tended to 1.8 ms. Afterwards, the BSP does not ac-
knowledge (NAK) the device address. The data line will
be left HIGH by the BSP and the clock line will be re-
leased. The master can then generate a STOPcondition
to abort the transfer.
The IC is selected by asserting a special device address
2
in the address part of an I C transmission. A device ad-
dress pair is defined as a write address (80, 84, or 88
)
hex
and a read address (81, 85, or 89 ). Writing is done by
hex
sending the device write address first, followed by the
subaddress byte, two address bytes, and two data by-
tes. Reading is done by sending the device write ad-
dress, followed by the subaddress byte and two address
bytes. Without sending a stop condition, reading of the
addresseddataiscompletedbysendingthedeviceread
By means of NAK, the master is able to recognize the er-
ror state and to reset the IC via I C-Bus. While transmit-
ting the reset protocol (s. 5.2.4.) to ‘CONTROL’, the
master must ignore the not acknowledge bits (NAK) of
the BSP.
2
2
address (81, 85, or 89 ) and reading two bytes of data.
A general timing diagram of the I C Bus is shown in
hex
Fig. 3–2.
2
Refer to Fig. 3–1: I C Bus Protocol and section 3.2. Pro-
2
posal for BSP 3505D I C Telegrams.
2
Table 3–1: I C Bus Device Addresses
ADR_SEL
Low
High
Left Open
Read
89
Mode
Write
80
Read
81
Write
84
Read
85
Write
88
BSP device address
hex
hex
hex
hex
hex
hex
2
Table 3–2: I C Bus Subaddresses
Name
Binary Value
Hex Value
Mode
Function
CONTROL
TEST
0000 0000
0000 0001
0001 0010
0001 0011
00
01
12
13
Write
Write
Write
Write
software reset
only for internal use
write address DSP
read address DSP
WR_DSP
RD_DSP
MICRONAS INTERMETALL
7
BSP 3505D
PRELIMINARY DATA SHEET
Table 3–3: Control Register (Subaddress: 00
)
hex
Name
Subaddress
00
MSB
14
13..1
LSB
CONTROL
1 : RESET
0 : normal
0
0
0
hex
3.1. Protocol Description
Write to DSP
S
write
device
address
Wait ACK
sub-addr
ACK
addr-byte
high
ACK addr-byte low ACK data-byte high ACK data-byte low ACK
P
Read from DSP
S
write
device
address
Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK
high low
S
read
device
address
Wait ACK data-byte ACK data-byte NAK
high low
P
Write to Control or Test Registers
S
write
device
address
Wait ACK
sub-addr
ACK
data-byte high
ACK
data-byte low
ACK
P
2
Note: S =
I C-Bus Start Condition from master
2
P =
I C-Bus Stop Condition from master
2
ACK = Acknowledge-Bit: LOW on I C_DA from slave (=BSP, gray)
or master (=CCU, hatched)
2
NAK = Not Acknowledge-Bit: HIGH on I C_DA from master (=CCU, hatched) to indicate ‘End of Read’
or from BSP indicating internal error state
2
Wait = I C-Clock line held low by the slave (=BSP) while interrupt is serviced (<1.8 ms)
1
0
2
I C_DA
S
P
2
I C_CL
2
Fig. 3–1: I C bus protocol
(MSB first; data must be stable while clock is high)
(Data: MSB first)
8
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
F
I2C
T
T
I2C3
I2C4
2
I C_CL
T
T
T
T
I2C2
I2C1
I2C5
I2C6
2
I C_DA as input
T
T
I2COL1
I2COL2
2
I C_DA as output
2
Fig. 3–2: I C bus timing diagram
2
3.2. Proposal for BSP 3505D I C Telegrams
3.2.1. Symbols
daw write device address
dar read device address
<
>
aa
dd
Start Condition
Stop Condition
Address Byte
Data Byte
3.2.2. Write Telegrams
<daw 00 d0 00>
write to CONTROL register
write data into DSP
<daw 12 aa aa dd dd>
3.2.3. Read Telegrams
<daw 13 aa aa <dar dd dd> read data from DSP
3.2.4. Examples
<80 00 80 00>
RESET BSP statically
clear RESET
<80 00 00 00>
<80 12 00 08 02 20>
set loudspeaker channel source
to SCART, stereo
MICRONAS INTERMETALL
9
BSP 3505D
PRELIMINARY DATA SHEET
2
3.3. Start Up Sequence: Power Up and I C-Controlling
After power on or RESET (see Fig. 3–3), the IC is in an
inactive state. The CCU has to transmit the required co-
2
efficient set for a given operation via the I C bus. Initial-
ization must start with the MODE Register.
The reset pin should not be >0.45*DVSUP (see recom-
mended conditions) before the 5 Volt digital power sup-
ply (DVSUP) and the analog power supply (AVSUP) are
>4.75 Volt AND the BSP clock is running. (Delay: 0.5 ms
typ, 2 ms max)
This means, if the reset low–high edge starts with a
delay of 2 ms after DVSUP and AVSUP >4,75 Volt, even
under worst case conditions, the reset is ok.
DVSUP/V
AVSUP/V
4.75
time / ms
time / ms
time / ms
Oscillator
max. 2
RESETQ
min. 2
0.45 * DVSUP
Note: The reset should
not reach high level be-
fore the oscillator has
started. This requires a
reset delay of >2 ms
Fig. 3–3: Power-up sequence
10
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
4. Programming the BSP 3505D
4.1. Register ‘MODE_REG’
The register ‘MODE_REG’ contains the control bits de-
termining the operation mode of the BSP 3505D;
Table 4–1 explains all bit positions.
Table 4–1: Control word ‘MODE_REG’: All bits are “0” after power-on-reset
Register
Protocol
Write Address (hex)
Function
MODE_REG
long
0083
mode register
Bit
[0]
[1]
Function
not used
Comment
Definition
must be 0
DCTR_TRI
Digital_Control_Output tristate
0 : active
1 : tristate
[2]
not used
not used
not used
not used
not used
must be 1
must be 0
must be 1
must be 0
must be 0
[3–4]
[5]
[6–9]
[10–15]
MICRONAS INTERMETALL
11
BSP 3505D
PRELIMINARY DATA SHEET
4.2. DSP Write Registers: Table and Addresses
Table 4–2: DSP Write Registers; Subaddress: 12 ; if necessary these registers are readable as well.
hex
DSP Write Register
Address High/ Adjustable Range, Operational Modes
Low
Reset Mode
Volume loudspeaker channel
Volume / Clipping Mode loudspeaker
Balance loudspeaker channel [L/R]
Balance Mode loudspeaker
0000hex
H
L
[+12 dB ... –114 dB, MUTE]
1/8 dB Steps / Reduce Vol., Tone, Comprom.
[0..100 / 100 % and vv][–127..0 / 0 dB and vv]
[Linear mode / logarithmic mode]
[+12 dB ... –12 dB]
MUTE
00hex
100%/100%
0001hex
H
L
linear mode
0 dB
Bass loudspeaker channel
0002hex
0003hex
0004hex
H
H
H
L
Treble loudspeaker channel
Loudness loudspeaker channel
Loudness Filter Characteristic
[+12 dB ... –12 dB]
0 dB
[0 dB ... +17 dB]
0 dB
[NORMAL, SUPER_BASS]
[–100%...OFF...+100%]
NORMAL
OFF
Spatial effect strength loudspeaker ch. 0005hex
Spatial effect mode/customize
H
L
[SBE, SBE+PSE]
SBE+PSE
00hex
Volume SCART1 channel
Volume / Mode SCART1 channel
Loudspeaker channel source
Loudspeaker channel matrix
SCART1 channel source
SCART1 channel matrix
Quasi-peak detector source
Quasi-peak detector matrix
Prescale SCART
0007hex
0008hex
000Ahex
000Chex
H
L
[00hex ... 7Fhex],[+12 dB ... –114 dB, MUTE]
[Linear mode / logarithmic mode]
[SCART]
linear mode
FM/AM
SOUNDA
FM/AM
SOUNDA
FM/AM
SOUNDA
00hex
H
L
[SOUNDA, SOUNDB, STEREO, MONO]
[SCART]
H
L
[SOUNDA, SOUNDB, STEREO, MONO]
[SCART]
H
L
[SOUNDA, SOUNDB, STEREO, MONO]
000Dhex
0013hex
H
H/L
[00hex ... 7Fhex
Bits [15..0]
]
ACB Register (SCART Switching
Facilities)
00hex
Beeper
0014hex
0029hex
H/L
H
[00hex ... 7Fhex]/[00hex ... 7Fhex
[off, on, decay time]
]
0/0
off
Automatic Volume Correction
4.3. DSP Read Registers: Table and Addresses
Table 4–3: DSP Read Registers; Subaddress: 13
hex
DSP Read Register
Address
0019
High/Low
H&L
H&L
Output Range
Quasi peak readout left
Quasi peak readout right
[00
[00
... 7FFF
... 7FFF
]
]
16 bit two’s complement
16 bit two’s complement
hex
hex
hex
hex
hex
001A
hex
12
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
4.4. DSP Write Registers: Functions and Values
The BSP 3505D loudspeaker volume function is divided
up in a digital and an analog section.
Write registers are 16 bit wide, whereby the MSB is de-
2
noted bit [15]. Transmissions via I C bus have to take
With Fast Mute, volume is reduced to mute position by
digital volume only. Analog volume is not changed. This
reduces any audible DC plops. Going back from Fast
Mute should be done to the volume step before Fast
Mute was activated.
place in 16-bit words. Some of the defined 16-bit words
are divided into low [7..0] and high [15..8] byte, or in an
other manner, thus holding two different control entities.
All write registers are readable. Unused parts of the
16-bitregistersmustbezero. Addressesnotgiveninthis
table must not be written at any time!
Clipping Mode
Loudspeaker
0000
[3..0]
hex
4.4.1. Volume Loudspeaker Channel
Reduce Volume
0000
RESET
0
hex
Volume
0000
[15..4]
hex
Loudspeaker
Reduce Tone Control
Compromise Mode
0001
1
2
hex
+12 dB
0111 1111 0000 7F0
hex
0010
hex
+11.875 dB
0111 1110 1110 7EE
hex
If the clipping mode is set to “Reduce Volume”, the fol-
lowing clipping procedure is used: To prevent severe
clipping effects with bass or treble boosts, the internal
volume is automatically limited to a level where, in com-
bination with either bass or treble setting, the amplifica-
tion does not exceed 12 dB.
+0.125 dB
0 dB
0111 0011 0010 732
0111 0011 0000 730
hex
hex
–0.125 dB
0111 0010 1110 72E
hex
–113.875 dB
–114 dB
Mute
0000 0001 0010 012
0000 0001 0000 010
hex
hex
hex
If the clipping mode is “Reduce Tone Control”, the bass
or treble value is reduced if amplification exceeds 12 dB.
0000 0000 0000 000
RESET
If the clipping mode is “Compromise Mode”, the bass or
treble value and volume are reduced half and half if am-
plification exceeds 12 dB.
Fast Mute
1111 1111 1110 FFE
hex
The highest given positive 8-bit number (7F ) yields in
hex
Example:
Vol.:
+6 dB
Bass:
+9 dB
Treble:
+5 dB
a maximum possible gain of 12 dB. Decreasing the vol-
ume register by 1 LSB decreases the volume by 1 dB.
Volume settings lower than the given minimum mute the
output. With large scale input signals, positive volume
settings may lead to signal clipping.
Red. Volume
Red. Tone Con.
Compromise
3
9
5
5
5
6
6
4.5
7.5
MICRONAS INTERMETALL
13
BSP 3505D
PRELIMINARY DATA SHEET
4.4.2. Balance Loudspeaker Channel
4.4.3. Bass Loudspeaker Channel
Positivebalance settings reduce the left channel without
affecting the right channel; negative settings reduce the
right channel leaving the left channel unaffected. In lin-
ear mode, a step by 1 LSB decreases or increases the
balance by about 0.8% (exact figure: 100/127). In loga-
rithmic mode, a step by 1 LSB decreases or increases
the balance by 1 dB.
Bass Loudspeaker
+20 dB
0002
H
hex
0111 1111
0111 1000
0111 0000
0110 1000
0110 0000
0101 1000
7F
78
70
68
60
58
hex
hex
hex
hex
hex
hex
+18 dB
+16 dB
+14 dB
Balance Mode
Loudspeaker
0001
[3..0]
hex
+12 dB
+11 dB
linear
0000
RESET
0
1
hex
+1 dB
0000 1000
0000 0001
08
hex
logarithmic
0001
hex
+1/8 dB
0 dB
01
00
hex
0000 0000
RESET
hex
Linear Mode
–1/8 dB
–1 dB
1111 1111
1111 1000
FF
F8
hex
Balance Loudspeaker
Channel [L/R]
0001
H
hex
hex
Left muted, Right 100%
Left 0.8%, Right 100%
0111 1111
0111 1110
7F
7E
hex
–11 dB
–12 dB
1010 1000
1010 0000
A8
A0
hex
hex
hex
Left 99.2%, Right 100%
Left 100%, Right 100%
0000 0001
01
00
hex
With positive bass settings, internal overflow may occur
even with overall volume less than 0 dB. This will lead to
a clipped output signal. Therefore, it is not recom-
mended to set bass to a value that, in conjunction with
volume, would result in an overall positive gain.
0000 0000
RESET
hex
Left 100%, Right 99.2%
1111 1111
FF
hex
Left 100%, Right 0.8%
Left 100%, Right muted
1000 0010
1000 0001
82
81
hex
hex
Logarithmic Mode
Balance Loudspeaker
Channel [L/R]
0001
H
hex
Left –127 dB, Right 0 dB
Left –126 dB, Right 0 dB
0111 1111
0111 1110
7F
hex
hex
7E
Left –1 dB, Right 0 dB
Left 0 dB, Right 0 dB
0000 0001
01
00
hex
0000 0000
RESET
hex
Left 0 dB, Right –1 dB
1111 1111
FF
hex
Left 0 dB, Right –127 dB
Left 0 dB, Right –128 dB
1000 0001
1000 0000
81
80
hex
hex
14
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
4.4.4. Treble Loudspeaker Channel
4.4.5. Loudness Loudspeaker Channel
Treble Loudspeaker
+15 dB
0003
H
Loudness
Loudspeaker
0004
H
hex
hex
0111 1000
0111 0000
78
70
hex
+17 dB
+16 dB
0100 0100
0100 0000
44
40
hex
+14 dB
hex
hex
+1 dB
0000 1000
0000 0001
08
hex
+1 dB
0 dB
0000 0100
04
00
hex
+1/8 dB
0 dB
01
00
hex
0000 0000
RESET
hex
0000 0000
RESET
hex
–1/8 dB
–1 dB
1111 1111
1111 1000
FF
F8
hex
Mode Loudness
Loudspeaker
0004
L
hex
hex
–11 dB
–12 dB
1010 1000
1010 0000
A8
A0
Normal (constant
volume at 1 kHz)
0000 0000
RESET
00
04
hex
hex
hex
Super Bass (constant
volume at 2 kHz)
0000 0100
hex
Withpositivetreblesettings, internaloverflowmayoccur
even with overall volume less than 0 dB. This will lead to
a clipped output signal. Therefore, it is not recom-
mended to set treble to a value that, in conjunction with
volume, would result in an overall positive gain.
Loudnessincreasesthevolumeoflowandhighfrequen-
cy signals, while keeping the amplitude of the 1 kHz ref-
erence frequency constant. The intended loudness has
to be set according to the actual volume setting. Be-
cause loudness introduces gain, it is not recommended
to set loudness to a value that, in conjunction with vol-
ume, would result in an overall positive gain.
By means of ‘Mode Loudness’, the corner frequency for
bass amplification can be set to two different values. In
Super Bass mode, the corner frequency is shifted up.
The point of constant volume is shifted from 1 kHz to
2 kHz.
MICRONAS INTERMETALL
15
BSP 3505D
PRELIMINARY DATA SHEET
4.4.6. Spatial Effects Loudspeaker Channel
There are several spatial effect modes available:
Mode A (low byte = 00 ) is compatible to the formerly
hex
Spatial Effect Strength
Loudspeaker
0005
H
hex
used spatial effect. Here, the kind of spatial effect de-
pends on the source mode. If the incoming signal is in
mono mode, Pseudo Stereo Effect is active; for stereo
signals, Pseudo Stereo Effect and Stereo Basewidth
Enlargement is effective. The strength of the effect is
controllable by the upper byte. A negative value reduces
the stereo image. A rather strong spatial effect is recom-
mended for small TV sets where loudspeaker spacing is
rather close. For large screen TV sets, a more moderate
spatial effect is recommended. In mode A, even in case
of stereo input signals, Pseudo Stereo Effect is active,
which reduces the center image.
Enlargement 100%
Enlargement 50%
0111 1111
0011 1111
7F
3F
hex
hex
Enlargement 1.5%
Effect off
0000 0001
01
00
hex
0000 0000
RESET
hex
Reduction 1.5%
Reduction 50%
Reduction 100%
1111 1111
1100 0000
1000 0000
FF
C0
hex
hex
hex
In Mode B, only Stereo Basewidth Enlargement is effec-
tive. For mono input signals, the Pseudo Stereo Effect
has to be switched on.
80
It is worth mentioning, that all spatial effects affect ampli-
tude and phase response. With the lower 4 bits, the fre-
Spatial Effect Mode
Loudspeaker
0005
[7..4]
hex
quency response can be customized. A value of 0000
bin
yields a flat response for center signals (L = R) but a high
pass function of L or R only signals. A value of 0110
bin
Stereo Basewidth En-
largement (SBE) and
Pseudo Stereo Effect
(PSE). (Mode A)
0000
RESET
0000
0
0
hex
has a flat response for L or R only signals but a lowpass
function for center signals. By using 1000 , the fre-
bin
hex
quency response is automatically adapted to the sound
material by choosing an optimal high pass gain.
Stereo Basewidth En-
largement (SBE) only.
(Mode B)
0010
2
hex
Spatial Effect Cus-
tomize Coefficient
Loudspeaker
0005
[3..0]
hex
max high pass gain
0000
0
hex
RESET
0010
0100
0110
2/3 high pass gain
1/3 high pass gain
min high pass gain
automatic
2
hex
4
hex
6
hex
8
hex
1000
16
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
4.4.7. Volume SCART1
4.4.8. Channel Source Modes
Volume Mode SCART1
0007
[3..0]
Loudspeaker Source
SCART1 Source
0008
H
H
H
hex
hex
linear
0000
RESET
0
hex
000A
hex
Quasi-Peak
Detector Source
000C
hex
logarithmic
0001
1
hex
NONE
0000 0000
RESET
00
(MSP3410: FM)
hex
Linear Mode
Volume SCART1
OFF
NONE (MSP3410: NICAM)
0000 0001
0000 0010
01
02
hex
0007
H
hex
SCART
hex
0000 0000
RESET
00
hex
hex
4.4.9. Channel Matrix Modes
0 dB gain
0100 0000
40
(digital full scale (FS)
Loudspeaker Matrix
SCART1 Matrix
0008
L
L
L
to 2 V
output)
hex
RMS
000A
+6 dB gain (–6 dBFS
to 2 V output)
0111 1111
7F
hex
hex
RMS
Quasi-Peak
000C
hex
Detector Matrix
SOUNDA / LEFT
0000 0000
RESET
00
hex
Logarithmic Mode
Volume SCART1
+12 dB
0007
[15..4]
hex
SOUNDB / RIGHT
STEREO
0001 0000
0010 0000
0011 0000
10
20
30
hex
hex
hex
0111 1111 0000 7F0
hex
+11.875 dB
0111 1110 1110 7EE
hex
MONO
+0.125 dB
0 dB
0111 0011 0010 732
0111 0011 0000 730
hex
4.4.10. SCART Prescale
hex
–0.125 dB
0111 0010 1110 72E
hex
Volume Prescale
SCART
000D
H
hex
–113.875 dB
–114 dB
Mute
0000 0001 0010 012
0000 0001 0000 010
hex
hex
hex
OFF
0000 0000
RESET
00
19
7F
hex
hex
hex
0000 0000 0000 000
RESET
0 dB gain (2 V
in-
0001 1001
RMS
put to digital full scale)
+14 dB gain
0111 1111
(400 mV
input to
RMS
digital full scale)
MICRONAS INTERMETALL
17
BSP 3505D
PRELIMINARY DATA SHEET
4.4.11. Definition of Digital Control Output Pins
4.4.13. Beeper
ACB Register
0013
[15..14]
Beeper Volume
0014
H
hex
hex
D_CTR_OUT0
OFF
0000 0000
RESET
00
hex
low
(RESET)
x0
x1
high
Maximum Volume (full
digital scale FDS)
0111 1111
7F
hex
D_CTR_OUT1
low
high
(RESET)
0x
1x
Beeper Frequency
16 Hz (lowest)
1 kHz
0014
L
hex
0000 0001
0100 0000
1111 1111
01
40
hex
hex
4.4.12. Definition of SCART-Switching Facilities
4 kHz (highest)
FF
hex
ACB Register
0013
[13..0]
hex
DSP IN
A squarewave beeper can be added to the loudspeaker
channel. The addition point is just before volume adjust-
ment.
Selection of Source:
* SC1_IN_L/R
MONO_IN
SC2_IN_L/R
Mute
xx xx00 xx00 0000
xx xx01 xx00 0000
xx xx10 xx00 0000
xx xx11 xx10 0000
SC1_OUT_L/R
Selection of Source:
SC2_IN_L/R
MONO_IN
SCART1 via D/A
SC1_IN_L/R
Mute
xx 01xx x0x0 0000
xx 10xx x0x0 0000
xx 11xx x0x0 0000
xx 01xx x1x0 0000
xx 11xx x1x0 0000
* = RESET position, which becomes active at the
time of the first write transmission on the control
bus to the audio processing part (DSP). By writing
to the ACB register first, the RESET state can be
redefined.
Note: After RESET, SC1_OUT_L/R is undefined!
Note: If “MONO_IN” is selected at the DSP_IN selec-
tion, the channel matrix mode of the corresponding out-
put channel(s) must be set to “sound A”.
18
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
4.4.14. Automatic Volume Correction (AVC)
To reset the internal variables, the AVC should be
switched off and on during any channel or source
change. For standard applications, the recommended
decay time is 4 sec.
AVC
on/off
0029
[15.12]
hex
AVC
off and Reset
of int. variables
0000
RESET
0
hex
Note: AVC should not be used in any Dolby Prologic
mode, except PANORAMA, where no other than the
loudspeaker output is active.
AVC
on
1000
8
hex
AVC
Decay Time
0029
[11..8]
hex
4.5. DSP Read Registers: Functions and Values
8 sec (long)
1000
0100
0010
0001
8
hex
4
hex
2
hex
1
hex
4 sec (middle)
2 sec (short)
20 ms (very short)
All readable registers are 16-bit wide. Transmissions via
2
I C bus have to take place in 16-bit words. Single data
entries are 8 bit. Some of the defined 16-bit words are
divided into low and high byte, thus holding two different
control entities.
Different sound sources fairly often do not have the
same volume level. Advertisement during movies, as
well, usually has a different (higher) volume level than
the movie itself. The Automatic Volume Correction
(AVC) solves this problem and equalizes the volume lev-
els.
These registers are not writeable.
4.5.1. Quasi-Peak Detector
Quasi-Peak
Readout Left
0019
H+L
H+L
]
hex
The absolute value of the incoming signal is fed into a
filter with 16 ms attack time and selectable decay time.
The decay time must be adjusted as shown in the table
above. This attack/decay filter block works similar to a
peak hold function. The volume correction value with its
quasi continuous step width is calculated using the at-
tack/decay filter output.
Quasi-Peak
Readout Right
001A
hex
Quasi peak readout
[0
hex
... 7FFF
hex
values are 16 bit two’s
complement
The Automatic Volume Correction works with an internal
reference level of –18 dBFS. This means, input signals
with a volume level of –18 dBFS will not be affected by
the AVC. If the input signals vary in a range of –24 dB to
0 dB, the AVC compensates this.
The quasi peak readout register can be used to read out
the quasi peak level of any input source, in order to ad-
just all inputs to the same normal listening level. The re-
fresh rate is 32 kHz. The feature is based on a filter time
constant:
Example: A static input signal of 1 kHz on Scart has an
output level as shown in the table below.
attack-time: 1.3 ms
decay-time: 37 ms
Scart Input
0 dbr = 2 Vrms
Volume
Correc-
tion
Main Output
0 dBr = 1.4 Vrms
0 dBr
–18 dB
–12 dB
–6 dB
–18 dBr
–18 dBr
–18 dBr
–18 dBr
–18 dBr
–24 dBr
–6 dBr
–12 dBr
–18 dBr
–24 dBr
–30 dBr
–0 dB
+ 6 dB
+ 6 dB
Loudspeaker Volume = 73
= 0 dBFS
hex
Scart Prescale = 20
i.e. 2.0 Vrms = 0 dBFS
hex
MICRONAS INTERMETALL
19
BSP 3505D
PRELIMINARY DATA SHEET
4.5.2. BSP Hardware Version Code
Hardware Version
Hardware Version
BSP 3505D – A2
001E
H
hex
[00
... FF
]
hex
hex
01
hex
A change in the hardware version code defines hard-
ware optimizations that may have influence on the chip’s
behavior. The readout of this register is identical to the
hardware version code in the chip’s imprint.
4.5.3. BSP Major Revision Code
Major Revision
001E
L
hex
BSP 3505D
04
hex
4.5.4. BSP Product Code
Product
001F
H
hex
BSP 3505D
05
hex
4.5.5. BSP ROM Version Code
ROM Version
001F
L
hex
Major software revision
BSP 3505D – A2
[00
... FF
]
hex
hex
02
hex
A change in the ROM version code defines internal soft-
ware optimizations, that may have influence on the
chip’s behavior, e.g. new features may have been in-
cluded. Whileasoftwarechangeisintendedtocreateno
compatibility problems, customers that want to use the
new functions can identify new BSP 3505D versions ac-
cording to this number.
20
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
5. Specifications
5.1. Outline Dimensions
±0.1
±0.1
16 x 1.27
= 20.32
1.1 x 45 °
±0.1
1.27
1.2 x 45°
9
1
61
10
60
1.6
2
2
9
15
9
26
44
1.9
4.05
27
43
0.1
±0.1
24.22
± 0.125
25.125
±0.15
4.75
SPGS7004-3/5E
Fig. 5–1:
68-Pin Plastic Leaded Chip Carrier Package
(PLCC68)
Weight approximately 4.8 g
Dimensions in mm
SPGS0016-4/3E
SPGS0015-1/2E
64
1
33
32
52
27
26
1
±0.1
19.3
±0.1
15.6
±0.1
±0.1
18
57.7
±0.1
±0.1
14
47
±0.06
0.27
±0.06
0.27
0°...15°
±0.5
±0.1
20.1
1
±0.1
1
0.457
0.457
±0.05
1.778
31 x 1.778 = 55.118
±0.05
1.778
±0.1
±0.1
1.29
25 x 1.778 = 44.47
Fig. 5–2:
Fig. 5–3:
64-Pin Plastic Shrink Dual Inline Package
(PSDIP64)
52-Pin Plastic Shrink Dual In Line Package
(PSDIP52)
Weight approximately 9.0 g
Dimensions in mm
Weight approximately 5.5 g
Dimensions in mm
MICRONAS INTERMETALL
21
BSP 3505D
PRELIMINARY DATA SHEET
23 x 0.8 = 18.4
0.8
±0.03
0.17
64
41
40
65
8
8
1.8
1.8
10.3
9.8
5
16
25
80
1.28
1
24
2.70
23.2
20
0.1
±0.2
3
SPGS0025-1/1E
Fig. 5–4:
80-Pin Plastic Quad Flat Package
(PQFP80)
Weight approximately 1.6 g
Dimensions in mm
10 x 0.8 = 8
0.8
0.18
33
23
34
22
12
3.0
1.3
44
1
11
2.0
2.15
1.75
13.2
10
0.1
SPGS0006-1/1E
Fig. 5–5:
44-Pin Plastic Quad Flat Package
(PQFP44)
Weight approx. 0.4 g
Dimensions in mm
22
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
5.2. Pin Connections and Short Descriptions
NC = not connected; leave vacant
LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram
AHVSS: connect to AHVSS
DVSS: if not used, connect to DVSS
Pin No.
Pin Name
Type
Connection
(if not used)
Short Description
PLCC
68-pin
PSDIP
64-pin
PSDIP
52-pin
PQFP
80-pin
PQFP
44-pin
1
16
–
14
–
9
–
TP
OUT
LV
LV
LV
LV
LV
LV
LV
X
Test pin
2
–
–
NC
Not connected
Test pin
3
15
14
13
12
11
10
9
13
12
11
10
9
8
–
TP
OUT
4
7
17
16
15
14
13
12
–
TP
IN
Test pin
5
6
TP
OUT
Test pin
6
5
TP
IN/OUT
IN/OUT
IN/OUT
IN/OUT
Test pin
7
4
TP
Test pin
8
8
3
I2C_DA
I2C_CL
NC
I2C data
9
7
2
X
I2C clock
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
8
–
1
LV
X
Not connected
Standby (low-active)
I2C Bus address select
Digital control output 0
Digital control output 1
Not connected
Not connected
Not connected
Not connected
Test pin
7
6
80
79
78
77
76
75
–
11
10
9
STANDBYQ
ADR_SEL
D_CTR_OUT0
D_CTR_OUT1
NC
IN
6
5
IN
X
5
4
OUT
OUT
LV
LV
LV
LV
LV
LV
LV
X
4
3
8
3
–
–
2
–
–
NC
–
–
–
NC
1
2
74
73
72
71
70
69
68
67
66
–
NC
64
63
62
61
60
59
58
57
1
7
TP
52
51
50
49
48
47
46
6
XTAL_OUT
XTAL_IN
TESTEN
NC
OUT
IN
Crystal oscillator
Crystal oscillator
Test pin
5
X
4
IN
X
–
LV
LV
LV
X
Not connected
Test pin
3
TP
IN
IN
2
TP
Test pin
1
AVSUP
Analog power supply
+5 V
–
–
–
65
–
AVSUP
X
Analog power supply
+5 V
–
–
–
–
–
–
64
63
–
–
NC
NC
LV
LV
Not connected
Not connected
MICRONAS INTERMETALL
23
BSP 3505D
PRELIMINARY DATA SHEET
Pin No.
Pin Name
Type
Connection
(if not used)
Short Description
PLCC
68-pin
PSDIP
64-pin
PSDIP
52-pin
PQFP
80-pin
PQFP
44-pin
27
–
56
–
45
–
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
–
AVSS
AVSS
MONO_IN
NC
X
Analog ground
Analog ground
Mono input
X
28
–
55
–
44
–
43
–
IN
LV
LV
X
Not connected
Reference voltage
Scart input 1 in, right
Scart input 1 in, left
Analog shield ground 1
Scart input 2 in, right
Scart input 2 in, left
Test Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
54
53
52
51
50
49
48
47
46
45
44
43
–
43
42
41
–
42
41
40
39
38
37
–
VREFTOP
SC1_IN_R
SC1_IN_L
ASG1
SC2_IN_R
SC2_IN_L
TP
IN
IN
LV
LV
AHVSS
LV
LV
LV
LV
LV
LV
LV
LV
LV
X
40
39
–
IN
IN
38
37
–
–
NC
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
–
NC
–
NC
–
–
NC
–
–
NC
–
–
NC
42
36
36
AGNDC
Analog reference volt-
age high voltage part
43
–
41
–
35
–
44
43
42
41
40
39
35
–
AHVSS
AHVSS
NC
X
Analog ground
X
Analog ground
–
–
–
–
LV
LV
X
Not connected
–
–
–
–
NC
Not connected
44
45
40
39
34
33
34
33
CAPL_M
AHVSUP
Volume capacitor MAIN
X
Analog power supply
8.0 V
46
47
48
49
38
37
36
35
32
31
30
29
38
37
36
35
32
31
30
29
NC
LV
LV
LV
X
Not connected
SC1_OUT_L
SC1_OUT_R
VREF1
OUT
OUT
Scart output 1, left
Scart output 1, right
Reference ground 1
high voltage part
50
51
52
34
33
–
28
27
–
34
33
32
28
–
NC
NC
NC
LV
LV
LV
Not connected
Not connected
Not connected
–
24
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
Pin No.
Pin Name
Type
Connection
(if not used)
Short Description
PLCC
68-pin
PSDIP
64-pin
PSDIP
52-pin
PQFP
80-pin
PQFP
44-pin
53
54
55
56
57
58
32
31
30
29
28
27
–
31
30
29
28
27
26
–
NC
LV
LV
LV
LV
LV
X
Not connected
26
–
–
NC
Not connected
–
NC
Not connected
25
24
23
27
26
25
DACM_L
DACM_R
VREF2
OUT
OUT
Loudspeaker out, left
Loudspeaker out, right
Reference ground 2
high voltage part
59
60
–
26
25
–
22
21
–
25
24
23
22
21
20
19
18
17
16
15
14
13
24
23
–
NC
LV
LV
LV
LV
X
Not connected
Not connected
Not connected
Not connected
Power-on-reset
Not connected
Not connected
Not connected
Test pin
NC
NC
–
–
–
–
NC
61
62
63
64
65
66
–
24
23
22
21
20
19
–
20
–
22
–
RESETQ
NC
IN
IN
LV
LV
LV
LV
X
–
–
NC
19
18
17
–
21
–
NC
TP
–
DVSS
DVSS
DVSS
DVSUP
Digital ground
Digital ground
Digital ground
–
X
–
–
–
20
19
X
67
18
16
X
Digital power supply
+5 V
–
–
–
12
11
10
–
DVSUP
DVSUP
TP
X
Digital power supply
+5 V
–
–
–
–
X
Digital power supply
+5 V
68
17
15
18
OUT
LV
Test pin
MICRONAS INTERMETALL
25
BSP 3505D
PRELIMINARY DATA SHEET
5.3. Pin Configurations
TP
NC
TP
TP
DVSUP
DVSS
TP
TP
TP
TP
NC
TP
NC
I2C_DA
I2C_CL
NC
RESETQ
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NC
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
STANDBYQ
ADR_SEL
D_CTR_OUT0
D_CTR_OUT1
NC
VREF2
DACM_R
DACM_L
NC
NC
NC
NC
NC
NC
NC
BSP 3505D
TP
NC
XTAL_OUT
NC
XTAL_IN
TESTEN
VREF1
SC1_OUT_R
SC1_OUT_L
NC
TP
NC
AHVSUP
CAPL_M
TP
AVSUP
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AVSS
MONO_IN
VREFTOP
SC1_IN_R
SC1_IN_L
ASG1
SC2_IN_R
SC2_IN_L
AHVSS
AGNDC
NC
NC
NC
NC
NC
NC
TP
Fig. 5–6: 68-pin PLCC package
26
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
1
TP
NC
1
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
TP
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
XTAL_OUT
NC
NC
2
XTAL_OUT
XTAL_IN
TESTEN
NC
2
XTAL_IN
TESTEN
NC
3
D_CTR_OUT1
D_CTR_OUT0
ADR_SEL
STANDBYQ
I2C_CL
I2C_DA
TP
3
D_CTR_OUT1
D_CTR_OUT0
ADR_SEL
STANDBYQ
NC
4
4
5
5
TP
TP
6
TP
6
7
TP
7
AVSUP
AVSS
AVSUP
AVSS
8
8
I2C_CL
I2C_DA
TP
9
9
MONO_IN
VREFTOP
SC1_IN_R
SC1_IN_L
TP
MONO_IN
VREFTOP
SC1_IN_R
SC1_IN_L
ASG1
10
11
12
13
14
15
16
10
11
12
13
14
15
16
TP
TP
TP
TP
TP
TP
SC2_IN_R
SC2_IN_L
NC
TP
TP
TP
TP
SC2_IN_R
SC2_IN_L
TP
DVSUP
DVSS
TP
NC
48
47
46
45
36
35
34
33
AGNDC
AHVSS
CAPL_M
AHVSUP
NC
TP
17
18
19
20
17
18
19
20
DVSUP
DVSS
TP
NC
NC
NC
NC
RESETQ
44
43
42
41
40
39
38
37
36
35
34
33
NC
32
31
30
29
28
27
21
22
23
24
25
26
27
28
29
30
31
32
21
22
23
24
25
26
NC
NC
NC
SC1_OUT_L
SC1_OUT_R
VREF1
NC
NC
NC
VREF2
DACM_R
DACM_L
NC
AGNDC
AHVSS
NC
RESETQ
CAPL_M
AHVSUP
NC
NC
NC
NC
VREF2
DACM_R
DACM_L
NC
SC1_OUT_L
SC1_OUT_R
VREF1
NC
Fig. 5–8: 52-pin PSDIP package
NC
NC
NC
Fig. 5–7: 64-pin PSDIP package
MICRONAS INTERMETALL
27
BSP 3505D
PRELIMINARY DATA SHEET
TP
SC2_IN_L
SC2_IN_R
ASG1
SC1_IN_L
SC1_IN_R
VREFTOP
NC
NC
NC
NC
NC
NC
NC
MONO_IN
AVSS
AGNDC
AHVSS
AHVSS
NC
AVSS
NC
NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AVSUP
AVSUP
65
CAPL_M
AHVSUP
40
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TP
TP
NC
SC1_OUT_L
SC1_OUT_R
VREF1
NC
NC
TESTEN
XTAL_IN
NC
NC
XTAL_OUT
TP
BSP 3505D
NC
NC
NC
NC
NC
NC
D_CTR_OUT1
D_CTR_OUT0
ADR_SEL
STANDBYQ
DACM_L
DACM_R
VREF2
NC
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC
I2C_CL
I2C_DA
NC
NC
NC
TP
RESETQ
TP
NC
TP
NC
TP
NC
TP
TP
TP
DVSS
TP
DVSUP
DVSUP
DVSS
DVSS
DVSUP
Fig. 5–9: 80-pin PQFP package
28
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
NC
VREF1
SC1_OUT_R
SC1_OUT_L
NC
DACM_L
DACM_R
VREF2
NC
AHVSUP
NC
33 32 31 30 29 28 27 26 25 24 23
CAPL_M 34
AHVSS 35
22 RESETQ
21 NC
AGNDC 36
SC2_IN_L 37
SC2_IN_R 38
ASG1 39
20 DVSS
19 DVSUP
18 TP
BSP 3505D
17 TP
SC1_IN_L 40
SC1_IN_R 41
VREFTOP 42
MONO_IN 43
AVSS 44
16 TP
15 TP
14 TP
13 I2C_DA
12 I2C_CL
1
2
3
4
5
6
7
8
9
10 11
AVSUP
STANDBYQ
TP
ADR_SEL
D_CTR_OUT0
D_CTR_OUT1
TP
TESTEN
XTAL_IN
TP
XTAL_OUT
Fig. 5–10: 44-pin PQFP package
MICRONAS INTERMETALL
29
BSP 3505D
PRELIMINARY DATA SHEET
5.4. Pin Circuits (pin numbers refer to PLCC68 package)
40 k
≈ 3.75 V
N
GND
Fig. 5–17: Input Pins 30, 31, 33, and 34
(SC1–2_IN_L/R)
Fig. 5–11: Input/Output Pins 8 and 9
(I C_DA, I C_CL)
2
2
125 k
≈ 3.75 V
Fig. 5–12: Input Pins 11, 12, and 61
(STANDBYQ, ADR_SEL, RESETQ)
Fig. 5–18: Pin 42 (AGNDC)
DV
SUP
P
N
0...2 V
GND
Fig. 5–19: Capacitor Pin 44 (CAPL_M)
Fig. 5–13: Output Pins 13, and 14
(D_CTR_OUT0/1)
P
N
40 pF
80 k
500 k
3–30 pF
300
≈ 3.75 V
3–30 pF
Fig. 5–14: Input/Output Pins 20 and 21
(XTALIN/OUT)
Fig. 5–20: Output Pins 47, 48
(SC1_OUT_L/R)
VREFTOP
≈2.6V
AHV
SUP
0...1.2 mA
Fig. 5–15: Pin 29 (VREFTOP)
3.3 k
24 k
≈ 3.75 V
Fig. 5–21: Output Pins 56, 57
(DACM_L/R)
Fig. 5–16: Input Pin 28 (MONO_IN)
30
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
5.5. Electrical Characteristics
5.5.1. Absolute Maximum Ratings
Symbol
Parameter
Pin Name
–
Min.
0
Max.
Unit
°C
°C
V
1)
T
A
Ambient Operating Temperature
Storage Temperature
First Supply Voltage
Second Supply Voltage
Third Supply Voltage
70
T
–
–40
–0.3
–0.3
–0.3
–0.5
125
9.0
6.0
6.0
0.5
S
V
SUP1
V
SUP2
V
SUP3
AHVSUP
DVSUP
AVSUP
V
V
dV
Voltage between AVSUP
and DVSUP
AVSUP,
DVSUP
V
SUP23
P
TOT
Chip Power Dissipation
AHVSUP,
DVSUP,
AVSUP
PLCC68 without Heat Spreader
PSDIP64 without Heat Spreader
PSDIP52 without Heat Spreader
PQFP44 without Heat Spreader
1200
1300
1200
mW
1)
960
V
Input Voltage, all Digital Inputs
Input Current, all Digital Pins
Input Voltage, all Analog Inputs
–0.3
–20
V
+0.3
+0.3
V
Idig
SUP2
2)
I
–
+20
mA
Idig
3)
3)
V
Iana
SCn_IN_s,
MONO_IN
–0.3
V
SUP1
V
2)
I
Input Current, all Analog Inputs
SCn_IN_s,
MONO_IN
–5
+5
mA
Iana
4) 5)
4) 5)
I
I
Output Current, all SCART Outputs
SC1_OUT_s
,
,
Oana
3)
4)
4)
Output Current, all Analog Outputs
except SCART Outputs
DACM_s
Oana
4)
4)
I
Output Current, other pins
connected to capacitors
CAPL_M
AGNDC
Cana
1)
2)
3)
4)
5)
For PQFP44 package, max. ambient operating temperature is 65 °C.
positive value means current flowing into the circuit
“n” means “1” or “2”, “s” means “L” or “R”
The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground.
Total chip power dissipation must not exceed absolute maximum rating.
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the
“Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maxi-
mum ratings conditions for extended periods may affect device reliability.
MICRONAS INTERMETALL
31
BSP 3505D
PRELIMINARY DATA SHEET
5.5.2. Recommended Operating Conditions
at T = 0 to 70 °C (65 °C for PQFP44)
A
Symbol
Parameter
Min.
Typ.
8.0
Max.
Unit
Pin Name
AHVSUP
DVSUP
V
SUP1
V
SUP2
V
SUP3
First Supply Voltage
Second Supply Voltage
Third Supply Voltage
7.6
8.4
V
V
V
4.75
4.75
5.0
5.0
5.25
5.25
AVSUP
V
RESET Input High-Low and Low-
High Transition Voltage
RESETQ
0.45
5
0.8
0.2
V
SUP2
REIL
t
RESET Low Time after DVSUP
Stable and Oscillator Startup
µs
REIL
V
V
Digital Input Low Voltage
Digital Input High Voltage
STANDBYQ,
ADR_SEL,
TESTEN
V
V
DIGIL
SUP2
0.8
1
DIGIH
SUP2
t
STANDBYQ Setup Time before
Turn-off of Second Supply Voltage
STANDBYQ,
DVSUP
µs
STBYQ1
2
I C-Bus Recommendations
2
2
V
V
I C-BUS Input Low Voltage
I C_CL,
0.3
1.0
V
V
I2CIL
I2CIH
SUP2
2
I C_DA
2
I C-BUS Input High Voltage
0.6
SUP2
2
2
f
t
t
t
t
t
I C-BUS Frequency
I C_CL
MHz
ns
I2C
2
2
I C START Condition Setup Time
I C_CL,
120
120
500
500
55
I2C1
I2C2
I2C3
I2C4
I2C5
2
I C_DA
2
I C STOP Condition Setup Time
ns
2
2
I C-Clock Low Pulse Time
I C_CL
ns
2
I C-Clock High Pulse Time
ns
2
2
I C-Data Setup Time Before
I C_CL,
ns
2
Rising Edge of Clock
I C_DA
2
t
I C-Data Hold Time
55
ns
I2C6
after Falling Edge of Clock
Crystal Recommendations
f
P
Parallel Resonance Frequency
at 12 pF Load Capacitance
18.432
MHz
f
Accuracy of Adjustment
–100
–50
+100
+50
ppm
ppm
TOL
D
Frequency Variation versus
Temperature
TEM
R
C
Series Resistance
8
25
Ω
R
Shunt (Parallel) Capacitance
6.2
7.0
pF
0
32
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
Symbol
Parameter
Min.
Typ.
Max.
Unit
Pin Name
Load Capacitance Recommendations
External Load Capacitance
1)
C
L
XTAL_IN,
XTAL_OUT
PSDIP
PLCC
1.5
3.3
pF
pF
Amplitude Recommendation for Operation with External Clock Input (C
after reset = 22 pF)
load
V
XCA
External Clock Amplitude
XTAL_IN
0.7
V
pp
Analog Input and Output Recommendations
C
C
AGNDC-Filter-Capacitor
AGNDC
–20% 3.3
–20% 100
–20% 330
µF
nF
nF
AGNDC
Ceramic Capacitor in Parallel
2)
DC-Decoupling Capacitor
in front of SCART Inputs
SCn_IN_s
+20%
inSC
V
V
SCART Input Level
2.0
2.0
V
V
inSC
RMS
Input Level, Mono Input
SCART Load Resistance
SCART Load Capacitance
Main Volume Capacitor
Main Filter Capacitor
MONO_IN
inMONO
RMS
2)
R
C
C
C
SC1_OUT_s
10
kΩ
nF
µF
nF
LSC
LSC
VMA
FMA
6.0
CAPL_M
10
2)
DACM_s
–10%
1
+10%
Recommendations for Reference Voltage Pin
C
VREFTOP-Filter-Capacitor
Ceramic Capacitor in Parallel
VREFTOP
–20% 10
µF
VREFTOP
–20% 100
nF
1)
External capacitors at each crystal pin to ground are required. The higher the capacitors, the lower the clock
frequency results. The nominal free running frequency should match 18.432 MHz as closely as possible. Due
to different layouts of customer PCBs, the matching capacitor size should be defined in the application. The sug-
gested values (1.5 pF/3.3 pF) are figures based on experience with various PCB layouts.
2)
“n” means “1” or “2”, “s” means “L” or “R”
MICRONAS INTERMETALL
33
BSP 3505D
PRELIMINARY DATA SHEET
5.5.3. Characteristics
at T = 0 to 70 °C (65 °C for PQFP44), f
= 18.432 MHz,
CLOCK
A
V
SUP1
= 7.6 to 8.4 V, V
= 4.75 to 5.25 V for min./max. values
SUP2
at T = 60 °C, f
= 18.432 MHz, V
= 8 V, V
= 5 V for typical values, T = Junction Temperature
SUP2 J
A
CLOCK
SUP1
MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
MHz
%
Test Conditions
f
Clock Input Frequency
Clock High to Low Ratio
XTAL_IN
18.432
CLOCK
D
45
55
50
CLOCK
JITTER
t
Clock Jitter (Verification not
provided in Production test)
ps
V
DC-Voltage Oscillator
2.5
0.4
V
xtalDC
t
Oscillator Startup Time at
XTAL_IN,
2
ms
Startup
VDD Slew-rate of 1 V/1 µs
XTAL_OUT
I
First Supply Current (active)
AHVSUP
SUP1A
Analog Volume for Main and Aux at 0dB
9.6
6.3
17.1
11.2
24.6
16.1
mA
mA
Analog Volume for Main and Aux at –30dB
I
I
I
Second Supply Current (active)
Third Supply Current (active)
First Supply Current
DVSUP
AVSUP
AHVSUP
86
15
3.5
95
25
5.6
102
35
mA
mA
mA
SUP2A
SUP3A
SUP1S
7.7
STANDBYQ = low
(standby mode) at T = 27 °C
j
2
2
V
I C-Data Output Low Voltage
I C_DA
0.4
1.0
V
I
= 3 mA
I2COL
I2COH
I2COL1
I2COL
2
I
t
I C-Data Output High Current
µA
ns
V
= 5 V
I2COH
2
2
I C-Data Output Hold Time
I C_DA,
15
2
after Falling Edge of Clock
I C_CL
2
t
I C-Data Output Setup Time
100
ns
f
= 1 MHz
I2COL2
I2C
before Rising Edge of Clock
Analog Ground
V
AGNDC Open Circuit Voltage
AGNDC Output Resistance
AGNDC
3.63
70
3.73
125
3.83
180
V
R
≥10 MΩ
load
AGNDC0
R
kΩ
3 V ≤ V
≤ 4 V
outAGN
AGNDC
Analog Input Resistance
1)
R
R
SCART Input Resistance
SCn_IN_s
25
15
40
24
58
35
kΩ
kΩ
f
f
= 1 kHz, I = 0.05 mA
= 1 kHz, I = 0.1 mA
inSC
signal
from T = 0 to 70 °C
A
MONO Input Resistance
MONO_IN
inMONO
signal
from T = 0 to 70 °C
A
Audio Analog-to-Digital-Converter
1)
V
AICL
Effective Analog Input Clipping
Level for Analog-to-Digital-
Conversion
SCn_IN_s,
MONO_IN
2.00
2.25
V
RMS
f
= 1 kHz
signal
1)
“n” means “1”, or “2”;
“s” means “L” or “R”
34
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
SCART Outputs
1)
R
SCART Output Resistance
SC1_OUT_s
f = 1 kHz, I = 0.1 mA
signal
outSC
at T = 27 °C
200
200
330
460
500
Ω
Ω
j
from T = 0 to 70 °C
A
dV
Deviation of DC-Level at SCART
Output from AGNDC Voltage
–70
+70
mV
dB
dB
OUTSC
1)
A
Gain from Analog Input
to SCART Output
SCn_IN_s
–1.0
–0.5
+0.5
+0.5
f = 1 kHz
signal
SCtoSC
MONO_IN
→
SC1_OUT_s
1)
1)
f
Frequency Response from Analog
Input to SCART Output
bandwidth: 0 to 20000 Hz
with resp. to 1 kHz
rSCtoSC
V
outSC
Effective Signal Level at SCART-
Output during full-scale digital in-
put signal from DSP
SC1_OUT_s
1.8
1.9
3.3
2.0
V
RMS
f
= 1 kHz
signal
signal
Main Outputs
1
R
Main Output Resistance
DACM_s )
f
= 1 kHz, I = 0.1 mA
outMA
at T = 27 °C
2.1
2.1
4.6
5.0
kΩ
kΩ
j
from T = 0 to 70 °C
A
V
DC-Level at Main-Output
for Analog Volume at 0 dB
for Analog Volume at –30 dB
outDCMA
1.8
2.04
61
2.28
1.51
V
mV
V
outMA
EffectiveSignalLevelatMain-Out-
put during full-scale digital input
signal from DSP for Analog Vol-
ume at 0 dB
1.23
1.37
V
RMS
f
= 1 kHz
signal
Analog Performance
SNR
THD
1)
Signal-to-Noise Ratio
from Analog Input to
SCART Output
MONO_IN,
SCn_IN_s
→
93
96
dB
%
Input Level = –20 dB,
f = 1 kHz,
sig
equally weighted
20 Hz...20 kHz
1)
1)
SC1_OUT_s
Total Harmonic Distortion
from Analog Input to
SCART Output
MONO_IN,
0.01
0.03
Input Level = –3 dBr,
1)
SCn_IN_s
f
sig
= 1 kHz,
→
equally weighted
20 Hz...20 kHz
1)
SC1_OUT_s
“n” means “1” or “2”;
“s” means “L” or “R”
MICRONAS INTERMETALL
35
BSP 3505D
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
XTALK
Crosstalk attenuation
– PLCC68
Input Level = –3 dB,
f
sig
= 1 kHz, unused ana-
– PSDIP64
log inputs connected to
ground by Z < 1 kΩ
between left and right channel within
SCART Input/Output pair (L→R, R→L)
equally weighted
20 Hz...20 kHz
1)
SCn_IN → SC1_OUT
PLCC68
PSDIP64
80
80
dB
dB
PSRR: rejection of noise on AHVSUP at 1 kHz
AGNDC
AGNDC
MONO_IN,
SCn_IN_s
SC1_OUT_s
80
70
dB
dB
From Analog Input to
SCART Output
1)
1)
DC
DC voltage at VREFTOP
“n” means “1” or “2”; “s” means “L” or “R”
VREFTOP
2.4
2.6
2.7
V
VREFTOP
1)
36
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
6. Application Circuit
C s. section 5.5.2.
10
µF
100
nF
+8.0 V
+
18.432
MHz
3.3
µF
100
nF
+
10 µF
+
1 µF
1 µF
28 (55) MONO_IN
DACM_L (29) 56
DACM_R (28) 57
330 nF
1 nF
MAIN
31 (52) SC1_IN_L
30 (53) SC1_IN_R
330 nF
330 nF
100Ω
22 µF
32 (51) ASG1
SC1_OUT_L (37) 47
SC1_OUT_R (36) 48
AHVSS
+
34 (49) SC2_IN_L
33 (50) SC2_IN_R
330 nF
330 nF
BSP 3505D
100Ω
22 µF
+
5V
11 (7) STANDBYQ
12 (6) ADR_SEL
D_CTR_OUT0 (5) 13
D_CTR_OUT1 (4) 14
5V
DVSS
DVSS
2
TESTEN (61) 22
8 (10) I C_DA
2
9 (9) I C_CL
AVSS
100
nF
100
nF
100
nF
+
ResetQ
(from CCU,
see
10 µF
5 V
5 V
8.0 V
section.3.3.)
Note: Pin numbers refer to the PLCC68 package, numbers in brackets refer to the PSDIP64 package.
Application Note:
more than one capacitor. By choosing different values,
the frequency range of active decoupling can be ex-
tended. In our application boards we use: 220 pF,
470 pF, 1.5 nF, and 10 µF. The capacitor with lowest val-
ue should be placed nearest to the DVSUP and DVSS
pins.
All ground pins should be connected to onelow-resistive
ground plane.
All supply pins should be connected separately with
short and low-resistive lines to the power supply.
Decouplingcapacitors fromDVSUPtoDVSS, AVSUPto
AVSS, and AHVSUP to AHVSS are recommended as
close as possible to these pins. Decoupling of DVSUP
and DVSS is most important. We recommend using
The ASG1 pin should be connected as closely as pos-
sibletotheMSPtoground. IfitisleadwiththeSC1input-
lines as shielding line, it should NOT be conneted to
ground at the SCART connector.
MICRONAS INTERMETALL
37
BSP 3505D
PRELIMINARY DATA SHEET
38
MICRONAS INTERMETALL
BSP 3505D
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
39
BSP 3505D
PRELIMINARY DATA SHEET
7. Appendix A: BSP 3505D Version History
8. Data Sheet History
1. Preliminary Data Sheet: “BSP 3505D Baseband
Sound Processor”, Oct. 21, 1998, 6251-481-1PD.
First release of the preliminary data sheet.
A2
First hardware release BSP 3505D
MICRONAS INTERMETALL GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
All information and data contained in this data sheet are with-
out any commitment, are not to be considered as an offer for
conclusion of a contract nor shall they be construed as to
create any liability. Any new issue of this data sheet invalidates
previous issues. Product availability and delivery dates are ex-
clusively subject to our respective order confirmation form; the
same applies to orders based on development samples deliv-
ered. By this publication, MICRONAS INTERMETALL GmbH
does not assume responsibility for patent infringements or
other rights of third parties which may result from its use.
Reprinting is generally permitted, indicating the source. How-
ever, our prior consent must be obtained in all cases.
E-mail: docservice@intermetall.de
Internet: http://www.intermetall.de
Printed in Germany
Order No. 6251-481-1PD
40
MICRONAS INTERMETALL
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