CDC3207G-B [TDK]
Microcontroller, 32-Bit, FLASH, ARM7 CPU, 50MHz, CMOS, PQFP128;
| 型号： | CDC3207G-B |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | Microcontroller, 32-Bit, FLASH, ARM7 CPU, 50MHz, CMOS, PQFP128 微控制器 |
| 文件： | 总230页 (文件大小：1800K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
CDC 32xxG-B
Automotive Controller
Family User Manual
CDC 3205G-B
Automotive Controller
Edition Nov. 28, 2002
6251-546-1PD
MICRONAS
CDC 32xxG-B
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
7
1.
Introduction
7
1.1.
Features
9
1.2.
1.3.
Abbreviations
Block Diagram
10
11
2.
Packages and Pins
11
2.1.
Pin Assignment
14
15
15
19
20
2.2.
2.3.
2.4.
2.5.
2.6.
Package Outline Dimensions
Multiple Function Pins
Pin Function Description
External Components
Pin Circuits
23
3.
Electrical Data
23
3.1.
Absolute Maximum Ratings
24
25
33
3.2.
3.3.
3.4.
Recommended Operating Conditions
Characteristics
Recommended Quartz Crystal Characteristics
35
4.
CPU and Clock System
35
4.1.
ARM7TDMI‘ CPU
35
38
40
41
42
44
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
CPU Modes
Clock System
EMI Reduction Module (ERM)
Memory Controller
Registers
PLL/ERM Application Notes
47
5.
Memory and Boot System
48
5.1.
RAM and ROM
49
50
5.2.
5.3.
I/O Map
Boot System
51
6.
Core Logic
51
6.1.
Control Word CW
52
54
56
59
6.2.
6.3.
6.4.
6.5.
Standby Registers
UVDD Analog Section
Reset Logic
Test Registers
61
7.
JTAG Interface
61
7.1.
Functional Description
62
62
7.2.
7.3.
External Circuit Layout
JTAG ID
63
8.
Embedded Trace Module (ETM)
63
8.1.
Functional Description
65
9.
IRQ Interrupt Controller Unit (ICU)
65
9.1.
Functional Description
2
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Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Contents, continued
Page
Section
Title
68
68
70
70
9.2.
9.3.
9.4.
9.5.
Timing
Registers
Principle of Operation
Application Hints
73
10.
FIQ Interrupt Logic
73
10.1.
Functional Description
73
74
10.2.
10.3.
Registers
Principle of Operation
75
11.
Port Interrupts
77
12.
Ports
77
12.1.
Analog Input Port
78
80
82
83
12.2.
12.3.
12.4.
12.5.
Universal Ports U0 to U8
Universal Port Registers
High Current Ports H0 to H7
High Current Port Registers
85
13.
AVDD Analog Section
86
13.1.
VREFINT Generator
86
86
86
87
87
89
13.2.
13.3.
13.4.
13.5.
13.6.
13.7.
BVDD Regulator
Wait Comparator
P0.6 Comparator
PLL/ERM
A/D Converter (ADC)
Registers
91
14.
Timers (TIMER)
91
14.1.
Timer T0
93
14.2.
Timer T1 to T4
95
15.
Pulse Width Modulator (PWM)
95
15.1.
Principle of Operation
96
15.2.
Registers
99
16.
Pulse Frequency Modulator (PFM)
99
16.1.
Principle of Operation
100
16.2.
Registers
101
17.
Capture Compare Module (CAPCOM)
103
17.1.
Principle of Operation
105
17.2.
Registers
107
18.
Stepper Motor Module VDO (SMV)
107
18.1.
Principle of Operation
111
112
18.2.
18.3.
Registers
Timing
113
19.
LCD Module
113
19.1.
Principle of Operation
Micronas
Nov. 28, 2002; 6251-546-1PD
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CDC 32xxG-B
PRELIMINARY DATA SHEET
Contents, continued
Page
Section
Title
116
116
19.2.
19.3.
Registers
Application Hints for Cascading LCD Modules
117
20.
DMA Controller
117
20.1.
Functions
119
120
121
20.2.
20.3.
20.4.
Registers
Principle of Operation
Timing Diagrams
125
21.
Graphic Bus Interface
125
21.1.
Functions
125
126
21.2.
21.3.
GB Registers
Principle of Operation
129
22.
Serial Synchronous Peripheral Interface (SPI)
130
22.1.
Principle of Operation
131
132
22.2.
22.3.
Registers
Timing
133
23.
Universal Asynchronous Receiver Transmitter (UART)
134
23.1.
Principle of Operation
136
138
23.2.
23.3.
Timing
Registers
141
24.
I2C-Bus Master Interface
142
24.1.
Principle of Operation
143
24.2.
Registers
145
25.
CAN Manual
146
25.1.
Abbreviations
146
152
157
159
25.2.
25.3.
25.4.
25.5.
Functional Description
Application Notes
Bit Timing Logic
Bus Coupling
161
26.
DIGITbus System Description
161
26.1.
Bus Signal and Protocol
161
162
163
26.2.
26.3.
26.4.
Other Features
Standard Functions
Optional Functions
165
27.
DIGITbus Master Module
165
27.1.
Context
166
168
171
174
27.2.
27.3.
27.4.
27.5.
Functional Description
Registers
Principle of Operation
Timings
175
28.
Audio Module (AM)
176
28.1.
Functional Description
4
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PRELIMINARY DATA SHEET
CDC 32xxG-B
Contents, continued
Page
Section
Title
180
28.2.
Registers
181
29.
Hardware Options
181
29.1.
Functional Description
182
183
29.2.
29.3.
Listing of Dedicated Addresses of the Hardware Options Field
HW Options Registers and Code
189
30.
Register Cross Reference Table
189
30.1.
8 Bit I/O Region
194
30.2.
32 Bit I/O Region
195
31.
Register Quick Reference
219
32.
Control Register and Memory Interface
219
32.1.
Control Register CR
222
32.2.
External Memory Interface
229
230
33.
34.
Differences
Data Sheet History
Micronas
Nov. 28, 2002; 6251-546-1PD
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CDC 32xxG-B
PRELIMINARY DATA SHEET
Contents, continued
Page
Section
Title
6
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
1. Introduction
The device is a microcontroller for use in automotive applica-
tions. The on-chip CPU is ARM processor ARM7TDMI
with 32bit data and address bus, which supports Thumb
format instructions.
The chip contains timer/counters, interrupt controller, multi
channel AD converter, stepper motor and LCD driver, CAN
interfaces and PWM outputs and a crystal clock multiplying
PLL.
1.1. Features
Table 1–1: CDC32xxG-B Family Feature List
This Device:
Item
CDC3205G-A
EMU
CDC3205G-B
EMU
CDC3207G-B
MCM-Flash
CDC3272G-B
Mask ROM
Core
CPU
32bit ARM7TDMI
CPU operation modes
CPU clock multiplication
DEEP SLOW, SLOW, FAST and PLL
PLL delivering up
to 24MHz
PLL delivering up to 50MHz
EMI Reduction Mode
Quartz oscillator
RAM, 32bit wide
ROM
-
selectable in PLL mode
4 to 5MHz
16kByte
32kByte
32kByte
12kByte
ROMless,
ROMless, ext. upto 512-kByte Flash
384kByte
ext. up to
4M x 32/
8M x 16,
int. 8-KByte Boot
ROM
(256K x 16)
top boot conf.,
int. 8-KByte Boot
ROM
(96K x 32/
192K x 16), +
8-KByte Test ROM
4M x 32/8M x 16,
int. 8-KByte Boot
ROM
Digital Watchdog
✔
✔
Central Clock Divider
Interrupt Controller expanding
IRQ
40 inputs,16 priority levels
Port Interrupts including Slope
Selection
6 inputs
-
Patch Module
Boot System
10 ROM locations
-
allows in-system downloading of external code to Flash memory
via JTAG
Micronas
Nov. 28, 2002; 6251-546-1PD
7
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 1–1: CDC32xxG-B Family Feature List
This Device:
Item
CDC3205G-A
EMU
CDC3205G-B
EMU
CDC3207G-B
MCM-Flash
CDC3272G-B
Mask ROM
Analog
Reset/Alarm
Combined Input for Regulator Input Supervision
Clock and Supply Supervision
10 Bit ADC, charge balance type
✔
16 channels (6
selectable as digi-
tal input)
16 channels (each selectable as digital input)
ADC Reference
Comparators
VREF Pin
VREF Pin, P1.0 Pin, P1.1 Pin or VREFINT Internal Bandgap
selectable
P06COMP with 1/2 P06COMP with 1/2 AVDD reference,
AVDD reference WAITCOMP with Internal Bandgap reference
LCD
Internal processing of all analog voltages for the LCD driver
Communication
DMA
1 DMA Channel for
servicing a port or
an SPI
3 DMA Channels, one each for servicing the Graphics Bus inter-
face, SPI0 and SPI1
UART
2: UART0 and UART1
2: SPI0 and SPI1
Synchronous Serial Peripheral
Interfaces
Full CAN modules V2.0B
3: CAN0, CAN1
and CAN2 with
256bytes of object
RAM each
3: CAN0, CAN1 and CAN2 with 512bytes
of object RAM each (LCAN0009)
2: CAN0 and CAN1
with 512bytes of
object RAM each
(LCAN0009)
(LCAN0009)
DIGITbus
I2C
1 master module
2 master modules: I2C0 and I2C1
Input & Output
Universal Ports selectable as 4:1
mux LCD Segment/Backplane
lines or Digital I/O Ports
up to 54 I/O or 50
LCD segment lines
(=200 segments)
up to 52 I/O or 48 LCD segment lines (=192 segments),
individually configurable as I/O or LCD
Universal Port Slew Rate
Mask selectable
7 Modules,
SW selectable
Stepper Motor Control Modules
with high current ports
32 dI/dt controlled ports
PWM Modules, each configurable
as two 8Bit PWMs or one 16Bit
PWM
6 Modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 and PWM10/11
Phase-Frequency Modulator
Audio Module with auto-decay
SW selectable Clock outputs
-
1: PFM0
✔
2
8
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 1–1: CDC32xxG-B Family Feature List
This Device:
Item
CDC3205G-A
EMU
CDC3205G-B
EMU
CDC3207G-B
MCM-Flash
CDC3272G-B
Mask ROM
Timers & Counters
16bit free running counters with
Capture/Compare modules
CCC0 with 4 CAPCOM
CCC1 with 2 CAPCOM
16bit timers
8bit timers
1: T0
4: T1, T2, T3 and T4
Miscellaneous
Scalable layout in CAN, RAM and
ROM
-
✔
Various randomly selectable HW
options
Set by copy from user program storage during system start-up
JTAG test interface
✔
allows Flash pro-
gramming
✔
On Chip Debug Aids
Core Bond-Out
Supply Voltage
Case Temperature Range
Package
Embedded Trace Module, JTAG
JTAG
-
✔
4.5 to 5.5V
0 to +70C
3.5 to 5.5V (limited I/O performance below 4.5V)
-40 to +105C
Type
Ceramic 257PGA
256
Plastic 128QFP
0.5mm pitch
Bonded Pins
128
126
ARM and Thumb are the registered trademarks of ARM Limited.
ARM7TDMI is the trademark of ARM Limited.
1.2. Abbreviations
AM
Audio Module
UART
Universal Asynchronous Receiver Transmitter
CAN
CAPCOM
CCC
CPU
DMA
ERM
ETM
ICU
Controller Area Network Module
Capture/Compare Module
Capture/Compare Counter
Central Processing Unit
Direct Memory Access Module
EMI Reduction Mode
WAITCOMP Wait Comparator
Embedded Trace Module
Interrupt Controller
I2C
I2C Interface Module
LCD
P06COMP
PINT
PWM
SM
Liquid Crystal Display Module
P0.6 Alarm Comparator
Port Interrupt Module
8Bit Pulse Width Modulator Module
Stepper Motor Control Module
Serial Synchronous Peripheral Interface
Timer
SPI
T
Micronas
Nov. 28, 2002; 6251-546-1PD
9
CDC 32xxG-B
PRELIMINARY DATA SHEET
1.3. Block Diagram
FVDD
FVSS
UVDD
UVSS
VDD
VSS
Data-,
RESETQ
Reset/Alarm
address- and
control bus,
(Emu only)
52
3.3V Reg.
2.5V Reg.
TEST
TEST2
Test
Watchdog
Clock
EVDD
EVSS
ETM
XTAL1
XTAL2
21
(Emu only)
PLL/ERM
WAIT
WAITH
40 Input
Interrupt
ARM7TDMI
CPU
Controller
VREFINT
VREF
AVDD
AVSS
BVDD
2.5V Reg.
JTAG
and
Interface
Test
Debug
5
SRAM
8K x 32
8
8
DMA Logic
8
8
32
ROMless
or
512K Flash
16
Wait Comp.
P06 Comp.
Memory
Controller
2
Boot ROM
4K x 16
Bandgap Ref.
10Bit ADC
4
4
4
4
4
4
4
4
7
Bridge
8
8
4
16Bit Timer 0
UART 0
UART 1
SPI 0
LCD Control
Stepper Motor
Control
16Bit CCC 0
8Bit Timer 1
8Bit Timer 2
8Bit Timer 3
8Bit Timer 4
CAPCOM 0
CAPCOM 1
CAPCOM 2
CAPCOM 3
8Bit PWM 0
Audio Module
8/16B PWM 1
Clock Out 0
Clock Out 1
8Bit PWM 2
SPI 1
4
8/16B PWM 3
16Bit CCC 1
8Bit PWM 4
CAN 0
CAN 1
CAN 2
DIGITbus
Phase-Freq.-
Modulator
CAPCOM 4
CAPCOM 5
8/16B PWM 5
3
4
8Bit PWM 6
8/16B PWM 7
8Bit PWM 8
8/16B PWM 9
2
8Bit PWM 10
I C 0
HVDD0
HVSS0
HVDD1
HVSS1
HVDD2
HVSS2
HVDD3
HVSS3
8/16B PWM 11
6
2
I C 1
UVDD
UVSS
Fig. 1–1: CDC3205G-B block diagram
10
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
2. Packages and Pins
2.1. Pin Assignment
CDC 32xxG-B
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Y
W
V
U
T
129 125 121 117 113 109 105 101 99 97 95 93 91 89 85 81 77 73 69 65
Y
W
V
U
T
133 127 123 119 115 111 107 103 104 98 96 90 87 83 79 75 71 67 63 61
137 131 128 124 120 116 114 110 108 102 92 86 84 80 76 72 68 64 59 57
141 135 132 130 126 122 118 112 106 100 94 88 82 78 74 70 66 60 55 53
145 139 136 134
149 143 140 138
153 147 144 142
155 151 148 146
157 154 150 152
159 160 156 158
161 162 166 164
163 168 172 170
165 167 174 176
169 171 178 182
173 175 180 186
177 179 184 190
62 56 51 49
58 52 47 45
54 50 43 41
48 46 39 37
42 44 40 35
36 38 34 33
30 28 32 31
24 22 26 29
18 20 23 27
14 16 19 25
10 12 15 21
R
P
N
M
L
R
P
N
M
L
Top View
K
J
K
J
H
G
F
H
G
F
E
D
C
B
A
257
181 183 188 194 198 202 206 210 216 222 228 234 240 246 250 254
6
2
8
4
11 17
E
D
C
B
A
7
3
13
9
185 187 192 196 200 204 208 212 214 220 230 236 238 242 244 248 252 256
189 191 195 199 203 207 211 215 218 224 226 232 231 235 239 243 247 251 255
193 197 201 205 209 213 217 219 221 223 225 227 229 233 237 241 245 249 253
5
1
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
65
129
Top View
1
A 1
193
257
Fig. 2–1: Pin Map of CPGA257 Package
Micronas
Nov. 28, 2002; 6251-546-1PD
11
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 2–1: Pin Assignment for CPGA257 Package
Table 2–1: Pin Assignment for CPGA257 Package
Pin Co-
No. ord.
Pin Functions
Port
Pin Co-
No. ord.
Pin Functions
Port
Basic
Port
LCD
Basic
Port
LCD
Function Special In
U5.3/GD3 CC4-IN
U5.2/GD2 SDA1
U5.1/GD1 SCL1
U5.0/GD0
Special Out
Mode
Function Special In
Special Out
Mode
1
A1
D4
C2
D3
B1
E4
D2
E3
C1
F4
E2
F3
D1
G4
F2
G3
E1
H4
G2
H3
F1
J3
CC4-OUT
SDA1
SEG5.3
SEG5.2
SEG5.1
SEG5.0
SEG2.1
SEG2.0
SEG1.7
SEG1.6
SEG1.5
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Y1
U4
EVSS6
D0
2
3
SCL1
W3 OEQ
4
PFM0
V4
Y2
U5
CE0Q
BWQ3
BWQ2
5
U2.1
U2.0
U1.7
U1.6
U1.5
TEST
SDA0/CAN0-RX
SDA0
6
SCL0
PINT0
PINT1
PINT2
SCL0/CAN0-TX
PFM0
7
W4 BWQ1
8
CO0/INTRES
CO0Q/CO1
V5
Y3
U6
BWQ0
9
EMUTRI
ABORT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
RESETQ/ALARMQ
W5 EXTERN0
XTAL2
XTAL1
VSS
V6
Y4
U7
EXTERN1
H7.3
SME1+/PWM4
SME1-/PWM6
SME2+/PWM8
SME2-/PWM9
H7.2
VDD
W6 H7.1
U1.4
ITSTOUT/AM-OUT SEG1.4
V7
Y5
U8
H7.0
SME-COMP
U1.3
MTO/AM-PWM
T0-OUT/INTRES
T1-OUT
SEG1.3
SEG1.2
SEG1.1
SEG1.0
SEG0.7
HVDD2
HVSS2
U1.2
U1.1
U1.0
U0.7
U0.6
U0.5
U0.4
U0.3
U0.2
U0.1
U0.0
D31
MTI/ITSTIN
W7 H6.3
PWM8
PWM9
PWM10
PWM11
SMD1+
SMD1-
T2-OUT
V8
Y6
V9
H6.2
H6.1
H6.0
T3-OUT
CC3-IN
PINT4
PINT5
T4-OUT/CC3-OUT SEG0.6
H2
J4
CC3-OUT
CO1
SEG0.5
SEG0.4
SEG0.3
SEG0.2
SEG0.1
SEG0.0
W8 H5.3
U9
Y7
H5.2
G1
J2
PWM0
PWM1
PWM2
PWM3
HVDD0
W9 HVSS0
Y8 H5.1
V10 H5.0
Y9 H4.3
H1
K3
J1
SMD2+
SMD2-
SMA1+
SMA1-
SMA2+
SMA2-
SMB1+
SMB1-
SMB2+
SMB2-
SMC1+
SMC1-
SMD-COMP
SMA-COMP
SMB-COMP
K4
K1
K2
L1
D30
U10 H4.2
Y10 H4.1
D29
W10
D28
H4.0
D27
Y11 H3.3
W11 H3.2
Y12 H3.1
L2
D26
M1 D25
L4
N1
L3
N2
EVDD8
100 U11 H3.0
101 Y13 H2.3
102 V11 H2.2
EVSS8
D24
W13
W12
D23
103
104
HVDD1
HVSS1
M2 D22
P1 D21
M4 D20
P2 D19
M3 D18
105 Y14 H2.1
106 U12 H2.0
SMC2+
SMC2-
SMF1+
SMF1-
SMF2+
SMF2-
SMC-COMP
SMF-COMP
W14
107
H1.3
108 V12 H1.2
109 Y15 H1.1
110 V13 H1.0
R1
N3
R2
N4
T1
P3
T2
R3
U1
P4
U2
T3
V1
R4
V2
U3
D17
D16
D15
D7
W15
111
HVDD3
112 U13 HVSS3
113 Y16 H0.3
114 V14 H0.2
D14
EVDD7
EVSS7
D6
SMG1+/PWM1
SMG1-/PWM3
SMG2+/PWM5
SMG2-/PWM7
W16
115
H0.1
116 V15 H0.0
117 Y17 nTRST
118 U14 ETDI
SMG-COMP
D13
D5
W17
ETMS
D12
D4
119
120 V16 ETCK
121 Y18 ETDO
122 U15 ABE
D11
D3
W18
CE1Q
D10
D2
123
124 V17 FBUSQ
125 Y19 AMCS1
126 U16 AICU2
W1 D9
T4 D1
W2 D8
V3 EVDD6
W19
127
AICU3
128 V18 EVSS5
12
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 2–1: Pin Assignment for CPGA257 Package
Table 2–1: Pin Assignment for CPGA257 Package
Pin Co-
No. ord.
Pin Functions
Port
Pin Co-
No. ord.
Pin Functions
Port
Basic
Port
LCD
Basic
Port
LCD
Function Special In
Special Out
Mode
Function Special In
Special Out
Mode
LCD-SYNC-OUT
CAN2-TX
129 Y20 EVDD5
130 U17 AICU4
131 V19 AICU5
132 U18 AICU6
193 A20 U8.5
194 D17 U8.4
195 B18 U8.3
196 C17 U8.2
197 A19 U8.1
198 D16 U8.0
199 B17 U4.3
200 C16 U4.2
201 A18 U4.1
202 D15 U4.0
203 B16 U3.7
204 C15 U3.6
205 A17 U3.5
206 D14 U3.4
207 B15 U3.3
208 C14 U3.2
209 A16 U3.1
210 D13 U3.0
211 B14 TEST2
212 C13 UVDD1
213 A15 UVSS1
CAN2-RX/PINT3
LCD-SYNC-IN
(CAN3-RX)
SEG8.5
SEG8.4
SEG8.3
SEG8.2
SEG8.1
SEG8.0
BP3
LCD-CLK-OUT
(CAN3-TX)
CC3-OUT
CC4-OUT
TO2
LCD-CLK-IN
W20
133
AICU7
134 T17 A8
135 U19 A18
136 T18 A19
137 V20 EVDD4
138 R17 EVSS4
139 T19 WEQ/RWQ
140 R18 A9
CAN0-RX
CAN0-TX
BP2
CC0-IN
SPI1-D-OUT
CC0-OUT
SPI1-CLK-OUT
SPI0-D-OUT
TO3
BP1
SPI1-D-IN
SPI1-CLK-IN
BP0
SEG3.7
SEG3.6
SEG3.5
SEG3.4
SEG3.3
SEG3.2
SEG3.1
SEG3.0
141 U20 A10
142 P17 A11
143 R19 A12
144 P18 A13
145 T20 A14
146 N17 A15
147 P19 EVDD3
148 N18 EVSS3
149 R20 A16
150 M18 A17
151 N19 A20
152 M17 A21
153 P20 A22
154 M19 A23
155 N20 AMCM21
156 L18 AMCM22
157 M20 EVDD2
158 L17 EVSS2
159 L20 AMCM23
160 L19 SEQ
161 K20 nMREQ
162 K19 MAS0
163 J20 MAS1
164 K17 nRESET
165 H20 P1.7
166 K18 P1.6
167 H19 P1.5
168 J19 P1.4
169 G20 P1.3
170 J17 P1.2
171 G19 P1.1
172 J18 P1.0
173 F20 VREF
174 H18 VREFINT
175 F19 AVDD
176 H17 AVSS
177 E20 BVDD
178 G18 WAIT
179 E19 WAITH
180 F18 P0.7
181 D20 P0.6
182 G17 P0.5
183 D19 P0.4
184 E18 P0.3
185 C20 P0.2
186 F17 P0.1
187 C19 P0.0
188 D18 P2.1
189 B20 P2.0
190 E17 U6.2
191 B19 U6.1
192 C18 U6.0
SPI0-D-IN
SPI0-CLK-IN
SPI0-CLK-OUT
CO0/TDO
CC0-OUT
CC1-OUT
CC2-OUT
CC0-IN / TCK
CC1-IN / TMS
CC2-IN / TDI
214 C12 TRACEPKT0 / TBIT
215 B13 TRACEPKT1 / nM0
216 D12 TRACEPKT2 / nM1
217 A14 TRACEPKT3 / nM2
218 B12 TRACEPKT4 / nM3
219 A13 TRACEPKT5 / nM4
220 C11 EVDD1
221 A12 EVSS1
222 D11 TRACEPKT6 / LOCK
223 A11 TRACEPKT7 / nEXEC
224 B11 TRACEPKT8 / nOPC
225 A10 TRACEPKT9 / nTRANS
226 B10 TRACEPKT10 / A5
227 A9
228 D10 TRACEPKT12 / RANGEOUT0
229 A8 TRACEPKT13 / RANGEOUT1
230 C10 TRACEPKT14 / A7
TRACEPKT15 / BREAKPT
TRACEPKT11 / A6
PINT5
PINT4
PINT3
PINT2
PINT1
PINT0
VREF1
VREF0
231 B8
232 B9
233 A7
234 D9
235 B7
236 C9
237 A6
238 C8
239 B6
240 D8
241 A5
242 C7
243 B5
244 C6
245 A4
246 D7
247 B4
248 C5
249 A3
250 D6
251 B3
252 C4
253 A2
254 D5
255 B2
256 C3
257 E5
PIPESTAT0 / nRW
PIPESTAT1 / A0
PIPESTAT2 / A1
EVDD0
EVSS0
TRACESYNC/A2
TRACECLK/A3
EXTTRIG/A4
FSYS
nWAIT
DBGACK
DBGRQ
UVDD
P0.6 Comp.
UVSS
U2.6
DIGIT-IN
UART0-RX
CC1-IN
DIGIT-OUT
CC1-OUT
UART0-TX
CC2-OUT
UART1-TX
CO0
SEG2.6
SEG2.5
SEG2.4
SEG2.3
SEG2.2
SEG7.7
SEG7.6
SEG7.5
SEG7.4
U2.5
U2.4
U2.3
UART1-RX
CC2-IN
U2.2
CC4-IN
U7.7/GD7
U7.6/GD6
U7.5/GD5
CO1
LCK(/PFM1)
CC5-OUT
GWEQ
GOEQ
SEG6.2
SEG6.1
SEG6.0
U7.4/GD4 CC5-IN
FVDD
CAN1-RX
CAN1-TX
FVSS
Extra insertion Pin: connect to system ground
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CDC 32xxG-B
PRELIMINARY DATA SHEET
2.2. Package Outline Dimensions
2 . 5 4 0 x 1 9 = 4 8 . 2 6
0 . ± 2
2 . 5 4 0
0 . ± 1 5
1
0 . ± 1
0 . 8
0 . 4 6
0 . ± 0 5
Fig. 2–2: CPGA257 Ceramic Pin Grid Array 257-Pin (Weight approx. 32g. Dimensions in mm)
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CDC 32xxG-B
2.3. Multiple Function Pins
2.3.1. U-Ports
2.3.3. Emulator Bus
Beside their basic function (digital I/O), Universal Ports (pre-
fix “U”) have overlaid alternative functions (see Table 2–1 on
page 12).
In contrast to the PQFP128 standard package, the
CPGA257 package has additional pins (Emulator Bus) which
serve as memory interface, Emulation JTAG interface or
connection to an external emulation or trace hardware
(Trace Bus).
How to enable Basic Function, Special In and Special Out
mode is explained in the functional description of the U-
Ports. How to enable LCD mode is explained in the func-
tional descriptions of LCD module and U-Ports.
The functionality of the memory interface and the Trace Bus
is controlled by register CR. Refer to section “Control Word”
for more information.
2.3.2. H-Ports
Some of the following pins are marked as being ARM or
ETM signals. For details of the functionality please refer to
ARM7TDMI Data sheet (Document Number: ARM DDI 0029)
or Embedded Trace Macro Cell (Document Number: ARM
IHI 0014 and ARM DDI 0158).
Beside their basic function (digital I/O), High Current Ports
(prefix “H”) have overlaid alternative functions (see Table 2–
1 on page 12).
How to enable Basic Function, Special In and Special Out
mode is explained in the functional description of the H-
Ports.
2.4. Pin Function Description
A0 to A7 (ARM) 1)
A8 to A23 (ARM) 4)
These 24 lines are the original CPU addresses. Some are
used for external memory access on the Emulator Bus. The
function is controlled by register CR.
AVDD
This is the positive power supply for ADC, P06COMP, WAIT-
COMP and BVDD regulator. AVDD should be kept at UVDD
±0.5V. It must be buffered by an external capacitor to analog
ground
ABE (ARM) 1) 2)
AVSS
This pin outputs the “Address bus enable” signal of the ARM.
It indicates that the CPU does not access the data and
address bus when low. It is not possible to influence the CPU
via this pin.
This is the negative reference for the ADC and the negative
power supply for ADC, P06COMP, WAITCOMP and PLL.
Connect to analog ground.
BP0 to BP3
ABORT (ARM) 3)
This is an input which allows the memory system to tell the
processor that a requested access is not allowed.
These pin functions serve as Backplane drivers for a 4:1
multiplexed LCD.
BREAKPT (ARM) 3)
AICU2 to AICU7 4)
This is the input pin for the ARM BREAKPT signal in Full
Trace mode. It allows external hardware to halt the execution
of the processor for debug purposes.
These pins correspond to the ARM address bus lines A2 to
A7 but can be modified by the ICU. In the latter case AICUx
and Ax are not equal.
BVDD
ALARMQ
This is the output of the internal 2.5V regulator for the PLL. It
must be buffered by an external capacitor to analog ground.
This is the second input comparator level on the RESETQ
pin.
BWQ0 to BWQ3 4)
AMCM21 to AMCM23 4)
This is the byte write control signal to an external 32bit mem-
ory.
These pins correspond to the ARM address bus lines A21 to
A23 but can be modified by the memory controller. In the lat-
ter case AMCMx and Ax are not equal.
CAN0-RX, CAN1-RX, CAN2-RX
These signals provide the input lines for the CAN0, CAN1,
CAN2 and CAN3 modules.
AMCS1 4)
This pin corresponds to the ARM address bus line A1 but
can be modified by the memory controller. In the latter case
AMCS1 and A1 are not equal.
CAN0-TX, CAN1-TX, CAN2-TX
These signals provide the output lines for the CAN0, CAN1,
CAN2 and CAN3 modules.
AM-OUT
CC0-IN, CC1-IN, CC2-IN, CC3-IN, CC4-IN, CC5-IN
These signals are the capture inputs of the CAPCOM0 to
CAPCOM5 modules.
This is the output signal of the Audio Module.
AM-PWM
This is the output signal of the 8-bit PWM of the Audio Mod-
ule. It is intended for testing only.
CC0-OUT, CC1-OUT, CC2-OUT, CC3-OUT, CC4-OUT,
CC5-OUT
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PRELIMINARY DATA SHEET
These signals are the compare outputs of the CAPCOM0 to
CAPCOM5 modules.
EVSS0 to EVSS8
These 9 lines form the negative supply of the Emulator Bus
and Trace drivers. EVSS0 to EVSS8 have to be hard wired
to system ground.
CE0Q 4)
Chip Enable output signal connects to external program
memory’s CEQ pin. With CR.EFLA set it serves to reduce
program memory’s power consumption when CPU operates
in slow mode. Active LOW.
EXTERN0, EXTERN1 (ARM) 3)
These are inputs to the ICEBreaker logic of the ARM which
allows breakpoints and/or watch points to be dependent on
an external condition.
CE1Q 4)
Chip Enable output signal connects to external RAM or Boot
ROM memory’s CEQ pin and reduces it’s power consump-
tion when CPU operates in slow mode. Active LOW.
EXTTRIG (ETM) 2)
This is a trigger input to the ETM.
FBUSQ 4)
CO0, CO0Q, CO1
This signal is the reference for access to external synchro-
nous memory. It is active for memory access only.
These signals provide frequency outputs. They are con-
nected to internal prescaler and multiplexer. They can be
hard wired by HW Option. Refer to section “Hardware
Options” for setting the CO0/CO1 options and section “CPU
and Clock System” setting the Clock Out 0 Selection regis-
ter.
FSYS
This signal provides the system frequency clock fSYS. It is
the PLL output frequency if PLL is enabled.
FVDD
This is the output of the internal 3.3V regulator for the exter-
nal Flash chip. It must be buffered by an external capacitor to
FVSS.
For testing purposes it is possible to drive clocks and other
signals of internal peripheral modules out of CO0 and CO1.
Selection is done via register TST2.
FVSS
D0 to D31 (ARM) 4)
This is the ground reference of the internal 3.3V regulator for
the external Flash chip.
These 32 signals are the original CPU bidirectional Data Bus
lines. They provide the 32bit data bus for use during data
exchanges between the microprocessor and external mem-
ory or peripherals.
GD0 to GD7
These eight Graphics IC Data lines provide an 8-bit DMA
controlled data link to an external IC.
DBGACK (ARM)
This is the debug acknowledge output signal of the ARM.
When high indicates ARM is in debug state.
GOEQ
This Graphics IC Read line provides the control signal for
read accesses via the GD7 to GD0 bus. Active LOW.
DBGRQ (ARM) 3)
This is the debug request input of the ARM. It is a level-sen-
sitive input, which when high causes ARM to enter debug
state after executing the current instruction.
GWEQ
This Graphics IC Write line provides the control signal for
write accesses via the GD7 to GD0 bus. Active LOW.
DIGIT-IN
H0.0 to H7.3
This is the receive input line of the DIGITbus module.
The High Current Ports are intended for use as digital I/O
which can drive higher currents than the Universal Ports.
DIGIT-OUT
This is the transmit output line of the DIGITbus module.
HVDD0 to HVDD3
The pins HVDD0 to HVDD3 are the positive power supply of
the high current ports H0.0 to H7.3. HVDD0 to HVDD3
should be kept at UVDD ±0.5V. Be careful to design the PCB
traces for carrying the considerable operating current on
these pins.
EMUTRI
This input signal allows to tristate (= high) the interface pins
to external memory (A8 to A23, AMCS1, AICU2 to AICU7,
AMCM21 to AMCM23, CE1Q, FBUSQ and WEQ/RWQ).
ETCK (ARM)
HVSS0 to HVSS3
This pin is the ARM “Test clock” input (TCK) of the Emulation
JTAG interface.
The pins HVSS1 to HVSS3 are the negative power supply
for the high current ports H0.0 to H7.3. HVSS0 to HVSS3
have to be hard wired to system ground. Be careful to layout
sufficient PCB traces for carrying the considerable operating
current on these pins.
ETDI (ARM)
This pin is the ARM “Test data input” (TDI) of the Emulation
JTAG interface.
ETDO (ARM)
INTRES
This pin is the ARM “Test data output” (TDO) of the Emula-
tion JTAG interface.
Test output of internal reset signal. Only for testing and avail-
able only in test mode.
ETMS (ARM)
ITSTIN
This pin is the ARM “Test mode select” (TMS) input of the
Emulation JTAG interface.
Test input signal for Interrupt Controller. Only for testing and
available only in test mode.
EVDD0 to EVDD8
ITSTOUT
These 9 lines form the positive power supply of the Emulator
and Trace Bus drivers. EVDD0 to EVDD8 may be connected
to any voltage between 3 to 5.5V. Normally they are con-
nected to FVDD.
Test output signal of internal peripheral modules. Only for
testing and available only in test mode.
LCD-CLK-IN
The Clock input of the LCD module receives the clock of an
optional external LCD master driver which is used to extend
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CDC 32xxG-B
the LCD driver capability. This input is active if the internal
LCD module is configured as slave and the external LCD
driver operates as master.
nTRST (ARM)
This pin is the “Not test reset” signal of the ARM. It resets the
boundary scan logic of the CPU when low. It is also the reset
for the Emulation JTAG interface (not for the application
JTAG interface).
LCD-CLK-OUT
The Clock output of the LCD module provides a clock signal
to optional external LCD slave drivers if the internal LCD
module is configured as master and the other LCD drivers
are slaves.
nWAIT (ARM) 1) 2)
This pin outputs the “Not wait” signal of the ARM. It is not
possible to cause a wait via this pin.
LCD-SYNC-IN
OEQ 4)
The Synchronization input of the LCD module receives the
sync signal from an optional external LCD master driver.
This input is active if the internal LCD module is configured
as slave and the external LCD driver serves as master.
The Output Enable signal connects to the OEQ pin of exter-
nal memory for read access. Active LOW.
P0.0 to P0.7, P1.0 to 1.7 and P2.0 to P2.1
P0.0 to P1.7 are 16 analog ports that are the multiplexed
input channels of the ADC. All analog ports P0.0 to P2.1 can
also be used as digital input lines. The analog ports P1.2 to
P1.7 can also be used as port interrupts.
LCD-SYNC-OUT
The Synchronization output of the LCD module provides a
sync signal to optional external LCD slave drivers if the inter-
nal LCD module is configured as master and the other LCD
drivers are slaves.
P06 Comp.
The analog port P0.6 is additionally input to the P06 compar-
LCK
ator.
This output signal indicates that the PLL has locked.
PFM0
LOCK (ARM) 1)
This is the output of the Pulse Frequency Module, PFM.
This is the LOCK output signal of the ARM indicating that the
processor is performing a “locked” memory access when
high.
PINT0 to PINT5
The Port Interrupt 0 to 5 inputs serves as inputs to the inter-
rupt controller via the port interrupt module. HW option
PM.PINT has to be set to determine which of the possible
input pins are used as source of PINT0 to 5.
MAS0, MAS1 (ARM) 1) 2)
These are ARM output signals used by the processor to indi-
cate to the external memory system when a word transfer or
a half-word or a byte length is required.
PIPESTAT0 to PIPESTAT2 (ETM) 2)
These signals indicate the pipeline status of the ETM.
MTI
PWM0 to PWM11
This is a test input line. It is intended for factory test only. The
These are the outputs of the PWM module. Some of these
PWM signals are directed to two pins.
application should not use this signal.
MTO
RANGEOUT0, RANGEOUT1 (ARM) 1)
This is a test output line. It is intended for factory test only.
The application should not use this signal.
These pins output the “ICEBreaker rangeout” signals of the
ARM. They indicate that ICEBreaker watch point register 0
or 1 has matched the conditions currently present on the
address, data and control busses.
nEXEC (ARM) 1)
This is the “Not executed” signal of the ARM indicating that
the instruction in the execution unit is not being executed
when high.
RESETQ
This bidirectional signal is used to initialize all modules and
start program execution.
nM0 to nM4 (ARM) 1)
These pins output the “Not processor mode” signal of the
ARM.
Two comparators distinguish three input levels:
– A low level resets all internal modules.
nMREQ (ARM) 1) 2)
This pin outputs the “Not memory request” signal of the
ARM. The processor requires memory access during the fol-
lowing cycle when low.
– A medium level activates all internal modules and starts
program execution. An alarm signal is generated which can
be directed to the interrupt controller.
– A high level keeps all internal modules active and cancels
the alarm signal.
nOPC (ARM) 1)
This pin outputs the “Not op-code fetch” signal of the ARM.
The processor is fetching an instruction from memory when
low.
The RESETQ input signal must be held low for at least two
clock cycles after VDD reaches operating voltage.
nRESET (ARM)
This pin outputs the “Not reset” signal of the ARM. This pin is
not an input.
Internal reset sources output their reset request on the
RESETQ pin via an internal open drain pull-down transistor.
Thus RESETQ can be wire-ored with external reset sources.
The internally limited pull-down current allows direct connec-
tion to large capacitors. The connection of such a capacitor
(e.g. 10nF) is recommended to reduce the capacitive influ-
ence of the neighboring XTAL2 pin.
nRW (ARM) 1)
This pin outputs the “Not read/write” signal of the ARM. High
indicates a processor write cycle, low a read cycle.
nTRANS (ARM) 1)
RESETQ must be pulled up by an external pull-up resistor
(e.g. 10kΩ).
This pin outputs the “Not memory translate” signal of the
ARM. When low it indicates that the processor is in user
mode.
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RWQ 4)
TEST, TEST2
This is an interface signal to external memory.
Pins TEST and TEST2 define the source for the Control
Word fetch during reset. Please refer to section “Core Logic”
for detailed information.
SCL0 to SCL1
These are the serial clock lines of the I2C modules.
TEST2 serves to enable the JTAG interface. Refer to section
“JTAG Interface“ for detailed information.
SDA0 to SDA1
These are the serial data lines of the I2C modules.
For normal operation with internal code connect TEST and
TEST2 to System Ground or leave it floating (internal pull-
down).
SEG0.0 to SEG8.5
These pin functions serve as Segment drivers for a 4:1 multi-
plexed LCD.
TMS (ARM)
SEQ (ARM) 1) 2)
This pin is the ARM “Test mode select” input of the applica-
tion JTAG interface.
This pin outputs the “Sequential address” signal of the ARM.
High indicates that the address of the next memory cycle will
be related to that of the last memory access.
TO2 and TO3
Test outputs.
SMA to SMG
These lines are intended for driving stepper motors. They
are the outputs of the SM. Two of these lines together with
an external coil form an H-bridge. Thus each of the signals
SMA to SMG can drive a two phase bipolar stepper motor.
TRACECLK (ETM) 2)
This is the output of the modified CLK signal of the ETM.
TRACEPKT0 to TRACEPKT15 (ETM) 2)
This is the trace packet port of the ETM.
SMA-COMP to SMG-COMP
TRACEPKT15 is pulled low to prevent floating, when full
trace mode is enabled.
These lines are comparator inputs that connect to one line
each of the SMA to SMG lines. They serve to distinguish
rotation from stand-still during zero detection in each stepper
motor.
TRACESYNC (ETM) 2)
This is the synchronization signal from the ETM, indicating
the start of a branch sequence on the trace packet port.
SPI0-CLK-IN, SPI1-CLK-IN
The Serial Synchronous Peripheral Interface Clock input
receives the bit clock from an external master, to shift data in
or out of SPI0 resp. SPI1 in slave mode. This means that the
external master controls the bit stream.
U0.0 to U8.5
Universal ports are intended for use as digital I/O or as LCD
driver outputs.
UART0-RX, UART1-RX
SPI0-CLK-OUT, SPI1-CLK-OUT
These are the Receive input lines of UART0 and UART1.
Polarity of the signals is settable by HW options UA0 resp.
UA1.
The Serial Synchronous Peripheral Interface Clock output
supplies the bit clock of SPI0 resp. SPI1 to an external slave,
to shift data in or out of SPI0 resp. SPI1 in master mode.
This means that the internal SPI controls the bit stream.
UART0-TX, UART1-TX
These are the data output lines of UART0 and UART1.
Polarity of signals is settable by HW options UA0 resp. UA1.
SPI0-D-IN, SPI1-D-IN
These are the data input lines of the SPI0 and SPI1 mod-
ules.
UVDD, UVDD1
The pins UVDD and UVDD1 are the positive 5V supply for
the U-Port output stages, for the VDD regulator and the
FVDD regulator. (see Fig. 2–3 for external connection). It
must be buffered by an external capacitor to UVSS resp.
UVSS1.
SPI0-D-OUT, SPI1-D-OUT
These are the data output lines of the SPI0 and SPI1 mod-
ules.
T0-OUT
The Timer 0 output is connected to the zero output of T0 by a
divide by 2 scaler. The scaler generates a 50% pulse duty
factor.
UVSS, UVSS1
The pins UVSS and UVSS1 are the negative power supply
for the U-Port output stages, and the ground reference for
the VDD and FVDD regulators. They have to be connected
to system ground (see Fig. 2–3).
T1-OUT to T4-OUT
These signals are connected to the overflow outputs of T1 to
T4.
VDD
This is the output of the internal 2.5V regulator for the inter-
nal digital modules (see Fig. 2–3 for external connection). It
must be buffered by an external capacitor to VSS.
TBIT (ARM) 1)
This pin outputs the TBIT signal of the ARM. High indicates
that the processor is executing the THUMB instruction set.
VREF, VREF0, VREF1
TCK (ARM)
These pins are selectable as positive reference inputs for the
ADC. The voltage on these pins should be set to a level
between 2.56 Volts and AVDD.
This pin is the ARM “Test clock” input of the application
JTAG interface.
TDI (ARM)
VREFINT
This pin is the ARM “Test data input” of the application JTAG
interface.
This pin is the positive reference output of the ADC. The volt-
age at this pin is generated internally (approx. 2.5V) and
must be buffered by an external capacitor to AVSS. No DC
load is allowed.
TDO (ARM)
This pin is the ARM “Test data output” of the application
JTAG interface.
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CDC 32xxG-B
VSS
WEQ 4)
The pin VSS is the negative supply terminal of the internal
digital modules (see Fig. 2–3 for external connection).
The output signal Write Enable connects to the external
memory’s WEQ pin and activates it for write access. Active
LOW.
WAIT
This is the positive input to the WAIT comparator. The nega-
tive input is VREFINT. The comparator level can be adjusted
by an external voltage divider.
XTAL1
This is the quartz oscillator or clock input pin (see Fig. 2–3
for external connection).
WAITH
XTAL2
This is the output of the WAIT comparator. The hysteresis
can be adjusted by an external feedback resistor to the volt-
age divider connected to the WAIT pin.
This is the quartz oscillator output pin for two pin oscillator
circuits (see Fig. 2–3 for external connection).
1) Trace Bus output. Active in Analyzer mode.
2) Trace Bus output. Active in ETM mode.
3) Trace Bus input. Always active.
4) Memory interface signal. Tristate if EMUTRI is high.
Please refer to section “Memory Interface” (see Table 32–1 on page 219) for details about interfaces and Trace Bus modes.
2.5. External Components
To provide effective decoupling and to improve EMC behav-
iour, the small decoupling capacitors must be located as
close to the supply pins as possible. The self-inductance of
these capacitors and the parasitic inductance and capaci-
tance of the interconnecting traces determine the self-reso-
nant frequency of the decoupling network. Too low a fre-
quency will reduce decoupling effectiveness, will increase
RF emissions and may adversely affect device operation.
strongly recommended to place quartz and oscillation capac-
itors as close to the pins as possible and to shield the XTAL1
and XTAL2 traces from other signals by embedding them in
a VSS trace.
The RESETQ pin adjacent to XTAL2 should be supplied with
a small capacitor, to prevent fast RESETQ transients from
being coupled into XTAL2, and to prevent XTAL2 from cou-
pling into RESETQ.
XTAL1 and XTAL2 quartz connections are especially sensi-
tive to capacitive coupling from other pc board signals. It is
FVDD
3.3V/5V
Supply
EVDD0 to 8
3.3µ
Tantal
ESR < 14Ω
470n
Ceramic
X7R
9 x 100n to 150n
3.3V
5V
System
Ground
FVSS
EVSS0 to 8
+5V
+5V
Supply
UVDD
UVDD1
HVDD0 to 3
Supply
2 x 100n to 150n
4 x 100n to 150n
5V
2.5V
System
System
Ground
UVSS
UVSS1
HVSS0 to 3
Ground
VDD
220n
Ceramic
X7R
10µ
Tantal
Low ESR
Analog
Supply
AVDD
VSS
100n to 150n
10n, Ceramic
VREFINT
XTAL1
5V
2.5V
18p
18p
Analog
Ground
AVSS
BVDD
150n
Ceramic, X7R
XTAL2
Resetq
RESETQ
Fig. 2–3: CDC3205G-B: Recommended external supply and quartz connection.
Micronas
Nov. 28, 2002; 6251-546-1PD
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CDC 32xxG-B
PRELIMINARY DATA SHEET
2.6. Pin Circuits
VSUP
VSUP
OUT
OUT
VSUP
VSUP
IN
IN
Input
Logic
Input
Logic
GND
GND
IN
IN
GND
GND
OUT
OUT
Fig. 2–4: Input Pins
Fig. 2–9: Push Pull I/O Pins with switchable Pull-Down
VSUP
OUT
VSUP
H
VSUP
IN
Regulator
Logic
Input
Logic
VSUP
L
GND
IN
GND
OUT
GND
GND
L
H
Fig. 2–5: Input Pins with Pull-Down
Fig. 2–10: Regulator Pins
VSUP
OUT
VSUP
IN
Input
Logic
GND
IN
GND
OUT
Fig. 2–6: Push Pull I/O Pins
VSUP
OUT
VSUP
IN
Input
Logic
GND
IN
GND
OUT
Fig. 2–7: Open Drain I/O
VSUP
OUT
GND
OUT
Fig. 2–8: Push Pull Output Pins
20
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 2–2: I/O Supply Catalog
Pin Names
Figure
VSUPOUT
UVDD
GNDOUT
UVSS
AVSS
VSUPIN
UVDD
AVDD
EVDD
GNDIN
UVSS
AVSS
EVSS
XTAL1, XTAL2
2–4
WAIT
AVDD
TCK, TDI, TMS
EVDD
EVSS
EMUTRI, ABORT, EXTERN0, EXTERN1, DBGRQ
2–5
2–6
TEST, TEST2
U-Ports
UVDD
UVSS
UVDD
UVSS
H-Ports
HVDD
AVDD
EVDD
HVSS
AVSS
EVSS
HVDD
AVDD
EVDD
HVSS
AVSS
EVSS
P-Ports
A31 to A0, ABE, AICU7 to 2, AMCM21 to 23,
AMCS1, BWQ0 to 3, CE0Q, CE1Q, D31 to D0,
DBGACK, EXTTRIG, FBUSQ, FSYS, MAS0, MAS1,
nMREQ, nRESET, nTRST, nWAIT, OEQ, PIPSTAT0
to 2, SEQ, TDO, TRACECLK, TRACEPKT0 to 14,
TRACESYNC
RESETQ
2–7
2–8
2–9
UVDD
AVDD
EVDD
UVSS
AVSS
EVSS
UVDD
EVDD
UVSS
EVSS
WAITH
TRACEPKT15
Table 2–3: Regulator Pin Supply Catalog
Regulator
VDD
Figure
VSUPH
UVDD
UVDD
AVDD
GNDH
UVSS
UVSS
AVSS
VSUPL
VDD
GNDL
VSS
2–10
FVDD
FVDD
BVDD
FVSS
AVSS
BVDD
Micronas
Nov. 28, 2002; 6251-546-1PD
21
CDC 32xxG-B
PRELIMINARY DATA SHEET
22
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
3. Electrical Data
3.1. Absolute Maximum Ratings
Table 3–1: UVSS=UVSS1=HVSSn=FVSS=EVSSn=AVSS=0V
Symbol
Parameter
Pin Name
Min.
Max.
Unit
VSUP
Main Supply Voltage
Analog Supply Voltage
SM Supply Voltage
UVDD, UVDD1
AVDD
HVDD0 .. HVDD3
EVDD0 .. EVDD8
-0.3
6.0
V
Flash Port Supply Voltage
VREG
Flash Supply Voltage
FVDD
-0.3
-0.3
4.0
3.0
V
V
Core Supply Voltage
PLL Supply Voltage
VDD
BVDD
ISUP
Core Supply Current
Main Supply Current
VDD, VSS,
UVDD, UVDD1,
UVSS, UVSS1
-100
100
100
mA
mA
Flash Port Supply Current
Analog Supply Current
EVDD0 .. EVDD8
EVSS0 .. EVSS8
-100
-20
AVDD, AVSS
20
mA
mA
SM Supply Current
HVDD0 .. HVDD3 -250
HVSS0 .. HVSS3
250
@TCASE=105C, Duty Factor=0.71 1)
Flash Supply Current
PLL Supply Current
Input Voltage
FDD, FVSS
BVDD
-50
50
mA
mA
V
-20
20
Vin
U-Ports, XTAL,
RESETQ, TEST,
TEST2
UVSS-0.5
UVDD+0.7
P-Ports, VREF
H-Ports
UVSS-0.5
HVSS-0.5
EVSS-0.5
0
AVDD+0.7
V
HVDD+0.7
V
E-Ports
EVDD+0.7
V
Iin
Io
Input Current
all Inputs
2
5
mA
mA
Output Current
U-Ports, E-Ports,
RESETQ, WAITH
-5
H-Ports
-60
60
mA
s
toshsl
Duration of Short Circuit to UVSS or
UVDD, Port SLOW Mode enabled
U-Ports, except in
DP Mode
indefinite
Tj
Junction Temperature under Bias
Storage Temperature
-45
-45
115
125
0.8
°C
°C
W
Ts
Pmax
Maximum Power Dissipation
1) This condition represents the worst case load with regard to the intended application
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended
Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Micronas
Nov. 28, 2002; 6251-546-1PD
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CDC 32xxG-B
PRELIMINARY DATA SHEET
3.2. Recommended Operating Conditions
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply.
Keep UVDD=UVDD1=AVDD during all power-up and power-down sequences.
Failure to comply with the above recommendations will result in unpredictable behaviour of the device and may result in device
destruction..
Table 3–2: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V
Symbol
Parameter
Pin Name
Min.
Typ
Max.
Unit
VSUP
Main Supply Voltage
Analog Supply Voltage
UVDD=UVDD1
=AVDD
3.5
5
5.5
V
Flash Port Supply Voltage
SM Supply Voltage
EVDDn
HVDDn
FVDD
3
5.5
V
V
V
V
HVSUP
VEXT
4.75
3
5
5.25
3.6
External Flash Supply Voltage
3.3
2.5
External Core Supply Voltage
External PLL Supply Voltage
VDD
BVDD
2.25
2.75
dVDD
Ripple, Peak to Peak
UVDD
AVDD
BVDD
FVDD
VDD
200
mV
dVDD/dt
Supply Voltage Up/Down Ramping UVDD
20
5
V/µs
Rate
AVDD
fXTAL
fSYS
fBUS
XTAL Clock Frequency
CPU Clock Frequency, PLL on
XTAL1
4
4
MHz
For a list of available settings see Tables 4–5
and 4–6.
Program Storage Clock Fre-
quency, PLL on
Vil
Automotive Low Input Voltage
U-Ports
H-Ports
P-Ports
0.5*xVDD
0.3*xVDD
V
V
(see Table 2-2
for a list of input
types and their
supply volt-
ages)
CMOS Low Input Voltage
U-Ports, TEST,
TEST2
H-Ports
P-Ports
TTL Low Input Voltage
E-Ports
0.8
V
V
Vih
Automotive High Input Voltage
U-Ports
H-Ports
P-Ports
0.86*xVDD
0.7*xVDD
(see Table 2-2
for a list of input
types and their
supply volt-
ages)
CMOS High Input Voltage
U-Ports,TEST,
TEST2
V
H-Ports
P-Ports
TTL High Input Voltage
E-Ports
2.2
V
V
V
RVil
Reset Active Input Voltage
RESETQ
RESETQ
0.75
2.3
RVim
Reset Inactive and Alarm Active
Input Voltage
1.5
3.2
RVih
Reset Inactive and Alarm Inactive
Input Voltage
RESETQ
V
24
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 3–2: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V
Symbol
VREFi
PVi
Parameter
Pin Name
Min.
2.56
0
Typ
Max.
AVDD
VREF
Unit
V
Ext. ADC Reference Input Voltage
VREF
ADC Port Input Voltage referenced P-Ports
to ext. VREF Reference
V
ADC Port Input Voltage referenced
to int. VREFINT Reference
0
VREFINT
3.3. Characteristics
Table 3–3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V,
3V<EVDDn<5.5V, TCASE=0 to +70C, fXTAL=5MHz, external components according to Fig. 2–3 (unless otherwise noted)
Typ 1)
Symbol
Parameter
Pin
Min.
Max.
Unit
Test Conditions
Name
Package
Rthjc
Thermal Resistance from
Junction to Case
15
C/W
Supply Currents (CMOS levels on all inputs, i.e. Vil=xVSS±0.3V and Vih=xVDD±0.3V, no loads on outputs)
UIDDp
UIDDpe
UIDDf
UVDD PLL Mode Supply
Current
UVDD+
UVDD1
35
mA
mA
mA
mA
mA
fSYS=24MHz, ETM off
fSYS=24MHz, ETM on
all Modules OFF, 2)
all Modules OFF, 2) 6)
all Modules OFF, 6)
ADC ON, PLL OFF
UVDD PLL Mode Supply
Current
UVDD+
UVDD1
45
UVDD FAST Mode Supply
Current
UVDD+
UVDD1
10
UIDDs
UIDDd
AIDDa
UVDD SLOW Mode Supply
Current
UVDD+
UVDD1
1.2
0.7
UVDD DEEP SLOW Mode
Supply Current
UVDD+
UVDD1
AVDD Active Supply Cur-
rent
AVDD
0.35
1
0.6
2
mA
mA
ADC, Buffer and PLL
ON, fSYS=24MHz
AIDDq
EIDDq
HIDDq
Quiescent Supply Current
AVDD
10
10
40
µA
µA
µA
ADC and PLL OFF
no Output Activity
EVDDn
Sum of
all
no Output Activity,
SM Module OFF
HVDDn
1) Typical values describe typical behaviour at room temperature (25C, unless otherwise noted), with typical
Recommended Operating Conditions applied (derived from device characterization, not 100% tested).
Micronas
Nov. 28, 2002; 6251-546-1PD
25
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 3–3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V,
3V<EVDDn<5.5V, TCASE=0 to +70C, fXTAL=5MHz, external components according to Fig. 2–3 (unless otherwise noted)
Typ 1)
Symbol
Parameter
Pin
Min.
Max.
Unit
Test Conditions
Name
Inputs
Vilha
Automotive Input Low to
High Threshold Voltage
U-Ports
H-Ports
P-Ports
0.68*
xVDD
0.76*
xVDD
0.84*
xVDD
V
4.5V<xVDD<5.5V, 3
(see Table 2-2 for a list
of input types and their
supply voltages)
Vihla
Automotive Input High to
Low Threshold Voltage
0.53*
xVDD
0.61*
xVDD
0.69*
xVDD
V
Vilha-Vihla
Automotive Input Hysteresis
0.1*
xVDD
0.15*
xVDD
0.2*
xVDD
V
Vilhc
CMOS Input Low to High
Threshold Voltage
U-Ports
H-Ports
P-Ports
TEST,
0.5*
xVDD
0.6*
xVDD
0.7*
xVDD
V
4.5V<xVDD<5.5V, 3
(see Table 2-2 for a list
of input types and their
supply voltages)
Vihlc
CMOS Input High to Low
Threshold Voltage
0.3*
xVDD
0.4*
xVDD
0.5*
xVDD
V
TEST2
V
ilhc-Vihlc
CMOS Input Hysteresis
Input Leakage Current
0.1*
xVDD
0.2*
xVDD
0.3*
xVDD
V
Ii
U-Ports
H-Ports
P-Ports
P06,
-1
-10
-1
1
10
1
µA
0<Vi<UVDD
0<Vi<HVDD
0<Vi<AVDD
WAIT
VREF
E-Ports
-0.2
-1
-1
0.2
1
1
0<Vi<AVDD
0<Vi<AVDD
0<Vi<EVDD
Ipd
Input Pull-Down Current
Input Pull-Up Current
TEST,
TEST2
E-Ports
10
100
100
-100
220
220
-10
µA
µA
V
Vi=UVDD
10
Vi=EVDD, when unused
Vi=0, when unused
Ipu
E-DB
-220
Outputs (4.5V<UVDD=EVDD<5.5V)
Vol
Port Low Output Voltage
U-Ports,
E-Ports
RESETQ
0.4
0.45
50
Io=2mA
H-Ports
0.125
-50
V
Io=27mA
Io=40mA@TCASE=-40C
Io=30mA@TCASE=25C
∆Vol
Spread of Vol Values within
one SM Driver Module
H-Ports
mV
V
Voh
Port High Output Voltage
U-Ports
E-Ports
UVDD
0.4
EVDD
0.4
-
Io=-2mA
-
H-Ports
H-Ports
HVDD
0.55
-
HVDD
0.125
-
V
Io=-27mA
Io=-40mA@TCASE=-40C
Io=-30mA@TCASE=25C
∆Voh
Spread of Voh Values within
one SM Driver Module
-50
50
mV
1) Typical values describe typical behaviour at room temperature (25C, unless otherwise noted), with typical
Recommended Operating Conditions applied (derived from device characterization, not 100% tested).
26
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 3–3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V,
3V<EVDDn<5.5V, TCASE=0 to +70C, fXTAL=5MHz, external components according to Fig. 2–3 (unless otherwise noted)
Typ 1)
Symbol
Parameter
Pin
Min.
Max.
Unit
Test Conditions
Name
dVoH/dt
H-Port Slew Rate with
Inductive Load
H-Ports
by first order approximation
defined by the quotient of
the inductive load current
and the external capaci-
tances on the port pin
V/ns
LVol
LCD Port Zero Output Volt-
age
U-Ports
U-Ports
-0.05
0.05
V
V
no load
no load
LVo1
LCD Port Low Output Volt-
age
1/3
*UVDD
1/3
*UVDD
-0.05
+0.05
LVo2
LCD Port High Output Volt-
age
U-Ports
2/3
*UVDD
-0.05
2/3
*UVDD
+0.05
V
no load
no load
LVoh
LCD Port Full Output Volt-
age
U-Ports
U-Ports
UVDD
0.05
-
UVDD
+0.05
V
ΣLIo1
Internal LCD-Low Supply
Short Circuit Current
0.3
mA
Pin Short to 2/3*UVDD
Pin Short to UVSS
-0.3
ΣLIo2
Internal LCD-High Supply
Short Circuit Current
U-Ports
0.3
mA
Pin short to UVDD
-0.3
23
Pin short to 1/3*UVDD
Ishf
Port FAST Short Circuit
Current
U-Ports
U-Ports
U-Ports
14
mA
mA
mA
Pin Short to UVDD or
UVSS, Port FAST Mode
Ishs
Port SLOW Short Circuit
Current
3.7
7.5
5.5
11
Pin Short to UVDD or
UVSS, Port SLOW Mode
Ishsd
Port SLOW Short Circuit
Current, DP Mode
Pin Short to UVDD, Port
SLOW and Double Pull-
Down Modes
References and Comparators, AVDD Section
VREFINT
VREFINT Generator Refer-
ence Output Voltage
VREFINT 2.38
VREFINT
2.51
500
V
External load current <
1uA
tREFINT
VREFINT Generator Setup
Time after Power-Up on
AVDD, or on leaving SLOW
or DEEP SLOW mode
µs
VREFP06
P06 Comparator Reference
Voltage
P06
0.49*
AVDD
0.51*
AVDD
V
V
V
3)
P06Vlh-
P06Vhl
P06ComparatorHysteresis, P06
symmetrical to VREFP06
0.02 *
AVDD
0.05 *
AVDD
VREFW
WAIT Comparator Refer-
ence Voltage
WAIT
0.98*
VRE-
1.02*
VRE-
FINT
FINT
VWol
WAIT Comparator Low Out- WAITH
put Voltage
0.4
V
4.5V<xVDD<5.5V
Io=50uA
1) Typical values describe typical behaviour at room temperature (25C, unless otherwise noted), with typical
Recommended Operating Conditions applied (derived from device characterization, not 100% tested).
Micronas
Nov. 28, 2002; 6251-546-1PD
27
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 3–3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V,
3V<EVDDn<5.5V, TCASE=0 to +70C, fXTAL=5MHz, external components according to Fig. 2–3 (unless otherwise noted)
Typ 1)
Symbol
VWoh
Parameter
Pin
Name
Min.
Max.
Unit
V
Test Conditions
WAIT Comparator High Out- WAITH
put Voltage
AVDD
0.4V
-
4.5V<xVDD<5.5V
Io=-50uA
tACDEL
P06, WAIT Comparator
Delay Time
P06
WAIT
1
µs
Overdrive=50mV
References and Comparators, UVDD Section
VBG
VBG Generator Reference
Output Voltage
2.25
2.5
2.75
V
V
V
V
V
V
µs
VREFR
RESET Comparator Refer-
ence Voltage
RESETQ
0.45*
VBG
0.45*
VBG
3)
3)
RVlh-
RVhl
RESET Comparator Hyster- RESETQ
esis, symmetrical to VREFR
0.25
0.375
VREFA
ALARM Comparator Refer-
ence Voltage
RESETQ
1.1*
VBG
1.1*
VBG
AVlh-
AVhl
ALARM Comparator Hyster- RESETQ
esis, symmetrical to VREFA
0.1
0.2
VREFPOR
UVDD Power On Reset
Threshold
UVDD
1.125*
VBG
1.125*
VBG
tUCDEL
RESET, ALARM, Compara-
tor Delay Time
RESETQ
1
Overdrive=50mV
References and Comparators, HVDD Section
VREFSM
SM Comparator Reference
Voltage
H00,
H04,
1/9*
HVDD
1/9*
HVDD
V
H20,
-0.07
+0.07
H24,
H32,
H40, H70
tHCDEL
SM Comparator Delay Time H00,
100
ns
Overdrive=50mV
H04,
H20,
H24,
H32,
H40, H70
VDD Regulator
VDD_ro
Regulator Output Voltage
VDD
1.02*
VBG
-30mV
1.02*
VBG
+30mV
V
V
DEEP SLOW Mode
1.02*
1.02*
PLL Mode, fSYS=50MHz
VBG
105mV
-
VBG -
0mV
IDD_rlim
Regulator Internal Output
Current Limit
VDD
VDD
120
275
120
460
400
mA
tVDD_su
Regulator Setup Time after
Power-Up on UVDD
µs
FAST Mode
1) Typical values describe typical behaviour at room temperature (25C, unless otherwise noted), with typical
Recommended Operating Conditions applied (derived from device characterization, not 100% tested).
28
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 3–3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V,
3V<EVDDn<5.5V, TCASE=0 to +70C, fXTAL=5MHz, external components according to Fig. 2–3 (unless otherwise noted)
Typ 1)
Symbol
Parameter
Pin
Min.
Max.
Unit
Test Conditions
Name
BVDD Regulator
BVDD_ro
Regulator Output Voltage
BVDD
VRE-
FINT
-25mV
VRE-
FINT
+25mV
V
PLLC.PMF > 0
PLLC.PMF > 0
BIDD_rlim
Regulator Internal Output
Current Limit
BVDD
BVDD
17
40
70
70
mA
tBVDD_su
Regulator Setup Time after
setting PLLC.PMF > 0
230
µs
FVDD Regulator
FVDD_ro
Regulator Output Voltage
FVDD
VBG
*1.34
-40mV
VBG
*1.34
+40mV
V
V
no load
VBG
VBG
IFVDD=-40mA
*1.34
-170m
*1.34
-40mV
FIDD_rlim
Regulator Internal Output
Current Limit
FVDD
FVDD
52
120
100
200
mA
tFVDD_su
Regulator Setup Time after
Power-Up on UVDD
330
µs
IFVDD=-40mA
ADC (conversion reference VREFC either equal to external reference VREF or internal reference VREFINT
)
LSB
LSB Value
VREFC
/1024
V
INL
Integral Non-Linearity:
-2.5
2.5
LSB
2.4V<VREFC<AVDD
4.5V<AVDD<5.5V
,
difference between the out-
put of an actual ADC and
the line best fitting the out-
put function (best-fit line)
ZE
Zero Error:
-1
-1
1
1
LSB
LSB
2.4V<VREFC<AVDD
4.5V<AVDD<5.5V
,
,
difference between the out-
put of an ideal and an actual
ADC for zero input voltage
FSE
Full-Scale Error:
2.4V<VREFC<AVDD
4.5V<AVDD<5.5V
difference between the out-
put of an ideal and an actual
ADC for full-scale input volt-
age
TUE
QE
Total Unadjusted Error:
maximum sum of integral
non-linearity, zero error and
full-scale error
-3.5
-0.5
3.5
0.5
LSB
LSB
2.4V<VREFC<AVDD
4.5V<AVDD<5.5V
,
Quantization Error:
uncertaincy because of
ADC resolution
2.4V<VREFC<AVDD
4.5V<AVDD<5.5V
,
1) Typical values describe typical behaviour at room temperature (25C, unless otherwise noted), with typical
Recommended Operating Conditions applied (derived from device characterization, not 100% tested).
Micronas
Nov. 28, 2002; 6251-546-1PD
29
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 3–3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V,
3V<EVDDn<5.5V, TCASE=0 to +70C, fXTAL=5MHz, external components according to Fig. 2–3 (unless otherwise noted)
Typ 1)
Symbol
Parameter
Pin
Min.
Max.
Unit
Test Conditions
Name
AE
Absolute Error:
-4
4
LSB
2.4V<VREFC<AVDD
4.5V<AVDD<5.5V
,
difference between the
actual input voltage and the
full-scale weighted equiva-
lent of the binary output
code, all error sources
included
R
A
Conversion Range
Conversion Result
P-Ports
AVSS
VREFC
V
2.4V<VREFC<AVDD
AVSS<Vin<VREFC
INT
hex
(Vin/
LSB)
000
hex
hex
µs
Vin<=AVSS
3FF
Vin>=VREFC
tc
Conversion Time
Sample Time
4
2
TSAMP=0, fIO=10MHz
ts
µs
Ci
Internal Sampling Capaci-
tance during Sampling
Period
7.5
2.5
pF
Buffer off
Buffer on
Ri
Internal Serial Resistance
during Sampling Period
7
kOhm
Buffer off
PLL and ERM
tSUPLL PLL Locking Time
100
µs
@fXTAL=4 MHz,
f
SYS=16MHz
dtPLL
I/O Clock Uncertainty due to
PLL Jitter, short term and
long term
±2.5
ns
ERM off
dtERM
I/O Clock Modulation due to
ERM action, short term and
long term
0
0
7.5
12.5
ns
ERM on, WEAK setting
ERM on, NORMAL set-
ting
0
20
ERM on, STRONG set-
ting
Clock Supervision
FSUP
Clock Supervision Thresh-
old Frequency
XTAL1
70
350
kHz
SPI (Fig. 3–1, Fig. 3–2)
tsoci
thoci
tsoce
Data out Setup Time with
internal clock
SPI-D-
OUT
60 4)
60 4)
ns
ns
ns
@Cl=30pF, Port FAST
mode
Data out Hold Time with
internal clock
SPI-D-
OUT
-60
@Cl=30pF, Port FAST
mode
Data out Setup Time with
external clock
SPI-D-
OUT
3/ fIO
@Cl=30pF, Port FAST
mode
+60 4)
1) Typical values describe typical behaviour at room temperature (25C, unless otherwise noted), with typical
Recommended Operating Conditions applied (derived from device characterization, not 100% tested).
30
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 3–3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V,
3V<EVDDn<5.5V, TCASE=0 to +70C, fXTAL=5MHz, external components according to Fig. 2–3 (unless otherwise noted)
Typ 1)
Symbol
thoce
tsi
Parameter
Pin
Name
Min.
Max.
Unit
ns
Test Conditions
Data out Hold Time with
external clock
SPI-D-
OUT
2/ fIO
60
-
@Cl=30pF, Port FAST
mode
Data in Setup Time with
external clock
SPI-D-IN
1/
ns
fIO+60
4)
thi
Data in Hold Time with
external clock
SPI-D-IN
1/
ns
fIO+60
4)
CAN (Fig. 3–3)
tsrx rx-strobe Time
CAN rx
CAN tx
0
10 4)
60 4)
ns
ns
reference is XTAL1 ris-
ing edge
tdtx
tx-drive Time
15
reference is XTAL1 fall-
ing edge
@Cl=30pF, Port FAST
mode
DIGITbus (Fig. 3–4)
tbtj
Bit Time jitter
DIGIT-
OUT
±10 4)
ns
ns
rising edges, internal
clock master
tfed
Falling edge delay
DIGIT-
OUT
15 5)
tBIT/64
+60 4)
reference is nominal fall-
ing edge
1) Typical values describe typical behaviour at room temperature (25C, unless otherwise noted), with typical
Recommended Operating Conditions applied (derived from device characterization, not 100% tested).
2) Value may be exceeded with unusual Hardware Option setting
3) Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise
4) When ERM is active, this time value is increased by 7.5ns with WEAK ERM setting, by 12.5ns with NORMAL ERM setting and
by 20ns with STRONG ERM setting.
5) When ERM is active, this time value is decreased by 7.5ns with WEAK ERM setting, by 12.5ns with NORMAL ERM setting and
by 20ns with STRONG ERM setting.
6) Measured with external clock. Add 120µA for operation on typical quartz with SR0.XTAL=0 (Oscillator RUN mode).
SPI-CLK-OUT
tsoci
thoci
SPI-D-OUT
SPI-D-IN
Fig. 3–1: SPI: Send and Receive Data with Internal Clock. Timing is valid for inverted clock too (Data valid at positive edge).
Micronas
Nov. 28, 2002; 6251-546-1PD
31
CDC 32xxG-B
PRELIMINARY DATA SHEET
SPI-CLK-IN
SPI-D-IN
thi
tsi
SPI-CLK-IN
SPI-D-OUT
tsoce
thoce
Fig. 3–2: SPI: Send and Receive Data with External Clock. Timing is valid for inverted clock too (Data valid at positive edge).
tcyc
XTAL1
tdtx
tsrx
TX
RX
Fig. 3–3: CAN I/O Timing.
tBIT
DIGIT-IN
DIGIT-OUT
tfed
tbtj
tbtj
nominal pulse
tNPL
tNPL: Nominal programmed Pulse Length. Depends on programmed phase, Baudrate and transmitted sign (0, 1, T).
Should be 1/4 for sign 0, 1/2 for sign 1 and 3/4 for sign T of tBIT
.
Fig. 3–4: DIGITbus I/O Timing
32
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
3.4. Recommended Quartz Crystal Characteristics
Table 3–4: 3.5V<UVDD<5.5V, external components according to Fig. 2–3, unless otherwise noted
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
fP
Parallel Resonance Fre-
quency @ CL=12pF
4
5
MHz
R1
Series Resonance Res. for
50ms Oscillation Start-Up
Time and Proper Function @
CL=12pF
@ fP=4MHZ
340
380
210
270
240
280
140
180
Ohm
START-UP
START-UP, 4.5V<UVDD<5.5V
RUN
RUN, 4.5V<UVDD<5.5V
START-UP
START-UP, 4.5V<UVDD<5.5V
@ fP=5MHz
RUN
RUN, 4.5V<UVDD<5.5V
CEXT
External Oscillation Capaci-
tances, connected to VSS
18
pF
Micronas
Nov. 28, 2002; 6251-546-1PD
33
CDC 32xxG-B
PRELIMINARY DATA SHEET
34
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
4. CPU and Clock System
4.1. ARM7TDMI CPU
The CPU is an ARM7TDMI 32-bit RISC processor. This is a
member of the Advanced RISC Machines (ARM) family. The
ARM7TDMI is a 3 stage pipeline machine and supports a 4
Gbit address range. Besides the 32bit standard ARM instruc-
tion set the ARM7TDMI supports the 16bit Thumb instruction
set which allows a higher code density. It includes a 64bit
result multiplier and a JTAG interface with an embedded
debug module.
4.1.1. CPU States
The ARM7TDMI CPU allows operation in two states:
– ARM state: 32bit instructions
– Thumb state: 16bit instructions
After reset and exceptions, ARM state is active.
4.2. CPU Modes
The CPU can be operated in four different clock modes
(Table 4–2). Core modules that are also affected by CPU
speed modes are:
Activating the PLL modes is done in FAST mode by the fol-
lowing routine:
1. For initialization, choose a pair of settings for the clock
multiplication factor and the clock prescaler from Tables 4–5
or 4–6 and write them to PLLC.PMF and IOC.IOP.
1. Interrupt Controller with all internal and external interrupts
2. RAM, ROM/Flash and DMA
2. When coming from SLOW or DEEP SLOW mode, allow
tREFINT to elapse for VREFINT and BVDD to set up. In all
other cases, wait the time of tBVDD_su for BVDD to set up.
3. Watchdog
Table 4–1 shows the operability of the peripheral modules in
the various clock modes.
3. Wait for at least tSUPLL before checking PLLC.LCK to be
set, to make sure that the PLL has locked.
4.2.1. FAST Mode
4. Disable ICU and DMA, if active.
5. Enable PLL mode by writing 0x03, or PLL2 mode by writ-
ing 0x07 to SR1.CPUM (32-bit access only).
After reset the CPU is in FAST mode. The CPU clock and the
I/O clock both equal the oscillator frequency fXTAL
.
6. As the System Frequency Divider and the Prescaler need
some time to synchronize, the PLL mode is not active until
PLLC.PLLM reads as 1.
Internal clock frequencies higher than fXTAL are not available
in this mode. Modules requiring f0 = 2fXTAL for operation will
not work properly, as f0 is set to f1 = fXTAL
.
7. At this point the ERM may be activated (see Section 4.4.3.
on page 40) and ICU and DMA may be (re-)enabled.
Returning CPU from any other mode to FAST mode is done
by selecting the appropriate mode in the standby registers
field SR1.CPUM (Table 4–2).
Returning to FAST mode is done by the following routine:
1. Deactivate the ERM, if active (see Section 4.4.4. on
page 40).
4.2.2. PLL Modes
2. Disable ICU and DMA, if active.
To increase CPU performance, a PLL allows to multiply
fXTAL. The CPU will operate at this higher frequency fSYS and
its speed is automatically reduced only for accesses to
slower modules (ROM/Flash, I/O).
3. Return to FAST mode by setting SR1.CPUM to 0x01 (32-
bit access only).
4. Wait for PLLC.PLLM to read as 0.
Table 4–5 gives recommended settings for control registers
and the various resulting operating frequencies for the PLL
5. Now the ICU and DMA may be (re-)enabled and the pro-
gram may resume.
mode. These recommended settings achieve f0 = 2*fXTAL
,
f1 = fXTAL and so forth, for unlimited operation of peripheral
modules.
Attention: The PLL modes must be entered and left only via
FAST mode. The registers PLLC.PMF and IOC.IOP may
only be changed in FAST mode.
A PLL2 mode allows bypassing of the first stage of the
divider chain. It allows a clock system with fSYS = n*fXTAL and
f0 = f1 = fXTAL for special applications, where the unlimited
operation of peripheral circuits has to be sacrificed (see
Table 4–6 for settings).
To reduce the power consumption in other modes than PLL
modes, the registers PLLC.PMF and IOC.IOP should be pro-
grammed to zero.
In both PLL modes, the EMI Reduction Module (ERM) can
be operated, which reduces electromagnetic energy emis-
sion (see Section 4.4. on page 40).
4.2.3. SLOW Mode
To considerably reduce power consumption, the user can
reduce the internal CPU clock frequency to 1/128 of the nor-
Micronas
Nov. 28, 2002; 6251-546-1PD
35
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 4–1: CPU-Active Modes and their effect on peripheral modules
Module
PLL
PLL2
FAST
SLOW
DEEP SLOW
Core
Digital Watchdog
IRQ Interrupt Controller Unit
FIQ Interrupt Logic
Port Interrupts
Analog
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
A/D Converter
✔
✔
✔1)
✔ 1)
✔ 1)
ALARM, P06 and WAIT Compara-
tors
✔
✔
✔
✔
LCD Module
Communication
DMA
✔
✔1)
✔ 1)
✔ 1)
✔ 3)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
DMA Timer, GBus
UART
✔1)
✔1)
✔1)
✔1)
✔1)
✔
✔ 1)
✔ 1)
✔ 1)
✔ 1)
✔ 1)
✔
✔ 1)
✔ 1)
✔ 1)
✔ 1) 4)
✔ 1) 4)
✔
✔ 3)
SPI
CAN
DIGITbus
✔ 3) 4)
I2C
Input & Output
Ports
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Stepper Motor Module
PWM
✔1)
✔1)
✔1)
✔1)
✔1)
✔ 1)
✔ 1)
✔ 1)
✔ 1)
✔ 1)
✔ 1)
✔ 1)
PFM
✔ 3)
✔ 3)
Audio Module
Clock Outputs
Timers & Counters
Capture Compare Module
Timers
✔ 1)
✔
✔
✔1)
✔1)
✔ 1)
✔ 1)
✔ 2)
✔ 1)
✔ 3) 4)
✔ 3)
Miscellaneous
JTAG
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Embedded Trace Module
1) Possibly affected by f0 equaling f1
2) Avoid write access to CCxI
3) Only clocks f5 and slower are available from Clock Divider
4) Don’t access registers or CAN RAM
36
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Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
mal fXTAL value. In this CPU SLOW mode, program execu-
tion is reduced to 1/128 of fXTAL
.
Some modules must not be operated during CPU SLOW
mode (e.g. CAN). Refer to module sections for details (see
Table 4–1 on page 36).
Internal clock frequencies higher than fXTAL are not available
in this mode. Modules requiring f0 = 2*fXTAL for operation will
not work properly, as f0 is set to f1 = fXTAL
.
For switching between SLOW and FAST modes, use the fol-
lowing routine:
1. Select the desired mode in the standby registers field
CPUM (Table 4–2). The new fBUS is effective after 2 fXTAL
cycles at most.
2. Now the program may resume.
4.2.4. DEEP SLOW Mode
To further reduce power consumption beyond SLOW mode,
DEEP SLOW mode also disables most of the internal periph-
eral clocking system. Table 4–1 shows which peripheral
modules can be operated in DEEP SLOW mode.
Only peripheral module clocks f5 and slower are available
from the divider chain. T0 can be operated only with this limi-
tation.
For switching between DEEP SLOW and FAST modes, use
the routine given for SLOW mode.
Micronas
Nov. 28, 2002; 6251-546-1PD
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CDC 32xxG-B
PRELIMINARY DATA SHEET
4.3. Clock System
The IC contains a quartz oscillator circuit that only requires
external connection of a quartz and of 2 oscillation capaci-
tors. Its start-up and run properties are controllable by SW.
See section “Core Logic” for details.
f
=
XTAL
4/5MHz
The oscillator clock fXTAL drives a clock system that supplies
the various modules with its specific clock.
PLL
x n
PLLC.LCK
pll_lock
PLLC.PMF
A frequency multiplying PLL allows to select the system
clock fSYS to be higher than fXTAL for high speed CPU and
module operation.
ERMC.EOM
ERM
ERMC.INPH
n f
XTAL
SR1.CPUM=3, 7
A divider chain divides fIO down to supply peripheral module
clocks f0 to f17. Module clock selection is software defined in
some cases, hardware or HW option defined in other cases.
The module descriptions give details.
f
SYS
CPU
SR1.CPUM=0, 2
1/128
ICU
DMA
Mem. Ctrl.
The standby register field SR1.CPUM selects the CPU mode
(Table 4–2).
nWAIT
Table 4–2: Clock Selection
≥1
waitq
f
&
BUS
SR1.CPUM CPU
Mode
fBUS
fIO
f0
f1
ROM
Flash
RAM
1/m
IOC.IOP
n/m f
0
0
0
SLO
W
fXTAL
128
/
/
fXTAL
128
/
/
fXTAL
fXTAL
XTAL
SR1.CPUM=3, 7
stpclk
SR1.CPUM=0, 2
0
0
0
1
1
0
FAST fXTAL
DEEP fXTAL
SLO
W
fXTAL
fXTAL
fXTAL
f
IO
I/O Bus
fXTAL
128
f0 to f4 = 0
f
SUP
&
128
f
0perm
0
1
1
PLL
n
fXTAL
n/m
fXTAL
n/m
fXTAL
n/2m
fXTAL
1/2
VDD
SR1.CPUM=2
f
f
0
1
1
1
0
1
x
0
Don’t
use
SR1.CPUM=3
1
1
1
PLL2
n
fXTAL
n/m
fXTAL
n/m
fXTAL
n/m
fXTAL
f
f
f
2
3
4
f
17
Fig. 4–1: Clock System
38
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
4.3.1. PLL
CO0SEL.CO00,
CO0SEL.CO01
HW Option
The PLL is composed of a Phase Comparator, a Voltage
Controlled Oscillator VCO, a Frequency Divider and an inter-
nal bypass. The Phase Comparator compares the input fre-
quency fXTAL with the output frequency of the Frequency
Divider, fREF. It outputs the voltage VP, which is proportional
to the phase difference of the two input frequencies. VP con-
trols the VCO which outputs the desired frequency. This fre-
quency is fed back by the Frequency Divider to the Phase
Comparator. The Frequency Divider divides the input fre-
2
HW Option
CO0
CO0
CO0
Mux0
Mux1
Mux2
1
CO0Q
CO0
1/1
1/1.5
1/2.5
4:1
Mux
f
XTAL
CO0
Interrupt
Source
quency down to fREF which ideally is the same as fXTAL
.
HW Option
Clock Out
1/1
1/1.5
1/2.5
The phase-locked state of the PLL is signaled by a lock sig-
nal. It is available as flag PLLC.LCK. It may be routed to the
LCK special output by selection in field ANAU.LS (UVDD
Analog Section).
CO1
CO1
Interrupt
Source
The block multiplies fXTAL by n = PMF+1 to achieve fSYS. PLL
Control register PLLC allows to set the desired value.
Fig. 4–3: Clock Outputs Diagram
Signal CO0 is the output of a prescaler and a 4 to 1 multi-
plexer. Prescaler and input for the multiplexer are selectable
by HW options (see Table 4–3). The output selection of the
multiplexer is done by register CO0SEL, bits CO01 and
CO00. The outputs of the pre scalers are fed not only to the
ports, but may also serve as interrupt source. The U-Ports
assigned to function as clock outputs (see Table 4–3) have to
be configured Special Out.
f
PMF = 0
XTAL
V
n f
Phase
Comp.
P
XTAL
VCO
f
REF
1/(PMF+1)
The interrupt source output of this module is routed to the
Interrupt Controller logic. But this does not necessarily select
it as input to the Interrupt Controller. Check section “Interrupt
Controller” for the actually selectable sources and how to
select them.
VP ~ f(Φ
- Φ
)
REF
XTAL
PMF = 1..15
Fig. 4–2: PLL Block Diagram
CO0 and CO1 are not affected by CPU SLOW mode.
4.3.2. I/O Clock Prescaler
This prescaler derives the clock for the peripheral modules
(the I/O clock fIO) from the system clock fSYS. It divides fSYS
by an integer number m. I/O Clock Control register IOC
allows to set the desired value. m is recommended to be set
equal to n/2.
Table 4–3: HW Options and Ports
Signal
HW Options
Item
Initialization
Address
Item
Setting
CO0
CO0
Prescaler
CO00C
CO0
output
U1.6, U3.3
or U7.7
special out
4.3.3. Divider Chain and Clock Outputs CO0 and
CO1
CO0Mux0
CO0Mux1
CO0Mux2
The peripheral module divider chain receives fSYS/m and
supplies the various modules with their specific clocks. Each
stage of the divider chain divides its input clock by two. Thus
only powers of two of the divider chain input clock are obtain-
able for the peripheral modules.
CO0Q U1.5 spe-
CO01C
CO02C
CO1C
output
cial out 1)
CO1
CO1
Prescaler
CO1
output
U0.4, U1.5
or U7.6
special
out1)
Table 4–2 shows the effect of CPU mode selection on the
divider output frequencies f0 through f17. Note that in modes
FAST, PLL and SLOW, with n = 2m (which is recommended),
f1 always equals fXTAL. Thus f1 and all further subdivided
clocks are unaffected by switching between these modes.
Clock Out
1) HW Options register flag PM.U15 switches between
CO0Q and CO1 at U1.5 special out.
Section “HW Options” gives details about HW option con-
trolled clocks, their selection and their activation.
Note that specifying 1/1.5 and 1/2.5 prescaled clocks result
in clock signals with 33% resp. 20% duty factor.
Two Clock Output signals CO0 and CO1 provide external vis-
ibility of internal clocks (Figure 4–3). Clocks are selected by
register CO0SEL.
Micronas
Nov. 28, 2002; 6251-546-1PD
39
CDC 32xxG-B
PRELIMINARY DATA SHEET
4.4. EMI Reduction Module (ERM)
The IC contains an EMI Reduction Module (ERM), which is
capable of reducing electromagnetic radiation that might
cause interference to other electronic equipment. The con-
cept of this circuit uses precisely defined time offsets of the
master clock phases as generated by the PLL. Thus, the
module is only available in PLL modes.
4.4.2. Rules for Setting Parameters
Each fSYS multiplier n and each mode requires its own set of
parameters. For individual settings other than those given in
Table 4–5 the rules are given below.
For mode 1 the limits are:
All internal clock signals except fXTAL are affected. Thus also
the sampling time points of clocked inputs and outputs of all
internal modules are modulated. To avoid a possible perfor-
mance degradation of, e.g., communication modules in a
user environment, the maximum possible delay of the sam-
pling clock phase can be controlled with the parameters
given in table 4–5. In critical applications, I/O sampling time
point modulation and EMI reduction can thus be compro-
mised. Section 4.7.gives application hints.
– The suppression strength has no effect and should be
kept at 0.
– The clock tolerance must not exceed the values given in
the columns for strong settings.
For modes 2 and 3 the limits are:
– Numbers must not exceed the values given in the col-
umns for strong settings.
– The clock tolerance must be equal to or less than (sup-
pression strength +1)/2.
Features
– Strong suppression of electromagnetic radiation
– In mode 2 the suppression strength must not exceed 43.
– Precisely controlled effect on sampling time points of
clocked I/O (ADC, CAN, UART, SPI etc.)
– In mode 3 the sum of clock tolerance and suppression
strength must not exceed 43.
– All parameters fully controllable and reproducible
– Three operation modes for different purposes
– Works for clock frequencies of up to 48 MHz
– No degradation of CPU performance
4.4.3. Initialization
For operation of the ERM, the clock system has to be in one
of the PLL modes. After Reset, the ERM is in mode 0. All
internal registers are reset to their default values.
4.4.1. Modes
The initialization must be done in the following order:
1. Set the clock tolerance (ERMC.TOL) to 1.
The ERM has 4 modes of operation:
– Mode 0, ERM off.
2. Set the suppression strength (ERMC.SUP) to 1 (modes 2
and 3 only).
– Mode 1 is intended for the low fSYS frequencies of 8 MHz
or 10 MHz with a clock multiplier of n = 2 (PLLC.PMF = 1).
Mode 1 with a clock tolerance of 7 has a similar harmon-
ics suppression as the formerly used EMI Reduction Mod-
ule V3.1.
3. Select the desired mode (1...3) in ERMC.EOM according
to Table 4–5.
4. Select the desired suppression strength (ERMC.SUP).
5. Select the desired clock tolerance (ERMC.TOL).
– Mode 2. This mode is primarily intended for the deactiva-
tion process of mode 3 but may also be used for opera-
tion. It performs best at high clock frequencies.
4.4.4. Deactivation
– Mode 3 gives best results at medium and high fSYS fre-
quencies. At medium frequencies it is even capable of a
certain suppression of the fundamental.
To deactivate the ERM, the following sequence must be
observed:
1. If in mode 3, enter mode 2 by writing 2 to field
ERMC.EOM.
In each of the three operation modes the parameters may be
particularly chosen with the help of registers ERMC.SUP and
ERMC.TOL, to achieve an optimum suppression while keep-
ing phase modulation of fIO as low as possible. In Table 4–5,
three sets of parameters with maximum fIO sampling delays
of:
2. Set the clock tolerance parameter (ERMC.TOL) to 1
(steps 1. and 2. must not be done in one operation).
3. Set the suppression strength (ERMC.SUP) to 1 (modes 2
and 3 only).
– 7.5 ns (weak),
4. Wait at least 8 fSYS cycles (e.g. CPU NOPs) before check-
ing the In-Phase flag ERMC.INPH.
– 12.5 ns (normal) and
– 20 ns (strong)
5. Wait for flag ERMC.INPH to be set (may take up to 80 fSYS
cycles), then clear the field ERMC.EOM to return to mode 0
This will turn off the ERM.
are given as examples. However, other individual settings
are possible (see section 4.4.2.).
At fSYS frequencies of 40 MHz and above only a limited EMI
suppression is possible. At an fSYS of 50 MHz the ERM must
be switched off (mode 0).
40
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PRELIMINARY DATA SHEET
CDC 32xxG-B
4.5. Memory Controller
The Memory Controller connects the CPU to the complex
memory system. It controls the various types of access and
wait states.
for access to asynchronous memory are programmed. The
access to the synchronous memory (I/O) works right after
reset, independent from any setting by software. Endian
mode is set by the Control Word via bit CR.ENDIAN.
First, initialize the wait state register WSR (cf. Table 4–5).
Then the PLL or PLL2 mode may be enabled, if desired.
Don’t change the wait state register while in PLL mode, this
may lead to a memory access with undetermined wait state
count in the following cycle.
Features
– support of one synchronous- and up to three different
asynchronous memory areas
– different wait state values for sequential and nonsequen-
tial accesses to asynchronous memory
4.5.1.3. Operation
– allows 8, 16 and 32bit memory accesses from CPU
– supports access to 8, 16 and 32bit wide memory
– allows big or little endianness.
With proper SW initialization, the Memory Controller is also
ready to access the asynchronous memory systems (ROM/
Flash, RAM, Boot ROM).
The MMU decides from the address and the CR setting,
which area in memory space contains a 8, 16 or 32bit mem-
ory system. It preselects the different types of memory
(ROM/Flash, RAM, Boot ROM and I/O-Pages) and computes
the address for ROM/Flash minus 200000hex, if ROM/Flash
should be mapped to base address 200000hex.
SWS
NWS
WSR
Mux
In presence of a Patch Module, the PATCHACC signal from
the Patch Module signals to the MMU that the next access
will be an access to the Patch Module instead to normal
ROM/Flash, RAM or Boot ROM.
WS Counter
The DMAACC signal from the DMA Module signals, that the
next address value will be driven by DMA and not by CPU.
Due to the fact that DMA always reads a location in ROM/
Flash, RAM or Boot ROM and writes to a location in the I/O
area within the same bus cycle, the MMU also preselects the
I/O area and the Memory Controller times the whole DMA
cycle to the restrictions of the slow synchronous I/O area.
f
SYS
predecrom
predecram
predecboot
predecio
waitq
f
IO
Addr
CR.MAP
Memory
Controller
SR1.CPUM=3, 7
PATCHACC
ICUACC
4.5.1.4. Inactivation
DMAACC
Returning the Memory Controller to CPU FAST mode
(SR1.CPUM=1) will immediately switch the CPU to FAST
mode and change any further access to asynchronous mem-
ory to non-wait-state operation.
CR.ENDIAN
CR.PSA
I/O
Bridge
Bridge
Bridge
CPU Bus
ROM
Boot
Emu
Flash
Fig. 4–4: Memory Controller Block Diagram
4.5.1. Principle of Operation
4.5.1.1. General
The Memory Controller contains a Memory Mapping Unit
(MMU) to control the mapping of the whole memory system,
a Wait State Register (WSR) to initialize the various wait
states, a Final State Machine and a Wait State Counter to
control the various types of access and wait states.
4.5.1.2. Initialization
After reset, the CPU runs in CPU FAST mode, the Wait State
Counter is disabled due to SR1.CPUM=1 and no wait states
Micronas
Nov. 28, 2002; 6251-546-1PD
41
CDC 32xxG-B
PRELIMINARY DATA SHEET
4.6. Registers
PLLC
PLL Control
IOC
I/O Control
7
6
LCK
x
5
PLLM
x
4
x
x
3
0
2
0
1
0
0
0
7
x
x
6
x
x
5
x
x
4
x
x
3
x
x
2
0
1
IOP
0
0
0
r/w
ACT
PMF
w
x
Res
Res
ACT
r1:
r0:
PLL Active
PLL started (PMF > 0)
PLL not activated (PMF = 0)
IOP
w
I/O Clock Prescaler (Table 4–5)
IOP is a write only field.
fSYS
f0 = ---------- = ------------------ = -------------------- fXTAL
IOP + 1
fSYS
PMF + 1
LCK
r1:
PLL Locked
PLL locked
m
IOP + 1
r0:
PLL not locked
Above formula relates to PLL mode.
PLLM
r1:
r0:
PLL Mode Acknowledge
The clock chain has switched to PLL mode
Not PLL mode
WSR
Wait State Register
7
6
5
4
3
2
1
0
PMF
w0:
PLL Multiplication Factor (Table 4–5)
PLL is switched off and internally bypassed.
This is the standby mode for the PLL.
Starts PLL with the corresponding frequency.
If not active anyway, the VREFINT Generator
and BVDD Regulator are enabled
w
NWS
SWS
w15-1:
0x00
Res
NWS
Nonsequential Wait State Bits
w:
Number of wait states at nonsequential
memory access.
PMF is a write only field. Don’t modify PMF
in PLL mode.
SWS
w:
Sequential Wait State Bits
Number of wait states at sequential access.
fSYS= n fXTAL= (PMF + 1) fXTAL
The WSR influences access to ROM, Flash and Boot ROM.
Above formula relates to PLL mode.
CO0SEL
Clock Out 0 Selection
ERMC
ERM Control
7
6
x
x
5
x
x
4
x
x
3
x
x
2
x
x
1
CO01
0
0
CO00
0
7
6
x
5
4
3
2
1
0
w
x
r/w
r/w
r/w
TSEL
3
x
Res
x
x
x
x
x
x
x
x
x
2
EOM
TOL
1
CO00, CO01 Clock Out Bit 0 and 1
w: Clock selection
r/w INPH
x
SUP
0
Table 4–4: CO00 and CO01 Usage
0x00000000
Res
CO01 CO00 Selection
TSEL
r/w
Test Select
Factory use only.
0
0
1
1
0
1
0
1
CO0Mux0
CO0Mux1
CO0Mux2
fXTAL
EOM
r/w3:
r/w2:
r/w1:
r/w0:
ERM Operation Mode
Mode 3
Mode 2
Mode 1
Off
TOL
Clock Tolerance
r/w15-0:
(see Table 4–5 and 4–6)
INPH
r1:
r0:
In Phase (during deactivation)
Phase is 0 or 1
Phase > 1
SUP
r/w63-0
Suppression Strength
(see Table 4–5 and 4–6)
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PRELIMINARY DATA SHEET
CDC 32xxG-B
It is required not to operate I/O faster than Flash.
4.6.1. Recommended Settings
Suppression Strength (SUP) and Clock Tolerance (TOL) may
be varied between zero and the values for strong settings
according to the rules in Section 4.4.2. The given limits must
not be exceeded
Tables 4–5 and 4–6 list settings available for the EMU
device. When emulating a specific target device (MCM or
mask ROM), use the Recommended Settings of that
device only. Settings differing from these two lists shall not
be used and may result in undefined behaviour.
Table 4–5: PLL and ERM Modes: Recommended Settings and Resulting Operating Frequencies (MHz)
fXTAL
CPU
fSYS
Program
Storage
I/O
ERMC.EOM = 1
ERMC.EOM = 2 or 3
Weak
Normal Strong
Weak
Normal Strong
PLLC.
PMF
fBUS
WSR fIO= IOC.
f0
IOP
4
8
1
3
8
16
8
0x00
0x00
0x11
0x11
0x22
0x11
0x22
0x00
0x00
0x11
0x11
0x22
8
0
0
0
0
4
8
8
0
0
0
0
0
0
0
0
7
13
14
13
13
6
0
0
0
11
13
15
4
8
8
2
4
4
6
6
6
6
3
7
14
14
4
6
7
11
22
6
6
16
1
22 11
24
32
5
7
12
8
2
3
0
0
0
0
0
12
12
6
0
13 12
13 12
21 11 31 12
21 11 31 12
0
16
10.7
10
20
10
15
10
0
6
6
16
16
5
28
28
8
6
6
4
37
37
14
6
6
7
6
6
0
0
5
10
20
1
3
10
0
1
5
8
14
set ERMC.EOM=0
set ERMC.EOM=0
0
0
0
10
8
0
0
0
15
8
0
0
0
15 10
5
8
8
17
26
26
9
8
8
28 12
30
5
2
8
8
15
15
35
35
8
8
8
8
Table 4–6: PLL2 and ERM Modes: Settings Sacrificing Unlimited Operation of Peripheral Modules and Resulting Operating
Frequencies (MHz)
fXTAL
CPU
Flash
fBUS
I/O
ERMC.EOM = 1
ERMC.EOM = 2 or 3
Weak
Normal Strong
Weak
Normal Strong
fSYS
PLLC.
PMF
WSR fIO= IOC.
f0
IOP
4
5
12
2
6
0x11
0x00
0x11
0x11
4
2
0
0
6
5
0
0
0
0
10
5
0
0
0
0
15
5
6
6
3
2
5
4
10
10
17
13
5
2
8
7
16
16
28
8
2
8
12
10
7.5
20
15
4
2
4
2
0
0
10
7
15
13
15 10
15
5
7
21 11
Micronas
Nov. 28, 2002; 6251-546-1PD
43
CDC 32xxG-B
PRELIMINARY DATA SHEET
4.7. PLL/ERM Application Notes
4.7.3.1. UART
4.7.1. PLL Jitter
Let’s consider the tolerable frequency offset in the case of
the UART.
The embedded PLL synchronizes every n-th fSYS cycle to
the externally applied fXTAL signal. This synchronization
smoothly tries to cancel out influences from power supply
noise and fXTAL fluctuations. Depending on the application,
this permanent re-synchronization process is expected to
introduce some nanoseconds of phase jitter to fIO.
The Baud Rate frequency is always the sample clock fre-
quency, divided by 8. The max. telegram length is 12 bit. A
transmitter frequency offset is tolerable as long as 12*8 ± 3
receiver sample clocks equal 12*8 transmitter sample clocks,
which gives a transmitter frequency of fTrans=fRec(12*8/
(12*8±3))=fRec±3.23% and TOL=±1.61%.
It is important to note that PLL jitter does not introduce a
noticeable frequency error, because the phase stays locked
to the fXTAL reference and fluctuates, even over long times,
only within the same tight limits. Even with a PLL induced fIO
jitter of ±10ns, the maximum observable frequency error
between two fIO clocks
PLL and ERM jitter claim a certain portion of this tolerable
offset. Let’s assume that both influences add up to ±20ns of
fIO jitter, and that fIO=f0=8MHz.
– spaced 1us apart is (1us±2 10ns)/1us=±2%,
– spaced 1ms apart is (1ms±2 10ns)/1ms=±20ppm,
– spaced 1s apart is (1s±2 10ns)/1s=±0.02ppm,
and so forth.
With the Baud rate set to 1MBaud, fSAMPLE equals 8MHz.
With this setting, PLL and ERM jitter consume
2*20ns/375ns=10.7%
of the tolerable transmitter frequency offset and reduce TOL
to 1.44%.
4.7.2. ERM “Jitter”
With the Baud Rate set to 19.23kBaud, fSAMPLE equals
153.84kHz. With this setting, PLL and ERM jitter consume
2*20ns/19.5us=0.2%
of the tolerable transmitter frequency offset and reduce TOL
only slightly to 1.605%.
The effect of the ERM on fIO phase and frequency is similar
to that of PLL jitter in that it adds limited phase modulation.
However, this ERM induced jitter is especially tailored to
improve the electromagnetic emission properties of the
device. Section 4.4.1. gives details on setting the maximum
phase delay:
4.7.3.2. CAN
– 7.5ns (weak) translates to ±3.75ns of fIO jitter,
– 12.5ns (normal) translates to ±6.25ns of fIO jitter,
– 20ns (strong) translates to ±10ns of fIO jitter.
The CAN Module contains logic that re-synchronizes a
receiver to a transmitter several times during a telegram. By
these means, a receiver is able to adapt to the transmitter
frequency within narrow limits.
From these figures it is evident, that ERM introduces a jitter
that, in its extent, is comparable to PLL jitter. Both influences
may be added to estimate the combined PLL/ERM effect on
I/O module operation.
Two situations have to be distinguished:
1. Bit stuffing guarantees a maximum of 10 bit periods
between two consecutive re-synchronization edges. There-
fore the accumulated phase error must be less than the pro-
grammed re-synchronization jump width (SJW). The limita-
tion that this situation imposes on the maximum TOL can be
expressed as:
4.7.3. Influence of PLL/ERM on Module Operation
DIGITbus, SPI and I2C synchronize external devices to one
master clock. Their operation is hardly impeded by PLL/ERM
jitter.
tSJW
-------------------
2 × TOL ≤
10 × tBit
Modules like UART and CAN communicate with external
fixed-frequency devices, and there is a maximum frequency
offset between transmitting and receiving station, that can be
tolerated without transmission error.
or
tSJW
----------------------------
TOL ≤
Viewed from the receiving station, a frequency offset of the
transmitting station is tolerable, as long as over the length of
a complete telegram, every bit can still be detected unambig-
uously. Once the tolerable frequency offset is exceeded,
communication is fatally disturbed. This tolerable offset is
dependent on the capability of the involved circuitry to detect
and compensate for frequency offset.
2 × 10 × tBit
2. Another limit on the maximum TOL is set by the situation
where the CAN logic must be able to correctly sample the
first bit after an error frame. This is the 13th bit after the last
re-synchronization. This limitation can be expressed as:
min(tPhase Seg1, tPhase Seg2
2 × TOL ≤ ---------------------------------------------------------------
13 × tBit – tPhase Seg2
)
In the further discussion, the clock tolerance TOL is defined
as percentage offset of the actual from the nominal fre-
quency
or
fact – fnom
TOL = --------------------------
fnom
min(tPhase Seg1, tPhase Seg2
TOL ≤ ---------------------------------------------------------------
2 × (13 × tBit – tPhase Seg2
)
)
Note that each transmitting and receiving station are allowed
this same tolerance from nominal:
ftrans=fnom±TOL and frec=fnom±TOL
The resulting maximum offset between transmitter and
receiver thus is 2 x TOL.
44
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Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Example (f0 = 10MHz)
period. Thus, a transmitter frequency offset is tolerable up to
fTrans = fRec(1±1/8) = fRec±12.5% and TOL = ±6.25%.
With the Baud rate set to 1MBd, tBit equals 1µs and is
divided into 10 time quants (tQ = 100ns). tSJW and tTSEG2 are
programmed to 3 tQ (= tPhase Seg1 = tPhase Seg2). 3 tQ are
reserved for the propagation delay segment. In the first case
the maximum tolerance TOL is 1.5% (edge to edge):
Again following the UART example, ERM/PLL jitter influ-
ences this tolerable offset:
With the Baud rate set to 31.25kBd, 1/8 of the bit period is
4µs. PLL/ERM jitter reduces the maximum tolerance TOL of
±6.25% by 2*20ns/4µs=1% to ±6.19%.
3
TOL ≤ --------------------------- = 0,015
2 × 10 × 10
4.7.3.4. SPI and I2C
Modules like SPI and I2C synchronize with external devices
by the serial clock. Thus, no frequency offset between trans-
mitting and receiving station can develop, and no adverse
effects of PLL/ERM operation are expected.
In the second case, TOL is 1.2% (edge to sample point):
3
TOL ≤ ---------------------------------------- = 0,012
2 × (13 × 10 – 3)
The smaller value of the above (1.2%) is relevant.
Following the UART example, PLL/ERM jitter consumes up
to 2*20ns of 300ns (SJW = 3 time quants). This makes 40ns/
300ns=13.3% of this tolerance, thus reducing TOL to
±1.04%.
With the Baud rate set to 500kBd, tBit=2µs and tQ=200ns.
The maximum tolerance TOL of 1.2% reduces by 2*20ns/
600ns=6.7% to ±1.12%.
Example (f0 = 8MHz)
With the Baud rate set to 1MBd, tBit equals 1µs and is
divided into 8 time quants (tQ = 125ns). tSJW and tTSEG2 are
programmed to 2 tQ (= tPhase Seg1 = tPhase Seg2). 3 tQ are
reserved for the propagation delay segment. In the first case
the maximum tolerance TOL is 1.25% (edge to edge):
2
TOL ≤ ------------------------ = 0,0125
2 × 10 × 8
In the second case, TOL is 0.98% (edge to sample point):
2
TOL ≤ ------------------------------------- = 0,0098
2 × (13 × 8 – 2)
The smaller value of the above (0.98%) is relevant.
Following the UART example, PLL/ERM jitter consumes up
to 2*20ns of 250ns (SJW = 2 time quants). This gives 40ns/
250ns=16% of this tolerance, thus reducing TOL to ±0.82%.
With the Baud rate set to 500kBd, tBit=2µs and tQ=250ns.
The maximum tolerance TOL of 0.98% reduces by 2*20ns/
500ns=8.0% to ±0.9%.
4.7.3.3. DIGITbus
The DIGITbus master synchronizes with external devices via
the serial data line. The slave node recovers the transmis-
sion clock from the data signal via an own PLL. This PLL will
lock to the long-term average frequency of the master, and
the slave node sees PLL/ERM jitter as a short-term fre-
quency offset.
Following the UART example, one can define the tolerable
frequency offset:
Every bit starts with a rising edge and thus every bit has a re-
synchronization point. The bit period (tBit) is divided into four
equal length parts. Falling edges happen nominally after 1/4,
2/4 or 3/4 of the bit period. After 4/4 of the bit period a rising
edge indicates the beginning of the next bit. The DIGITbus
logic tolerates a jitter of these edges up to ±1/8 of the bit
Micronas
Nov. 28, 2002; 6251-546-1PD
45
CDC 32xxG-B
PRELIMINARY DATA SHEET
46
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Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
5. Memory and Boot System
RESETQ = 1
CR.MAP = 01
RESETQ = 0
address range
(16M)
CR.MAP = 00
CR.MAP = 1x
TEST2-Pin = 0
TEST2-Pin = 1
00FF.FFFF
.5M
.5M
I/O
I/O
I/O
F8.0000
F0.0000
E0.0000
Boot
Boot
Boot
rsvd
debug
2M
RAM
RAM
RAM
C0.0000
A0.0000
8M
ROM/Flash
ROM/Flash
20.0000
2M
ROM/Flash
ROM/Flash
RAM
Boot
Boot
0
Fig. 5–1: Address Map. Most Common Settings
Micronas
Nov. 28, 2002; 6251-546-1PD
47
CDC 32xxG-B
PRELIMINARY DATA SHEET
rored to physical address 0. The I/O area will grow
upward from physical address 0x0F80000 to 0x0FFFFFF
(0.5MByte). It is 16bit wide and is asynchronously
accessed with wait states.
5.1. RAM and ROM
On-chip RAM is composed of static RAM cells. It is protected
against disturbances during reset as long as the specified
operating voltages are available.
Mirrored means the memory is accessible at both locations.
Remapped means the memory is accessible at the new loca-
tion only.
The 128PQFP Multi Chip Module also contains a 512K byte
Flash EEPROM of the AMD Am29LV400BT type (top boot
configuration). This device exhibits electrical byte program
and sector erase functions. Refer to the AMD data sheet for
details.
All parts (ROM, Flash and Emu) contain at least the I/O, the
RAM and the Boot ROM.
5.1.1. Reserved Addresses
Future mask ROM derivatives may be specified to contain
less or more internal RAM and ROM than this IC:
Reserved Addresses are memory locations which define the
behavior of internal HW or external systems. In our system
the memory locations at address 0 and following have dedi-
cated functions. The function of these memory locations
depend on which kind of physical memory is mapped to
these locations. As you can see at table 5–1 ROM/Flash or
Boot ROM has to be mapped to location 0 at reset. Other-
wise Control Word can not define the HW behavior and no
ingenious instruction is available at the reset start address.
As long as RAM is mirrored to location 0 addresses 20 and
following have no influence on the internal HW.
– ROM will grow upward from 0x0200000 to 0x09FFFFF
(8MByte) and can be remapped to physical address 0
(growing upward to 0x07FFFFF). It is 16bit wide and is
asynchronously accessed with wait states.
– RAM will always grow upward from physical address
0x0C00000to 0x0DFFFFF (2MByte) and can be mirrored
to physical address 0. It is 32bit wide and is asynchro-
nously accessed without wait states.
– Boot ROM will grow upward from physical address
0x0F00000 to 0x0F7FFFF (0.5MByte) and can be mir-
Table 5–1: Reserved Addresses
Addresses
Size
[byte]
Usage if mapped/mirrored to 0
RAM
ROM/Flash
Boot ROM
030 - 5F
02C - 2F
02A - 2B
028 - 29
024 - 27
020 - 23
01C - 1F
018 - 1B
014 - 17
010 - 13
00C - 0F
008 - 0B
004 - 07
000 - 03
48
4
2
2
4
4
4
4
4
4
4
4
4
4
General purpose RAM. No
HW defined action.
HW Options
Factory ID
reserved
ROM ID
Security Vector
Control word
ARM ID
FIQ (Fast Interrupt)
IRQ (Interrupt)
Reserved
Data Abort
Prefetch Abort
SWI (Software Interrupt)
Undefined instruction
Reset
5.1.1.1. HW Options
But nevertheless this are HW Options. It is not intended to
modify them by SW in ROM parts. In this case the result is
unpredictable.
Please refer to section “Hardware Options” for information
about layout of the HW Options field and the corresponding
Registers in the I/O area. To activate the HW Options related
functions, the SW has to copy them to the corresponding
locations in the I/O area.
48
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PRELIMINARY DATA SHEET
CDC 32xxG-B
5.1.1.2. ROM ID
The following sequence of actions has to be done in order to
reprogram a Flash ROM:
The ROM ID serves as identification of the corresponding
application/boot program. It will be read by an external sys-
tem (test, debug) and doesn’t influence internal HW.
1. Clear the Security Vector (0x00000000).
2. Clear the Flash ROM (Security Vector = 0xFFFFFFFF).
3. Program all of the Flash ROM without the Security Vector.
4. Verify the Flash ROM.
The ROM ID contains a half-word sized hexadecimal value.
The range is 0x0000 to 0xFFFF.
5. If ok, write 0x55AA55AA to the Security Vector. Otherwise
go to step 2 again.
5.1.1.3. Factory ID
The Factory ID contains a factory defined code. It contains
information about the HW version, frequency, etc. It will be
read by an external system (test, debug) and doesn’t influ-
ence internal HW. The Boot system may use this information
and adopt its behavior according to the Factory ID. The lay-
out of the Factory ID is not yet defined TBD.
This proceeding guarantees that the JTAG interface will be
enabled after reset via Boot ROM, if something goes wrong
during Flash ROM programming.
A correct application program should provide a different way
and interface to enable JTAG and to modify the Security
Vector.
5.1.1.4. Security Vector
During developing and debugging the Security Vector can be
written to a non valid value to allow easy JTAG access.
The main job of the Security Vector is to enable the JTAG
interface via Boot ROM if the Flash ROM does not contain a
correct application program (see Section 5.3. on page 50).
The Boot ROM program can not enable the JTAG interface if
the Security Vector contains the value 0x55AA55AA. This is
the way the application program can disable JTAG access.
5.1.1.5. ARM ID
The ARM core can contain a System Control Coprocessor
(CP15) which contains among other things an ID Register. It
allows the identification of the implemented processor. There
is no CP15 implemented up to now, but the ARM ID field
may contain the same information.
An empty (not programmed) Flash ROM contains all ones.
Hence the Security Vector contains a non valid pattern and
the Boot ROM enables the JTAG interface.
5.1.1.6. Control Word
The Control Word defines the behavior of the HW during
reset. Refer to section “Core Logic” for information about
Control Word definition.
5.2. I/O Map
The I/O region is divided into the lower part (addresses
00F80000 to 0x00FBFFFF) which is connected to the 8 bit
wide bus and into the upper part (addresses 00FC0000 to
0x00FFFFFF) which is connected to the 32 bit wide bus.
Please refer to section “Register Cross Reference Table” for
detailed I/O register mapping.
Table 5–2: I/O Map
Address
Size Access
What
00FBFFFF
00F90800
190k 8bit,
Free
synchronous,
Access to I/O modules which are connected to the 8 bit wide
bus is restricted: If not otherwise mentioned those modules
must be accessed by byte access only. This memory area is
organized in little endian format. If the CPU operates in big
endian format, only byte access is recommended.
wait states
00F907FF
00F90000
2k
59.5k
512
Registers
Free
00F8FFFF
00F81200
Table 5–2: I/O Map
00F811FF
00F81000
CAN registers
CAN-RAM
Address
Size Access
What
00F80FFF
00F80000
4k
00FFFFFF
00FFFF00
256 32bit,
IRQ and FIQ reg-
asynchronous, isters
no wait states
00FFFEFF
00FFFE00
256
512
DMA registers
Core registers
Free
00FFFDFF
00FFFC00
00FFFBFF
00FC0000
255k
Micronas
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CDC 32xxG-B
PRELIMINARY DATA SHEET
5.3. Boot System
The job of the Boot System is to enable the JTAG interface if
necessary. Further actions as there are download, Flash
ROM programming or debugging and monitoring has to be
done via JTAG interface.
If TEST2 pin is held high during reset, the Control Word from
the Boot ROM is copied to the Control Register by HW. The
Boot ROM Control Word is configured to start program exe-
cution from the Boot ROM, mirrored to location 0. The Boot
ROM Control Word disables JTAG.
5.3.1. Principle of operation
The Boot ROM is accessible at two locations, originally at
address 0xF00000 and mirrored at address 0x0. The first
instruction of the Boot ROM (Reset Vector) loads the
address of the next instruction in the original Boot ROM
(0xF00100, above the Boot ROM HW Options) into the pro-
gram counter. This causes a jump from the mirrored Boot
ROM to the original Boot ROM. The remaining part of the
program is running in the original Boot ROM and remapping
of the memory does not influence correct operation of the
boot program.
The program reads the TEST pin in order to distinguish
between application and factory boot program. In case of the
security vector is set in the application program, the applica-
tion is started, otherwise the JTAG interface is enabled and
program stays in an endless loop. In case of factory boot
program a test program is started.
The watchdog is not triggered in the Boot ROM program.
Especially when the program is in the endless loop this may
cause problems. But this endless loop will not be reached in
ROM parts, where the watchdog may be HW enabled
(option), as long as the security vector is valid. In Flash ROM
parts the watchdog should not be HW enabled.
boot()
{
Jump to 0xF00100;
if(TEST pin low)
{
/* Custom boot */
if(security vector)
{
/* Application available */
Load Control Registers with
application Control Word;
Jump to location 0x0;
}
else
{
/* No application */
Enable JTAG;
Endless loop;
}
}
else /* TEST pin high */
{
/* Factory boot */
Run test program;
}
}
Fig. 5–2: Boot program
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PRELIMINARY DATA SHEET
6. Core Logic
CDC 32xxG-B
6.1. Control Word CW
Some system configuration items are freely selectable dur-
ing device start-up by means of a unique Control Word (CW).
Table 6–2: CW fetch in EMU parts (CPGA257)
Control Word Fetch desired from Necessary Reset
Config. of pins
6.1.1. Reset Active
TEST2
TEST
During Reset, the device fetches this CW from address loca-
tions 0x20 to 0x23 of a source that is determined by the state
of pins TEST and TEST2, see Table 6–1 for MCM and ROM
parts and Table 6–2 for EMU parts.
External via Emu port
0
0
1
0
1
x
External via Multi Function port
Internal Boot ROM
Table 6–1: CW fetch in MCM and ROM parts (QFP128)
Control Word Fetch desired from Necessary Reset
config. of pins
6.1.2. Reset Inactive
TEST2
TEST
When exiting Reset, the CW is loaded into the Control Regis-
ter (CR) and the system will start up according to the config-
uration defined therein.
Internal ROM/Flash
0
0
1
0
1
x
Normally the CW is fetched from the same memory that the
system will later start executing code from. Table 6–3 gives
fix CWs for a list of the most commonly used configurations.
External via Multi Function port
Internal Boot ROM
For special purposes, the CW source and the program
source may differ. For these purposes, a detailed description
of the CW and CR function is given in the chapter “Control
Register and Memory Interface”.
Table 6–3: Some common system configurations and the corresponding CW setting
Part
Type
Program Start desired from
Additional desired properties
Necessary CW
31:16
15:0
EMU
ext. 32-Bit sync SRAM (e.g. MT55L256L32F)
on EMU port
Trace Bus ETM mode
0xFFBA
0x835F
0x835F
16-Bit ROM/Flash emulation,
Trace Bus ETM mode
0xFFBB
16-Bit ROM/Flash emulation,
Trace Bus Analyzer mode,
Appl. JTAG released
0xFFBB
0xFFBA
0xA3DF
0x675F
ext. 32-Bit async auto-power-down Flash (2x
Am29LV400BT) on EMU port
-
ext. 16-Bit async. auto-power-down Flash
(Am29LV400BT) on EMU port
Trace Bus Analyzer mode
Don’t care
Don’t care
Don’t care
Don’t care
0x2F5F
0x4F5F
0x7F5F
0x7F5F
Trace Bus ETM mode
MCM
ROM
int. 16-Bit Flash (Am29LV400BT)
int. 16-Bit ROM
-
-
Micronas
Nov. 28, 2002; 6251-546-1PD
51
CDC 32xxG-B
PRELIMINARY DATA SHEET
6.2. Standby Registers
The Standby Registers SR0 to SR1 allow the user to switch
on/off power or clock supply of single modules. With these
flags it is possible to greatly influence power consumption
and its related electromagnetic interference.
UART0
r/w1:
r/w0:
UART 0
Module active.
Module off.
ADC
r/w1:
r/w0:
ADC Module
Module active.
Module off.
For details about enabling and disabling procedures and the
standby state refer to the specific module descriptions.
TIM1
r/w1:
r/w0:
Timer 1
Module active.
Module off.
SR0
Standby Register 0
Offs
7
6
I2C0
TIM3
x
5
4
3
2
1
0
XTAL
r/w1:
r/w0:
Quartz Oscillator Mode
Start-Up Mode active (default after Reset).
Run Mode active.
r/w
r/w
r/w
r/w
I2C1
TIM2
LCD
SM
x
x
x
x
CAN2
CCC1
TIM1
CCC0
CAN1
x
3
TIM4
UART1
x
DGB
x
2
SM
r/w1:
r/w0:
Stepper Motor
Module active.
Module off.
PSLW UART0
ADC
SPI1
XTAL
SPI0
1
x
x
x
CAN0
0
SPI1
r/w1:
r/w0:
SPI 1
Module active.
Module off.
0x00000100
Res
I2C1
r/w1:
r/w0:
I2C Module 1
Enabled
CAN0
r/w1:
r/w0:
CAN Module 0
Module active.
Module off.
Disabled
I2C0
r/w1:
r/w0:
I2C Module 0
Enabled
CCC0
r/w1:
r/w0:
Capture Compare Counter 0
Module active.
Module off.
Disabled
CAN2
r/w1:
r/w0:
CAN Module 2
Module active.
Module off.
SPI0
r/w1:
r/w0:
SPI 0
Module active.
Module off.
CAN1
r/w1:
r/w0:
CAN Module 1
Module active.
Module off.
SR1
Standby Register 1
TIM2
r/w1:
r/w0:
Timer 2
Offs
7
6
x
5
4
3
2
x
x
1
x
0
x
x
Module active.
Module off.
r/w
r/w
r/w
r/w
x
x
x
x
x
3
TIM3
r/w1:
r/w0:
Timer 3
x
x
x
x
x
2
Module active.
Module off.
x
PFM0 PWM11 PWM9 PWM7 PWM5 PWM3 PWM1
FIQ CPUM
1
TIM4
r/w1:
r/w0:
Timer 4
IRQ
x
x
x
0
Module active.
Module off.
0x00000001
Res
UART1
r/w1:
r/w0:
UART 1
Module active.
Module off.
PFM0
r/w1:
r/w0:
Pulse Frequency Modulator 0
On
Off
DGB
r/w1:
r/w0:
DIGITbus Master
Module active.
Module off.
PWM11
r/w1:
r/w0:
Pulse Width Modulator 11
On
Off
CCC1
r/w1:
r/w0:
Capture Compare Counter 1
Module active.
Module off.
PWM9
r/w1:
r/w0:
Pulse Width Modulator 9
On
Off
LCD
r/w1:
r/w0:
LCD Module
Module active.
Module off.
PWM7
r/w1:
r/w0:
Pulse Width Modulator 7
On
Off
PSLW
r/w1:
r/w0:
Port Slow Mode
Slow mode.
Fast mode.
PWM5
r/w1:
r/w0:
Pulse Width Modulator 5
On
Off
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PRELIMINARY DATA SHEET
CDC 32xxG-B
PWM3
r/w1:
r/w0:
Pulse Width Modulator 3
On
Off
PWM1
r/w1:
r/w0:
Pulse Width Modulator 1
On
Off
IRQ
r/w1:
IRQ Interrupt Controller
Enabled
r/w0:
Disabled
FIQ
r/w1:
r/w0:
FIQ Interrupt Controller
Enabled
Disabled
CPUM
CPU Mode
Clock selection for CPU and peripheral modules (Section
“CPU and Clock System”).
Micronas
Nov. 28, 2002; 6251-546-1PD
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CDC 32xxG-B
PRELIMINARY DATA SHEET
6.3. UVDD Analog Section
VBG
2.5V 10%
VBG Generator
UVDD
UVSS
UVDD
Logic
+
-
2.5V
err
VDD
VSS
VDD Regulator
VDD
Logic
+
1.2V
-
VDD Auxiliary
+
-
ext. Flash
3.3V
err
FVDD
FVDD Regulator
FVSS
+
-
RESETQ
RESET/
ALARM
Interrupt
Source
ALARM Comp.
&
ANAU.EAL
f
IO
2
ANAU.LS
LCK
-
fvdd_err
vdd_err
global reset
+
VREFR
MUX
RESET Comp.
bvdd_err
pll_lock
+
-
ANAU.FVE
ANAU.VE
Supply Supervision
POR
≥1
SR0.LCD
en
-
2
/ UV
3
DD
DD
+
-
1
/ UV
3
+
LCD Supply
VSS
XTAL1
XTAL2
run
SR0.XTAL
XTAL Oscillator
Fig. 6–1: UVDD Analog Section Block Diagram
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PRELIMINARY DATA SHEET
CDC 32xxG-B
6.3.1. VBG Generator
The low-power VBG Generator generates bias signals which
are necessary for the operation of all UVDD Analog Section
modules. Furthermore, it produces a reference voltage VBG,
that is delivered to the VDD and FVDD Regulators, the
RESET and ALARM Comparators and the UVDD Supply
Supervision.
This module is permanently enabled.
6.3.2. VDD Regulator
The VDD Regulator generates the 2.5V VDD supply voltage
for the internal core logic from the 5V UVDD. It derives its
reference from the VBG Generator.
During this time, the Supply Supervision (cf. 6.3.7.) gener-
ates a Power-On Reset.
An overload condition in the regulator (current or voltage
drop-out) generates an immediate Reset and is stored in flag
ANAU.VE. The immediate overload signal may be routed to
the LCK special output by selection in field ANAU.LS.
VDD must be buffered externally by a 220nF ceramic capac-
itor in parallel with a 10uF tantalum capacitor.
This module is permanently enabled. A certain set-up time
has to elapse after power-up of UVDD for VDD to stabilize.
6.3.3. VDD Auxiliary Regulator
The low-power VDD Auxiliary Regulator is designed to
deliver a halt mode supply voltage to the core logic, where
no clocked operation is required.
This module is permanently disabled and available only in
Test modes.
6.3.4. FVDD Regulator
The FVDD Regulator generates the 3.3V FVDD supply volt-
age for the external Flash memory device from the 5V
UVDD. It derives its reference from the VBG Generator.
During this time, the Supply Supervision (cf. 6.3.7.) gener-
ates a Power-On Reset.
An overload condition in the regulator (current or voltage
drop-out) generates an immediate Reset and is stored in flag
ANAU.FVE. The immediate overload signal may be routed to
the LCK special output by selection in field ANAU.LS.
FVDD must be buffered externally by a 470nF ceramic
capacitor in parallel with a 3.3uF tantalum capacitor.
This module is permanently enabled. A certain set-up time
has to elapse after power-up of UVDD for FVDD to stabilize.
6.3.5. ALARM Comparator
The Alarm Comparator on the pin RESETQ allows the detec-
tion of a threshold higher than the reset threshold. An alarm
interrupt can be triggered with the output of this comparator.
The interrupt source output is routed to the Interrupt Control-
ler logic. But this does not necessarily select it as input to the
Interrupt Controller. Check section “Interrupt Controller” for
the actually selectable sources and how to select them.
To obtain a result that is independent from UVDD, the level
of pin RESETQ is compared to the VBG reference voltage.
The comparator features a small built-in hysteresis. The out-
put constitutes the RESETQ/ALARM Interrupt Source and
must be enabled by setting flag ANAU.EAL. Please refer to
section 6.4.1. for functional details.
The alarm interrupt is a level triggered interrupt. The interrupt
is active as long as the voltage on pin RESETQ remains
between the two thresholds of the ALARM and the RESET
comparator.
6.3.6. RESET Comparator
As long as the Reset Comparator on the pin RESETQ
detects the low level, the overall IC is reset.
Please refer to sections 6.4.2. and 6.4.4. for functional
details.
To obtain a result that is independent from UVDD, the level
of pin RESETQ is compared to the scaled down VBG refer-
ence voltage. The comparator features a built-in hysteresis.
6.3.7. Supply Supervision
When UVDD drops below a level VREFPOR of approx. 2.8V,
or when the internal VDD or FVDD Regulators detect an
overload condition, this module generates a Power-On reset
signal POR that is routed to the Reset Logic.
Refer to section 6.4.2.1. for more details.
6.3.8. XTAL Oscillator
The XTAL Oscillator generates a 4 to 5 MHz reference signal
from an external quartz resonator, cf. section “Electrical
characteristics” for quartz data.
Micronas
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CDC 32xxG-B
PRELIMINARY DATA SHEET
A reset sets the module to START-UP mode, where, at the
expense of a higher current consumption, marginal quartzes
receive more drive to ease start-up of oscillation.
For operation at UVDD levels between 3.5V and 4.5V, con-
tinuous operation of the module in START-UP mode may be
necessary, to guarantee sufficient drive to the connected
quartz.
After start-up of the CPU program, register SR0.XTAL may
be cleared by SW to set the XTAL Oscillator to RUN mode,
where current consumption is at its standard level.
Switching between START-UP and RUN modes must not be
done in CPU modes PLL or PLL2, as this might lead to
unpredictable behaviour of the clock system.
6.3.9. UVDD Analog Registers
w1:
w2:
w3:
VDD Regulator Error.
FVDD Regulator Error.
BVDD Regulator Error.
ANAU
Analog UVDD Register
7
6
5
4
3
2
1
FVE
0
0
VE
0
FVE
r1:
r0:
w1:
w0:
FVDD Regulator Error Flag
Out of specification.
Normal operation.
Reset flag.
r/w
EAL
x
LS
x
x
0
0
0
No action.
EAL
Enable RESET/ALARM Interrupt Source
output
Enabled.
Disabled.
VE
r1:
r0:
w1:
w0:
VDD Regulator Error Flag
Out of specification.
Normal operation.
Reset flag.
r/w1:
r/w0:
No action.
LS
LCK output Select
w0:
PLL Lock Signal.
6.4. Reset Logic
As long as the Reset Comparator on the pin RESETQ
detects the low level, the overall IC is reset.
6.4.1. Alarm Function
The Alarm Comparator on the pin RESETQ allows the detec-
tion of a threshold higher than the reset threshold. An alarm
interrupt can be triggered with the output of this comparator.
The state of the flags CSW1.FHR, CSW1.CLM, CSW1.PIN,
CSW1.POR and CSW1.WDRES, read directly after a system
reset, allows to distinguish the cause of this last system reset
(Table 6–5).
The intended use of this function is made, when a system
uses a 5V regulator with an unregulated input. In this case,
the unregulated input, scaled down by a resistive divider, is
fed to the RESETQ pin. With falling regulator input voltage
this alarm interrupt is triggered first. Then the reset threshold
is reached and the IC is reset before the regulator drops out.
6.4.2.1. Supply Supervision
A UVDD level below the Supply Supervision threshold VREF-
POR, or an overload condition in the internal VDD or FVDD
Regulators will permanently pull the pin RESETQ low and
thus hold the IC in reset (see Fig. 6–2 on page 57). With HW
Option CM.WCM = 0, this reset source can be enabled/dis-
abled by flag CMA in register CSW0 (see Section 6.4.2.2.
on page 56).
The time interval between the occurrence of the alarm inter-
rupt and the reset may be used to save process data to non-
volatile memory. In addition, power saving steps like turning
off stepper motor drivers may be taken to increase the time
interval until reset.
6.4.2.2. Clock Supervision
6.4.2. Internal Reset Sources
The Clock Supervision monitors the frequency at the oscilla-
tor input XTAL1 and also the frequency fSUP that is present
at the input of the central clock divider (see Fig. 4–1). Fre-
quencies below the clock supervision threshold of approx.
200kHz will permanently pull the pin RESETQ low and thus
hold the IC in reset (see Fig. 6–2 on page 57). With HW
Option CM.WCM = 0, this reset source can be enabled/dis-
abled by flag CMA in register CSW0.
This IC contains four internal circuits that are able to gener-
ate a system reset: watchdog, supply supervision, clock
supervision and FHR flag.
All internal resets are directed to the open drain output of pin
RESETQ. Thus a “wired or” combination with external reset
sources is possible. The RESETQ pin is current limited and
therefore large external capacitances may be connected.
Frequencies exceeding the specified IC frequency are not
detected.
All internal reset sources initially set a reset request flag.
This flag activates the pull-down transistor on the RESETQ
pin. An internal reset timer starts, as soon as no internal
reset source is active any more. It counts 2048 fXTAL periods
(for alternative settings refer to HW options register CR) and
then resets the reset request flag, thus releasing the
RESETQ pin.
There are two general operation options which can be
selected in the HW Options field CM:
1. Flag WCM = 1:
Clock and Supply Supervision are permanently active. They
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PRELIMINARY DATA SHEET
CDC 32xxG-B
can not be deactivated. The Watchdog must be serviced by
SW. This mode is recommended for all stand-alone applica-
tions requiring high operational reliability.
The three Watchdog registers are programmed by writes to
the same location CSW1. First write the desired watchdog
timer value (only values between 1 and 255 are allowed):
2. Flag WCM = 0:
Clock and Supply Supervision are active after reset, but can
be enabled/disabled by the clock monitor active flag CMA of
register CSW0. The Watchdog must be serviced only after a
first write access to register CSW1. This mode is recom-
mended for test and evaluation purposes only.
Interval × f15
FAST and PLL modes: Value = ------------------------------- – 1
1
Interval × f15
SLOW modes: Value = ------------------------------- – 1
128
6.4.2.3. Watchdog
On further writes, to trigger a reload of the counter, alternat-
ingly write a retrigger value (routed to trigger register 1) (not
necessarily the former timer value) and its bit-complement
(routed to trigger register 2) to CSW1. Failure to reload will
result in a counter underflow and a Watchdog reset.
The Watchdog module serves to monitor undisturbed pro-
gram execution. A failure of the program to retrigger the
Watchdog within a preselectable time will pull the pin
RESETQ low and thus reset the IC (Fig. 6–2 and 6–3). With
HW Option CM.WCM = 0, this reset source is only enabled
after a write access to register CSW1 (see Section 6.4.2.2.
on page 56).
Never change the retrigger value. Writing a wrong value to
CSW1 immediately prohibits further reloading of the watch-
dog counter.
The Watchdog (Fig. 6–3) contains a down-counter that gen-
erates a reset when it wraps from zero to 0xFF. It is reloaded
with the content of the watchdog timer register, when, upon a
write access to location CSW1, watchdog trigger registers 1
and 2 contain bit-complemented values. An IC reset resets
the watchdog timer register to 0xFF, thus setting the Watch-
dog to the maximum reset interval.
The flag CSW1.WDRES is set as soon as the watchdog
counter wraps to 0xFF. Thus, it is true after a Watchdog
reset. Only a Supply Supervision reset or a write access to
CSW1 clears it.
-
+
global reset
RESETQ
V
REFR
Reset extension
8 or 2048
&
oscillator pulses
reset in
Watchdog
WDRES
S Q
R
HW option
CM.WCM
>1
CSW0.CMA
0
1
V
DD
f
power on
XTAL
&
clock
supervision
f
SUP
CLS
≥
1
POR
≥
1
res CSW1
&
wr CSW1
wr1 CSW0.FHR
CSW1.FHR
S Q
R
S Q
R
CSW1.CLM
CSW1.POR
CSW1.PIN
S Q
R
S Q
R
Fig. 6–2: Reset Logic Block Diagram
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57
CDC 32xxG-B
PRELIMINARY DATA SHEET
CSW1
2.write
CSW1
Trigger Reg2
CSW1
3.write
& odd
& even
1. write
Trigger Reg1
Timer Register
8
8
8
pll,fast: f
clk
15
slow: f /128
1. write
15
load
=
≥1
&
8-Bit-Counter
zero
&
D
C
S
Q
2.write & even
3.write & odd
≥1
reset in
HW Option
1. write
S Q
R
&
WDRES
power on
VDD
S
R
Q
CSW1.WDRES
res CSW1
Fig. 6–3: Watchdog Block Diagram
6.4.3. Forced Hardware Reset
6.4.5. Summary of Module Reset States
Setting flag CSW0.FHR immediately forces the RESETQ pin
low. This allows the SW to restart the whole system by HW
reset.
After reset the IC modules are set to the reset state (Fig. 6–
4)
Table 6–4: Status after Reset
6.4.4. External Reset Sources
Module
Status
As long as the Reset Comparator on the pin RESETQ
detects the low level, the overall IC is reset. On this pin,
external reset sources may be wire-ored with the IC internal
reset sources, leading to a system wide reset signal combin-
ing all system reset sources.
CPU
CPU Fast mode (fOSC).
Interrupt
Controller
Interrupts are disabled. Priority regis-
ters, request flip flops and stack are
cleared.
U-Ports
Normal mode. Output is tristate.
Normal mode. Output is low.
High current
ports
LCD module
Watchdog
Registers are reset. No display.
Depends on mask option.
EMU option: Switched off. SW activa-
tion is possible.
Stand-alone option: Permanently
active.
Clock monitor
Depends on mask option.
EMU option: Active. SW may toggle.
Stand-alone option: Permanently
active.
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PRELIMINARY DATA SHEET
CDC 32xxG-B
CLM
Clock Supervision Reset (Table 6–5)
6.4.6. Reset Registers
PIN
RESETQ Pin Reset (Table 6–5)
Supply Supervision Reset (Table 6–5)
Watchdog Reset (Table 6–5)
CSW0
Clock, Supply & Watchdog Register 0
POR
7
6
x
x
5
x
x
4
x
x
3
x
x
2
x
x
1
x
x
0
CMA
1
WDRES
w
FHR
Table 6–5: Source of last Hardware Reset
0
Res
Source
This register controls the Supply and Clock Supervision
modules and allows to force a system reset.
FHR
w1:
w0:
Forced Hardware Reset
Reset forced
no action
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
0
0
0
1
0
0
1
0
0
0
external from RESETQ pin
internal Watchdog Reset
CMA
w1:
w0:
Clock and Supply Monitor Active
Both Enabled.
Both Disabled.
internal Clock Supervision Reset
internal Supply Supervision Reset
internal Forced Hardware Reset
Can be written to zero only after power on reset or clock
supervision reset and before first write access to register
CSW1 if allowed by HW option.
The registers sum up the source of all HW resets that
ocurred since the last write to register CSW1. Any write
access to CSW1 resets all flags to 0.
CSW1
Clock, Supply & Watchdog Register 1
7
6
x
-
5
x
-
4
FHR
0
3
CLM
0
2
PIN
0
1
0
r
TST
POR WDRES
CSW1
Clock, Supply & Watchdog Register 1
-
0
0
Res
7
6
1
5
4
3
2
1
0
w
Watchdog Time and Trigger Value
The Reset state in the register frame above describes the
state after a write to register CSW1.
1
1
1
1
1
1
1
Res
TST
r1:
r0:
TEST Pin State
TEST is 1.
TEST is 0.
This register controls the Watchdog module. Only values
between 1 and 255 are allowed.
FHR
Force Hardware Reset (Table 6–5)
6.5. Test Registers
Test registers are for manufacturing test only. They must not
be written by the user with values other than their reset val-
ues (00h). They are valid independent of the TEST input
state.
TST2
Test Register 2
7
6
0
5
4
3
2
0
1
0
0
0
In all applications where a hardware reset may not occur
over long times, it is good practice to force a software reset
on these registers within appropriate intervals.
w
For testing purposes only
0
0
0
0
Res
TST1
Test Register 1
TST3
Test Register 3
7
6
0
5
4
3
2
0
1
0
0
0
7
6
0
5
4
3
2
0
1
0
0
0
w
For testing purposes only
w
For testing purposes only
0
0
0
0
Res
0
0
0
0
Res
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TST4
Test Register 4
7
6
0
5
4
3
2
0
1
0
0
0
w
For testing purposes only
0
0
0
0
Res
Res
Res
Res
TST5
Test Register 5
7
6
0
5
4
3
2
0
1
0
0
0
w
For testing purposes only
0
0
0
0
TSTAD2
Test Register AD2
7
6
0
5
4
3
2
0
1
0
0
0
w
For testing purposes only
0
0
0
0
TSTAD3
Test Register AD3
7
6
0
5
4
3
2
0
1
0
0
0
w
For testing purposes only
0
0
0
0
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7. JTAG Interface
This module provides JTAG style access to 5 internal scan
chains. These allow testing, debugging, EmbeddedICE and
ETM (Embedded Trace Module) programming. The scan
chains are controlled by a JTAG style Test Access Port (TAP)
controller. For further details on operating TAP controller,
EmbeddedICE and ETM, please refer to ARM7TDMI Data
Sheet (Document Number: ARM DDI 0029), Embedded
Trace Macrocell Specification (Document Number: ARM IHI
0014) and ETM7 Technical Reference Manual (Document
Number: ARM DDI 0158).
Features
– 2 Interfaces selectable
– Access to CPU periphery
– Access to EmbeddedICE
– Access to Embedded Trace Module
7.1. Functional Description
TCK
TMS
ETCK
ETMS
ETDI
JTAG TAP
TDI
0
MUX
1
Controller
TDO
ETDO
nTRST
nTRST
&
POR
TCK/U3.2
TMS/U3.1
TDI/U3.0
TDO/U3.3
TEST2
1)
&
1) Gnd @ PQFP128
CR.JTAG
Fig. 7–1: JTAG Interface Block Diagram
The TAP controls the access to the scan chains. Scan chain
0 allows access to the entire periphery of the CPU. Scan
chain 1 is a subset of the scan chain 0. Scan chain 2 allows
programming of the EmbeddedICE debug module. Scan
chain 3 is reserved for the boundary scan of the pads of the
packaged device. Scan chain 6 allows programming of the
ETM.
Two interfaces can be selected to access the TAP controller.
The selection has to be done by the control register flag
CR.JTAG and the pins TEST2 and nTRST.
7.1.1. Application JTAG Interface
The application JTAG interface is connected to the special
inputs and outputs of U-Ports. The U-Port for the signal TDO
has to be configured as special out, those for the signals
TCK, TMS and TDI as special in. The application JTAG inter-
face is available if enabled and the external circuit layout
allows it. It is enabled if the TEST2 pin is high, the nTRST pin
is low and the flag CR.JTAG is set to one. The TEST2 pin is
the nTRST input of the application JTAG interface.
Table 7–1: Scan Chains
Number
Size [Bit]
Function
0
1
2
3
6
105
33
38
-
ARM7 Macrocell
Part of scan chain 0
EmbeddedICE
reserved for Boundary scan
ETM
If TEST2 pin is high during reset, U-Port U3.3 (= JTAG TDO)
is forced to Port, Special, Output mode until programmed by
SW. Otherwise the emulation JTAG interface couldn’t be
operated without internal SW support. To avoid conflicts
between JTAG mode and SW control on this port bit, never
mix these two modes in one application. The application SW
must not initialize the involved U-Ports if flag CR.JTAG is set
to one.
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7.1.2. Emulation JTAG Interface
7.1.4. Pin TEST2
The emulation JTAG interface is connected to dedicated pins
of the emulation parts (CPGA257 package). Series parts
(PQFP128 package) do not provide this interface. It is
enabled as long as the application JTAG interface is dis-
abled.
The pin TEST2 is weakly pulled down to UVSS by the cur-
rent Ipd. Refer to section “Electrical Characteristics” for
details. Besides JTAG, the pin TEST2 controls the behavior
of the IC during reset. Refer to section “Core Logic” for fur-
ther details.
7.1.3. Boundary Scan
The boundary scan is not implemented in this IC.
7.2. External Circuit Layout
The emulation JTAG interface uses TTL level input compara-
tors. The emulation JTAG inputs ETCK, ETMS, ETDI and
nTRST need external pull-up resistors to EVDD. This has to
be done in a way, that the TAP controller sees a logic one if
the emulation JTAG interface is enabled but not driven.
TDI shall see logic one level. If it is enabled and driven, the
external application circuit shall not influence proper opera-
tion of the JTAG interface. The external host must be able to
drive the levels at the inputs TCK, TMS and TDI to CMOS
logic one and logic zero levels and it must be the only source
of these signals. The TAP controller must be able to drive the
output TDO to both CMOS levels, logic one and zero, and
must be the only source of this signal.
The application JTAG interface shares its input and output
pins with the I/O of U-Ports. The external circuit layout has to
be done carefully in order to guarantee functionality of the
JTAG interface. As long as the application JTAG interface is
enabled and not driven, the TAP controller inputs TMS and
Common JTAG tools expect to see pull-up resistors at
nTRST (TEST2), TCK,TMS and TDI.
7.3. JTAG ID
The JTAG ID is not implemented in this IC.
Bits 1 to 19 are manufacturer defined. Bits 0 and 20 to 31 are
ARM defined.
The JTAG TAP controller contains a HW coded JTAG ID
which can be read serially via the JTAG interface. The CPU
can’t access this ID.
Version
31 28
Part Number
23 20 19
c2 c1 c0 Family
Manufacturer ID
12 11
1
27 26 25 24
0
1
1
Device Number
Fig. 7–2: JTAG ID Format
Bit 31 to 28 Version
9:
A:
etc.
ARM9.
ARM10.
0:
1:
2:
ARM core revision 0.
ARM core revision 1.
etc.
Bit 19 to 12 Device Number
Bit 27
0:
1:
Manufacturer device number 0 to 255.
ARM core ID.
Non ARM core ID.
Bit 11 to 1
Manufacturer ID
Manufacturer ID is the compressed JEDEC code (0x06C).
Bit 26
0:
1:
Capability bit 2
Standard part.
‘E’ part.
Bit 0
Fixed value.
Marker
The necessity of using bits 19 to 12 as manufacturer device
number forces us to use the Non ARM core ID format of the
JTAG ID. This is the reason why some debug tools can’t use
auto configuration, but must be configured by the user for the
correct core and revision.
Bit 25
Capability bit 1 (Reserved)
Bit 24
0:
1:
Capability bit 0
Hard macro.
Synthesisable.
The part number shall be selected in a way that no two com-
ponent types in the same package with TAP pins in the same
location have the same part number.
Bit 23 to 20 Family
7:
ARM7.
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8. Embedded Trace Module (ETM)
This module provides instruction and data trace capability.
The ETM is controlled by a JTAG style Test Access Port
(TAP) controller. For further details on the installed Rev1A
please refer to Embedded Trace Macrocell Specification
(Document Number: ARM IHI 0014) and ETM7 Technical
Reference Manual (Document Number: ARM DDI 0158).
– Data trace
– Trace before, about, after trigger
– Trigger and filter capabilities
– Access to Embedded Trace Module
– Normal trace data format
– Full-rate and half-rate clocking
– 4/8/16bit maximum port width
Features
– Instruction trace
8.1. Functional Description
TRACECLK
PIPESTAT0 to 2
TRACEPKT0 to 15
TRACESYNC
EXTTRIG
ETM7
Rev1A
FSYS
≥1
CLK
PWRDOWN
ETCK
ETMS
ETDI
DBGRQ
nRESET
0
MUX
1
TCK
TMS
ETDO
nTRST
JTAG TAP
Controller
TDI
TDO
TCK/U3.2
TMS/U3.1
TDI/U3.0
TDO/U3.3
TEST2
nTRST
&
POR
&
CR.JTAG
RESETQ
&
CR.TETM
≥1
DBGRQ
DBGACK
BREAKPT
EXTERN0
EXTERN1
RANGEOUT0
RANGEOUT1
nEXEC
ARM and
EmbeddedICE
nRESET
nRESET
Fig. 8–1: ETM Interface Block Diagram
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The ETM is controlled via scan chain 6 of the JTAG interface.
The process of remapping or loading code to RAM and exe-
cute it there is a problem for the ETM because one address
can contain different code (overlay). The solution is based on
the requirement that the memory map into which overlays
are loaded exists in multiple places in the address space.
The memory controller of the IC decodes the 24 LSB
address lines A0 to A23. This results in an memory map of
16 MByte. This memory map is repeated 256 times within
the 32 bit ARM core address space of 4 GByte.
Thus it is possible to have one static image of the code being
executed for the trace tool, with different possible overlays
statically linked into the appropriate area of the address
space.
Loading code into the RAM and execute it there means, copy
the code into the RAM and then jump to its overlay. The ETM
sees the full 32 bit address and reports this jump to the trace
tool which has the static image with a memory map for each
configuration at different places of its address space. The
memory controller sees the 24 lower address lines only,
therefor the jump is directed to the correct location.
The supported trace features are listed in Tabel 8–1.
Table 8–1: Trace Features
Features
Supported
Demultiplexed trace data format
Multiplexed trace data format
Normal trace data format
Full-rate clocking
-
-
✔
✔
Half-rate clocking
✔
Maximum port width
4/8/16-bit
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9. IRQ Interrupt Controller Unit (ICU)
The Interrupt Controller Unit manages up to 63 interrupt
sources. Each interrupt source has its own interrupt vector
pointing to an interrupt service routine. One of 16 priorities
can be assigned to each channel or it can be disabled. The
Interrupt Controller Unit is connected to the nIRQ input of the
CPU.
Features
– Expanding nIRQ input of ARM7TDMI
– Up to 63 interrupt sources (39 implemented)
– 16 priority levels
– HW vectoring
– HW prioritization
– HW stacking of priority levels
– 2 cycles maximum from input to CPU nIRQ
9.1. Functional Description
IntSrc
IntSrc
ISN
IntSrc
ISN
IRQ: PC = 0x00000018
Int. Src. Node
IAck <- Read from address [VTB]
IExit <- Write to address [VTB]+0x100
E
P
src prio. level
a
prio
4
a>b
&
nIRQ
Priority Encoder
CRI.GE
6
IExit
IAck
src#
Act. Prio. Level
act. prio.
Vect. Tab. Base
24
4
b
CRI.TE
force prio
Vector Table Logic
LDR PC,[PC,#±<12_bit_offset>]
Address Bus
from CPU
24
24
Address Bus to Mem. Ctrl. LDR PC,[VTB]
Fig. 9–1: Block Diagram
The Interrupt Controller Unit (ICU) is composed of an Inter-
rupt Source Node (ISN) for each interrupt source, of a Prior-
ity Encoder, of a Vector Table Logic, of an Active Priority
Level Logic and a comparator (Fig. 9–1).
table is programmable to any memory location. This allows
easy switching between different tables.
E
Each falling edge of an interrupt source signals an interrupt
request to its ISN and sets its Pending flag P (Fig. 9–2).
Besides the P flag each ISN consists of an Enable flag (E)
and a Source Priority register containing the priority of the
corresponding interrupt source. As long as both flags (E and
P) are true, the ISN outputs its priority. Otherwise it outputs
the lowest priority (that is no priority).
DB
D
Q
Q
src prio level
4
&
P
IntSrc
DB
S
D
R
IAck
src#
&
to Priority Encoder
6
The Priority Encoder outputs number and priority of the ISN
with the highest active priority. If several ISNs with the same
priority are active at the same time, the ISN with the lowest
source number is selected, thus the ISNs are operated in a
HW defined order. The interrupt vector table contains the
start addresses of the interrupt service routines (ISR). The
Vector Table Base register points to the first entry of the
interrupt vector table. Thus the location of the interrupt vector
Fig. 9–2: ISN Flags
The Active Priority Level Logic outputs the priority of the cur-
rently running task (lowest priority is the background task).
The comparator activates its output if this priority is lower
than the priority output from the Priority Encoder.
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If the ICU’s output is enabled by the Global Enable flag (GE)
the nIRQ input of the CPU is activated and held active until
acknowledged. The IRQ is granted by the CPU as soon as
the CPU internal IRQ flag (flag I in CPU register CPSR) is
enabled by SW. In the meantime between interrupt activation
in the ICU and granting by the CPU, higher priority interrupt
requests may be signaled to the ICU, raising the priority out-
put of the Priority Encoder.
ning task. Writing the maximum priority to the Forced Priority
register is another way to disable the ICU because no ISN
can generate an IRQ. Raising of the priority in this way does
not take effect as long as nIRQ is active.
The Global Enable (GE) signal at the output of the compara-
tor disables the ICU output. It is impossible to inactivate an
active nIRQ output by modifying an ISN, the GE flag or forc-
ing the priority. Only IAck resets the nIRQ output.
The SW has to read the address where the Vector Table
Base register points to ([VTB]) in order to get the start
address of the ISR for the ISN with the currently highest
active priority (Fig. 9–3). A data fetch from this location gen-
erates an internal interrupt acknowledge signal (IAck). With
IAck the Active Priority Level Logic accepts the new priority
and internally saves the priority of the interrupted task. IAck
clears the P flag in the corresponding ISN and deactivates
the nIRQ output. The ICU is ready for new interrupts now.
The size of the ICU can be scaled in steps of 8 ISNs. This IC
has 40 Interrupt Source Nodes implemented (ISN0 to
ISN39). Derived parts can contain 40, 32 (ISN0 to ISN31), 24
(ISN0 to ISN23) or less ISNs.
The Pending flags P in the ISNs are operating even when
the ICU is disabled (CRI.GE = 0). To be exact, only the ICU
output is disabled. This avoids further interrupts. Interrupted
ISRs will be finished and the Act. Prio. Level stack will be
handled properly if those ISRs generate IExit before return-
ing.
Before leaving the interrupt service routine, the SW has to
write to the address where VTB points to plus 0x100
([VTB]+0x100). A write to this location generates an internal
interrupt exit signal (IExit). With IExit the Active Priority Level
Logic internally deletes the priority of the current task and
outputs the priority of the interrupted task where the immedi-
ately following return instruction jumps to.
reset CRI, AFP, ISN
and internal logic
SR1.IRQ
R Q
CRI.GE
R Q
reset
disable nIRQ
100
0FC
0F8
0F4
0F0
Exit
interrupt exit address
ISN63 ISR
ISN62 ISR
ISN61 ISR
ISN60 ISR
Fig. 9–4: Reset Structure
Figure 9–4 shows the reset structure. Registers can’t be writ-
ten until the IRQ flag in the standby register SR1 is set. The
pending flags P in the ISNs are not reset by the standby reg-
ister. It can be operated by HW even while SR1.IRQ is zero.
Reading and writing of the P flags is impossible unless
SR1.IRQ is set to one.
source number
00C
008
004
000
ISN2 ISR
ISN2 ISR
ISN1 ISR
ISN0 ISR
interrupt entry address
Vector Table Base
32 Bit
Fig. 9–3: Interrupt Vector Table
Each ISN has a dedicated source number. A maximum of 64
ISNs can be connected to the Priority Encoder. The Priority
Encoder outputs source number 0 as long as all ISNs output
priority 0 or no ISN is active or the comparator output is inac-
tive. This is to guarantee a valid state of the Priority Encoder
and return a valid start address even if no interrupt source is
active. The corresponding vector is the first in the vector
table (default vector). For this reason ISN0 can’t be used for
connecting an interrupt source, because ISN0 is not the only
user of the corresponding interrupt vector. For example,
reading the address location pointed to by the Vector Table
Base register while nIRQ is inactive will return the ISR start
address of ISN0.
Additional to the ISNs whose inputs are connected to a HW
module, some ISNs are necessary whose inputs are not con-
nected or unused. Those interrupts can be activated by SW
solely (delayed interrupt).
The output of the Active Priority Level Logic may be forced
by writing a higher priority to the Forced Priority register. This
allows temporary raising of the priority of the currently run-
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Table 9–1: Interrupt Assignment
ISN Interrupt Source
Table 9–1: Interrupt Assignment
32
33
34
35
36
37
38
39
PINT5
ISN Interrupt Source
CAN2
0
Default vector, not connected
CC0OR
CC0COMP
CC1COMP
CC2COMP
CC3COMP
PINT4
1
2
CC1OR
3
PINT0
4
PINT1
5
CAN0
GBus
6
SPI0
7
Timer 1
8
Timer 0
9
P06 COMP
RESET/ALARM
WAIT COMP
UART0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PINT2
reserved for WAPI
CC2OR
CC3OR
Timer 2
reserved for RTC
I2C0
Timer 3
SPI1
COMMRX
COMMTX
PINT3
DIGITbus
I2C1
CAN1
CC4OR
CC5OR
Timer 4
UART1
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9.2. Timing
CPU
f
SYS
prio
comp
(ECLK)
IntSrc
nIRQ
src#
Fig. 9–5: Timing
The sample period of an incoming interrupt request lasts one
cycle in the worst case. It is sampled by an ISN with the fall-
ing edge of fSYS. Priority Encoder and comparator require
another cycle. The CPU finally evaluates with the next falling
edge of fSYS
.
This results in a maximum delay of 2 fSYS cycles from
request to CPU input.
9.3. Registers
FPRIO
Forced Priority
r/w:
(Table 9–3)
CRI
Control Register IRQ
Writing a value higher than the APRIO value to this location
raises the priority of the actual running ISR. It doesn’t change
APRIO. Only ISRs with a priority higher than the forced prior-
ity are able to interrupt now.
7
6
TE
0
5
x
x
4
x
x
3
x
x
2
x
x
1
x
x
0
x
x
r/w
GE
0
Res
It is necessary to first save the original FPRIO value before
raising the own priority by overwriting FPRIO. The saved
FPRIO value has to be restored before ISR exit.
GE
r/w1:
r/w0:
Global Enable
Enable IRQ.
Disable IRQ.
Disabling happens as soon as nIRQ is inactive. An active
nIRQ will not be interrupted by writing a zero to GE.
PEPRIO
Priority Encoder Priority output
7
6
x
x
5
x
x
4
x
x
3
2
1
0
TE
r/w1:
r/w0:
Table Enable
Enable.
Disable.
r
x
Priority
x
0
0
0
0
Res
The Vector Table Logic doesn’t work if TE is disabled. Nei-
ther the correct ISR start address is returned nor the internal
signals IAck and IExit are generated on accessing the dedi-
cated memory location.
This register shows the priority of the highest pending and
enabled interrupt source.
AFP
Actual and Forced Priority Register
PESRC
Priority Encoder Source output
7
6
0
5
4
3
2
1
0
7
6
x
x
5
4
3
2
1
0
r/w
APRIO
FPRIO
r
x
Source
0
0
0
0
0
0
0
Res
x
0
0
0
0
0
0
Res
APRIO
r:
Actual Priority
(Table 9–3)
This register shows the number of the highest pending and
enabled interrupt source.
This field indicates the programmed priority of the actually
running ISR. It is modified by HW only.
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this interrupt source node is enabled, this flag is cleared by
HW as soon as the corresponding ISR is called.
VTB
Vector Table Base
Table 9–2: Pending Flag Access
Offs
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
0
0
0
0
0
0
0
0
3
2
1
0
M
0
0
1
1
P
0
1
0
1
Read
Write
Address bit 23 to 16
Address bit 15 to 9
Not pending
Pending
Don’t modify P
0
0
0
0
0
0
0
0
0
0x00000000
Res
Not possible
Clear P
Set P
The register VTB has to be programmed with the memory
base address of the interrupt vector table. The interrupt vec-
tor table has to start at an even page address (9 LSB are
zero) and is not longer than one page (256 bytes). Besides
the start address of the interrupt vector table VTB defines
two addresses which perform HW actions when accessed
and CRI.TE is set.
E
Enable
Enable interrupt.
Disable interrupt.
r/w1:
r/w0:
This flag is modified by SW only.
PRIO Interrupt Source Node Priority
This field is modified by SW only (Table 9–3).
Every word read access to the location addressed by VTB
deactivates the nIRQ output. If the comparator output is
active, the internal signal IAck is activated, which returns the
ISR start address of the ISN with the highest active priority,
clears the corresponding P flag and saves the interrupted
priority.
Table 9–3: Priority Encoding
PRIO
Priority number
Every word write access to the location addressed by VTB
plus 0x100 activates the internal signal IExit.
3
0
0
0
:
2
1
0
0
1
:
0
0
1
0
:
0
0
0
:
0 (No priority)
Accessing these locations ([VTB] and [VTB]+0x100) without
generating IAck or IExit is possible when the Vector Table
Logic is disabled (CRI.TE = 0).
1 (Lowest priority)
2
ISNx
Interrupt Source Node Register x
:
7
6
P
x
5
E
0
4
x
x
3
2
1
0
1
1
1
1
1
1
0
1
14
r/w
M
PRIO
15 (Highest priority)
0
0
0
0
0
Res
M
w1:
Modify Pending Flag (Table 9–2)
Modify Pending flag.
r/w0:
Don’t modify Pending flag.
This flag is modified by SW only and always reads as 0. It
allows modification of register ISNx without influence to flag
P. Without this flag a HW modification of flag P could be cor-
rupted by a simultaneous read-modify-write of register ISNx.
P
r/w1:
r/w0:
Pending (Table 9–2)
Interrupt is pending.
No interrupt pending.
This flag can be modified by HW and SW. It is set by HW
when the corresponding interrupt source input is activated. If
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9.4. Principle of Operation
rupt service routine has to be done by the PC relative load
PC instruction
LDR PC,[PC,#<12_bit_offset>],
where the operand [PC,#<12_bit_offset>] must point to the
first entry of the vector table. Due to the 12_bit_offset the
vector table has to be located within ±4kB from the above
instruction. Above instruction is called vectoring. There are
two possibilities for the point of time, direct and delayed,
when vectoring takes place.
9.4.1. Reset
Clearing standby register flag SR1.IRQ resets the ICU (see
Fig. 9–4 on page 66). The registers are reset to their men-
tioned values (see Section 9.3. on page 68) and cannot be
modified. The nIRQ output is inactive and the actual priority
level logic is cleared.
9.4.2. Initialization
Proper configuration of the interrupt sources in the peripheral
modules has to be made prior to initialization of the ICU.
9.4.3.1. Direct Vectoring
Above instruction is the first instruction which is executed
when an interrupt occurs. The address 0x18 contains the PC
relative load PC instruction.
Initialization is possible after the standby register flag
SR1.IRQ has been written to one. Now the registers can be
modified by SW. But no interrupt request is generated to the
CPU.
9.4.3.2. Delayed Vectoring
Install the vector table beginning at an even page address (9
LSB are zero). Each entry has to be a 32 bit start address of
an interrupt service routine. The vector table has to be
located near (±4kB) the load PC instruction. Write the start
address of the vector table to the Vector Table Base register
VTB. Further access to register VTB is not necessary until
you want to switch to another vector table at another loca-
tion.
Above instruction is delayed. The address 0x18 contains a
jump to a short piece of code which does all what has to be
done for every ISR (Save LR, SPSR and working registers).
After this common prefix the jump to the appropriate ISR is
launched by the PC relative load PC instruction.
9.4.4. Inactivation
Set up the Interrupt Source Node registers ISNx with the
necessary priority and enable them. The pending flags have
to be cleared, because they are not cleared by SR1.IRQ and
are operative all the time. Clearing an active pending flag
and enabling the corresponding ISN must not be done with a
single instruction. This might lead to an unwanted (spurious)
interrupt which is directed to the default vector. First clear P
and then set E in two instructions. Interrupt sources which
shall not generate interrupts must not be enabled and need
no priority (PRIO=0), but can be operated by polling and
resetting the pending flag P by SW.
An interrupt source can be disabled locally by clearing the
enable flag E in the corresponding ISN register. Even a
pending interrupt can be disabled this way. A disabled ISN
does not participate in sending interrupt requests to the
CPU.
All interrupt sources can be disabled globally by clearing the
global enable flag CRI.GE. It is impossible to inactivate an
active nIRQ output signal by clearing CRI.GE. An active
nIRQ will be served and only further IRQs can be sup-
pressed by setting the GE flag.
The pending flag P stays operative in both cases and may be
polled by SW.
9.4.3. Operation
The ICU is operable in all CPU modes.
A zero in the standby register flag SR1.IRQ immediately
resets registers and logic and forces the nIRQ output to inac-
tive.
Setting both flags CRI.GE and CRI.TE enables the ICU at
last. When an interrupt occurs, execution starts at address
0x18. For proper operation of the ICU the jump to the inter-
9.5. Application Hints
module has to be switched off or its interrupt source output
has to be disabled.
9.5.1. Hardware Triggered Interrupts
Normally the connected peripheral modules are setting the
pending flag P. If the ISN is enabled (E=1) and the priority is
not zero, an IRQ is generated. The P flag will be reset as
soon as the corresponding interrupt service routine is called.
It is not required and should be avoided to modify the P flag
of those ISNs by SW.
The ISN has to be enabled (E=1) and programmed to the
desired priority (PRIO>0). Setting the pending flag P by SW
generates an interrupt. This interrupt will be processed as
soon as possible. When the CPU responds to the interrupt
request and jumps to the corresponding ISR, the pending
flag is cleared automatically.
9.5.2. Software Triggered Interrupts
9.5.2.1. Delayed Interrupt
Any ISN which is not used by the connected peripheral mod-
ule can be used for generating IRQ interrupts by SW. It must
be avoided that the interrupt source of this ISN is also gener-
ating interrupt requests. Either the corresponding peripheral
Any ISN which is not used by the connected peripheral mod-
ule can be used for implementing the delayed interrupt
mechanism for an operating system. The ISN has to be
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enabled (E=1) and programmed to priority 1 (the lowest pri-
ority which can generate an interrupt). Setting the pending
flag P by OS-SW within a higher priority interrupt service rou-
tine generates a delayed interrupt, which is processed after
all higher priority interrupts are finished.
not be re-enabled by clearing the I flag of the CPSR. No IExit
shall be generated on interrupt exit by writing to
[VTB]+0x100 because there was no IAck at interrupt entry.
Unintentional inactivation of an active comparator output sig-
nal can be caused by modifying the ISN which is the only
source for the momentary active nIRQ output. This can be
done by disabling (E=0), or clearing the P flag, or lowering
the priority of this ISN. Those actions may lead to a default
vector interrupt.
9.5.3. Polling
Polling means that the pending flag P is observed by SW.
Set by the corresponding interrupt source, the SW recog-
nizes the P flag to be set, calls the corresponding routine and
clears the P flag. The ISN should be disabled (E=0), other-
wise unwanted IRQs would be generated.
9.5.6. Debugger
Unintentional access to vector table addresses [VTB] and
[VTB]+0x100 can result in malfunction of the interrupt sys-
tem (HW and SW). If it is necessary, for instance, to dump
the vector table, there are two ways to do this without gener-
ation of IAck or IExit:
9.5.4. Operating Nested Interrupts
Nested interrupt service routines use common data
resources. Every routine, which may have interrupted a
lower priority routine, has to save common data resources
upon interrupt entry and restore them before returning to the
interrupted routine. This is efficiently done by an entry and an
exit sequence which are enclosing the interrupt service rou-
tine.
The first way is to clear the flag CRI.TE which controls the
vector table logic. Clearing it disables HW actions on access-
ing above addresses. But ensure that no interrupts are pos-
sible while TE is disabled.
The second way is to access above addresses by byte or
half word operations only. The HW actions are only gener-
ated by word access. Disabling interrupts is not required in
the latter case.
9.5.4.1. Interrupt Entry Sequence
The IRQ disable flag I in the core register CPSR is set after
an IRQ, thus disabling further IRQs. Before the interrupt is
enabled again, the user has to take the following steps:
9.5.7. Critical Code
1. For direct vectoring: Jump to the corresponding interrupt
service routine by loading the first element from the vector
table into the program counter by an LDR instruction.
Critical code is a sequence of instructions which must not be
interrupted, because it modifies common data resources.
Protection from being interrupted can be achieved by dis-
abling interrupts during critical code. There are several ways
of doing this:
2. Save Link Register (R14), SPSR and working registers to
stack.
3. For delayed vectoring: Jump to the corresponding inter-
rupt service routine by loading the first element from the vec-
tor table into the program counter an LDR instruction.
9.5.7.1. ARM core’s Interrupt Disable Flag I and F
The ARM core itself provides the interrupt disable bits I and
F in the program status register CPSR.
4. Clear CPSR.I to re-enable IRQs.
Now the actual application ISR can start.
The control bits of the CPSR (I, F and others) can be SW
altered only when the processor is in a privileged mode.
ARM recommends to modify the CPSR by a read-modify-
write instruction sequence in order to leave the reserved bits
unchanged.
9.5.4.2. Interrupt Exit Sequence
Before returning, it is necessary to clear the interrupt cause.
Upon exit from an ISR some actions have to be taken with-
out being interrupted:
MRS
ORR
MSR
r0,cpsr
r0,r0,#I_Bit ;disable interrupts
cpsr_c,r0
1. Set CPSR.I to disable further IRQs.
2. Restore Link Register (R14), SPSR and working registers
from stack.
The interesting case is when an interrupt comes in during
execution of the MSR instruction. The core commits to taking
an interrupt before the instruction being executed completes.
Therefore even though an MSR instruction may have written
to the CPSR to disable interrupts, the interrupt will still be
taken. A NOP between the MSR instruction and the first
instruction of the critical code is not necessary. If an interrupt
occurs during an MSR instruction, it will return to the instruc-
tion immediately following the MSR.
3. Generate the signal IExit by performing a word write by an
STR instruction to the interrupt exit address at [VTB]+0x100.
4. Returning to the interrupted routine has to be done by an
instruction, which simultaneously writes the PC (R15) and
CPSR with the values in R14 and SPSR (e.g. SUBS
PC,R14_irq,#4).
9.5.5. Default Vector
9.5.7.2. Global Enable Flag GE
Any read access to vector table address [VTB] will deliver
the default vector, but will not generate IAck as long as the
comparator output is inactive or the priority output of the pri-
ority encoder is zero. Due to this the default vector ISR runs
with the priority of the interrupted routine. This is the only ISR
which could be interrupted by itself. As long as this default
vector ISR is not programmed reentrant, interrupts should
Protection of critical code can be achieved by disabling the
nIRQ output with the global enable flag CRI.GE. The GE flag
changes its value in the cycle after the data transfer of the
store instruction. In this cycle the next instruction is in the
execution stage of the CPU and will be executed. Due to this
one NOP is required between the store instruction, which
clears CRI.GE, and the first instruction of the critical code.
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9.5.7.3. Force Priority
To protect critical code, further IRQ interrupts can be dis-
abled by writing the maximum priority to the forced priority
register AFP. Modifying AFP works like clearing the GE flag.
One NOP is required between the store instruction, which
writes AFP, and the first instruction of the critical code.
9.5.7.4. Disabling via ISN
At last, critical code protection can be achieved by disabling
all ISNs by clearing their enable flag E. The priority encoder
is calculated at the beginning of a cycle. Due to this, chang-
ing an ISN register becomes effective only in the next cycle.
Two NOPs are required between the store instruction, which
clears the flag E, and the first instruction of the critical code.
9.5.8. Switching an Interrupt Vector
Interrupt service routines of an interrupt source can easily be
changed by entering the start address of the new ISR at the
corresponding entry of the interrupt vector table.
9.5.9. Switching the Vector Table
It can be switched between different vector tables if they
have been installed. Changing the vector table is simply
done by writing the base address of the new vector table to
register VTB. All subsequent interrupt service routines must
relate to this vector table. Due to this, it is necessary for an
ISR in such an environment, to read the location of the cur-
rent vector table from register VTB before accessing it.
Be careful when doing vector table switching within an ISR.
Interrupted ISRs could try to do the IExit from an outdated
table.
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10. FIQ Interrupt Logic
The FIQ Interrupt Logic selects one out of eight interrupt
sources as the CPU’s nFIQ input. An interrupt request is
latched in a pending flag until it is cleared by SW. The output
can be disabled.
Features
– Expanding nFIQ input of ARM7TDMI
– 1 of 8 selection
– IRQ or FIQ selectable
10.1. Functional Description
CRF.SEL
Interrupt Sources
FIQ0
FIQ1
FIQ2
FIQ3
FIQ4
FIQ5
FIQ6
FIQ7
0
1
CRF.GE
D
Q
Q
DB
DB
nFIQ
&
CRF.P
S
D
≥1
to ISNs
Fig. 10–1: Block Diagram FIQ
At one time, only one interrupt source can be connected to
the nFIQ input of the CPU. The interrupt source which is con-
nected to the nFIQ, is disconnected from the corresponding
ISN. This ISN can then be used by SW.
SR1.FIQ
R Q
reset
reset CRF
Fig. 10–2: Reset Structure
Figure 10–2 shows the reset structure. Registers can’t be
written until the FIQ flag in the standby register SR1 is set.
10.2. Registers
This Flag is set by HW and SW. It must be cleared by SW
before re-enabling FIQ by bit F in the core’s CPSR register,
or no further interrupt can occur.
PRF
Pending Register FIQ
7
6
x
x
5
x
x
4
x
x
3
x
x
2
x
x
1
x
x
0
P
0
r/w
x
CRF
Control Register FIQ
x
Res
7
6
x
x
5
x
x
4
x
x
3
2
1
0
0
0
P
r/w1:
r/w0:
FIQ Pending
Pending FIQ.
No pending FIQ.
r/w
GE
SEL
0
0
0
Res
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GE
r/w1:
r/w0:
Global Enable FIQ
Enable FIQ.
Disable FIQ.
SEL
r/w:
Select FIQ Source
(Table 10–1)
Disabling happens as soon as nFIQ is inactive. An active
nFIQ will not be interrupted by clearing GE.
Table 10–1: FIQ Source Selection
SEL
3
Switched to nFIQ
2
x
1
x
0
x
Select
None
FIQ0
FIQ1
FIQ2
FIQ3
FIQ4
FIQ5
FIQ6
FIQ7
ISN Interrupt Source
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
SPI0
1
11 WAIT COMP
12 UART0
13 PINT2
1
1
1
15 CC2OR
17 Timer 2
19 I2C0
1
1
1
5
CAN0
10.3. Principle of Operation
10.3.1. Reset
Clearing standby register flag SR1.FIQ resets the FIQ Inter-
rupt Logic (see Fig. 10–2 on page 73). The registers are
reset to their mentioned values (see Section 10.2. on
page 73) and cannot be modified. The nFIQ output is inac-
tive.
10.3.2. Initialization
Proper configuration of the interrupt sources in the peripheral
modules has to be made prior to initialization of the FIQ
Interrupt Logic.
Initialization is possible after the standby register flag
SR1.FIQ has been set. Now the registers can be modified by
SW. But no interrupt request is generated to the CPU.
The FIQ Interrupt Logic is operable in all CPU speed modes.
10.3.3. Operation
Setting flag CRF.GE enables the FIQ Interrupt Logic. When
an interrupt occurs, execution starts from address 0x1C.
10.3.4. Inactivation
The FIQ Interrupt Logic can be disabled by clearing the glo-
bal enable flag CRF.GE. An active nFIQ will be served, how-
ever, and only future FIQs will be suppressed by clearing the
GE flag.
Clearing the standby register flag SR1.FIQ immediately
resets registers and logic and forces the nFIQ output to inac-
tive.
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11. Port Interrupts
Port interrupts are the interface of the Interrupt Controller to
the external world. Six U-Port pins and alternatively six P-
Port pins are connected to the module via their special input
lines (Fig. 11–1). HW Option programmable multiplexers
define which port signal is actually connected to the Trigger
Mode Logic (Table 11–1). The P-Ports are actually analog
input ports, thus Schmitt Triggers are enabled if the P-Ports
are selected as port interrupts. The input sampling frequency
is f0perm, which is not disabled by CPU SLOW or DEEP
SLOW modes.
Trigger is enabled. This is the reason why input levels other
than ground or digital supply may cause quiescent currents
in the Schmitt Trigger circuit and thus lead to higher power
consumption.
Table 11–1: Module specific settings
Mod-
ule
Name Item
HW Options
Initialization
Address Item Setting
HW Option
f
0perm
PM.PINT
PINT0 Port Multi- PM.PINT PINT0 U1.7 special in
0
PINT0
PINT1
PINT2
PINT3
PINT4
PINT5
U1.7
P1.2
U1.6
P1.3
U1.5
P1.4
U8.5
P1.5
U0.5
P1.6
U0.4
P1.7
PINT0
Interrupt
Source
plexers
IPRM0
1
P1.2
PINT1
PINT2
PINT3
PINT4
PINT5
PINT1 U1.6 special in
P1.3
PINT2 U1.5 special in
P1.4
PINT1
Interrupt
Source
Trigger
Mode
PINT3 U8.5 special in
P1.5
PINT2
Interrupt
Source
PINT4 U0.5 special in
P1.6
PINT3
Interrupt
Source
PINT5 U0.4 special in
P1.7
PINT4
Interrupt
Source
IPRM1
Trigger
Mode
IRPM0
Interrupt Port Mode Register 0
7
6
0
5
4
3
2
1
0
0
PINT5
Interrupt
Source
r/w
PIT3
PIT2
PIT1
PIT0
0
0
0
0
0
0
Res
Fig. 11–1: Port Interrupts
IRPM1
Interrupt Port Mode Register 1
7
6
x
x
5
x
x
4
x
x
3
2
1
0
0
The user can define the trigger mode for each port interrupt
by the interrupt port mode register.
r/w
x
PIT5
PIT4
x
0
0
0
Res
The Trigger Mode defines on which edge of the interrupt
source signal the Interrupt Controller is triggered. The trig-
gering of the Interrupt Controller is shown in figure 11–2.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
Precautions
Parallel usage of a P-Port as analog and port interrupt input
is possible but not recommended. In this case the Schmitt
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PITn
Port interrupt trigger number n
This field defines the trigger behavior of the associated port
interrupt (Table 11–2).
Table 11–2: PITn usage
PITn
0h
Trigger Mode
Interrupt source is disabled
Rising edge
1h
2h
Falling edge
3h
Rising and falling edges
port input
Interrupt
Falling edge
Rising edge
(low active)
Interrupt
(low active)
Interrupt
(low active)
Falling and rising
edge trigger mode
Fig. 11–2: Interrupt Timing
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12. Ports
This chapter describes the P-, U- and H-Ports.
The universal ports U0 to U8 serve as digital I/O and can be
configured as LCD drivers.
The analog input ports, P0 and P1, serve as input for the
analog to digital converter and may be used as digital inputs.
The high current ports H0 to H7 serve as digital I/O and can
be configured as stepper motor drivers.
P2 may be used as digital input, only.
12.1. Analog Input Port
The 16 pin analog input port is composed of ports P0 and
P1. All port pins can be configured as digital input. P0.6 is
connected to a comparator, which may be selected as inter-
rupt source. P1.2 to P1.7 can be used as port interrupts. The
2-pin port P2 solely serves as digital input.
Features
– 16 pin analog input multiplexer.
– 18 pins configurable as digital input ports.
– Schmitt hysteresis digital input buffer, CMOS level (2.5V)
or Automotive level (3.3V) selectable.
– 6 pins configurable as port interrupts.
P0.6 to Alarm Comparator
8
8
2
8
8
P0.0 to P0.7
P1.0 to P1.7
P2.0 to P2.1
16:1
MUX
To A/D converter
P1.2 to P1.7 to port interrupts 0 to 5
PxPIN.Py
18
PxLVL.Ay
PxIE.Iy
rd
Fig. 12–1: P-Ports with Input Multiplexer and P0.6 Alarm Comparator
P0 and P1 analog input lines are connected to a multiplexer.
The output of this multiplexer is connected to the 10-bit A/D
converter.
P0 to 7
r:
Pin Data 0 to 7
Read Pin state
Port P0.6 is, in addition, the input of the P0.6 Alarm Compar-
ator, described in the chapter on the Analog Section.
PxLVL
Port x Input Level Register
7
6
A6
0
5
A5
0
4
A4
0
3
A3
0
2
A2
0
1
A1
0
0
A0
0
P0 and P1 pins may alternatively, P2 may exclusively be
used as digital input if enabled by setting the individual pin’s
enable flag PxIE.Iy. CMOS or Automotive Schmitt trigger
input level may individually be selected by writing registers
PxLVL. The digital value of the input pins is obtained by read-
ing registers PxPIN. Disabled inputs read as 1. Pins should
either be used as analog or digital inputs, not both at the
same time.
r/w
A7
0
Res
A0 to 7
r/w1:
Automotive Flag 0 to 7
Schmitt trigger input level is Automotive
Schmitt trigger input level is CMOS
r/w0:
Six of the analog input pins (P1.2 to P1.7) may be used as
port interrupt input if selected by HW Option PM.PINT (see
sections “Port Interrupts” and “HW Options” for more details).
Configure as digital input for this operation.
PxIE
Port x Input Enable Register
7
6
I6
0
5
I5
0
4
I4
0
3
I3
0
2
I2
0
1
I1
0
0
I0
0
r/w
I7
PxPIN
Port x Pin Register
0
Res
7
6
P6
1
5
P5
1
4
P4
1
3
P3
1
2
P2
1
1
P1
1
0
P0
1
I0 to 7
r/w1:
r/w0:
Digital Input Enable 0 to 7
Enable input buffer
Disable input buffer
r
P7
1
Res
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12.2. Universal Ports U0 to U8
Universal Ports are pin-configurable as SW I/O port, Special
Input/Output port (SI/SO) to special internal hardware mod-
ules or direct drive of 4:1 multiplexed LCD segment and
backplane lines (LCD port).
Features
– Pin-configurable as I/O or Special Port or LCD driver.
– LCD mode: 1:4 multiplex, 5V supply.
– PORT mode: push-pull or open-drain output.
– Two output current fold-back characteristics selectable
The output drivers feature a current fold-back characteristic
to allow shorting the output and to improve EMI perfor-
mance.
– Schmitt hysteresis input buffer, CMOS level (2.5V) or
Automotive level (3.3V) selectable.
UxMODE.Ly
UV
UV
DD
Special In
UxPIN.Py
SS
UxLVL.Cy
UxSLOW.Sy
UV
DD
UxTRI.Ty
Current
0
Fold
UxD.Dy
Special Out
UxNS.Sy
&
1
Back
0
1
Ux.y
Current
Fold
Back
≥1
From LCD
UxDPM.Dy
UV
SS
Analog Switch and
Segment Driver
MUX
2
/ UV
x: Port number 0 to 8
y: Port pin number 0 to 7
3
DD
DD
1
/ UV
3
Fig. 12–2: Universal Port Pin Circuit Diagram
The Universal Port pins can be configured for several basic operating modes (Table 12–1)
Table 12–1: Universal Port basic Operating Modes
Modes
Function
Port Mode
Normal Input
Special Input
Normal Output
Special Output
The SW uses the port as digital input.
The port input is additionally connected to specific hardware modules.
The SW uses the port as latched digital tristateable output.
The output signals of specific hardware modules are directly port output source.
The port pin serves as backplane/segment driver for a 4:1 multiplexed LC display
LCD Mode
See the chapter on Pinning for information about specific
hardware module connections to individual port pins for Spe-
cial Input and Special Output purposes.
After reset, all Universal Ports are in Port, Normal, tristate,
CMOS input level condition. SLOW mode is disabled.
12.2.1. Port Mode
Universal Port control is distributed among eight registers.
Four of these registers have duplicate functions for Port and
LCD mode. All register bits corresponding to one U-Port pin
are controlled by the same bus bit.
For Port mode, the respective UxMODE register bit has to be
cleared for mode selection.
In both LCD and Port modes, the SLOW mode may be
defined for each individual U-Port pin. It reduces the current
drive capability of the output stage. Set flag SR0.PSLW to
enable this operation mode.
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The function of the seven remaining registers is given in
Table 12–2.
The output sequence timing on backplane and segment out-
put ports in LCD Mode is controlled by the LCD module.
Please refer to section LCD Module for information about
operation of this module.
Table 12–2: Register Functions in Port Mode
As generation of the backplane port output sequence is fully
done by the LCD module, no segment line data setting is
necessary for these ports.
Register
UxD
Function
r/w Data register
enable/disable output
12.2.3. Port Fast and Slow Modes
UxTRI
UxNS
Once individual port pins have been enabled for Port Slow
mode by setting registers UxSLOW, set flag SR0.PSLW to
simultaneously enter this mode in all respective ports.
select Data register or specific hardware
module as output source
UxDPM
UxSLOW
UxLVL
select push-pull or open-drain, double drive
mode for output drivers
All U-Ports exhibit two operating regions in the DC output
characteristic (see Fig. 12–3). Near zero output voltage the
internal driver transistors operate non-limited, to offer a lin-
ear, low on-resistance. With larger output voltages, however,
the output current folds back to a a limited value. This mea-
sure helps to fight supply current transients and related EMI
noise during port switching.
enable/disable Port Slow mode for output
drivers
select CMOS or Automotive Schmitt trigger
input level
In the fold-back region, Port Fast mode and Port Slow mode
select two different current limits Ishf and Ishs. Port Slow
mode sets a limit where the output may even be shorted con-
tinuously to either supply rail. Thus, wired-or configurations
may be realized. The external load resistance should be
greater than 5kOhms in Port Slow mode.
UxPIN
read pin state
In Port Mode, the Special Input path is always operative.
This allows manipulating the input signal to the specific hard-
ware module through Normal Output operations by software.
For actually switching to Port Slow mode, both registers
UxSLOW and SR0.PSLW have to be set. In all other cases,
Port Fast mode is selected.
Because register UxPIN allows reading the pin level also in
Special Output mode, the output state of the specific hard-
ware module may be read by the CPU.
It is recommended to place all LCD ports in Port Slow mode.
12.2.2. LCD Mode
Io
For LCD Mode, the respective UxMODE register bit has to
be set for mode selection.
Non-
limited
region
Limited
region
The function of the seven remaining registers is given in
Table 12–3.
Table 12–3: Register Functions in LCD Mode
Register
UxD
Function
r/w phase 0 segment line data
r/w phase 1 segment line data
r/w phase 2 segment line data
r/w phase 3 segment line data
Port Fast Mode
Ishf
UxTRI
UxNS
UxDPM
UxSLOW
enable/disable Port Slow mode for output
drivers
Port Slow Mode
Ishs
UxLVL
UxPIN
no function
no function
0
1V
2V
3V
4V
5V
By writing segment line data registers, only a master is
changed. Any write to global register ULCDLD will transfer
all master settings to the respective slaves and thereby
change the LC display in one instant.
Vol
Fig. 12–3: Typical U-Port pull-down DC output characteris-
tic (pull-up characteristic is complementary).
Registers UxD, UxTRI, UxNS and UxDPM compose a word-
aligned 32bit register and may be accessed by one 32bit
operation.
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12.3. Universal Port Registers
Eight U-Port registers are basically available for 9 U-Ports
U0 to U8, each. Because some U-Ports are less than 8 pins
wide, not all of the described bits are available for every port.
Furthermore, the respective device’s pinning may require a
reduction in available U-Ports. See the respective pinning
table for details.
UxNS
Universal Port x Normal-Special /
Segment 2 Register
7
6
5
4
3
2
1
0
r/w
S7
S6
S5
S4
S3
S2
S1
S0
Port
The general U-Port register model is given below.
r/w SG7_2 SG6_2 SG5_2 SG4_2 SG3_2 SG2_2 SG1_2 SG0_2 LCD
Res
0
0
0
0
0
0
0
0
UxMODE
Universal Port Mode Register
S0 to 7
r/w1:
r/w0:
Normal/Special Mode Flag 0 to 7
Special Mode. Special hardware drives pin.
Normal Mode. Data latch drives pin.
7
6
5
4
L4
0
3
L3
0
2
L2
0
1
L1
0
0
L0
0
r/w
L7
L6
0
L5
0
0
Res
UxDPM
Universal Port x Double Pull-Down
Mode / Segment 3 Register
L0 to 7
Port Mode Flag
Select the mode of the corresponding port pins.
7
6
5
4
3
2
1
0
r/w1:
r/w0:
Port pin is in LCD mode.
Port pin is in Port mode.
r/w
D7
D6
D5
D4
D3
D2
D1
D0
Port
r/w SG7_3 SG6_3 SG5_3 SG4_3 SG3_3 SG2_3 SG1_3 SG0_3 LCD
Res
UxD
Universal Port x Data / Segment 0
Register
0
0
0
0
0
0
0
0
D0 to 7
r/w1:
Double Pull-Down Mode
Output driver is pull-down,
Ishs (Port Slow mode) doubled.
Standard.
7
6
5
4
3
2
1
0
r/w
D7
D6
D5
D4
D3
D2
D1
D0
Port
r/w0:
r/w SG7_0 SG6_0 SG5_0 SG4_0 SG3_0 SG2_0 SG1_0 SG0_0 LCD
All U-Port pins may be switched into a Double Pull-down
Mode (DPM) by setting the appropriate DPMx flag, where
0
0
0
0
0
0
0
0
Res
– the short circuit current Ishs is doubled (with Port Slow
Mode enabled for these ports, and SR0.PSLW set to 1)
D0 to 7
w:
r:
Data Latch
Write latch.
Read latch.
– the output configuration is pull-down, not the standard
push-pull.
SG0_0 to 7_3
Segment Data Latch
Write latch.
Read latch.
w:
r:
By these means these ports may be configured to operate as
connection to a wired-or, single-wire bus (e.g. DIGITbus or
I2C) with external pull-up resistor.
In LCD mode, U-Port registers UxD, UxTRI, UxNS and
UxDPM store LCD segment information. Segment register
bits UxY.SGm_n contain the information for segment line m
during phase n, which controls segment m_n. Thus, register
bits UxD.SG0_0, UxTRI.SG0_1, UxNS.SG0_2 and
UxPIN.SG0_3 contain the complete information for segment
line 0 in U-Port x.
UxSLOW
Universal Port x Slow Mode Register
7
6
S6
0
5
S5
0
4
S4
0
3
S3
0
2
S2
0
1
S1
0
0
S0
0
r/w
S7
Please refer to Pin Assignment and Description for segment/
pin number assignment. Information about the usage of the
LCD Segment field will be found at the functional description
of the LCD Module.
0
Res
S0 to 7
Slow Flag 0 to 7
r/w1:
r/w0:
Output driver is in Port Slow mode
Output driver is in Port Fast mode
UxTRI
Universal Port x Tristate / Segment 1
Register
UxLVL
Universal Port x Input Level Register
7
6
5
4
3
2
1
0
7
6
5
4
A4
0
3
A3
0
2
A2
0
1
A1
0
0
A0
0
r/w
T7
T6
T5
T4
T3
T2
T1
T0
Port
r/w
A7
0
A6
0
A5
0
r/w SG7_1 SG6_1 SG5_1 SG4_1 SG3_1 SG2_1 SG1_1 SG0_1 LCD
Res
Res
1
1
1
1
1
1
1
1
A0 to 7
r/w1:
r/w0:
Automotive Flag 0 to 7
Schmitt trigger input level is Automotive
Schmitt trigger input level is CMOS
T0 to 7
r/w1:
r/w0:
Output Tristate Flag 0 to 7
Output driver is disabled (tristate)
Output driver is enabled
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CDC 32xxG-B
UxPIN
Universal Port x Pin Register
7
6
P6
x
5
P5
x
4
P4
x
3
P3
x
2
P2
x
1
P1
x
0
P0
x
r
P7
x
Res
P0 to 7
Pin Data 0 to 7
r:
Read Pin state.
ULCDLD
Universal Port LCD Load Register
7
LCDSLV
0
6
x
5
4
3
2
1
0
x
0
w
x
x
x
x
x
0
0
0
0
0
0
Res
LCDSLV LCD Module is Slave
Select the mode of the LCD module.
w1:
w0:
LCD module is slave.
LCD module is master.
A write access to this memory location simultaneously loads
all segment information of all U-Ports in LCD mode to the
display. The flag LCDSLV is available only in LCD mode.
12.3.1. Special Register Layout of U-Port 4
U4.0 to U4.3 provide backplane signals in LCD Mode. To
operate any ports as LCD segment driver it is necessary to
switch all these ports to LCD mode. This has to be done by
setting flags U4MODE.L0 through U4MODE.L3.
As backplane ports U4.0 to U4.3 require no segment data
setting, SG0_0 through SG3_3 bits are not available in U4
registers.
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12.4. High Current Ports H0 to H7
High Current Ports 0 to 7 are used to drive coils of stepper
motors. All ports are 4 pins wide to facilitate control of indi-
vidual stepper motors. The H-Ports are similar to universal
ports but as the name says, they can drive higher currents.
H-Ports can be operated by software like Universal Ports
(Port Mode). Their Special Out inputs are connected to the
stepper motor module or to PWM outputs.
Features
– Pin-configurable as I/O or Special Port driver
– 30mA output current
– Schmitt hysteresis input buffer, CMOS level (2.5V) or
Automotive level (3.3V) selectable.
– Reduced slew rate of current and voltage for driving resis-
tive, capacitive or inductive loads.
HV
HV
DD
x: Port number 0 to 7
y: Port pin number 0 to 3
Special In
HxPIN.Py
HxLVL.Cy
SS
HV
DD
Slew
HxTRI.Ty
Rate
&
&
0
1
HxD.Dy
Special Out
HxNS.Sy
Control
Hx.y
Slew
Rate
Control
HV
SS
Fig. 12–4: High Current Port Pin Circuit Diagram
The H-Port pins can be configured for several basic operat-
ing modes (Table 12–4)
The function of the five registers is given in Table 12–5.
Table 12–5: Register Functions
Table 12–4: High Current Port basic Operating Modes
Register
HxD
Function
Mode
Function
r/w Data register
enable/disable output
Normal Input
The SW uses the port as digital
input.
HxTRI
HxNS
Special Input
The port input is additionally con-
nected to specific hardware mod-
ules.
select Data register or specific hardware
module as output source
HxLVL
HxPIN
select CMOS or Automotive Schmitt trigger
input level
Normal Output
Special Output
The SW uses the port as latched
digital tristateable output.
read pin state
The output signals of specific
hardware modules are directly
port output source.
The Special Input path is always operative. This allows
manipulating the input signal to the specific hardware mod-
ule through Normal Output operations by software.
See the chapter on Pinning for information about specific
hardware module connections to individual port pins for Spe-
cial Input and Special Output purposes.
Because register HxPIN allows reading the pin level also in
Special Output mode, the output state of the specific hard-
ware module may be read by the CPU.
H-Port control is distributed among five registers. All register
bits corresponding to one H-Port pin are controlled by the
same bus bit.
Two high current ports together with a coil build a H-bridge.
Two H-bridges are necessary to operate a stepper motor.
The n-channel and the p-channel transistor of the output
driver are controlled separately, to eliminate crossover cur-
rents.
After reset, all H-Ports are in Normal, Output, Low, CMOS
input level condition.
The reset output levels of the ports are low to avoid floating
coils.
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CDC 32xxG-B
12.5. High Current Port Registers
Five H-Port registers are basically available for 8 H-Ports H0
to H7, each. But the respective device’s pinning may require
a reduction in available H-Ports. See the respective pinning
table for details.
P0 to 3
r:
Pin Data 0 to 3
Read Pin state.
The general H-Port register model is given below.
HxD
High Current Port x Data Register
7
6
x
x
5
x
x
4
x
x
3
D3
0
2
D2
0
1
D1
0
0
D0
0
r/w
x
x
Res
D0 to 3
w:
r:
Data Latch
Write latch.
Read latch.
HxTRI
High Current Port x Tristate Register
7
6
x
x
5
x
x
4
x
x
3
T3
0
2
T2
0
1
T1
0
0
T0
0
r/w
x
x
Res
T0 to 3
r/w1:
r/w0:
Output Tristate Flag 0 to 3
Output driver is disabled (tristate)
Output driver is enabled
HxNS
High Current Port x Normal/Special
Register
7
6
x
x
5
x
x
4
x
x
3
S3
0
2
S2
0
1
S1
0
0
S0
0
r/w
x
x
Res
S0 to 3
r/w1:
r/w0:
Normal/Special Mode Flag 0 to 3
Special Mode. Special hardware drives pin.
Normal Mode. Data latch drives pin.
HxLVL
High Current Port x Input Level Reg-
ister
7
x
x
6
x
x
5
x
x
4
x
x
3
A3
0
2
A2
0
1
A1
0
0
A0
0
r/w
Res
A0 to 3
r/w1:
r/w0:
Automotive Flag 0 to 3
Schmitt trigger input level is Automotive
Schmitt trigger input level is CMOS
HxPIN
High Current Port x Pin Register
7
6
x
x
5
x
x
4
x
x
3
P3
0
2
P2
0
1
P1
0
0
P0
0
r
x
x
Res
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PRELIMINARY DATA SHEET
CDC 32xxG-B
13. AVDD Analog Section
The Analog Section operates from the AVDD supply pin and
comprises the PLL/ERM module, the ADC, the P06 and the
WAIT Comparators. In addition it contains support circuits
like the VREFINT Generator, the BVDD Regulator and the
necessary biasing circuits. Fig. 13–1 gives an overview.
External
Internal
VREFINT
components components
2k
AVDD
2.5V 2%
VREFINT
Generator
en
AVSS
BVDD
+
-
bvdd_err
ANAA.BVE
err
en
2.5V
+12V
WAIT
BVDD Regulator
-
+
ANAA.WAIT
WAIT COMP
Interrupt
&
&
WAITH
WAIT Comp.
en
Source
f
IO
ANAA.EP06
P06 COMP
Interrupt
Source
P06
-
+
R
R
SR0.ADC
en
en
ANAA.P06
P06 Comp.
ADC
≥1
RESETQ
VREF,
VREF0,
VREF1
SR1.CPUM
= 1, 3, 7
≥1
PLLC.PMF > 0
en
PLL/ERM
lck
pll_lock
Fig. 13–1: AVDD Section
Table 13–1: Activation of AVDD Analog Section modules
CPU Mode
VREFINT Gen.
PLL/ERM and
BVDD Regulator
ADC, P06, WAIT
RESET
on
on
off
off
FAST, PLL and PLL2 modes
SLOW and DEEP SLOW modes
on if PLLC.PMF > 0
on if SR0.ADC=1
on if PLLC.PMF > 0 or
SR0.ADC=1
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13.1. VREFINT Generator
The VREFINT Generator generates bias signals which are
necessary for the operation of all Analog-Section modules.
Furthermore, it produces a tightly controlled reference volt-
age VREFINT, that is delivered to the BVDD Regulator and
the WAIT Comparator. Via a decoupling resistor it also is
routed to the VREFINT pin.
The VREFINT-pin voltage, which has to be buffered exter-
nally by a 10-nF ceramic capacitor, is input to the ADC as
alternative, internally generated, reference voltage.
This module is permanently enabled during reset, in the CPU
modes FAST, PLL and PLL2, and whenever SR0.ADC or
PLLC.PMF is not 0. A certain set-up time has to elapse after
enabling the module for VREFINT to stabilize.
No resistive load must be connected to the VREFINT pin.
13.2. BVDD Regulator
The BVDD Regulator generates the 2.5-V BVDD supply volt-
age for the internal PLL/ERM module from the 5-V AVDD. It
derives its reference from the VREFINT Generator.
This module is permanently enabled whenever PLLC.PMF is
not 0. A certain set-up time has to elapse after enable for
BVDD to stabilize.
BVDD must be buffered externally by a 150-nF ceramic
capacitor.
An overload condition in the regulator (current or voltage
drop-out) is stored in flag ANAA.BVE. The immediate over-
load signal may be routed to the LCK special output by
selection in field ANAU.LS (UVDD Analog Section).
13.3. Wait Comparator
The level on pin WAIT is compared to the internal reference
VREFINT. The state of the comparator output is available as
flag ANAA.WAIT and as WAIT Comparator interrupt source.
assure that the necessary VREFINT set-up time has
elapsed, before using comparator results (flag and interrupt).
The interrupt source output is routed to the Interrupt Control-
ler logic. But this does not necessarily select it as input to the
Interrupt Controller. Check section “Interrupt Controller” for
the actually selectable sources and how to select them.
Furthermore, the output is available on pin WAITH, so that
the hysteresis of this comparator can be set with an external
positive-feedback resistor (100kOhms min.).
After reset, the module is off (zero standby current). The
module is enabled by setting flag SR0.ADC, together with
the P0.6 Comparator and the ADC. If the VREFINT Genera-
tor is powered up as well (cf. Table 13–1), the user has to
The WAIT Comparator interrupt source toggles with fIO, to
generate interrupts as long as the level on pin WAIT is lower
than the internal reference.
13.4. P0.6 Comparator
The level on port P0.6 is compared to AVDD/2. The compar-
ator features a small built-in hysteresis. The state of the com-
parator output is available as flag ANAA.P06 and as P0.6
Comparator interrupt source.
The P0.6 Comparator interrupt source toggles with fIO, to
generate interrupts as long as the level on pin P0.6 is lower
than the internal reference.
After reset, the module is off (zero standby current). The
module is enabled by setting flag SR0.ADC, together with
the WAIT Comparator and the ADC. If the VREFINT Genera-
tor is powered up as well (cf. Table 13–1), the user has to
assure that the necessary VREFINT set-up time has
elapsed, before using comparator results (flag and interrupt).
The interrupt source output, which must be enabled by set-
ting flag ANAA.EP06, is routed to the Interrupt Controller
logic. But this does not necessarily select it as input to the
Interrupt Controller. Check section “Interrupt Controller” for
the actually selectable sources and how to select them.
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CDC 32xxG-B
13.5. PLL/ERM
The PLL and ERM modules are operated on the internally
generated 2.5V BVDD supply voltage.
For details on operating this module please refer to section
“CPU and Clock System”.
13.6. A/D Converter (ADC)
The Analog to Digital Converter allows the conversion of an
analog voltage ranging from AVSS to either one of three
external references VREF, VREF0, VREF1 (2.5 to 5V) or the
internal reference VREFINT (~2.5V), to a 10-bit digital value.
A multiplexer connects one of 16 analog input ports to the
ADC. A sample and hold circuit holds the analog voltage dur-
ing conversion. The duration of the sampling time is pro-
grammable.
– Successive approximation, charge balance type.
– 16 channel input multiplexer.
– Input buffering for high ohmic sources selectable.
– Sample and hold circuit.
– 4/8/16/32µs conversion selectable for optimum through-
put/accuracy balance.
– 2.5V internal reference (VREFINT) or
2.5 to 5V external references (VREF, VREF0, VREF1)
selectable
Features
– 10-bit resolution.
– Zero standby current
AD0.REF
2
VREF
VREFINT
MUX
VREF0
VREF1
AVDD
P0.0
P0.1
P0.2
P0.3
P0.4
AD1.BUF
P0.5
1
A
10
2
Buf
P0.6
S&H
ADx.AN0 to AN9
0
D
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Bypass
MUX
AD0.EOC
AD0.TSAMP
en
SR0.ADC
ADC-Block
4
AVSS
AD0.CHANNEL
Fig. 13–2: ADC Block Diagram
assure that the necessary VREFINT-set-up time has
elapsed.
13.6.1. Principle of Operation
After reset, the module is off (zero standby current). The
module is enabled by setting flag SR0.ADC. The user has to
Before starting a conversion, select input-buffer usage or
bypass with flag AD1.BUF. Note that the input buffer requires
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a 1us setup time before usage. When the buffer is never
used, leave flag AD1.BUF cleared. When the buffer is always
used, leave this flag set. When toggling buffer usage, set this
flag at least 1us before starting a conversion.
has to make sure that at the end of this sampling period, the
voltage on the sampling capacitance is within ±0.1 LSB from
the source voltage.
Measurement errors may occur, when the voltage of high-
impedance sources has to be measured:
Before starting a conversion, check flag AD0.EOC to be set.
– To reduce these errors, the sampling time may be
increased by programming the field AD0.TSAMP.
A conversion is started by a write access to register AD0,
selecting sample time (AD0.TSAM), reference source
(AD0.REF) and input channel (AD0.CHANNEL).
– In cases where high-impedance sources are only rarely
sampled, a 100nF capacitor from the input to AVSS is a
sufficient measure to ensure that the voltage on the sam-
pling capacitance reaches the full source voltage, even
with the shortest sampling time.
Sampling starts one f0 clock cycle after completion of the
write access to AD0. Flag AD0.EOC signals the end of con-
version. The 10-bit result is stored in the registers AD1 (8
MSB) and AD0.
– In some high-impedance applications a charge-pumping
effect may noticeably influence the measurement result:
Charge pumping from a high-potential to a low-potential
source will occur when such two sources are measured
alternatingly. This results in a current that appears as
flowing from the high-potential source through the IC into
the low-potential source. This current explains from the
fact that during the respective sampling period the high-
potential source always charges the sampling capaci-
tance, while the low-potential source always discharges it.
Usage of the input buffer (AD1.BUF) substantially reduces
this effect.
The conversion time depends on f0 and the programmed
sample time (Table 13–2).
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
13.6.1.1. Conversion Law
The result of A/D conversion is described by the following
formula:
UIn
URef
-------------
1LSB
DV = INT
where 1LSB = -----------
1024
DV = Digital Value; INT = Integer part of the result
DV
3FF
3FE
3FD
03
02
01
00
1
2 3
1021 1023
UIn [LSB]
Fig. 13–3: Characteristic Curve
The voltage on the reference-input pins VREF, VREF0 and
VREF1 may be set to any level in the range from AVSS to
AVDD. However, accuracy is only specified in the range from
2.56V (1 LSB = 0.25mV) to 5.12V (1 LSB = 0.5mV).
13.6.1.2. Measurement Errors
The result of the conversion mirrors the voltage potential of
the sampling capacitance (typically 8pF) at the end of the
sampling time. This capacitance has to be charged by the
source through the source impedance within the sampling-
time period. To avoid measurement errors, system design
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CDC 32xxG-B
13.7. Registers
be read from register AD1. The two LSB can be read from
register AD0. The result is available until a new conversion is
started.
AD0
ADC Register 0
7
6
5
4
3
2
1
0
BUF
w1:
w0:
Input Buffer Usage
Buffer used
Buffer bypassed
r
EOC
TSAMP
x
x
x
x
TEST
AN1
AN0
w
REF
CHANNEL
TEST
for factory use only
0
0
0
0
0
0
0
0
Res
ANAA
Analog AVDD Register
AD1
ADC Register 1
7
r/w EP06
0
6
5
4
3
2
1
0
BVE
0
7
6
AN8
x
5
AN7
x
4
AN6
x
3
AN5
x
2
AN4
x
1
AN3
x
0
AN2
BUF
0
P06
WAIT
x
x
x
x
r
AN9
x
Res
w
EP06
Enable P06 Comparator Interrupt Source
Res
output
Enabled.
Disabled.
r/w1:
r/w0:
EOC
r1:
End of Conversion
End of conversion
Busy
P06
r1:
r0:
P06 Comparator Output
P0.6 is lower than AVDD/2.
P0.6 is higher than AVDD/2.
r0:
EOC is reset by a write access to the register AD0. EOC
must be true before starting the first conversion after
enabling the module by setting SR0.ADC.
WAIT
r1:
r0:
WAIT Comparator Output
WAIT is lower than VREFINT.
WAIT is higher than VREFINT.
TSAMP
Sampling Time
TSAMP adjusts the sample conversion times.
BVE
r1:
r0:
w1:
w0:
BVDD Regulator Error Flag
Out of specification.
Normal operation.
Reset flag.
Table 13–2: TSAMP Usage: Sample and Conversion
Time
No action.
TSAMP
0H
tSample
20/f0
tConversion
40/f0
1H
60/f0
80/f0
2H
140/f0
300/f0
160/f0
320/f0
3H
REF
Conversion Reference
w0:
w1:
w2:
w3:
External reference from VREF pin used
Internal reference on VREFINT pin used
External reference from VREF0 pin used
External reference from VREF1 pin used
CHANNEL Channel of Input Multiplexer
CHANNEL selects from which pin of port P0 or P1 the con-
version is done. The MSB of CHANNEL is bit 3.
Table 13–3: CHANNEL Usage: ADC Input Selection
CHANNEL
0 to 7
Port Pin
P0.0 to P0.7
P1.0 to P1.7
8 to 15
AN 9 to 0
Analog Value Bit 9 to 0
The 10-bit data format is positive integer, i.e. 000H for lowest
and 3FFH for highest possible input signal. The 8 MSB can
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14. Timers (TIMER)
Five general purpose timers are implemented. T0 is a 16 bit
timer, T1 to T4 are 8 bit timers.
14.1. Timer T0
Timer T0 is a 16bit auto reload down counter. It serves to
deliver a timing reference signal to the ICU, to output a fre-
quency signal or to produce time stamps.
Features
– 16bit auto reload counter
– Time value readable
– Interrupt source output
– Frequency output
TIM 0
w
Reload-reg.
clk
HW Option
16
TIM 0
T0
Interrupt
Source
underflow
16 bit Auto-reload
Down counter
r
T0-OUT
1/2
Fig. 14–1: Timer T0 Block Diagram
On reaching zero, the counter generates a reload signal,
which can be used to trigger an interrupt. The same signal is
connected to a divide by two scaler to generate the output
signal T0-OUT with a pulse duty factor of 50%.
14.1.1. Principle of Operation
14.1.1.1. General
The timer’s 16bit down-counter is clocked by the input clock
and counts down to zero. One clock count after reaching
zero, it generates an output pulse, reloads with the content of
the TIM0 reload register and restarts its travel.
The interrupt source output of this module is routed to the
Interrupt Controller logic. But this does not necessarily select
it as input to the Interrupt Controller. Check section “Interrupt
Controller” for the actually selectable sources and how to
select them.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
The state of the down-counter is readable by reading the
16bit register TIM0, low byte first. Upon reading the low byte,
the high byte is saved to a temporary latch, which is then
accessed during the subsequent high byte read. Thus, for
time stamp applications, read consistency between low and
high byte is guaranteed.
14.1.1.2. Operation
The clock input frequency is settable by HW option (see
Table 14–1 on page 92).
Prior to entering active mode, proper SW initialization of the
U-Ports assigned to function as T0-OUT outputs has to be
made (Table 14–1). The ports have to be configured Special
Out. Refer to “Ports” for details.
14.1.1.3. Precautions
Use 8bit load/store operations to access Timer 0 register
rather than 16bit access.
T0 is always active (no standby mode). After reset the timer
starts counting with reload value 0xFFFF generating a maxi-
mum period output signal.
A new time value is loaded by writing to the 16bit register
TIM0, high byte first. Upon writing the low byte, the reload
register is set to the new 16bit value, the counter is reset,
and immediately starts down-counting with the new value.
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Table 14–1: Module specific settings
Module
Name
HW Options
Item
Initialization
Item
Enable Bit
Address
Setting
T0
Input clock
T0C
T0-OUT output
U1.2 special out
14.1.2. Registers
TIM0L
T0 low byte
7
1
6
5
4
3
2
1
0
r
Read low byte of down-counter and latch high byte
Write low byte of reload value and reload down-counter
w
1
1
1
1
1
1
1
Res
TIM0H
T0 high byte
7
6
1
5
4
3
2
1
1
0
1
r
w
1
Latched high byte of down-counter
High byte of reload value
1
1
1
1
Res
TIM0 has to be read low byte first and written high byte first.
Table 14–2: Reload Register Programming
Reload
value
Output interrupt
source frequency is divided by
divided by
Output T0-OUT is
0x0000
0x0001
0x0002
:
1
2
2
4
3
6
:
:
0xFFFF
65536
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14.2. Timer T1 to T4
Timer T1 to T4 are 8bit auto reload down counters. They
serve to deliver timing reference signals to the ICU or to out-
put frequency signals.
Features
– 8bit auto reload counter
– Interrupt source output
– Frequency output
Table 14–3 describes implementation specific HW Option
addresses and enable flags of T1 to T4.
TIMx
w
Reload-reg.
8
0
1
clk
HW Option
0
1
Tx
Interrupt
Source
underflow
8 bit Auto-reload
Down counter
enable
1
1/2
Tx-OUT
0
Fig. 14–2: Timer T1 to T4 Block Diagram
On reaching zero, the counter generates a reload signal,
which can be used to trigger an interrupt. The same signal is
connected to a divide by two scaler to generate the output
signal Tx-OUT with a pulse duty factor of 50%.
14.2.1. Principle of Operation
14.2.1.1. General
The timer’s 8bit down-counter is clocked by the input clock
and counts down to zero. One clock count after reaching
zero, it generates an output pulse, reloads with the content of
the TIMx reload register and restarts its travel.
The interrupt source output of this module may be but must
not be connected to the interrupt controller. Please refer to
section Interrupt Controller.
Returning Tx to standby mode by resetting its respective
enable bit will halt its counter and will set its outputs LOW.
The register TIMx remains unchanged.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
The state of the down-counter is not readable.
14.2.1.2. Operation
The clock input frequencies are settable by HW options (see
Table 14–3 on page 94). After reset, the 8bit timer is in
standby (inactive).
Prior to entering active mode, proper SW initialization of the
U-Ports assigned to function as Tx-OUT outputs has to be
made (Table 14–3). The ports have to be configured Special
Out. Refer to “Ports” for details.
To initialize a timer, reload register TIMx has to be set to the
desired time value, still in standby mode.
For entering active mode, set the corresponding enable bit in
the standby registers (see Table 14–3 on page 94). The
timer will immediately start counting down from the time
value present in register TIMx.
During active mode, a new time value is loaded by simply
writing to register TIMx. Upon writing, the counter is reset,
and immediately starts counting down from the new time
value.
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Table 14–3: Module specific settings
Module
Name
HW Options
Item
Initialization
Item
Enable Bit
Address
T1C
Setting
T1
T2
T3
T4
Input clock
Input clock
Input clock
Input clock
T1-OUT output
T2-OUT output
T3-OUT output
T4-OUT output
U1.1 special out
U1.0 special out
U0.7 special out
SR0.TIM1
SR0.TIM2
SR0.TIM3
T2C
T3C
T4C
U0.6 special out, PM.U06 = 0
SR0.TIM4
14.2.2. Registers
TIMx
Timer x
7
6
0
5
4
3
2
0
1
0
0
w
Reload value
0
0
0
0
0
Res
Table 14–4: Reload Register Programming
Reload
value
Output interrupt
source frequency is divided by
divided by
Output Tn-OUT is
0x00
0x01
0x02
:
1
2
2
4
3
6
:
:
0xFF
256
512
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15. Pulse Width Modulator (PWM)
A PWM is an auto reload down-counter with fixed reload
interval. It serves to generate a frequency signal with vari-
able pulse width or, with an external low pass filter, as a digi-
tal to analog converter.
Features
– Two 8bit or one 16bit pulse width modulator
– Wide range of HW option selectable cycle frequencies
This module is combined of two independently operatable
8bit PWMs which can be combined to a single 16bit PWM.
The number of PWMs implemented is given in table 15–1.
The “x” in register names distinguishes the module number
and can be 1, 3, 5, 7, 9, 11.
PWMx-1
8
PWMx
LSB
MSB
1
0
8
S
R
Q
Q
PWMx-1
PWMx
period
clock
PxP
PxC
1
HW Option
clk load
en
clk load
en
1
0
1
0
ovf
8bit down counter
1
ovf
S
R
8bit down counter
0
1
SR1.PWMx
x = 1, 3, 5, 7, 9, 11
PWMC.P16x
Fig. 15–1: PWM Block Diagram
15.1. Principle of Operation
15.1.1. General
15.1.3. Initialization
A PWM’s down-counter is clocked by its input clock and
counts down to zero. Reaching zero, it stops and sets the
output to LOW. A period input pulse reloads the counter with
the content of the PWM register, restarts it and sets the out-
put to HIGH.
Prior to entering active mode, proper SW initialization of the
H-Ports and U-Ports assigned to function as PWMx outputs
has to be made (Table 15–1). The ports have to be config-
ured Special Out. Refer to “Ports” for details.
It has to be decided which PWM module shall work as one
16bit or as two 8bit PWMs. Selection has to be done via the
PWM control register PWMC as long as the PWM module is
disabled.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
15.1.2. Hardware settings
15.1.4. Operation
The clock and period input frequencies are settable by HW
option (Table 15–1). There is one common source for both
8bit PWMs, one for clock and one for period, thus clock and
period are not independently selectable for the two 8bit
PWMs. For full resolution a clock to period frequency ratio of
256 (65536 in 16bit mode) is recommended. Should other
ratios be used, make sure that the combination of clock,
period and pulse width setting allow the PWM to generate an
output signal with a LOW transition.
After reset, a PWM is in standby mode (inactive) and the out-
put signal PWMx is LOW.
For entering active mode, select the desired mode (8-/16bit
mode) and then set the respective enable bit (Table 15–1).
Then write the desired pulse width value to register PWMx
(write low byte first in 16bit mode). Each PWM will start pro-
ducing its output signal immediately after the next subse-
quent input pulse on its period input.
During active mode, a new pulse width value is set by simply
writing to the register PWMx. Upon the next subsequent
input pulse on its period input the PWM will start producing
an output signal with the new pulse width value, starting with
a HIGH level.
Some of the PWM outputs share pins with outputs of other
modules. The output multiplexer is controlled by HW option
(Table 15–1).
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Table 15–1: Module specific settings
Module
Name
HW Options
Initialization
Enable Bit
Item
Address
P1C, P1P
PM.H0
Item
Setting
U0.3 special out
PWM1
PWM3
PWM5
Clock and period
PWM0
PWM1
PWM2
PWM3
SR1.PWM1
SR1.PWM3
SR1.PWM5
H0.3 SMG/PWM1 output multiplexer
Clock and period
U0.2 and/or H0.3 special out
U0.1special out
P3C, P3P
PM.H0
H0.2 SMG/PWM3 output multiplexer
Clock and period
U0.0 and/or H0.2 special out
P5C, P5P
PM.H7
H7.3 SME/PWM4 output multiplexer
H0.1 SMG/PWM5 output multiplexer
Clock and period
PWM4
PWM5
H7.3 special out
H0.1 special out
PM.H0
PWM7
PWM9
PWM11
P7C, P7P
PM.H7
SR1.PWM7
SR1.PWM9
SR1.PWM11
H7.2 SME/PWM6 output multiplexer
H0.0 SMG/PWM7 output multiplexer
Clock and period
PWM6
PWM7
H7.2 special out
H0.0 special out
PM.H0
P9C, P9P
PM.H7
H7.1 SME/PWM8 output multiplexer
H7.0 SME/PWM9 output multiplexer
Clock and period
PWM8
PWM9
PWM10
PWM11
H7.1 and/or H6.3 special out
H7.0 and/or H6.2 special out
H6.1 special out
PM.H7
P11C,
P11P
H6.0 special out
Returning a PWM to standby mode by resetting its respec-
tive enable flag will immediately set its output LOW.
Due to EMI reduction the start of a period is delayed for dif-
ferent PWMs (Table 15–2).
The 8bit PWM output PWMx-1 is not usable in 16bit mode.
Table 15–2: Module Delay
The state of the down-counters and the PWM registers is not
readable.
Module Number
PWM 0, 4, 8
Delay
0
PWM 1, 5, 9
1/f0
2/f0
3/f0
PWM 2, 6, 10
PWM 3, 7, 11
15.2. Registers
PWMx
PWMx Register
PWMx-1
PWMx-1 Register
7
6
0
5
4
3
2
0
1
0
0
0
7
6
0
5
4
3
2
0
1
0
0
0
w
Pulse width value
w
Pulse width value
0
0
0
0
Res
0
0
0
0
Res
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Table 15–3: 8bit Mode Pulse Width Programming
Pulse width
value
Pulse duty factor
0x00
0x01
0x02
:
0% (Output is permanently low)
1/256
2/256
:
0xFE
0xFF
254/256
100% (Output is permanently high) 1)
1) Pulse duty factor 255/256 is not selectable.
Table 15–4: 16bit Mode Pulse Width Programming
Pulse width
value
Pulse duty factor
0x0000
0x0001
0x0002
:
0% (Output is permanently low)
1/65536
2/65536
:
0xFFFE
0xFFFF
65534/65536
100% (Output is permanently high) 1)
1) Pulse duty factor 65535/65536 is not selectable.
PWMC
PWM Control Register
7
6
x
x
5
P1611
0
4
P169
0
3
P167
0
2
P165
0
1
P163
0
0
P161
0
w
x
x
Res
P16x
w1:
w0:
PWM 16 Mode of Module x
16bit mode.
8bit mode.
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16. Pulse Frequency Modulator (PFM)
The PFM generates a signal with variable frequency and
variable pulse width. Together with external elements it may
serve to generate a negative voltage for LCD elements.
Features
– Pulse width and period separately controllable
– Pulse width and period counters operate with HW option
selectable clock
– Output polarity selectable
– Standby mode
8 Bit Reload-reg.
Pulse Width
HW Option
1
PFM0.INV
PF0C
clk
ld
1
0
1
0
1
0
zero
zero
en
8 Bit Down Counter
1
PFM0
ld
16 Bit Down Counter
16 Bit Reload-reg.
clk
Period Length
SR1.PFM0
Fig. 16–1: PFM Block Diagram
16.1. Principle of Operation
16.1.1. General
The pulse width and the period counter start synchronously
with down-counting. As long as the pulse width counter is
running, it’s zero output is LOW. When this counter reaches
zero it stops counting and sets the zero output to HIGH.
When the period counter reaches zero, it reloads both
counters, which starts a new count cycle. The zero output of
the pulse width counter can be driven out directly or inverted
via pin PFM0.
Table 16–1: Module specific settings
HW Options Initialization
Address Item Setting
PF0C PFM0
Enable Bit
Item
Input
clock
U5.0
and/or
U1.7
special
out
SR1.PFM0
The module is operable in PLL, FAST and SLOW mode. As
long as PF0C is available it is also operable in DEEP SLOW
mode. See also chapter “CPU and Clock System” for further
details.
16.1.3. Initialization
16.1.2. Hardware Settings
Prior to entering active mode, proper SW initialization of the
U-Ports assigned to function as PFM0 output has to be made
(Table 16–1). The ports have to be configured Special Out.
Refer to “Ports” for details.
The clock input frequency PF0C is settable by HW option
(see Table 16–1).
16.1.4. Operation
After reset the PFM is in standby mode (inactive) and the
output signal is LOW.
To prepare for active mode, write new values, if needed, for
the pulse width and the period length to the respective PFM0
register and select output inversion, if necessary, with flag
INV. For entering active mode set the enable bit SR1.PFM0.
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Changing the PFM0 register setting during active mode, is
simply done by writing a 32bit word to this register. After the
register has been updated, the PFM will produce an output
signal with the new pulse width and period length starting
with the next subsequent load signal of the period counter.
Returning the PFM to standby mode by clearing its Enable
Bit SR1.PFM0 will immediately set its output to INV and dis-
able the clock input. The content of the PFM0 register is not
affected by standby mode.
The state of the counters and the reload registers is not
readable.
For data consistency, when using 8bit and 16bit writes, new
values will only become valid after a write to the pulse width
register (byte 2 in the PFM0 register).
16.2. Registers
PFM0
Pulse Width and Period Register
Offs
7
6
5
4
3
2
1
0
w
w
w
w
INV
x
x
x
x
x
x
x
3
2
1
0
Pulse Width
Period Length (High Byte)
Period Length (Low Byte)
0x00
Res
INV
r/w1:
Invert Output Signal
inverted
r/w0:
direct
The pulse width counter zero output HIGH time is calculated
by
Pulse Width
tHIGH = ----------------------------
FPF0C
and the duration of the period time by
Period Length
tPeriod = ---------------------------------
FPF0C
Therefore, the pulse width counter zero output LOW time is
tLOW= tPeriod – tHIGH
Table 16–2 shows the relation of the Pulse Width and the
Period Length and its effect on the PFM0 output.
Table 16–2: Pulse Width to Period Length Relation
Pulse Width
PeriodLength INV PFM0 output
0
x
0
Always low
Always high
High pulses
Always high
Always low
Low pulses
> 0
> 0
0
≤ Pulse Width
> Pulse Width
x
1
> 0
> 0
≤ Pulse Width
> Pulse Width
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17. Capture Compare Module (CAPCOM)
The IC contains two Capture Compare Modules (CAPCOM).
– 16bit free running counter with read out.
– 16bit capture register.
– 16bit compare register.
A CAPCOM is a complex relative timer. It comprises a free
running 16bit Capture Compare Counter (CCC) and a num-
ber of Subunits (SU). The timer value can be read by SW.
– Input trigger on rising, falling or both edges.
A SU is able to capture the relative time of an external event
input and to generate an output signal when the CCC passes
a predefined timer value. Three types of interrupts enable
interaction with SW. Special functionality provides an inter-
face to the asynchronous external world.
– Output action: toggle, low or high level.
– Three different interrupt sources: overflow, input, compare
– Designed for interface to asynchronous external events
fCC1IN
HW Option
fC1C
clk
CCC1OFL
Interrupt
Source
CCC1
ofl
16
Timer Value
SR0.CCC1
2
2
CC4I
CC4M
CAP CMP OFL LAC RCR
X
X
X
MCAP MCMP MOFL FOL
OAM
IAM
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0 0
0 1
1 0
CC4-IN
&
&
&
1 1
CC4OR
Interrupt
Source
Input Action Logic
>1
3
2
LOW 0 0
0 1
1 0
1 1
TOGGLE
>1
CC4-OUT
Output Action Logic
16
CC4COMP
Interrupt
Source
A
B
reset
=
load
r
16-Bit Capture-Register
16-Bit Compare-Register
w
16
CC4
Subunit 4
Timer Value
ofl
16
CC5-IN
CC5OR
CC5COMP
Subunit 5
CC5-OUT
Fig. 17–1: CAPCOM Module 1 Block Diagram
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fCC0IN
HW Option
fC0C
clk
CCC0OFL
Interrupt
Source
CCC0
ofl
16
Timer Value
SR0.CCC0
2
2
CC0I
CC0M
CAP CMP OFL LAC RCR
X
X
X
MCAP MCMP MOFL FOL
OAM
IAM
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0 0
0 1
1 0
CC0-IN
&
&
&
1 1
CC0OR
Interrupt
Source
Input Action Logic
>1
3
2
LOW 0 0
0 1
1 0
1 1
TOGGLE
>1
CC0-OUT
Output Action Logic
16
CC0COMP
Interrupt
Source
A
B
reset
=
load
r
16-Bit Capture-Register
16-Bit Compare-Register
w
16
CC0
Subunit 0
Timer Value
ofl
16
CC1-IN
CC1OR
Subunit 1
Subunit 2
Subunit 3
CC1-OUT
CC1COMP
Timer Value
ofl
ofl
16
CC2-IN
CC2OR
CC2-OUT
CC2COMP
Timer Value
16
CC3-IN
CC3OR
CC3-OUT
CC3COMP
Fig. 17–2: CAPCOM Module 0 Block Diagram
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17.1. Principle of Operation
Table 17–1: Unit 0 specific settings
17.1.1. General
The Capture Compare Module (CAPCOM, Fig. 17–1, 17–2)
contains one common free running 16bit counter (CCC) and
a number of capture and compare subunits (SU). More
details are given in Tables 17–1 and 17–2. The timer value
can be read by SW from 16bit register CCC. The CCC pro-
vides an interrupt on overflow.
Sub- HW Options
Initialization
Address Item Setting
Enable
Bit
unit
Item
SU0
SU1
SU2
SU3
CC0-
OUT
U3.2, U4.0
special out
SR0.
CCC0
Each SU is able to capture the CCC value at a point of time
given by an external input event processed by an Input
Action Logic.
Input PM.
CC0-IN U3.2, U4.1
special in
CACO
A SU can also change an output line level via an Output
Action Logic at a point of time given by the CCC value.
CC1-
OUT
U3.1, U2.5
special out
Thus, a SU contains a 16bit capture register CCx to store the
input event CCC value, a 16bit compare register CCx to pro-
gram the Output Action CCC value, an 8bit interrupt register
CCxI and an 8bit mode register CCxM. Two types of inter-
rupts per SU enable interaction with SW.
Input PM.
CACO
CC1-IN U3.1, U2.4
special in
CC2-
OUT
U3.0, U2.3
special out
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
Input PM.
CACO
CC2-IN U3.0, U2.2
special in
Output PM.
U06
CC3-
OUT
U0.5, U0.6,
U8.1
17.1.2. Hardware Settings
special out
The CCC0 and CCC1 clock frequency must be set via HW
option (Table 17–1 and 17–2). Some SUs use several ports.
They can be selected via HW Option Port Multiplexer (PM).
Refer to “HW Options” for setting them.
CC3-IN U0.6
special in
SU0, Clock C0C
17.1.3. Initialization
SU1,
SU2,
SU3
After system reset the CCC and all SUs are in standby mode
(inactive).
In standby mode, the CCC is reset to value 0x0000. Capture
and compare registers CCx are reset. No information pro-
cessing will take place, e.g. update of interrupt flags. How-
ever, the values of registers CCxI and CCxM are only reset
by system reset, not by standby mode. Thus it is possible to
program all mode bits in standby mode and a predetermined
start-up out of standby mode is guaranteed.
Table 17–2: Unit 1 specific settings
Sub- HW Options
unit
Initialization
Enable
Bit
Item
Address Item
Setting
SU4
CC4-
OUT
U5.3, U8.0
special out
SR0.
CCC1
Prior to entering active mode, proper SW configuration of the
U-Ports assigned to function as Input Capture inputs and
Output Action outputs has to be made (Table 17–1, 17–2).
The Output Action ports have to be configured as special out
and the Input Capture ports as special in. Refer to “Ports” for
details.
Input PM.
CC4I
CC4-IN U5.3, P0.0
special in
SU5
CC5-
OUT
U7.4
special out
17.1.3.1. Subunit
CC5-IN U7.4
special in
For a proper setup the SW has to program the following SU
control bits in registers CCxI and CCxM: Interrupt Mask
(MSK), Force Output Logic (FOL, 0 recommended), Output
Action Mode (OAM), Input Action Mode (IAM), Reset Cap-
ture Register (RCR, 0 recommended), and Lock After Cap-
ture (LAC). Refer to section 17.2. for details.
SU4, Clock C1C
SU5
17.1.4. Operation of CCC
Please note that the compare register CCx is reset in
standby mode. It can only be programmed in active mode.
For entering active mode of the entire CAPCOM module set
the enable bit (Table 17–1 and 17–2).
The CCC will immediately start up-counting with the selected
clock frequency and will deliver this 16bit value to the SUs.
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The state of the counter is readable by reading the 16bit reg-
ister CCC, low byte first. Upon reading the low byte, the high
byte is saved to a temporary latch, which is then accessed
during the subsequent high byte read. Thus, for time stamp
applications, read consistency between low and high byte is
guaranteed.
overwrite the capture register, lock the Input Action logic if in
LAC mode and generate an interrupt. Make sure that SW is
prepared to handle such a situation.
For testing purposes, a permanent reset (0xFFFF) may be
forced on capture register CCx by setting bit CCxI.RCR.
Make sure that the reset is only temporary.
The CCC is free running and will overflow from time to time.
This will cause generation of an overflow interrupt event. The
interrupt (CCCxOFL) is directly fed to the Interrupt Controller
and also to all SUs where further processing takes place.
17.1.5.3. Interrupts
Each SU supplies two internal interrupt events:
1. Input Capture event and
17.1.5. Operation of Subunit
2. Comparator equal state.
In addition to the above mentioned two, the CCC Overflow
interrupt event sets flag CCxI.OFL in each SU. Thus, three
interrupt events are available in each SU. As previously
explained, interrupt events will set the corresponding flags in
register CCxI. The corresponding flags are masked with their
mask bits in register CCxM and passed to a logical or. The
result (CCxOR) is fed to the interrupt controller as a first
interrupt source. In addition, the Comparator equal (CCx-
COMP) interrupt is directly passed to the interrupt controller
as second interrupt source. Thus a SU offers four types of
interrupts: CCC overflow (maskable ored), input capture
event (maskable ored) and comparator equal state
(maskable ored and non-maskable direct).
17.1.5.1. Compare and Output Action
To activate a SUs compare logic the respective 16bit com-
pare register CCx has to be programmed, low byte first. The
compare action will be locked until the high byte write is com-
pleted. As soon as CCx setting and CCC value match, the
following actions are triggered:
– The flag CMP in the CCxI register is set.
– The CCxCOMP interrupt source is triggered.
– The CCxOR interrupt source is triggered if activated.
– The Output Action logic is triggered.
Four different reactions are selectable for the Output
Action signal: according to field CCxM.OAM (Table 17–3)
the equal state will lead to a high or low level, toggling or
inactivity on this output.
Another way to control the Output Action is bit CCxM.FOL.
E.g. rise-mode and force will set the output pin to high
level, fall-mode and force to low level. This forcing is
static, i.e. it will be permanently active and may override
compare events. Thus it is recommended to set and reset
shortly after that, i.e. to pulse the bit with SW. Toggle
mode of the Output Action logic and forcing leads to a
burst with clock-frequency and is not recommended.
All interrupt sources act independently, parallel interrupts are
possible. The interrupt flags enable SW to determine the
interrupt source and to take the appropriate action. Before
returning from the interrupt routine the corresponding inter-
rupt flag should thus be cleared by writing a 1 to the corre-
sponding bit location in register CCxI.
The interrupts generated by internal logic (CCC Overflow
and Comparator equal) will trigger in a predetermined and
known way. But as explained in 17.1.5.2. erroneous input
signals may cause some difficulties concerning the Input
Capture input as well as interrupt handling. To overcome
possible problems the Input Capture Interrupt flag CCxI.CAP
is double buffered. If a second or even more input capture
interrupt events occur before the interrupt flag is cleared (i.e.
SW was not able to keep track), the flag goes to a third state.
Two consecutive writes to this bit in register CCxI are then
necessary to clear the flag. This enables SW to detect such
a multiple interrupt situation and eventually to discard the
capture register value, which always relates to the latest
input capture event and interrupt.
17.1.5.2. Capture and Input Action
The Input Action logic operates independently of the Output
Action logic and is triggered by an external input in a way
defined by field CCxM.IAM. Following Table 17–4 it can com-
pletely ignore events, trigger on rising or falling edge or on
both edges. When triggered, the following actions take place:
– Flag CCxI.CAP is set.
– The CCxOR interrupt source is triggered if activated.
The internal CAPCOM module control logic always runs on
the clock divider chain f0 frequency, regardless of CPU clock
mode. Avoid write accesses to the CCxI register in CPU
Slow mode since the logic would interpret one CPU access
as many consecutive accesses. This may yield to unex-
pected results concerning the functionality of the interrupt
flags. The following procedure should be followed to handle
the capture interrupt flag CAP:
– The 16bit capture register CCx stores the current CCC
value, i.e. the “time” of the external event. Read CCx low
byte first. Further capture and input action will be locked
until the subsequent high byte read is completed. Thus a
coherent result is ensured, no matter how much time has
elapsed between the two reads.
Some applications suffer from fast input bursts and a lot of
capture events and interrupts in consequence. If the SW
cannot handle such a rate of interrupts, this could evoke
stack overflow and system crash. To prevent such fatal situ-
ations the Lock After Capture (LAC) mode is implemented. If
bit CCxI.LAC is set, only one capture event will pass. After
this event has triggered a capture, the Input Action logic will
lock until it is unlocked again by writing an arbitrary value to
register CCxM. Make sure that this write only restores the
desired setting of this register.
1. SW responds to a CAPCOM interrupt, switching to CPU
Fast or PLL mode if necessary and determining that the
source is a capture interrupt (CAP flag =1).
2. The interrupt service routine is processed.
3. Just before returning to main program, the service routine
acknowledges the interrupt by writing a 1 to flag CAP.
4. The service routine reads CAP again. If it is reset, the rou-
tine can return to main program as usual. If it is still set an
external capture event overrun has happened. Appropriate
actions may be taken (i.e. discarding the capture register
value etc.).
Programming the Input Action logic while an input transition
occurs may result in an unexpected triggering. This may
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CDC 32xxG-B
5. go to 3.
17.1.7. Precautions
The CCxI register must not be written in CPU Slow mode
(see Section 17.1.5.3. on page 104). Read-Modify-Write
operations on single flags of register CCxI must be avoided.
Unwanted clearing of other flags of this register may be the
result otherwise.
17.1.6. Inactivation
The CAPCOM module is inactivated and returned to standby
mode (power down mode) by setting the enable bit to 0. Sec-
tion 17.1.3. applies.
CCxI and CCxM are only reset by system reset, not by
standby mode.
17.2. Registers
The CAPCOM counter and the Capture/Compare registers
have to be read/written low byte first to avoid inconsisten-
cies. The memory controller accesses multiple byte quanti-
ties low byte first. Thus the 16 bit CAPCOM counter and the
16 bit Capture/Compare registers can be accessed 16 bit
wide.
OAM
r/w:
Output Action Mode
Defines behavior of Output Action logic.
Table 17–3: OAM usage
Bit
3 2
Output Action Logic Modes
CCCyL
CAPCOM Counter low byte
0 0
0 1
1 0
1 1
Disabled, ignore trigger, output low level.
Toggle output.
7
6
0
5
4
3
2
1
0
0
r
Read low byte and lock CCC
Output low level.
0
0
0
0
0
0
Res
Res
Res
Output high level.
CCCyH
CAPCOM Counter high byte
IAM
r/w:
Input Action Mode
Defines behavior of Input Action logic.
7
6
0
5
4
3
2
1
0
0
r
Read high byte and unlock CCC
Table 17–4: IAM usage
0
0
0
0
0
0
Bit
1 0
Input Action Logic Modes
CCxM
CAPCOM x Mode Register
0 0
0 1
1 0
1 1
Disabled, don’t trigger.
7
6
5
4
FOL
0
3
2
1
0
0
Trigger on rising edge.
r/w MCAP MCMP MOFL
OAM
IAM
Trigger on falling edge.
0
0
0
0
0
0
Trigger on rising and falling edge.
MCAP
r/w1:
Mask CAP Flag
Enable.
r/w0:
Disable.
CCxI
CAPCOM x Interrupt Register
MCMP
r/w1:
r/w0:
Mask CMP Flag
Enable.
Disable.
7
6
CMP
0
5
OFL
0
4
LAC
0
3
RCR
0
2
x
0
1
0
x
0
r/w
CAP
x
MOVL
r/w1:
Mask OVL Flag
Enable.
0
0
Res
r/w0:
Disable.
CAP
r1:
r0:
w1:
w0:
Capture Event
Event.
No Event.
Clear flag.
No change.
FOL
r/w1:
r/w0:
Force Output Action Logic
Force Output Action logic.
Release Output Action logic.
This flag is static. As long as FOL is true neither comparator
can trigger nor SW can force, by writing another “one”, the
Output Action logic. After forcing it is recommended to clear
FOL unless Output Action logic should not be locked.
CMP
r1:
Compare Event
Event.
r0:
No Event.
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w1:
w0:
Clear flag.
No change.
OFL
r1:
r0:
Overflow Event
Event.
No Event.
w1:
w0:
Clear flag.
No change.
LAC
r/w1:
r/w0:
Lock After Capture
Enable.
Disable.
Refer to section 7.1.5.2
RCR
Reset Capture Register
r/w1:
Reset capture register permanently to
0xFFFF.
r/w0:
Release capture register.
CCxL
CAPCOM x Capture/Compare Regis-
ter low byte
7
6
5
4
3
2
1
0
r
Read low byte of capture register and lock it.
Write low byte of compare register and lock it.
w
1
1
1
1
1
1
1
1
Res
CCxH
CAPCOM x Capture/Compare Regis-
ter high byte
7
6
5
4
3
2
1
0
r
w
1
Read high byte of capture register and unlock it.
Write high byte of compare register and unlock it.
1
1
1
1
1
1
1
Res
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CDC 32xxG-B
18. Stepper Motor Module VDO (SMV)
The SMV module serves to control air cored movements or
stepper motors that are directly coupled in H-bridge forma-
tion to H-Ports. Upon CPU programming it creates all wave-
forms necessary to position the drive pointer as desired. In
addition it supports the Rotor Zero Position Detection by sup-
plying motor blockage information.
Features
– Multi channel pulse width modulated output
– Outputs offset for improved EMC properties
– Four quadrant operation
– 8bit resolution
The Rotor Zero Position Detection capability is protected by
a patent from Mannesmann VDO and may only be used with
VDO’s prior approval.
– Analog voltage sampling for Rotor Zero Position Detection
support
– HW Option selectable output cycle frequency
The number of motors that are controllable by subunits (con-
trol units) of the module is given in Table 18–1.
18.1. Principle of Operation
display angle of a pointer that is driven by the motor via a
mechanical transmission.
18.1.1. General
An 8bit, free-running counter FRC (Fig. 18–1) operates on
the fSM input clock (generally 4MHz) and creates an 8bit
counter word that is fed to a number of control units SMx.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
A control unit (Fig. 18–1) contains 8bit sine and cosine com-
pare registers. One comparator each is associated with
these registers and creates a compare signal when register
content and FRC word are equal. An output flip-flop associ-
ated with each comparator is set when the FRC word is zero
and reset by the respective compare signal. A delay stage
associated with each control unit delays the flip-flop output
signals by a fixed number of fSM cycles to achieve non-syn-
chronism between the output signals of the various control
units, thus achieving an improved EMC behavior of the SMV
(cf. Fig. 18–3). According to the setting of a quadrant register
associated with each control unit, each of a unit’s two output
signals is multiplexed to signals SMxn+ and SMxn- so as to
properly control 2 individual H-Ports that form an H-bridge
together with the connected motor coil. By these means, a
control unit supplies two H-bridges with signals SMx1+,
SMx1-, SMx2+ and SMx2- to function as variable pulse width
modulator outputs with selectable polarity.
18.1.2. Hardware settings
Prior to entering active mode, the fSM input clock has to be
set by HW Option (see Table 18–1 on page 108). A fre-
quency value of 4MHz is recommended resulting in a pulse
width modulator cycle frequency of 4MHz/256.
Some H-Ports may receive the output signals either of the
SMV module or of PWM modules as an alternative. Refer to
Table 18–1 for the necessary settings.
Refer to section “HW Options” for details.
18.1.3. Initialization
Prior to entering active mode, proper SW initialization of the
H-Ports assigned to function as H-bridge outputs SMxn+ and
SMxn- has to be made (Table 18–1). The H-Ports have to be
configured Special Out. Refer to “Ports” for details.
Summing up: when the compare registers are set to the sine
and cosine value of a desired rotor angle and the quadrant
register is set to the desired quadrant, an air cored move-
ment or a stepper motor connected to the unit’s 4 H-Ports
will carry the proper average coil currents of proper polarity
so that its rotor will assume the desired rotary angle.
18.1.4. Operation
After reset, the SMV is in standby mode (inactive). The out-
put lines to the H-Ports are low.
Three registers control readjustment of a rotor to a new
angle. Sine, cosine and unit/quadrant registers serve as tem-
porary storage of new sine, cosine, related quadrant and unit
selection values. A scheduler logic times the synchronous
downloading of the three buffered words to the respective
unit’s sine, cosine and quadrant registers, so as to avoid
inconsistencies among them. A Busy bit may be read out sig-
naling completion of the downloading.
For entering active mode, set bit SR0.SM. The FRC will
immediately start counting but the control units’ output lines
will still be low.
18.1.4.1. Generating Output
After entering active mode, the SMV’s control units are ready
to receive sine, cosine and quadrant values.
Each control unit contains circuitry to detect an induced volt-
age resulting from the rotation of the connected motor’s rotor
(Fig. 18–2). A comparator compares the input voltage from
one of the unit’s H-Ports to 1/9th of the supply voltage. A
capture logic opens a capture window and samples the com-
parator output. The capture result signal supplies a rotor
blockage information necessary for the Rotor Zero Position
Detection in all cases where the CPU has lost track of the
First load the unit/quadrant information to register SMVC,
then the cosine value to register SMVCOS and last the sine
value to register SMVSIN. Upon writing SMVSIN, the sched-
uler logic will set flag SMVSIN.BUSY and load the buffered
values to the respective unit’s sine, cosine and quadrant reg-
isters on the next zero transition of the FRC, after a maxi-
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PRELIMINARY DATA SHEET
Table 18–1: Unit specific settings
Contr.
Unit
HW Options
Item
Initialization
Address Item
Enable Bit
Setting
SMA
SMB
SMC
SMD
SME
SMF
SMG
All
SMAn+/- outputs
SMA-COMP input
SMBn+/- outputs
SMB-COMP input
SMCn+/- outputs
SMC-COMP input
SMDn+/- outputs
SMD-COMP input
SMEn+/- outputs
SME-COMP input
SMFn+/- outputs
SMF-COMP input
SMGn+/- outputs
SMG-COMP input
H4.0 to H4.3 special out
H4.0 special in
SR0.SM
H3.0 to H3.3 special out
H3.0 special in
H2.0 to H2.3 special out
H2.0 special in
H5.0 to H5.3 special out
H5.0 special in
SME/PWM selection
PM.H7
H7.0 to H7.3 special out
H7.0 special in
H1.0 to H1.3 special out
H1.0 special in
SMG/PWM selection
Input clock selection
PM.H0
SM
H0.0 to H0.3 special out
H0.0 special in
mum of 256 fSM input clock cycles. After completing the
download, flag BUSY is reset and the respective unit will
immediately start producing the output signals with the
desired timing (see Table 18–4) on the proper pins (see
Table 18–3).
Parallel Rotor Zero Position Detection on all control units is
permitted.
After completion of Rotor Zero Position Detection, reconfig-
ure the comparator input port as Special Out.
The above procedure for loading values to a first unit is
repeated for all others. Make sure that the BUSY flag is 0
before rewriting registers SMVC, SMVCOS and SMVSIN.
18.1.5. Inactivation
Returning the SMV module to standby mode by resetting bit
SR0.SM will immediately halt the FRC, return all output sig-
nals to 0, reset all internal registers and disconnect the com-
parators from supply.
18.1.4.2. Rotor Zero Position Detection
During Rotor Zero Position Detection one of a unit’s H-Ports
(Table 18–1) has temporarily to be operated as input to an
internal analog comparator. Reconfigure this port as Special
Input. Refer to “Ports” for details.
Reading of the induced voltage at the measured motor wind-
ing is started by setting the questioned unit’s control bit
SMVCMP.ACRx to 1. The respective analog comparator’s
output will now be sampled. Once three consecutive “1”
samples (spaced 1/fCPU) - indicating a sufficient analog com-
parator input voltage - are received, a 1 may be read from
the questioned unit’s result flag SMVCMP.ACRx, indicating
that the Rotor Zero Position Detection is under way.
Resetting the questioned unit’s control bit SMVCMP.ACRx to
0 stops the sampling and resets the result flag. When after a
restart of the above sampling procedure and after a suffi-
ciently long capture period still no 1 was read from the ques-
tioned unit’s result flag SMVCMP.ACRx, this indicates that
Rotor Zero Position Detection is complete.
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CDC 32xxG-B
SMVC
w
x x
SEL
x QUAD
SR0.SM
3
fSM
fSM /256
Busy
Load
Scheduler
7
fCLK
ftrig
OVFL
8bit FRC
S
S
Comparator sin A “=”
R
DELAY
0 / fSM
SMA1+
SMA1-
SMA2+
SMA2-
Q
Q
sin
sin A comp. latch
(reload register)
Quadrant
Load A
R
register
and
decoder
Comparator cos A “=”
DELAY
0 / fSM
cos
cos A comp. latch
(reload register)
SMA
SMB
SMC
SMD
SMB1+
SMB1-
SMB2+
SMB2-
DELAY
1 / fSM
sin B / cos B
sin C / cos C
sin D / cos D
SMC1+
SMC1-
SMC2+
SMC2-
DELAY
2 / fSM
SMD1+
SMD1-
SMD2+
SMD2-
DELAY
3 / fSM
HW Option
PWM4
SME1+
SME1-
SME2+
SME2-
PWM6
PWM8
PWM9
DELAY
4 / fSM
sin E / cos E
SME
SMF
SMG
SMF1+
SMF1-
SMF2+
SMF2-
DELAY
5 / fSM
sin F / cos F
HW Option
SMG1+
SMG1-
SMG2+
SMG2-
PWM1
PWM3
PWM5
PWM7
DELAY
6 / fSM
sin G / cos G
Fig. 18–1: Block Diagram of Output Generation Circuit
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PRELIMINARY DATA SHEET
f
SM
0
SMA
R
Debouncer and
measurement
window
SMA-COMP
+
−
S
Result
latch
4
1
5
2
6
3
SMB-COMP
SMC-COMP
SMD-COMP
+
SMB
SMC
SMD
SME
SMF
SMG
−
+
−
+
−
SME-COMP
SMF-COMP
+
−
+
−
SMG-COMP
+
−
SR0.SM
8R
R
HV
DD0
r/w
x
F D B G E C A
SMVCMP
6
5 4 3 2 1 0
HV
HV
HV
DD1
DD2
DD3
Fig. 18–2: Block Diagram of Rotor Zero Position Detection Circuit
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CDC 32xxG-B
18.2. Registers
SMVCOS
Stepper Motor VDO, Cosine Register
SMVC
Stepper Motor VDO, Control Register
7
6
0
5
4
3
2
1
0
7
6
x
x
5
4
SEL
0
3
2
x
x
1
0
w
8bit Cosine Value
w
x
QUAD
0
0
0
0
0
0
0
Res
x
0
0
0
0
Res
BUSY
r0:
r1:
Scheduler Busy Flag
Scheduler not busy
Scheduler busy, do not write registers
SMVC, SMVCOS, SMVSIN
SEL
Control unit Selection field (Table 18–2)
Quadrant selection field (Table 18–3)
QUAD
Table 18–2: SEL usage
Table 18–4: Usage of SMVSIN and SMVCOS registers
SEL
000
001
010
011
100
101
110
111
selected control unit
Value
Duty factor
Pulse Diagram
SMA
00h
0/256 (continu-
ously low)
SMB
SMC
01h
02h
:
1/256
2/256
:
SMD
SME
SMF
FEh
FFh
254/256
255/256 1)
SMG
Not permitted
1) 256/256 (continuously high) is not available.
Table 18–3: QUAD setting and resulting control unit output
signal function
SMVCMP
Stepper Motor VDO, Comparator Reg-
ister
7
6
5
4
3
2
1
0
QUAD Control unit output signal function
r/w
x
ACRF ACRD ACRB ACRG ACRE ACRC ACRA
SMx1+
sine
SMx1-
VSS
VSS
sine
SMx2+
cosine
VSS
SMx2-
VSS
x
0
0
0
0
0
0
0
Res
00
01
10
11
ACRA to G Analog Comparator Control and Result
for SMA to SMG
sine
cosine
cosine
VSS
r0:
r1:
w0:
w1:
Capture result: no induced voltage detected
Capture result: induced voltage detected
Stop capture and clear result flag
Start capture
VSS
VSS
VSS
sine
cosine
SMVSIN
Stepper Motor VDO, Sine Register
7
6
5
4
3
2
1
0
r
x
x
x
x
x
x
x
BUSY
w
8bit Sine Value
0
0
0
0
0
0
0
0
Res
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CDC 32xxG-B
PRELIMINARY DATA SHEET
18.3. Timing
1/ftrig
ftrig =fSM /28
SMA1+
SMA1−
SMA2+
SMA2−
Example:
SMA in
1st quadrant
tdA = 0/ fSM
SMB1+
SMB1−
SMB2+
SMB2−
Example:
SMB in
4th quadrant
tdB = 1/ fSM
Fig. 18–3: Timing Diagram of Output Signals
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CDC 32xxG-B
19. LCD Module
The Liquid Crystal Display (LCD) Module is designed to
directly drive a 1:4 multiplexed liquid crystal display. It gener-
ates all signals necessary to drive 4 backplane and 48 seg-
ment lines which are output via U-Ports in LCD mode. Up to
192 segments or pixels can be controlled if all U-Ports are
designated as segment outputs.
Features
– 1:4 multiplex
– 5V supply
– Maximum of 192 segments
– Cascadable with external expansion ICs
– 0.3mA buffered 1/3 and 2/3 voltage divider
– Zero standby current
In addition, the module provides functions that enable the
user to cascade it with external expansion ICs providing
more segment lines. It can be operated as master or slave in
such an extended system.
– 200µA no load active current
– Frame frequency HW Option selectable
19.1. Principle of Operation
19.1.1. General
19.1.2. Hardware settings
Each LCD pixel or segment which is controlled by the LCD
module is located at the crossing point of a segment line and
a backplane line. The LCD module co-ordinates the output
sequences of backplane and segment lines (see Fig. 19–3
on page 115).
The LCD frame frequency is settable by HW option LC. The
resulting frame frequency is the selected input frequency,
divided by 120. It should be in the range from 50 to 200Hz.
For best electromagnetic interference results it is recom-
mended to operate all segment and backplane U-Ports in
Port Slow mode. Refer to “Ports” for more details and to
“HW-Options” for setting the corresponding HW options. Set
flag PSLW in register SR0 to HIGH to enable Port Slow
mode.
BP3
BP2
BP1
BP0
SEGn-1
SEGn
19.1.3. Initialization
After reset, the LCD module is in standby mode (inactive)
and all U-Ports are in Port mode, non-conducting.
SEGn+1
All U-Ports designated to function as backplane or segment
outputs are to be set to LCD mode. Refer to “Ports” for more
details. This will set these U-Ports to output LOW state.
Fig. 19–1: Segments and Backplanes
After reset the content of the segment registers is undefined.
It must be set by writing the desired segment information to
the segment registers and by validating it by a write access
to register ULCDLD (write 0x00 for master mode, 0xFF for
slave mode), before the LCD module is enabled.
A segment pin can drive 4 different voltage levels (UVSS, 1/3
UVDD, 2/3 UVDD, UVDD) in LCD mode. The output of each
segment pin is controlled by the corresponding segment bits
of the registers UxD, UxTRI, UxNS and UxDPM (further
called segment registers). Each such register contains one
bit (of a 4 bit segment field) for each of its port pins. Each
segment bit (0 to 3) of a segment field corresponds to a
backplane line (BP0 to BP3). If the segment bit, correspond-
ing with the backplane line BPx is true, then the segment at
the crossing of the two lines is on (black).
19.1.4. Operation
For entering active mode, set flag LCD in register SR0. Each
segment and backplane U-Port will immediately start produc-
ing its LCD output signal according to the segment informa-
tion provided during initialization.
The LCD module does not contain a display ROM translating
character information into segment code. The advantage is
that arbitrary characters or displays can be generated just by
changing the program code. Segment information is directly
entered by writing to the corresponding segment bit. It is val-
idated (loaded to all corresponding slave registers) for all
segment U-Ports simultaneously by a write access to regis-
ter ULCDLD.
During active mode, a new segment information is entered
by simply writing the desired segment information to the seg-
ment registers and by validating it by a write access to regis-
ter ULCDLD (write 0x00 while in master mode, 0xFF while in
slave mode). Each segment and backplane U-Port will
immediately start producing an LCD output signal according
to the new segment information.
Two internal voltage sources provide the U-Port circuits and
the backplane generator with the voltage levels 1/3 UVDD
and 2/3 UVDD. These levels are generated by a buffered
resistor divider.
Returning the LCD module to standby mode by resetting flag
LCD in register SR0 will immediately return all segment and
backplane U-Ports to the output LOW state.
Micronas
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CDC 32xxG-B
PRELIMINARY DATA SHEET
ULCDLD.LCDSLV
SR0.LCD
HW Option
8 x frame frequency
3
HW Option
1/1
0
1
1/1.5
1/2.5
f
CLK
1/15
1
LCD-CLK-IN
UV
DD
2
8 State
Counter
LCD-CLK-OUT
/ UV
overflow
reset
3
DD
1
/ UV
0
1
3
DD
wr ULCDLD
load
UV
LCD-SYNC-IN
SS
LCD-SYNC-OUT
U0MODE.L0
U0D.SG0_0
U0TRI.SG0_1
U0NS.SG0_2
U0DPM.SG0_3
Analog Switch
and
Segment Driver
U0.0
1
U0MODE.L1
U0D.SG1_0
U0TRI.SG1_1
U0NS.SG1_2
U0DPM.SG1_3
Analog Switch
and
Segment Driver
U0.1
1
U8MODE.L5
U8D.SG5_0
U8TRI.SG5_1
U8NS.SG5_2
U8DPM.SG5_3
Analog Switch
and
Segment Driver
U8.5
1
U4MODE.L0
1
Analog Switch
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Backplane
Generator
and
U4.0
1
0
1
2
3
Backplane Driver
Analog Switch
and
Backplane Driver
UV
U4.1
1
DD
en
SR0.LCD
Analog Switch
and
Backplane Driver
U4.2
1
-
2
/ UV
3
DD
DD
+
Analog Switch
and
Backplane Driver
-
+
1
/ UV
3
U4.3
1
LCD Supply
Fig. 19–2: Block Diagram
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
For master mode, set flag LCDSLV in register ULCDLD
LOW. The module always directs signal LCD-SYNC-OUT to
pins U8.5 and LCD-CLK-OUT to pins U8.3. They connect to
external slave ICs’ SYNC-IN and CLK-IN inputs for synchro-
nization.
19.1.5. Cascading of LCD Driver Modules
For slave mode, set flag LCDSLV in register ULCDLD HIGH.
Configure pins U8.4 and U8.2 to receive signals LCD-SYNC-
IN and LCD-CLK-IN from an external master IC’s SYNC-
OUT and CLK-OUT outputs. These signals will then substi-
tute the LCD module’s own HW option frame frequency set-
tings.
For expansion purposes, the LCD module may be cascaded
with external LCD driver ICs. Master or slave mode is select-
able for the LCD module while in standby. Special signals
provide phase and frequency synchronism for the LCD frame
among the cascaded ICs.
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CDC 32xxG-B
Starting up and shutting down such an expanded system is
described in section 19.3.
1 Frame
Segment off
Segment on
V
DD
2/3
1/3
0
BP0
BP1
BP2
BP3
Pin
Segment Data Latches
U0D.SG0_0 = 0
U0TRI.SG0_1 = 0
U0NS.SG0_2 = 0
U0DPM.SG0_3 = 0
SEG0.0
U0D.SG1_0 = 0
U0TRI.SG1_1 = 0
U0NS.SG1_2 = 0
U0DPM.SG1_3 = 1
SEG0.1
SEG0.2
SEG0.3
SEG0.4
U0D.SG2_0 = 0
U0TRI.SG2_1 = 1
U0NS.SG2_2 = 1
U0DPM.SG2_3 = 0
U0D.SG3_0 = 0
U0TRI.SG3_1 = 1
U0NS.SG3_2 = 0
U0DPM.SG3_3 = 1
U0D.SG4_0 = 1
U0TRI.SG4_1 = 1
U0NS.SG4_2 = 1
U0DPM.SG4_3 = 1
Fig. 19–3: Frame Timing Diagram
A segment at a crossing of backplane and segment lines is
turned black when at the same time the backplane driver out-
puts a full swing and the segment driver outputs a full swing
of opposite polarity.
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19.2. Registers
Please refer to section “Universal Port Registers” for details
on segment register layout.
A write access to this memory location simultaneously loads
all segment information of all U-Ports in LCD mode to the
display.
19.2.1. Special Register Layout of U-Port 4
ULCDLD
Universal Port LCD Load Register
7
6
x
5
4
3
2
1
0
x
0
U4.0 to U4.3 provide backplane signals in LCD Mode. To
operate any ports as LCD segment driver it is necessary to
switch all these ports to LCD mode. This has to be done by
setting flags U4MODE.L0 through U4MODE.L3.
w
LCDSLV
x
x
x
x
x
0
0
0
0
0
0
0
Res
As backplane ports U4.0 to U4.3 require no segment data
setting, SG0_0 through SG3_3 bits are not available in U4
registers.
LCDSLV LCD Module is Slave
Select the mode of the LCD module.
w1:
w0:
LCD module is slave.
LCD module is master.
19.3. Application Hints for Cascading LCD Modules
lag between write accesses to ULCDLD of the master and of
the slave is kept as small as possible. Suggestion: Lower ms
range or customer specification.
19.3.1. Power On and Start Up Procedure
1. The SW in master and slave configures the corresponding
IC.
Table 19–1: Suggested sequence
19.3.3. Power Off Procedure
1. (Optional) The processor which decides that the display is
to be switched off signals this to the other via IPI.
Master
Slave
2. The slave continuously scans the inputs LCD-CLK-IN and
LCD-SYNC-IN for the bit combination “11” (SW debouncing
required).
Load LCD display register.
Clear flag LCDSLV.
Load LCD display register.
Set flag LCDSLV.
3. The master LCD module is switched off. LCD-CLK-OUT
and LCD-SYNC-OUT switch to “11”.
LCD-CLK-OUT, and
LCD-SYNC-OUT:
Configure universal ports
LCD-CLK-IN, and
LCD-SYNC-IN:
Configure universal ports
4. The slave CPU detects the bit combination “11” and imme-
diately switches off the slave LCD module.
as Special Out Ports.
as Special In Ports.
Note: Keep time delay as short as when switching on.
5. All LCD ports output a low signal now. The LCD display is
now inactive.
2. Optionally the slave signals to the master via handshake
link or an inter processor interface (IPI) that it is ready to dis-
play.
3. The slave continuously scans the inputs LCD-CLK-IN and
LCD-SYNC-IN for the bit combination “01” (SW debouncing
required).
4. The master LCD module is switched on. LCD-CLK-OUT
and LCD-SYNC-OUT switch to “01”.
5. The slave CPU detects the bit combination “01” and
immediately switches on the slave LCD module. The slave
LCD now generates a display.
Note: During the time that the slave needs to detect the bit
combination “01”, master and slave operate asynchronously.
Suggestion: limit time to approximately 100 to 200ms.
6. The LCD modules now operate in controlled synchroniza-
tion.
19.3.2. Operation
In order to obtain optimum synchronization of LCD switch-
over, a change of display must be coordinated between mas-
ter and slave (preferably via IPI) in such a way, that the time
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PRELIMINARY DATA SHEET
CDC 32xxG-B
20. DMA Controller
The DMA controller allows transferring data fields between
internal memory and either an external IC via U-Ports (G-
Bus), or an SPI module, with minimum CPU interaction.
tion, to construct long serial data transfer sequences. It frees
the CPU of repeatedly reloading data, e.g. under interrupt
control.
DMA transfers can be triggered by the interrupt source out-
put of the corresponding module (self timed), a dedicated
DMA Timer output or a port interrupt.
Features
– 3 DMA channels:
The G-Bus is intended to support the operation of external
LCD driver ICs (e.g. SED1560 by Epson):
direct 8bit data read or write between memory and U-
Ports U5 and U7 (G-Bus),
The DMA module copies 8bit pixel data bytes by direct mem-
ory access (DMA) to the external IC’s graphic RAM with help
of that IC’s internal autoincrement address counter, and with-
out CPU interaction. Other off-chip registers, allowing control
of the display behavior (blinking, scrolling, etc.), have to be
addressed by CPU operations.
direct 8bit data read or write between memory and SPI0,
direct 8bit data read or write between memory and SPI1
– 256 byte maximum DMA block size
– one byte DMA block alignment
– CPU cycle steal
In SPI mode, the DMA module copies data bytes by direct
memory access (DMA) to the SPIxD data register, self timed
or under timing of the DMA timer and without CPU interac-
– Interrupt on DMA sequence finished
20.1. Functions
The DMA Controller contains one DMA channel logic for
each DMA channel, the priority encoder, the control logic,
the DMA vector base register, address and cycle count
buffer, and the bus interface (see Fig. 20–2 on page 118).
CPU
ICU
The DMA vector base register points to the beginning of the
DMA table which is filled with a DMA vector for each DMA
channel. Location zero contains the default vector and is not
assigned to any DMA channel. Each DMA vector is com-
posed of a 24 bit source/destination address and a 8 bit
cycle counter value (see Fig. 20–5 on page 119).
3
A DMA cycle is divided in a sequence of three steps:
Bus
DMA
Controller
Controller
1. Output Address of the DMA vector and read source/desti-
nation address and cycle counter.
2. Output Address of the DMA vector and write back incre-
mented source/destination address and decremented cycle
counter.
3
4
3. Output source/destination address and write/read data to/
from I/O module.
SRAM
I/O-Module
Each step is one bus access which holds the CPU (cycle
stealing). The DMA Controller generates the necessary con-
trol signals for above bus accesses.
An I/O module requests a DMA cycle via its interrupt source
output which is connected to the DMA request input (DREQ)
of the corresponding DMA channel logic. The DMA interrupt
output (DINT) is connected to the ICU instead where it indi-
cates the end of a DMA sequence (see Fig. 20–3 on
page 119). The signal DINT is connected to the G-Bus logic
too, where it sets a flag indicating the end of the DMA
sequence (see Fig. 20–4 on page 119).
ROM
Flash
Fig. 20–1: System Block Diagram
The DMA Controller transfers bytes (8 bit) between I/O mod-
ules and memory. One transfer is called a DMA cycle. The
transfer of a block of bytes is called a DMA sequence.
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CDC 32xxG-B
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BYPx
DINTx
to ICU
DREQx
fDMA
pending
S Q
R
HW Opt.
DMATx
1
src#
&
Mux
PINT0
PINT1
&
2
DMA
Channel
Logic
3 Priority
Encoder
n
enable
TRIGx
31
ENx
D Q
R
DACKx
Once per DMA channel
fSYS
&
DWAIT
DMA
Control
Logic
A<23:0>
D<31:0>
MAS<0>
MAS<1>
nRW
Memory
Controller
LOCK
DACC
DACK
D<31:0>
DMA Vec. Base
Fig. 20–2: DMA Controller
The DMA channel logic contains an input multiplexer which
selects one of four possible DMA request sources (see
Table 20–2 on page 120). The output of this multiplexer sets
a pending flag which is automatically reset when the DMA
cycle is finished. An enable flag (EN) masks the pending flag
output to the priority encoder. A bypass flag (BYP) allows to
redirect DREQ to DINT and thus generate no DMA request
but an interrupt.
There are two fundamentally different modes to operate
DMA sequences.
– Self timed describes the situation where the correspond-
ing I/O module requests a DMA transfer when it’s ready.
In this case the I/O module starts the DMA module when
there is something to transfer and the DMA controller
starts the I/O module after the transfer is finished. This is
the fastest possible way to transfer information via DMA.
Trying to get it faster enforces the danger that one of the
communication partners is not ready.
The priority encoder assigns each DMA channel a fixed
unique priority (Table 20–1). This is necessary when more
than one DMA channel signals a DMA request at the same
time. The priority encoder outputs the source number with
the highest priority.
– External triggered describes the situation where a third
party requests a DMA transfer. This can be a DMA timer
or a port interrupt. The SW design has to guarantee that
the I/O module as well as DMA controller can do their
work between two consecutive DMA requests.
The control logic controls the above described three steps of
bus accesses and generates the DMA acknowledge signal
(DACKx) which indicates to the requesting module that the
DMA transfer has finished.
Table 20–1: DMA Channels
Priority
I/O-Module
Default
U-Port
Register Name
0
1
2
3
GD
SPI 0
SPI0D
SPI1D
SPI 1
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CDC 32xxG-B
SPI0
DMA
ICU
32 Bit
00C
008
004
000
DMA Vector 3
DMA Vector 2
DMA Vector 1
Default
Int Src
DREQx
DACKx
DMA Vector Base +
DMA Channel * 4
start SPI0
DINTx
SPIx
DMA Vector Base
rd
≥1
rd SPI0D
wr SPI0D
&
&
8-bit count
24-bit DMA Block Addr.
nRW
7
Data
Data
Data
Data
Data
Data
Data
Data
6
5
4
3
2
1
0
Fig. 20–3: DMA SPI Interaction
GBus
DMA
ICU
DREQ1
DACK1
DINT1
DREQ1
DACK1
Fig. 20–5: DMA Vector Table
DINT1
GBus
rd
≥1
&
&
rd GD
wr GD
nRW
Fig. 20–4: DMA Port Interaction
20.2. Registers
The DMA registers can be read or written 32-bit wide, asyn-
chronous and without wait states.
DE
r/w1:
r/w0:
DMA Enable
enable DMA controller
disable DMA controller
Enables the DMA controller clock (fSYS) and the clock for all
DMA Timer (fDMA).Before setting to 0, make sure that all
individual DMA channels are terminated.
DVB
DMA Vector Base
Offs
7
6
5
4
3
2
1
0
SRC
r31-0:
Priority source output
The number of the highest pending and
enabled DMA request.
r/w
r/w
r/w
r/w
0
0
0
0
0
0
0
0
3
2
1
0
A23 to A16
A15 to A8
DCxM
DMA Channel x Mode Register
A7
0
0
0
0
0
0
0
Offs
7
6
5
DMAT
x
4
3
2
1
0
0x0000
Res
r/w
r/w
P
TRIG
1
0
EN
x
x
BYP
DIR
MAS
DST
DMA Status Register
0x0000
Res
Offs
7
6
5
4
3
2
1
0
P
r1:
r0:
DMA Pending
DMA transfer pending
No DMA transfer pending
r/w
DE
x
x
SRC
0
0x00
Res
w1:
w0:
No action
Clear P
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DMAT
r/w7-0:
DMA Timer
DMA timing, equation:
EN
r1:
r0:
w1:
w0:
Enable DMA channel
DMA sequence active
DMA sequence finished
enable DMA channel
disable DMA channel
fDMA
fDMAT = ----------------------
2DMAT + 1
BYP
r/w1:
r/w0:
Bypass Interrupt
don’t bypass DMA-Request to ICU
bypass DMA-Request to ICU.
TRIG
r/w15-0:
Trigger Source
(see Table 20–2)
Table 20–2: DMA Trigger Sources
DIR
r/w1:
r/w0:
DMA Direction
write to I/O-module
read from I/O-module
TRIG
Source
MAS
r/w3:
r/w2:
r/w1:
r/w0:
Memory Access Size
reserved
32-bit (not supported)
16-bit (not supported)
8-bit
3
x
x
x
x
2
1
0
0
1
1
0
0
1
0
1
DMA request from I/O-module
x
x
x
x
DMATx
PINT0
PINT1
20.3. Principle of Operation
The DMA Controller is operable in all CPU modes.
20.3.4. Self Timed DMA Read from I/O Operation
Flag DIR in register DCxM must contain a zero for reading
from an I/O module.
20.3.1. Initialization of the DMA Controller
The DMA vector table has to be installed starting at a 128
byte aligned address. See figure 20–5 for DMA vector layout.
Write the start address of the DMA vector table as a 32 bit
address to the DMA Vector Base register (DVB) and note
that only bits 7 to 23 may be modified. The other bits are
forced to zero. Enable the DMA controller by setting flag DE
in the DMA Status register (DST).
Write the destination address (24 bit), pointing to the first ele-
ment, and the block size (8 bit) to the corresponding DMA
vector table entry.
Start an SPI DMA sequence by writing to register SPIxD of
the corresponding SPI module. The data of this write may be
omitted. Then enable the DMA channel.
The input frequency fDMA for all DMA timer can be selected
by the register DMAC in the HW Options field.
Start a Graphic Bus DMA sequence by reading from register
GD. The data of this read may be omitted. Then enable the
DMA channel.
20.3.2. Initialization of a DMA Channel
20.3.5. External Triggered DMA Operation
All steps necessary to initialize the involved I/O module have
to be taken according to the description in the respective
chapter.
The procedure is the same as with the self timed operation
with some distinctions.
Write the appropriate values to the DMA Channel Mode reg-
ister (DCxM). Select the trigger source by field TRIG, pro-
gram the DMA timer by field DMAT if necessary, select trans-
fer direction (DIR) and size (MAS) and set BYP to one.
In both cases (read/write) the SW initiates the first action in
the peripheral module. Enable the DMA channel after this
module has finished it’s work. Otherwise a DMA cycle may
happen to early transferring invalid data.
It is possible to do external triggered DMA transfers without
the SW initiating the first action. In this case the maximum
block size is limited to 255 byte because the count value in
the DMA vector has to be programmed with block size plus
one. In a write case (Fig. 20–7), the sequence starts with
data D1. In a read case (Fig. 20–8), the first DMA cycle
reads invalid data D0. The first element of the transferred
block has to be omitted in the latter case.
20.3.3. Self Timed DMA Write to I/O Operation
Flag DIR in register DCxM must contain a one for writing to
an I/O module.
Write the source address (24 bit), pointing to the first plus
one element, and the block size (8 bit) to the corresponding
DMA vector table entry.
Start the DMA sequence by writing the first element to be
transferred to the data register of the corresponding I/O mod-
ule and enable the DMA channel.
20.3.6. End of DMA Sequence
The end of the DMA sequence is indicated by the enable flag
(EN=0) and an interrupt which calls the ISR of the corre-
sponding I/O module.
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The address field of the corresponding DMA vector points to
the next element after the last transferred element. The
counter field is at zero.
20.3.8. Termination of a DMA Sequence
A final termination of a DMA sequence can be achieved by
first disabling the DMA channel (DCxM.EN=0) and the
source of the DMA requests and secondly clearing the pend-
ing flag (DCxM.P=0).
20.3.7. Enabling of a DMA Channel
Setting the flag EN to one enables the DMA channel. Make
sure that there is no pending DMA request at that point of
time. Clearing an active pending flag P and enabling the cor-
responding DMA channel must not be done with a single
instruction. This might lead to an unwanted DMA cycle. First
clear P and then set EN in two instructions.
20.3.9. Disabling of the DMA Controller
First terminate all DMA channels (see 20.3.8.) and then clear
flag DST.DE. Do not simply clear flag DST.DE, as this might
result in undefined clock system behaviour.
20.4. Timing Diagrams
f
SYS
DREQx
DACC
A
DMA Vector
DMA Vector
Adr
Adr
D
Adr++
Data
nRW
DACKx
pending
DINTx
EN
Fig. 20–6: DMA Cycle Timing
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20.4.1. DMA Sequences SPI
DREQx
CPU
D0
DMA
D2
DMA
D3
DMA
D1
A,D
DACKx
SPIwr
D0
D1
D2
D3
SPIio
counter
4
3
2
1
0
DINTx
pending
EN
Fig. 20–7: SPI Write Sequence (serial out)
DREQx
CPU
Start
DMA
D0
DMA
D1
DMA
D2
DMA
D3
A,D
DACKx
SPIwr
SPIio
D0
D1
D2
D3
4
3
2
1
0
counter
DINTx
pending
EN
Fig. 20–8: SPI Read Sequence (serial in)
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20.4.2. DMA Sequences Graphic Bus Interface
DREQx
CPU
D0
DMA
D2
DMA
D3
DMA
D1
A,D
DACKx
wr GD
GDB
D0
D1
D2
D3
GWEQ
DINTx
DTA, EN
Fig. 20–9: Graphic Bus Write Sequence (parallel out)
DREQx
DMA
D1
DMA
D2
CPU
Start
DMA
D0
DMA
D3
A,D
DACKx
rd GD
GDB
D0
D1
D2
D3
GOEQ
DINTx
DTA, EN
Fig. 20–10: Graphic Bus Read Sequence (parallel in)
The final DMA request pulse clears the DMA Transfer Active
(DTA) flag additional to generating an interrupt.
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21. Graphic Bus Interface
The Graphic Bus Interface (GB) is intended to support the
operation of external LCD driver ICs (e.g. SED1560 by
Epson).
Features
– DMA read/write to external device
– CPU read/write to external device
– Read/write timing generation
– Read/write control signals generation
21.1. Functions
The DMA module copies 8bit pixel data bytes by direct mem-
ory access (DMA) to the external IC’s graphic RAM with help
of that IC’s internal autoincrement address counter, and with-
out CPU interaction. Other off-chip registers, allowing control
of the display behavior (blinking, scrolling, etc.), have to be
written and read by CPU operations.
the CPU. Please refer to section DMA for information about
GB DMA interaction.
The register GD provides the data interface for the GB. Writ-
ing to GD outputs the data byte at U5.0 to U5.3 (low nibble)
and U7.4 to U7.7 (high nibble). Reading from GD inputs a
data byte from above pins. The assignment to external sig-
nals is shown in table 21–1.
fIO
D
GOEQ
GWEQ
GD0 to7
Table 21–1: Port Assignment
Port
U5.0
:
Name
GDB0
:
wr GD
rd GD
DACKx
DINTx
DREQx
nRW
Graphic
Bus
Interface
External data bus
U7.7
1)
GDB7
GADB
GWEQ
GOEQ
External address bus
External write signal
External read signal
Fig. 21–1: Port Bus Block Diagram
U6.2
U6.1
The necessary timing is done autonomously by the GB logic.
Any U-Port may be used as address output port operated by
1) Any U-Port may be used as address output port.
21.2. GB Registers
GD
Graphic Bus Data Register
GC
Graphic Bus Control Register
Offs
Offs
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
r/w
Data
0
r/w
TIM
E
BSY
SEQ
DTA
0
0x00
Res
0x00
Res
A write access to this register generates the DACK signal
and writes to registers UxD. A read access to this register
generates the DACK signal and reads from registers UxPIN.
TIM
w15-1:
GB Timer
GB timing, equation:
2TIM + 1
-----------------
=
tGB
fIO
w0:
GB logic is disabled, clock input is disabled
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E
r/w1:
r/w0:
Enable
Enable timing generation
Disable timing generation
Every DACKx or access to GD signal sets this flag and the
DINTx signal clears it again.
DTA
r1:
DMA Transfer Active
DMA sequence started
DMA sequence is finished
Set DTA
BSY
r1:
r0:
Busy
GB timing is active
GB timing is not active
r0:
w1:
Every DACKx signal or access to GD sets this flag and every
DREQx signal clears it again.
w0:
No action
This flag indicates the end of a DMA sequence. It has to be
set by SW before a DMA sequence is started. It is cleared by
signal DINTx.
SEQ
r1:
DMA Sequence
DMA sequence is active
DMA sequence is not active
r0:
21.3. Principle of Operation
not finished and read the register GD. The DMA Controller
reads the remaining bytes from register GD and generates
an interrupt when finished. DTA low marks the end of the
DMA sequence.
21.3.1. Initialization
Table 21–2 shows the necessary settings of the port configu-
ration registers.
Table 21–2: Port Configurations
21.3.2.3. CPU Write Access
Writing the byte to register GD is sufficient. The end of the
transfer is indicated by flag BSY.
Register
Setting
Mode
U5MODE,
U7MODE,
U6MODE
0x00
Port mode
21.3.2.4. CPU Read Access
The read access must be initiated by a dummy read access
to register GD. After BSY is low the desired byte can be read
from register GD. This last step automatically initiates the
next read timing of the GB logic. If this is not desired,
because GOEQ stays active until the next access to GD,
after BSY became low, first disable the GB timing generation
by clearing flag E in register GC and then read register GD.
U5NS, U7NS
U6NS
0x00
0x06
0x00
Normal
Special
Out
U5TRI,
U7TRI,
U6TRI
21.3.3. Inactivation
Enable the timing generation by setting flag E in register GC.
Enable the clock input and select the desired timing of the
control signals GOEQ and GWEQ in the field GC.TIM. The
minimum high time of the control signals is one fIO cycle.
Inactivation is easily done by writing GC.TIM to zero. Make
sure not to switch off the GB as long as a transfer is active
(DTA or SEQ or BUSY are set).
21.3.4. Precautions
21.3.2. Data transfer
A write to register GD alters the universal ports data latches
U5D and U7D even if the GB is disabled (GC.TIM = 0).
Data to/from an external device can be transferred directly by
CPU access or, especially for bigger amounts of data and
with help of the external device’s autoincrement address
counter, a DMA sequence can be started. Make sure not to
start a GB transfer unless the flags DTA, SEQ and BSY are
zero.
21.3.2.1. DMA Write Sequence
After initialization of the corresponding DMA channel, set flag
DTA to show others that a DMA sequence was initiated but
not finished and write the first value to be transferred via the
GB to the register GD. The DMA Controller writes the
remaining bytes to register GD and generates an interrupt
when finished. DTA low marks the end of the DMA
sequence.
21.3.2.2. DMA Read Sequence
After initialization of the corresponding DMA channel, set flag
DTA to show others that a DMA sequence was initiated but
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21.3.5. Timings
DREQx
A
A++ D1
A
A++ D2
A,D
DACKx
Enable
Count (fIO)
GDB
tGB
D1
D2
tWDH
tWDS
GWEQ
DTA
tWH
1)
Fig. 21–2: DMA Write (parallel out)
DREQx
A
A++ D2
A
A++ D3
A,D
DACKx
Enable
Count (fIO)
GDB
tGB
D2
D3
tACC
GOEQ
DTA
tRH
1)
Fig. 21–3: DMA Read (parallel in)
1) DTA at the end of the last DMA cycle.
DACKx can be replaced by write to GD or read from GD if
direct CPU access is desired. The signals Enable and Count
are internal signals.
tWDS: Write data setup time
tWDH: Write data hold time
tWH: DMA write high time
tRH: DMA read high time
tACC: Read access time
tGB: GB time
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22. Serial Synchronous Peripheral Interface (SPI)
A SPI module provides a serial input and output link to exter-
nal hardware. An 8 or 9 bit data frame can be transmitted in
synchronism to an internally or externally generated clock.
Features
– 8 or 9 bit frames
– Internal or external clock
The SPI module can be operated via direct access or via
DMA.
– Programmable data valid edge
– Programmable clock polarity
– Three internal clock sources programmable
– Input deglitcher for clock and data
– DMA interface
The number of SPIs implemented is given in Table 22–1. The
“x” in register names distinguishes the module number.
HW Option
0
SI
SPIx-D-IN
0
0
Deglitcher
1
shift in
1
1
1
0
1
0
SO
SPIx-D-OUT
SPIxD
shift out
8
7
7
6
5
4
3
2
1
0
1
1
HW Option
RXSEL
Deglitcher
BIT8
6
INTERN
SPIxM
5
4
3
2
1
0
LEN9
3xT0
SPIx
Interrupt
Source
Scheduler
clk
1
SR0.SPIx
0
clkout
SO
2
SPIx-CLK-OUT
1
1
0
SI
Deglitcher
SPIx-CLK-IN
1
1
HW Option
HW Option
0
1
extclk
F0SPI
F1SPI
F2SPI
1/1
intclk
3:1
MUX
1/1,5
1/2,5
INTERN
1
0
2
CSF0/1
Fig. 22–1: Block Diagram
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22.1. Principle of Operation
Table 22–1: Module specific settings
22.1.1. General
A SPI serves as an 8 or 9 bit wide input/output shift register.
Either an internally or an externally generated clock can be
used to shift data in and out.
Module HW Options
Initialization
Address Item Setting
Enable
Bit
Name
Item
The input SPIx-D-IN is connected to the LSB of the shift reg-
ister. The output of the shift register is connected to output
signal SPIx-D-OUT. Thus each time a frame is transmitted
by shifting bits out, bits are shifted in simultaneously and vice
versa. Deglitchers in the data and clock input paths are
active only in external clock mode. The input and output can
be inverted by HW Option.
All SPIs F0SPI SP0C
clock
F1SPI SP1C
clock
If the deglitcher is active, input changes polarity after three
consecutive samples have shown the same new polarity.
Thus, a delay of three oscillator clock cycles is introduced.
This feature imposes a limit on the maximum transmission
frequency.
F2SPI SP2C
clock
SPI0
D in
SP0C
SP0C
SMC
SPI0-D- U3.5
IN
input
SR0.
special SPI0
in
inver-
sion
The interrupt is generated after the last bit is clocked out.
The interrupt source output of this module is routed to the
Interrupt Controller logic. But this does not necessarily select
it as input to the Interrupt Controller. Check section “Interrupt
Controller” for the actually selectable sources and how to
select them.
D out
inver-
sion
SPI0-D- U3.6
OUT
output
special
out
Pres-
caler
SPI0-
U3.4
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
CLK-IN special
input
in
SPI0-
CLK-
OUT
U3.4
special
out
22.1.2. Hardware settings
Clock frequency settings and the polarity of the data connec-
tions of the SPIs are settable by HW Options (Table 22–1).
Refer to “HW Options” for setting them.
output
SPI1
D in
inver-
sion
SP1C
SP1C
SMC
SPI1-D- U4.0
IN
input
SR0.
special SPI1
in
22.1.3. Initialization
D out
inver-
sion
SPI1-D- U4.1
OUT
output
After reset, a SPI is in standby mode (inactive).
special
out
Prior to entering active mode, proper SW configuration of the
U-Ports assigned to function as data in- or outputs and clock
in- or outputs has to be made (Table 22–1). Refer to “Ports”
for details.
Pres-
caler
SPI1-
CLK-IN special
U3.7
input
in
For entering active mode of a SPI, set the respective enable
bit (Table 22–1).
SPI1-
CLK-
OUT
U3.7
special
out
Prior to operation, the desired clock frequency and telegram
length have to be selected.
output
22.1.3.1. Clock Source
If flag INTERN is zero, the SPI operates as clock slave and
an externally generated clock is used. The external clock is
input by signal SPIx-CLK-IN.
The SPI can be operated as clock master, using an internally
generated clock, or as clock slave, using an externally gen-
erated clock.
The polarity and the sampling edge of the clock is defined by
field SCLK in register SPIxM.
The flag INTERN must be set in the SPIxM Mode register to
operate the SPI as clock master. There are several options
for selection of the internal clock. Each input of a 3 to 1 multi-
plexer can be programmed by HW Options to a different fre-
quency. These three input frequencies F0SPI, F1SPI and
F2SPI are used for all SPIs. The output of the 3 to 1 multi-
plexer is programmed by way of clock selection field (CSF) in
register SPIxM. This clock can be used as shift clock directly,
inverted and divided by 1.5 or 2.5. The shift clock is output by
signal SPIx-CLK-OUT.
22.1.3.2. Telegram Length
Flag LEN9 in register SPIxM defines the length of a trans-
ferred frame. The ninth bit of the shift register is read or writ-
ten at the location of flag BIT8 in register SPIxM.
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22.1.4. Operation
22.1.5. Inactivation
Returning a SPI module to standby mode by resetting its
respective enable bit (Table 22–1) will immediately terminate
any running receive or transmit operation and will reset all
internal registers.
22.1.4.1. Transmit Mode
Transmission is initiated by a write access to data register
SPIxD. The SPI will immediately begin transmitting the
selected number of data bits out from its shift register, in syn-
chronism with the selected clock. A write access during a
transmission is ignored. The frame is transmitted MSB first.
In nine-bit mode flag BIT8 is MSB of the shift register (Fig.
22–2 to 22–5). At the end of the frame, an interrupt source
signal is generated which may be selected to trigger an inter-
rupt.
22.1.6. Precautions
A single wire bus is easiest implemented by a wired-or con-
figuration of the SPIx-D-OUT output port and the open drain
output of the external transmitter:
simply configure the SPIx-D-OUT output port in Port Slow
mode, always operate it in Port Special Output mode and
connect it directly to the external open drain output. An exter-
nal pull-up resistor is not necessary in this configuration
because the SPIx-D-OUT output port supplies the necessary
pull-up drive.
If the SPIx-D-OUT output port has to be operated in Port
Fast mode, this simple scheme is not possible, because the
pull-down action of the external open drain output may
exceed the absolute maximum current rating of the SPIx-D-
OUT output port. A discrete external wired-or is recom-
mended for this situation.
22.1.4.2. Receive Mode
The receive mode must be activated by a write access to
register SPIxD. The SPI will immediately begin clocking in
the selected number of data bits into its shift register, in syn-
chronism with the selected clock. At the end of the frame, an
interrupt source signal is generated which may be selected
to trigger an interrupt.
22.1.4.3. DMA
During operation, make sure, that the external clock does not
start until after SPIxD has been written, otherwise correct
data transfer is not be guaranteed.
Please refer to section “DMA” for information about operation
of the SPI in DMA mode.
22.2. Registers
The following registers are available once for SPI0 and SPI1
each.
SCLK
r/w:
Sample Clock
Clock polarity and edge of data sampling.
(Table 22–2)
Table 22–2: SCLK usage
SPIxD
SPI x Data Register
7
6
0
5
4
3
2
1
0
0
0
SCLK
Clock
Polarity
Sampling
Edge
See Fig.
r/w
Bit 7 to 0 of Rx/Tx Data
1
0
0
1
1
0
0
1
0
1
0
0
0
0
0
Res
low
falling
rising
rising
falling
22–3
22–5
22–2
22–4
SPIxM
SPI x Mode Register
7
6
5
4
3
2
1
0
0
0
high
r/w
BIT8
LEN9 RXSEL INTERN
SCLK
CSF
0
0
0
0
0
0
Res
CSF
wr:
Clock Selection Field
Source of internal clock (Table 22–3)
BIT8
r/w:
Bit 8 of Rx/Tx Data
Rx/Tx data bit.
In 8 bit mode (LEN9 = 0) this bit is undefined when read.
Table 22–3: CSF usage
LEN9
r/w0:
r/w1:
Frame Length 9 Bit Selection
8 bit mode.
9 bit mode.
CSF
Source of internal clock
1
0
0
1
0
0
1
x
RXSEL
r/w0:
r/w1:
Receive Selection
Input active.
Low level at input.
F0SPI
F1SPI
F2SPI
INTERN
r/w0:
r/w1:
Internal/External Clock Selection
Use external clock.
Use internal clock.
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22.3. Timing
wr SPIxD
clk out
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SPIx-D-OUT
SPIx-D-IN
SPIx Int. Src.
Fig. 22–2: Nine bit frame. Data valid at rising edge. Clock inactive high
wr SPIxD
clk out
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SPIx-D-OUT
SPIx-D-IN
SPIx Int. Src.
Fig. 22–3: Eight bit frame. Data valid at falling edge. Clock inactive low
wr SPIxD
clk out
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SPIx-D-OUT
SPIx-D-IN
SPIx Int. Src.
Fig. 22–4: Nine bit frame. Data valid at falling edge. Clock inactive high
wr SPIxD
clk out
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SPIx-D-OUT
SPIx-D-IN
SPIx Int. Src.
Fig. 22–5: Eight bit frame. Data valid at rising edge. Clock inactive low
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23. Universal Asynchronous Receiver Transmitter (UART)
A UART provides a serial Receiver/Transmitter. A 7bit or 8bit
telegram can be transferred asynchronously with or without a
parity bit and with one or two stop bits. A 13bit baud rate
generator allows a wide variety of baud rates. A two word
receive FIFO unburdens the SW. Incoming telegrams are
compared with a register value. Interrupts can be triggered
on transmission complete, reception complete, compare and
break.
Features
– Full duplex.
– 7bit or 8bit frames.
– Parity: None, odd or even.
– One or two stop bits.
– Receive compare register.
– Two word receive FIFO.
– 13bit baud rate generator.
The number of UARTs implemented is given in Table 23–1.
The “x” in register names distinguishes the module number.
UAxIF
UAxIM
UAxD
UAxCA
w
2
1
0
2
1
0
r
r
w
compare address register
rx FIFO
8
&
&
8
=
8
3
break
UART
Interrupt
Source
>
1
2 of 3
rx
rx shift register
&
received
4
rx control
tx control
tx
1
tx shift register
tx data register
tx
7
6
6
5
5
4
3
3
2
2
1
1
0
r
UAxD
w
7
4
0
w
UAxC
4
fBR
1/8
UAxBR1
UAxBR0
fsample
f0
clk
zero
clk
zero
5 bit down cnt
8 bit down counter
Fig. 23–1: Block Diagram
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23.1. Principle of Operation
23.1.1. General
23.1.3. Initialization
A UART module contains a receive shift register that serves
to receive a telegram via its RX input. A FIFO is affixed to it
that stores two previously received telegrams.
After reset, a UART is in standby mode (inactive).
Prior to entering active mode, proper SW configuration of the
U-Ports assigned to function as RX input and TX output has
to be made (Table 23–1). The RX port has to be configured
Special In and the TX port has to be configured Special Out.
Refer to “Ports” for details.
A transmit shift register serves to transmit a telegram via its
TX output.
Other features include a receive compare function, flexible
interrupt generation and handling, and a set of control, error
and status flags that facilitate management of the UART by
SW.
For entering active mode of a UART, set the respective
enable bit (Table 23–1).
Prior to operation, the desired baud rate, telegram format,
compare address and interrupt source configuration have to
be made.
The interrupt source output of this module is routed to the
Interrupt Controller logic. But this does not necessarily select
it as input to the Interrupt Controller. Check section “Interrupt
Controller” for the actually selectable sources and how to
select them.
23.1.3.1. Baud Rate Generator
The receive and transmit baud rate is internally generated.
The Baud Rate registers UAxBR0 (low byte) and UAxBR1
(high byte) serve to enter the desired 13bit setting. Write
UAxBR0 first, UAxBR1 last.
A programmable baud rate generator generates the required
bit clock frequency.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
The baud rate generator is a 13bit down-counter which is
clocked by f0. It generates the sample frequency:
A UART module is only capable to receive telegrams that dif-
fer by no more than ± 2.5% from its own baud rate setting.
f0
fsample = --------------------------------------------------------------------------------
Value of Baud Rate Registers + 1
23.1.2. Hardware settings
The polarity of most RX and TX connections of the UART is
settable by HW Options (See table 23–1 and figure 23–2).
Refer to “HW Options” for setting them.
Its output frequency fsample is divided by eight to generate
the baud rate (bit/second).
f0
fsample
BR = ---------------------------------------------------------------------------------------------- = --------------
HW Option
0
UARTx-TX
tx
(Value of Baud Rate Registers + 1) × 8
8
SR0.UARTx
f0
clk
1
SO
f0
1
Value of Baud Rate Registers = ---------------- – 1
UARTx
rx
BR × 8
UARTx-RX
SI
0
1
1
HW Option
Fig. 23–2: Context Diagram
23.1.3.2. Telegram Format
The format of a telegram is configured in the Control and
Status register UAxC. A telegram starts with a start bit fol-
lowed by the data field. The data field consists of 7 or 8 data
bit. There can be a parity bit after the data field. The telegram
is finished by one or two stop bits (see Table 23–3 on
page 138).
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Table 23–1: Module specific settings
Module
Name
HW Options
Item
Initialization
Enable Bit
Address
Item
Setting
UART0
UART1
RX inversion
TX inversion
RX inversion
TX inversion
UA0
UART0-RX input
UART0-TX output
UART1-RX input
UART1-TX output
U2.5 special in
SR0.UART0
U2.4 special out
U2.3 special in
U2.2 special out
UA1
SR0.UART1
ter UAxIF and can be enabled by setting bits in the Interrupt
Mask register UAxIM.
S
S
S
S
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
7
P T0 T1
1. When the flag TBUSY in register UAxC is set to zero, the
interrupt source output is triggered. This indicates that a
transmission is finished and the transmit buffer is empty.
There is neither an interrupt flag to indicate this event, nor a
mask flag to disable this interrupt.
7 T0 T1
2. RCVD is generated by the receive control logic at the end
of each received telegram even if the FIFO is full. This signal
is enabled by setting the corresponding bit in register UAxIM.
6 T0
6
7 P T0
3. BRK is generated by the receive control logic each time a
break is detected. This signal is enabled by setting the corre-
sponding bit in register UAxIM.
S = Start bit
P = Parity bit
T0 = 1. stop bit
T1 = 2. stop bit
4. ADR is generated by the address comparator. This signal
is enabled by setting the corresponding bit in register UAxIM.
Fig. 23–3: Examples of Telegram Formats
BRK and ADR also set flags in the Interrupt Flag register
UAxIF when enabled. The first RCVD interrupt, when the
FIFO has been empty before, sets a flag in UAxIF too. Even
if all interrupts are enabled in register UAxIM, the interrupt
source output is triggered only once within a telegram. UAxIF
flags remain valid until the end of the next telegram. ADR is
not generated and the ADR flag is not set if a frame or parity
error was detected in the corresponding telegram.
The level of the start bit is always opposite to the neutral
level. The level of the stop bits is always the same as the
neutral level. If a parity bit is programmed, odd or even parity
can be selected.
Table 23–2: Definition of Parity Bit
23.1.4. Operation
Parity Flag
odd
Number of Ones
Parity Bit
With proper HW configuration and SW initialization, a UART
module is ready to transmit and receive telegrams in the
selected format.
odd
0
1
1
0
odd
even
odd
23.1.4.1. Transmit
even
A write access to UART Data register UAxD immediately
loads the transmit shift register and starts transmission with
sending the start bit. The flag TBUSY in register UAxD is set.
even
even
As a general rule, the parity bit completes the number of
ones in the data field to the selected parity.
At the end of transmission the interrupt source signal is trig-
gered and the flag TBUSY is reset.
23.1.3.3. Compare Address
To avoid data corruption, ensure that flag TBUSY is LOW
before writing to UAxD
The content of the Compare Address register UAxCA is
compared with each received telegram. On a match, the
interrupt flag ADR is set and the interrupt source signal is
triggered.
23.1.4.2. Receive
A first negative edge of a telegram on the RX line of a UART
starts a receive cycle and sets the flag RBUSY in UAxC.
After reception of the last bit of the telegram, the telegram
content, together with its status information, is transferred to
the receive FIFO and an interrupt is generated. RBUSY is
resetted. Telegram data are available in register UAxD, tele-
gram status in register UAxC.
The MSB of register UAxCA must be set to zero if transmis-
sion of a seven bit data field is configured in register UAxC.
23.1.3.4. Interrupt
Four signals can trigger the UART interrupt source output.
Three of them set their own flags in the Interrupt Flag regis-
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During reception, the following checks are performed
according to the register UAxC setting:
too. The flags PAER, FRER and BRKD in register UAxC
apply to a certain telegram and are thus double buffered.
1. A parity error is detected if the parity of the received tele-
gram does not match the programmed parity. The flag PAER
in register UAxC is set in this case. Differing telegram length
settings in register UAxC and receiver may also cause parity
errors.
The receive FIFO is full if two telegrams were received but
the SW did not yet read register UAxD. If there is a third tele-
gram, it is not written to the FIFO and its data are lost. The
flags EMPTY, FULL and OVRR show the status of the FIFO.
EMPTY indicates that there is no entry in the FIFO. FULL will
be set with the second entry in the receive FIFO and indi-
cates that there is no more entry free. OVRR indicates that
there was a third telegram which could not be written to the
FIFO.
2. A frame error is detected if the level of start or stop bits
violate the transmission rule. The flag FRER in register
UAxC is set in this case.
3. A break condition is detected if the receive input remains
low for one complete telegram duration. When a break starts
during telegram, this condition must extend over another
telegram length to be properly detected. This event sets the
flag BRKD in register UAxC and can trigger the interrupt
source output if enabled. After a break, the receive input
must be high for at least 1/4 of the bit length before a new
telegram can be received.
Status flags are readable as long as the corresponding data
field was not read from register UAxD. As soon as a FIFO
entry is read out, the status flags of this entry are lost. They
are overwritten by the flags of the second entry. SW first has
to read the flags and then the corresponding FIFO entry.
The flags PAER, FRER and BRKD apply to a certain tele-
gram and are only valid if there is at least one entry in the
FIFO (EMPTY = 0). The flags EMPTY, FULL and OVRR
apply to the FIFO and are valid all the time.
Telegrams of an external RS232 interface are correctly
received, even if they are transmitted without gaps (the start
bit immediately follows the stop bit of the preceding tele-
gram).
23.1.5. Inactivation
Returning a UART module to standby mode by resetting its
respective enable bit (Table 23–1) will immediately terminate
any running receive or transmit operation and will reset all
internal registers.
23.1.4.3. Receive FIFO
The receive FIFO is able to buffer the data fields of two con-
secutive telegrams. But not only the data field of a telegram
is double buffered, the related information is double buffered
23.2. Timing
The duration of a telegram results from the total telegram
length in bits (LTG) (see Table 23–3 on page 138) and the
baud rate (BR).
LTG
tTG = ---------
BR
The incoming signal is sampled with the sample frequency
and filtered by a 2 of 3 majority filter. A falling edge at the
output of the majority filter starts the receive timing frame for
the telegram. An individual bit is sampled with the fifth sam-
ple clock pulse within that timing frame (cf. Fig. 23–4 and
23–5). If a bit was the last bit of its telegram, reception of a
new telegram can start immediately after this sample. With a
receive telegram, interrupt source is triggered and flags are
set just after the sample of the last stop bit. With a transmit
telegram, interrupt source is triggered and BUSY reset after
the nominal end of the last stop bit.
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1
2
3
4
5
6
7
8
fsample
rxdat asynchron
1. sample
2. sample
3. sample
start
startbit
bit 0
bit 1
indicates the recognition of the low level of the filtered input signal
data
sample clock
Fig. 23–4: Start of Telegram
1
2
3
4
5
6
7
8
fsample
rxdat asynchron
1. sample
2. sample
3. sample
start
1. stopbit
2. stopbit
startbit
data
sample clock
Rx Interrupts
Tx Interrupt
BUSY
Flags are set
Fig. 23–5: End of Telegram
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23.3. Registers
LEN
w0:
w1:
Length of Frame
7bit frame.
8bit frame.
UAxD
UART x Data Register
7
6
5
4
3
2
1
0
r
Receive register
Transmit register
Table 23–3: Telegram Format and Length
w
x
x
x
x
x
x
x
x
Res
LEN
0
PAR
0
STPB
Format
LTG
9
0
1
0
1
0
1
0
1
S, 7D, T0
UAxC
UART x Control and Status Register
0
0
S, 7D, T0, T1
S, 7D, P, T0
S, 7D, P, T0, T1
S, 8D, T0
10
10
11
10
11
11
12
7
6
5
4
3
2
1
0
0
1
r
RBUSY BRKD
FRER
OVRR
PAER EMPTY FULL TBUSY
0
1
0
x
x
0
x
1
0
0
Res
Res
w
x
x
x
x
STPB
ODD
PAR
LEN
1
0
x
x
x
x
0
0
0
0
1
0
S, 8D, T0, T1
S, 8D, P, T0
S, 8D, P, T0, T1
RBUSY
r0:
Receiver Busy
Not busy.
Busy.
1
1
r1:
1
1
BRKD
r0:
r1:
Break Detected
No break.
Break.
UAxBR0
UART x Baud Rate Register low byte
FRER
r0:
Frame Error Detected
No error.
r1:
Error.
7
6
0
5
0
4
3
2
0
1
0
0
0
OVRR
r0:
r1:
Overrun Detected
No overrun.
Overrun.
w
Bit 7 to 0 of Baud Rate
0
0
0
Res
PAER
r0:
r1:
Parity Error Detected
No error.
Error.
UAxBR1
UART x Baud Rate Register high byte
7
6
x
5
4
3
2
1
0
EMPTY
r0:
r1:
Rx FIFO Empty
Not empty.
Empty.
w
x
x
Bit 12 to 8 of Baud Rate
There is at least one entry present if EMPTY is zero. PAER,
FRER and BRKD are not valid if EMPTY is set.
-
-
-
0
0
0
0
0
Res
The Baud Rate Registers UAxBR0 and UAxBR1 have to be
written low byte first to avoid inconsistencies. UAxBR0 is the
low byte.
FULL
r0:
r1:
Rx FIFO Full
Not full.
Full.
Valid entries in the Baud Rate Registers range from 1 to
8191. Don’t operate the baud rate generator with its reset
value zero.
TBUSY
r0:
r1:
Transmitter Busy
Not busy.
Busy.
Do not write to register UAxD as long as BUSY is true.
STPB
w0:
w1:
Stop Bits
One stop bit.
Two stop bits.
UAxCA
UART x Compare Address Register
7
6
0
5
4
3
2
1
0
w
Bit 7 to 0 of address
ODD
w0:
w1:
Odd Parity
Even parity.
Odd parity.
0
0
0
0
0
0
0
Res
PAR
w0:
w1:
Parity On
No parity.
Parity on.
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UAxIM
UART x Interrupt Mask Register
7
6
x
-
5
x
-
4
x
-
3
x
-
2
ADR
0
1
BRK
0
0
RCVD
0
w
x
-
Res
ADR
w0:
w1:
Mask Compare Address Detected
Disable interrupt.
Enable interrupt.
BRK
w0:
w1:
Mask Break Detected
Disable interrupt.
Enable interrupt.
RCVD
w0:
Mask Received a Telegram
Disable interrupt.
w1:
Enable interrupt.
UAxIF
UART x Interrupt Flag Register
7
6
Test
-
5
Test
-
4
Test
-
3
Test
-
2
ADR
x
1
BRK
0
0
RCVD
0
r
Test
-
Res
Test
Reserved for test (do not use)
ADR
r0:
r1:
Compare Address Detected
No Interrupt.
Interrupt pending.
BRK
r0:
r1:
Break Detected
No Interrupt.
Interrupt pending.
RCVD
r0:
r1:
Received a Telegram
No Interrupt.
Interrupt pending.
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24. I2C-Bus Master Interface
The IC contains two independent I2C-bus Master Interface
units (I2C), 0 and 1. They are pure master systems, multi
master busses are not realizable. The units contain read and
write buffers with interrupt logic which makes automatic and
software independent operation possible for most types of
I2C telegrams. Because of the internal clock pre-scaler, tele-
gram clock rate does not depend on system clock rate.
WR_Data (subaddress=control info)
Address
Decoder
D0 to D7
WR
0
f1
Clock Prescaler
1
Write
FIFO
5 x 11
half full
empty
SR0.I2Cx
control
busy
2
Write Logic
Read Logic
SDAx
SCLx
in
SR
out
I2CMx.DGL
Deglitcher
Read
FIFO
3 x 8
Ack = 0
received
empty
Start Condition:
- resets ACK flags
- deletes Read FIFO
S R
S R
Q
Q
D0 to D7
RD_Data
Status Register
D0 to D7
I2C Interrupt Source
RD_Status
Fig. 24–1: Block diagram of I2C-Bus Master Interface
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24.1. Principle of Operation
value. By default, the input deglitcher is on, limiting the
obtainable bit rate to 208.3kbit/s (see Table 24–2).
24.1.1. General
In standby mode the clock is halted. Programming of the I2C
registers is possible and the Write-FIFO can be filled.
24.1.2. Hardware Settings
Since the telegram clock rate is register programable there is
no HW option for the I2C-Bus Master Interface.
Prior to operation, proper SW configuration of the U-Ports
assigned to function as I2C Double Pull-down port has to be
made. See table 24–1 and section "Ports" for details.
24.1.3. Initialization
After system reset the I2C is in standby mode, i.e. the block
internal clock is halted and all registers are set to their reset
Table 24–1: Module specific settings
Module
Name
HW Options
Item
Initialization
Address Item Setting
Enable Bit
I2C0
I2C1
U2.0 CAN0/SCL0 output multiplexer PM.U20 SCL0
U2.0 special out, double pull-down mode SR0.I2C0
U2.1 special out, double pull-down mode
U2.1 CAN0/SDA0 output multiplexer
SDA0
SCL1
SDA1
U5.1 special out, double pull-down mode SR0.I2C1
U5.2 special out, double pull-down mode
The bit rate and the desired input deglitcher configuration
has to be set up in register I2CMx in order to get into an
active and useful mode. All other registers serve I2C data I/O
purposes.
If a read instruction is handled, the interface must send the
data word 0xFF so that the responding slave can insert its
data. In this case the Read-FIFO contains the read-in data.
If telegrams longer than 3 bytes (1 address, 2 data bytes) are
received, the software must check the filling condition of the
Write-FIFO and, if necessary, fill it up and read out the
Read-FIFO. A variety of status flags is available for this pur-
pose:
24.1.4. Operation
A complete telegram is assembled by the software out of
individual sections. Each section contains 8-bit data. This
data is written into one of the six possible write registers.
Depending on the chosen address, a certain part of an
I2C-bus cycle is generated: start, data, stop, with or without
acknowledge. By means of corresponding calling sequences
it is therefore possible to join even very long telegrams (e.g.
long data files for auto increment addressing of I2C slaves).
- The ‘half full’ flag I2CRSx.WFH is set if the Write-FIFO is
filled with exactly three bytes.
- The ‘empty’ flag I2CRSx.RFE is set if there is no more data
available in the Read-FIFO.
- The ‘busy’ flag I2CRSx.BUSY is activated by writing any
byte to any one of the Write registers. It stays active until
the I2C-bus activities are stopped after the stop condition
generation.
The software interface contains a 5 word deep Write-FIFO
for the control-data registers as well as a 3 word deep Read-
FIFO for the received data. Thus most of the I2C telegrams
can be transmitted to the hardware without the software hav-
ing to wait for empty space in the FIFO.
Moreover the ACK-bit is recorded separately on the bus lines
for the address and the data fields. However, the interface
itself can set the address ACK=0. In any case the two ACK
flags show the actual bus condition. These flags will be reset
with the next I2C start condition.
An interrupt is generated on two conditions:
- The Write-FIFO was filled with 5 entries and reaches the
‘half full’ state.
There is one data acknowledge (DACK) flag available. It indi-
cates the level of the last received ACK bit. It will be cleared
to zero with the reception of a zero and it will be set to one
with the reception of a one within the acknowledge field of a
data byte. Thus, after the stop condition, it indicates whether
the last of the data bytes was acknowledged or not.
- The Write-FIFO is empty and stop condition is completed.
There is no ‘Write-FIFO half full’ interrupt unless the Write-
FIFO was previously filled completely.
All address and data fields appearing on the bus are con-
stantly monitored and written into the Read-FIFO. The soft-
ware can then check these data in comparison with the
scheduled data.
The bus activity starts immediately after the first write to the
Write-FIFO. The transmission can be synchronized by an
artificial extension of the low phase of the clock line. Trans-
mission is not continued until the state of the clock line is
high once again. Thus an I2C slave device can adjust the
transmission rate to its own abilities.
Every reception of a start or restart condition immediately
empties the Read-FIFO. The Read-FIFO stops if it is full. It’s
not overwritten, further received data are lost.
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The figures 24–2, 24–3 and 24–4 show the basic principle
of I2C telegram transmission as a quick reference. Refer to
the official I2C documentation for more details.
24.1.6. Precautions
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
24.1.4.1. Example of Operation
Note: The I2C block uses U-Ports as connection to the out-
side world. This implies that neither logic output low level
switching specs nor logic input value specs of the official I2C
specification document are literally met. Refer to section
"Ports" for the actual spec values of this implementation.
The software has to work in the following sequence (ACK=1)
to read a 16-bit word from an I2C device address 0x10 (on
condition that the bus is not active):
-write 0x21 to
I2CWS0x
I2CWD0x
I2CWP1x
I2CRSx
I2CRDx
I2CRSx
I2CRDx
I2CRSx
I2CRDx
-write 0xFF to
-write 0xFF to
-read RFE bit from
-read dev. address from
-read RFE bit from
-read 1st databyte from
-read RFE bit from
-read 2nddatabyte from
1T
SDA
SCL
1/2T
1T
1/4T
The value 0x21 in the first step results from the device
address in the 7 MSBs and the R/W-bit (read=1) in the LSB.
If the telegrams are longer, the software has to ensure that
neither the Write-FIFO nor the Read-FIFO can overflow.
Fig. 24–2: Start or Restart Condition I2C-Bus
To write data to this device:
-write 0x20 to
-write 1st databyte to
-write 2nd databyte to
I2CWS0x
I2CWD0x
I2CWP0x
1T
SDA
repeated
8 times
24.1.5. Inactivation
Since the described block is an I2C master, all I2C bus activ-
ity stops if the end of a telegram is reached. I2C slaves can-
not start any bus activity on their own. However, the block
internal clock is always running at full speed of I2C clock (4
or 5 MHz), independent of the bit rate divider setting. The
standby mode is therefore intended for the lowest possible
power consumption.
SCL
1/4T
1/4T
1/2T
Fig. 24–3: Single Bit on I2C-Bus
Make sure to switch off the module only if it is not active.
Switching off during transmission of a telegram may cause
an output to stay at low level. Hence lowest possible power
consumption can’t be achieved because SDA and SCL use
open drain output ports.
SDA
SCL
3/4T
1/4T
Fig. 24–4: Stop Condition I2C-Bus
24.2. Registers
I2CWS0x
I2C Write Start Register 0
I2CWS1x
I2C Write Start Register 1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
w
I2C Address
w
I2C Address
0x00
Res
0x00
Res
Writing this register moves I2C start condition, I2C Address
and ACK=1 into the Write FIFO.
Writing this register moves I2C start condition, I2C Address
and ACK=0 into the Write FIFO.
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AACK
r1:
r0:
Address Acknowledge
Not acknowledged (received a one)
Acknowledged (received a zero)
I2CWD0x
I2C Write Data Register 0
7
6
5
4
3
2
1
0
DACK
r1:
r0:
Data Acknowledge
Not acknowledged (received a one)
Acknowledged (received a zero)
w
I2C Data
0x00
Res
BUSY
r1:
r0:
Busy
I2C Master Interface is busy.
I2C Master Interface is not busy.
Writing this register moves I2C Data and ACK=1 into the
Write FIFO.
WFH
r1:
r0:
Write-FIFO Half Full
Write-FIFO contains exactly 3 bytes.
Write-FIFO contains more or less than
3 bytes.
I2CWD1x
I2C Write Data Register 1
7
6
5
4
3
2
1
0
RFE
r1:
r0:
Read-FIFO Empty
Read-FIFO is empty.
Read-FIFO is not empty.
w
I2C Data
0x00
Res
Writing this register moves I2C Data and ACK=0 into the
Write FIFO.
I2CMx
I2C Mode Register
7
DGL
1
6
5
4
3
2
1
0
w
SPEED
0x02
I2CWP0x
I2C Write Stop Register 0
Res
7
6
5
4
3
2
1
0
DGL
w1:
w0:
Input Deglitcher
Deglitcher is active.
Deglitcher is bypassed.
w
I2C Data
0x00
Res
If the deglitcher is active, the maximum bit rate is limited.
SPEED must be programmed to 6 at least. The maximum bit
rate may be further reduced by the bus load.
Writing this register moves I2C Data, ACK=1 and I2C stop
condition into the Write FIFO.
SPEED
w:
Speed Select (Table 24–2)
I2C Bit Rate = f1 / (4 * SPEED).
I2CWP1x
I2C Write Stop Register 1
Table 24–2: SPEED Usage: I2C Bit Rates
7
6
5
4
3
2
1
0
w
I2C Data
0x00
SPEED
f1 Divi-
sion by
Bit Rate @
f1=5MHz
Bit Rate @
f1=4MHz
Res
0
128*4 (!)
1*4
9.8 kbit/s
1.25 Mbit/s
625 kbit/s
416.7 kbit/s
312.5 kbit/s
250 kbit/s
208.3 kbit/s
178.6 kbit/s
...
7.8 kbit/s
Writing this register moves I2C Data, ACK=0 and I2C stop
condition into the Write FIFO.
1 1)
2 1)
3 1)
4 1)
5 1)
6
1.00 Mbit/s
500 kbit/s
333.3 kbit/s
250 kbit/s
200 kbit/s
166.7 kbit/s
142.9 kbit/s
2*4
I2CRDx
I2C Read Data Register
3*4
7
6
5
4
3
2
1
0
4*4
r
I2C Data
0x00
5*4
Res
6*4
Reading this register returns the content of the Read FIFO.
7
7*4
...
I2CRSx
I2C Read Status Register
7
6
5
4
3
2
WFH
0
1
RFE
0
0
x
0
127
127*4
9.8 kbit/s
7.9 kbit/s
r
x
OACK AACK DACK BUSY
1) These bit rates may only be set with a bypassed
input deglitcher (I2CMx.DGL=0)
0
0
0
0
0
Res
OACK
"OR"ed Acknowledge
r:
AACK OR DACK.
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25. CAN Manual
This manual describes the user interface of the CAN module.
For further information about the CAN bus, please refer to
the CAN specification 2.0B from Bosch.
– Sleep mode
The CAN interface is a VLSI module which enables coupling
to a serial bus in compliance with CAN specification 2.0B. It
controls the receiving and sending of telegrams, searches for
Tx telegrams and interrupts and carries out acceptance filter-
ing. It supports transmission of telegrams with standard (11
bit) and extended (29 bit) addresses.
Features
– Bus controller according to CAN Licence Specification
1992 2.0B
The CAN interface can be configured as BasicCAN or Full-
CAN. It enables several active receive and transmit tele-
grams and supports the remote transmission request. The
number of telegrams which can be handled depends mainly
on the size of the communication RAM (16 byte per tele-
gram), the system clock and the transmission speed. A max-
imum of 254 telegrams can be handled.
– Supports standard and extended telegrams
– FullCAN: up to 32 Rx and Tx telegrams
– Variable number of receive buffers
– Programmable acceptance filter
Single, group or all telegrams received.
– Time stamp for each telegram
A mask register makes it possible to receive different groups
of telegram addresses with different receive telegrams.
Transmitting or receiving of a telegram as well as the occur-
rence of an error can trigger an interrupt.
– Overwrite mode programmable for each telegram
– Programmable baud rate. Max. 1 MBd @ 8 MHz
CPU
Address
CAN
Bus
Error
Managem.
Logic
Global Con-
Data
trol and Sta-
tus Register
Interrupt
Source
CAN RAM
f0
(Com.
Area)
Rx. Obj.
Bit Timing
Logic
Protocol
Manager
Interface
Managm.
Logic
Tx. Obj.
Rx/Tx-
Buffer
Fig. 25–1: Block diagram of the CAN bus interface
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25.1. Abbreviations
BI
CAN Bus Interface
ID
Identifier
BTL
Bit Timing Logic
IML
Interface Management Logic
Receive Object
CAN
CA
Controller Area Network
Communication Area
Communication Object
Communication Mode
Cyclic Redundancy Code
Data Length Code
Rx. Obj.
RxTg
Std. ID
Std. Tg
TD
Receive Telegram
Standard Identifier
Standard Telegram
Telegram Descriptor
Telegram
CO
CM
CRC
DLC
EoCA
Ext. ID
Ext. Tg
GCS
Tg
End of CA
TQ
Time Quantum
Extended Identifier
Tx. Obj.
TxTg
Transmit Object
Extended Telegram
Global Control and Status Register
Transmit Telegram
25.2. Functional Description
Receive Object: The BI enters received telegrams into a
matching Rx-Object. It can be retrieved from the application.
25.2.1. HW Description
The CAN bus interface consists of the following components:
Transmit Object: The application enters data into the Tx-
Object and reports it ready for transmission. The BI sends
the telegram as soon as the bus traffic allows.
Bit Timing Logic: Scans the bus and synchronizes the CAN
bus controller to the bus signal.
Protocol Manager: The PM monitors or generates the com-
position of a telegram and performs the arbitration, the CRC
and the bit stuffing. It controls the data flow between Rx/Tx
buffer and CAN bus. It also drives the Error Management
Logic.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
25.2.2. Memory Map
Error Management Logic: Adds up the error messages
received from the protocol manager and generates error
messages when particular values are exceeded. Guarantees
the error limitation as per the CAN Spec. V2.0B.
From the CAN bus interface the user sees two storage areas
in the user RAM area. The BI is configured with the Global
Control and Status Registers (GCS). It also indicates the sta-
tus here. The communication area (CA) contains the Rx and
Tx telegrams.
Interface Management Logic: The IML scans the Commu-
nication Area (CA) in the CAN-RAM for transmit telegrams.
As soon as it finds one, it enters it into the Rx/Tx buffer and
reports it to the protocol manager as ready for transmission.
If a telegram is received, the IML carries out the acceptance
filtering, i.e. scans the CA, taking into account the Identifier
Mask Register in the GCS, for a Tg with the appropriate
address. After correct reception, it copies the Tg from the Rx/
Tx buffer to the CA. The IML also reports to the CPU the
valid transfer of a telegram or given errors per interrupt.
The communication area lies in the CAN-RAM. The end of
the Com. Area is fixed by the first control byte of an object
whose 3 MSBs contain only ones (Communication Mode = 7
= EoCA). The area after this is available to the user.
The CA consists of communication objects (COs). A CO con-
sists of 6 bytes telegram descriptor (TD), 8 data bytes and
the Time Stamp which is 2 bytes long. The TD contains the
address (ID) and the length of a telegram (DLC) as well as
control bits which are needed for access to the CO and for
the transmission of a telegram.
The interrupt source output of this module is routed to the
Interrupt Controller logic. But this does not necessarily select
it as input to the Interrupt Controller. Check section “Interrupt
Controller” for the actually selectable sources and how to
select them.
In the BasicCAN and the FullCAN versions, all the communi-
cation objects have the same, maximum size of 16 byte.
Unassigned storage locations in the data area of a CO can
be freely used.
Rx/Tx buffer: This is used to buffer a full telegram (ID, DLC,
data) during sending and receiving.
The maximum number of COs is limited by the time which
the CAN interface has to search for an identifier in the Com.
Area.
Global Control and Status Register: The GCS contains
registers for the configuration of the BI. It also contains error
and status flags and an identifier mask. The Error Counter
and the Capture Timer can be read from the GCS.
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timing, error status, output control registers, baud rate pre-
scalers, Tx and Rx error counters as well as the capture
timer.
25.2.3. Global Control and Status Registers (GCS)
The GCS registers can be used to determine the behavior of
the CAN interface. As well as flags for the interrupts, halt and
sleep modes, they also contain interrupt index, ID mask, bus
Global Control and Status
Communication Area
Control
Status
Error Status
Interrupt Index
ID Mask 28 ... 21
ID Mask 20 ... 13
ID Mask 12 ... 5
ID Mask 4 ... 0
Bit Timing 1
CTR
STR
ESTR
IDX
Control
Com.-Obj. 0
0
0
1
2
ID 28 ... 21
ID 20 ...13
ID 12 ... 5
ID 4 ... 0 and Control
DLC and Control
Data 0
Data 1
Data 2
Data 3
Data 4
Telegram
Descriptor
TD
IDM
BT1
BT2
BT3
ICR
Bit Timing 2
Bit Timing 3
Input Control
Data 5
Output Control
Transmit Error Counter
Receive Error Counter
Capture Timer low
Capture Timer high
OCR
TEC
REC
Data 6
Data 7
Time Stamp low
Time Stamp high
15
16
15
16
CTIM
TD
Com.-Obj. 1
Com.-Obj. 2
Data and Time Stamp
TD
31
32
Data and Time Stamp
47
TD
Com.-Obj. n
n*16
Data and Time Stamp
Control: CM = 7
n*16+15
(n+1)*16
End of Com. Area
Fig. 25–2: Memory allocation
Access modes:
Puts the CAN interface in the halt mode. Transmissions
which have been started are brought to an end. The halt
acknowledge is indicated in the status register (HACK). Re-
initialization can be carried out in the halt mode (HACK is
set). After this, the halt flag must be deleted again. After a
reset, HLT is set.
r:
read
w:
i:
w0:
w1:
write
init (BI halted)
clear
set
If HLT is set during a Tx-Tg and this has to be repeated
(error or no acknowledge), the BI stops yet. The correspond-
ing TxCO is still reserved, however, and can no longer be
operated from BI. Therefore, when HLT is set, the CA should
always be re-initialized if the last Tx-Tg has not been cor-
rectly transmitted (Status Transfer Flag is still deleted).
CANxCTR
Control Register
7
6
SLP
0
5
GRSC
0
4
EIE
0
3
GRIE
0
2
GTIE
0
1
rsvd
x
0
rsvd
x
r/w
HLT
1
Res
If HLT is set during the BI is in Bus-Off mode, the BI stops
after Bus-Off mode is finished. Flag BOFF is cleared then
and receive and transmit error counters are reset to zero.
HLT
Halt
r/w0:
r/w1:
Run.
Halt.
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SLP
r/w0:
r/w1:
Sleep
Run.
Sleep.
entered in the register CANxIDX as soon as it is free, and the
interrupt source output is triggered.
To erase a bit in the CANxESTR the user must write a one at
the appropriate place. Places at which he writes a zero will
not be changed. Because it makes sense to erase only those
bits which have previously been read, only the byte which
has been read has to be re-written.
The BI goes into the sleep mode when the sleep flag is set
and a started Tg is terminated. The sleep mode is finished as
soon as a dominant bus level is detected, or the sleep flag is
deleted.
GRSC
r0:
r/w1:
Global Rescan
Don’t rescan.
Rescan.
CANxESTR
Error Status Register
The microprocessor can set this flag in order to initiate a
transmit telegram search at the beginning of the Com. Area.
The BI resets the bit. The BI also sets the GRSC flag if the
flag RSC has been set in a telegram descriptor of a Tx-Tg
just operated, and thereby initiates a rescan. If the micropro-
cessor writes a zero, nothing happens.
7
r/w GDM
0
6
CTOV
0
5
ECNT
0
4
BIT
0
3
STF
0
2
CRC
0
1
FRM
0
0
ACK
0
Res
Read-Modify-Write operations on single flags of this register
must be avoided. Unwanted clearing of other flags of this
register may be the result otherwise.
EIE
r/w0:
r/w1:
Error-Interrupt-Enable
Disabled.
Enabled.
GDM
r0:
r1:
w0:
w1:
Good Morning
No wake-up.
Wake-up.
Unaffected.
Clear.
GRIE
r/w0:
r/w1:
Global Rx-Interrupt-Enable
Disabled.
Enabled.
GTIE
r/w0:
r/w1:
Global Tx-Interrupt-Enable
Disabled.
Enabled.
Is set by the BI when it is aroused from the sleep mode by a
dominant bus level. The user must delete it.
CTOV
r0:
r1:
w0:
w1:
Capture Time Overflow
No overflow.
Overflow.
Unaffected.
Clear.
CANxSTR
Status Register
7
6
5
EPAS
0
4
ERS
0
3
rsvd
x
2
rsvd
x
1
rsvd
x
0
rsvd
x
r
HACK BOFF
Is set by the BI when the capture timer (CTIM) overflows.
The user must delete it.
1
0
Res
ECNT
r0:
r1:
w0:
w1:
Error Counter Level
No error counter.
Error counter.
Unaffected.
HACK
r0:
Halt-Acknowledge
Running.
Halted.
r1:
Is set by the BI when it enters the halt mode. It is deleted
again when the halt mode is exited.
Clear.
Is set by the BI as soon as the transmit error counter or the
receive error counter exceeds a limit value. The user must
delete it.
BOFF
r0:
Bus-Off
Bus active.
Bus off.
r1:
BIT
r0:
r1:
w0:
w1:
Bit Error
No bit error.
Bit error.
Unaffected.
Clear.
With this flag the BI indicates whether the node is still
actively participating in the bus. If the transmit error counter
reaches a value of > 255 (overflow), the node is separated
from the bus and the flag is set.
Is set by the BI when a transmitted bit is not the same as the
bit received. The user must delete the flag.
EPAS
r0:
Error-Passive
Error active.
r1:
Error passive.
STF
r0:
r1:
w0:
w1:
Stuff Error
No stuff error.
Stuff error.
Unaffected.
Clear.
With this flag the BI indicates whether the node is still partici-
pating in the bus with active Error Frames. If an error counter
has reached a value > 127, the node only transmits passive
error frames and the flag is set.
Is set by the BI when 6 identical bits are received succes-
sively in one Tg. The user must delete it.
ERS
r0:
Error-Status
No Errors.
Errors.
r1:
CRC
r0:
CRC Error
No stuff error.
Stuff error.
Unaffected.
Clear.
This flag is set when the BI detects an error. It is set even if
an error counter is greater than 96. It means that a bit has
been set in the error status register. As soon as all the flags
in the error status register are deleted, ERS is also deleted.
r1:
w0:
w1:
Is set by the BI when the CRC received does not coincide
with the CRC calculated. The user must delete it.
As long as a bit is set in the CANxESTR, the ERS bit is also
set in the status register. If EIE has been set in the control
register, an interrupt is triggered too; i.e. the value 254 is
FRM
Form Error
r0:
No form error.
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r1:
w0:
w1:
Form error.
Unaffected.
Clear.
SYN
r/w0:
r/w1:
Sync On
Synchronization with falling edges only.
Synchronization with rising edges too.
Is set by the BI when an incorrect bit is received in a field
with specified bit level (start of frame, end of frame, ...). The
user must delete it.
BPR
r/w:
Baud Rate Pre-scaler
Pre-scaler value.
The baud rate pre-scaler sets the length of a time quantum
ACK
r0:
r1:
w0:
w1:
Acknowledge Error
No acknowledge error.
Acknowledge error.
Unaffected.
for the bit timing logic.
tQ = (BPR + 1) / f0.
With the 6-bit counter it is possible to extend tQ by a factor of
1...64. Values from 0 to 63 are allowed.
Clear.
Is set by the BI when there is no acknowledge for a transmit-
ted Tg. The user must delete it.
0: tQ = 1 / f0
1: tQ = 2 / f0
2: tQ = 3 / f0
3: tQ = 4 / f0
etc.
CANxIDX
Interrupt Index Register
7
6
1
5
4
3
2
1
1
0
1
CANxBT2
Bit Timing Register 2
r/w
Interrupt Index
7
6
0
5
TSEG2
0
4
3
2
1
0
0
0
1
1
1
1
1
Res
r/w
rsvd
TSEG1
The interrupt index indicates the source of the interrupt. If a
transmission has been the cause of an interrupt, the interrupt
index points to the corresponding telegram descriptor
(CANxIDX = 0..253). If an error has been responsible for the
interrupt, the interrupt index designates the error status reg-
ister (CANxIDX = 254). After dealing with the interrupt, the
user must eliminate the cause of the interrupt and set the
interrupt index to minus one (255 = EMPTY). As soon as
CANxIDX is empty, the BI can enter a new index and initiate
an interrupt. An interrupt can only be initiated when CANx-
IDX contains the value 255.
0
0
0
0
Res
TSEG2
r/i:
Time Segment 2
TSEG2 value.
TSEG2 determines the number of time quanta after the sam-
ple point. Permitted entries: 1...7 (result in 2...8 TQ).
TSEG1
r/i:
Time Segment 1
TSEG1 value.
TSEG1 determines the number of time quanta before the
sample point. Permitted entries: 2...15 (result in 3...16 TQ).
CANxIDM
Identifier Mask Register
CANxBT3
Bit Timing Register 3
7
6
5
4
3
2
1
0
7
6
5
rsvd
x
4
rsvd
x
3
rsvd
x
2
1
SJW
0
0
0
r/w
r/w
r/w
r/w
Identifier Mask Bits 4 to 0
x
x
x
3
r/w
rsvd
rsvd
Identifier Mask Bits 12 to 5
2
x
x
0
Res
Identifier Mask Bits 20 to 13
Identifier Mask Bits 28 to 21
1
SJW
r/i:
Synchronization Jump Width
SJW value.
0
SJW defines by how many TQs a bit may be lengthened or
shortened because of resynchronization. Permitted entries:
1...4 (result in 1...4 TQ). Values greater than 4 must not be
used.
0
0
0
0
0
0
0
0
Res
r/w0:
r/w1:
Don’t care.
Compare.
The identifier mask register is 29 bits long; the MSB is in the
MSB position in the lowest byte address. The CANxIDM
defines a mask for the acceptance of address groups. Only
the permitted bits are used for comparison with a received
identifier. Whether the mask is used can be determined indi-
vidually for each receive object.
CANxICR
Input Control Register
7
6
5
rsvd
x
4
rsvd
x
3
rsvd
x
2
XREF
0
1
REF1
0
0
REF0
0
r/w
rsvd
rsvd
x
x
Res
CANxBT1
Bit Timing Register 1
XREF
r/w0:
r/w1:
able.
External Reference
The internal reference is used.
The external reference is used where avail-
7
6
5
4
3
2
1
0
0
0
r/w MSAM
SYN
BPR
0
0
0
0
0
0
Res
REF1
r/w0:
r/w1:
nal.
Use Reference for RxD1
RxD is used as inverted input signal.
Supply voltage is used as inverted input sig-
MSAM
r/w0:
r/w1:
Multi Sample
Bus level is determined only once per bit.
Bus level is determined three times per bit.
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REF0
r/w0:
r/w1:
Use Reference for RxD0
RxD is used as input signal.
Ground is used as input signal.
The Capture Timer is incremented with a clock pulse derived
from the CAN bus. Because it can only be read byte-wise,
the low byte must be read first. The corresponding high byte
is latched at the same time. When CANxCTIM overflows, the
flag CTOV in the error status register is set. The Capture
Timer will not be incremented during CAN module sleep
mode (SLP = 1).
CANxOCR
Output Control Register
7
rsvd
x
6
rsvd
x
5
rsvd
x
4
rsvd
x
3
rsvd
x
2
rsvd
x
1
rsvd
x
0
ITX
0
25.2.4. Communication Area (CA)
r/w
Res
The CA is located in the CAN-RAM. It consists of com.
objects each of which is 16 bytes long. The CA begins at
address 0 of the CAN-RAM with the first byte of a CO. It
ends with the first byte of a CO which contains ones in its 3
MSBs (communication mode = 7 = EoCA). The following
bytes can be used by the application. If the CAN-RAM is
filled completely with COs, there is no place left and no need
to mark the end of CA.
ITX
r/w0:
r/w1:
Inverted transmission
Tx output is not inverted.
output is inverted.
CANxTEC
Transmit Error Counter
Every telegram which this node is to receive or transmit is
represented by a CO. As well as the data and the time
stamp, this also contains a header, the telegram descriptor
(TD), in which the attributes of the communication object are
stored.
7
6
0
5
4
3
2
1
0
0
0
r
Counter Bit 7 to 0
0
0
0
0
0
Res
The COs are entered in order of priority into the CA. This
starts with the highest priority (the lowest identifier). The
identifier defines the priority of a Tg. If the first eleven bits of
an ext. Tg are the same as the identifier of a std. Tg, the Tg
with standard identifier has higher priority.
CANxREC
Receive Error Counter
7
6
5
4
3
2
1
0
0
0
r
x
Counter Bit 6 to 0
25.2.4.1. Telegram Descriptor (TD)
x
0
0
0
0
0
Res
The telegram descriptor is 6 bytes (TD0 to TD5) long and
forms the beginning of a CO. Telegrams with std. and ext.
identifiers have different TDs. They differ only in the length of
the identifiers. 18 bits therefore are not allocated in the TD of
a std. Tg. They cannot be used by the application because
they are overwritten by the reception of a Tg.
CANxCTIM
Capture Timer
7
6
5
4
3
2
1
0
r
r
Timer Bit 15 to 8
Timer Bit 7 to 0
1
0
0
0
0
0
0
0
0
0
Res
Extended Addr. Format (EXF is set)
Standard Addr. Format (EXF is deleted)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
0
1
2
3
4
5
CM
RSC MID OW rsvd LCK
CM
RSC MID OW rsvd LCK
28
20
12
4
ID
ID
ID
21
28
20
ID
21
2
3
4
5
ID
18
don’t use
13
5
don’t use
ID
DLC
0 EXF RSR ACC
TIE RIE SR TS
don’t use
DLC
EXF RSR ACC
TIE RIE SR TS
Fig. 25–3: Extended and Standard TD Map
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Forms of access:
In the provide mode, RSR signals a send request from out-
side; in the fetch mode it means that a remote Tg is being
sent. It is set by the BI if a remote telegram has been
received. It is deleted as soon as the corresponding data
telegram has been transmitted.
r:
w:
i:
read
write
init (BI halted or CM = inactive)
w0:
w1:
clear
set
EXF
r/w0:
r/w1:
Extended Format
Standard.
Extended.
CM
r/i:
Communication Mode
Mode.
CM defines the type of telegram.
In order to send/receive telegrams with extended address
format, this flag must be switched on. For standard tele-
grams it is deleted.
0: Inactive
1: Send
Inactive. No participation in the bus traffic.
Send data.
2: Receive
3: Fetch
4: Provide
5: Rx-All
6: rsvd
Receive data.
DLC
r/w:
Data Length Code
Data length.
Fetch data via remote frame.
Have data fetched via remote frame.
Receive every telegram.
Don’t use (provis. EoCA).
End of Communication Area.
The DLC defines the number of data bytes transmitted. Only
telegrams with 0 to max. 8 data bytes are transmitted. If the
DLC of a TxTg contains a value >8, the entered DLC and
exactly 8 bytes will be transmitted. In the case of RxTgs the
received DLC, and therefore also values > 8 will be entered
by BI.
7: EoCA
As long as the CO is inactive (CM = 0) or locked (LCK =
TRUE), the BI accesses the first byte of the CO only by read-
ing. All other bytes are neither read nor written. The inactive
mode is suitable therefore for re-configuration of a CO on-
line; i.e. while the node is taking part in the bus traffic.
TIE
r/w0:
r/w1:
Tx Interrupt Enable
Disable.
Enable.
Masks the Tx interrupt for this com. object.
RSC
r/w0:
r/w1:
Rescan
Don’t rescan.
Rescan.
RIE
r/w0:
r/w1:
Rx Interrupt Enable
Disable.
Enable.
If the rescan bit has been set in a transmit object just pro-
cessed, the search for active Tx objects is started at the
beginning of the communication area. Otherwise, the search
continues at this transmit object until the end of the CA is
reached. From there, the system jumps back to the begin-
ning of the CA.
Masks the Rx interrupt for this com. object.
SR
Send Request
r0:
r/w1:
Successful transmission.
Send request.
With SR, the microprocessor issues a send request. Both the
microprocessor and the BI write the SR flag. If the micropro-
cessor writes a one, the telegram is sent. The BI deletes the
SR flag after successful transmission.
MID
r/w0:
r/w1:
Mask Identifier
Don’t mask.
Mask.
If MID has been deleted, the identifier received is compared
bit-by-bit with the identifier from the telegram descriptor, i.e.
the entire identifier must be the same so that the telegram
received is transferred into this CO. If MID has been set, only
bits which are allowed in the ID mask register of the GCS are
used for the comparison.
TS
r/w0:
r/w1:
Transfer Status
Ready for Transfer.
Successful transfer.
The TS flag is set by BI after a successful transfer and is
deleted by the microprocessor after a com. object has been
processed.
OW
r/w0:
r/w1:
Overwrite
Don’t overwrite.
Overwrite.
25.2.4.2. Data Field
When OW is set, the com. object may be overwritten even if
the application has not yet fetched the contents (TS set). The
BI must of course obtain right of access (LCK deleted).
The data field consists of 8 Byte. They are filled with tele-
gram data according to the DLC. Unused data bytes (DLC
less than 8) can be used by the user.
LCK
r/w0:
r/w1:
Lock
25.2.4.3. Time Stamp
BI has right of access.
BI does not have right of access.
TIMST
Time Stamp
Counter value.
Lock determines the right of access for the BI.
r:
The last two bytes in the CO are used for the time stamp.
ID
Identifier
r/i:
Identifier.
At each SoF (Start of Frame) the free-running 16-bit counter
CANxCTIM is loaded into a register. When the Tg has been
correctly transmitted, this register is copied to the two time
stamp bytes of the corresponding CO.
The ID contains the address of the telegram. 11 bits in the
standard mode or 29 bits in the extended mode.
ACC
r/w0:
r/w1:
Access
CPU does not have right of access.
CPU has right of access.
Access determines the right of access for the CPU. The CPU
should not modify this flag after initialization. In operation
mode only the BI modifies it and the CPU reads it.
RSR
r/w0:
r/w1:
Remote Send Request
Remote telegram received.
Corresponding data transmitted.
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Data 5
Data 6
Data 7
14 Time Stamp low
15 Time Stamp high
Fig. 25–4: Time stamp
25.3. Application Notes
Special In and the TX port has to be configured Special Out.
Refer to “Ports” for details.
25.3.1. Initialization
After reset, a CAN Module is in standby mode (inactive).
For entering active mode of a CAN, set the respective enable
bit (Table 25–1).
Prior to entering active mode, proper SW configuration of the
U-Ports assigned to function as RX input and TX output has
to be made (Table 25–1). The RX port has to be configured
Table 25–1: Module specific settings
Module HW Options
Name
Initialization
Enable Bit
SR0.CAN0
SR0.CAN1
SR0.CAN2
Item
Address Item
Setting
PM.U20 CAN0-RX U2.1 or U4.3 special in
CAN0-TX U2.0 or U4.2 special out
CAN1-RX U6.1 special in
CAN0
CAN1
CAN2
CAN0-RX input multiplexer
CAN0-TX output multiplexer
CAN1-TX U6.0 special out
CAN2-RX U8.5 special in
CAN2-TX U8.4 special out
In the initialization phase, a configuration of the CAN node
takes place. The mode of operation of the BTL and the bus
coupling is set. The communication area is created in the
CAN-RAM. The different telegrams are specified in it.
The CA must be created in the CAN-RAM. The different COs
are created one after the other starting at the address 0. It is
important at this point that the three MSBs have been set in
the first byte after the last CO, i.e. at an address divisible by
16 (CM = End of CA). This is not necessary if the CAN-RAM
is completely filled with COs.
The CAN node must be halted (HACK = TRUE) to carry out
the initialization. After a reset, the flags HLT and HACK are
set and initialization can take place. If initialization is required
on-line, the flag HLT must be set. However, the BI must ter-
minate any current transmission before it comes to a halt.
For the user this means that he must wait until HACK has
been set. If HLT is deleted after initialization, then BI begins
to participate in the bus traffic and to scan the CA for tasks.
Communication mode (CM), identifier, data length code,
extended format flag (EXF) and remote send request flag
must be initialized in each CO. Lock flag (LCK) must be
deleted and access flag (ACC) must be set in order that the
BI may also view this CO. Transfer status flag (TS) must be
deleted so that interrupts are not initiated erroneously.
During initialization, the error status register (CANxESTR)
and the interrupt index (CANxIDX) should be deleted, other-
wise no interrupts can be initiated.
25.3.2. Handling the COs
25.3.2.1. Principles
If telegrams with different identifiers are to be received in a
single CO, the identifier mask register must be initialized.
This defines which bit of the ID received must be the same
as the ID in the CO.
If the user wishes to access a CO, then he must lock out the
BI from access to it. Also the BI reserves access for itself to
one CO. In this case the user may not have access. When
scanning the CA, the BI ignores inactive or locked COs; i.e. it
reads only the first byte and then jumps to the next CO.
Bit timing registers 1, 2 and 3 and the output control registers
1 and 2 must be initialized in all cases.
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Reservations Procedure
25.3.2.3. Transmit Telegram
CM = Send
If the user would like to access a com. object, then he must
first set LCK. Then he must read ACC. If it is TRUE, he has
right of access. After the operation he must delete LCK.
A transmit telegram is used to send data. How many data
bytes will be sent is fixed in the DLC. The data is entered
directly after the TD. Unused data bytes can be freely used
by the user. If after the transmission of this telegram the user
would like the next Tx-Tg in the CA to be sent, he deletes the
RSC flag. If he sets the RSC, then the transmit search starts
again at the beginning of the CA. The RSR flag has to be
deleted.
LCK = TRUE;
if (ACC == TRUE)
{
/* CPU has right of access */
}
LCK = FALSE;
_______________ or _________________
LCK = TRUE;
The set SR flag tells BI that this telegram is to be sent; SR
can be likened to a postage stamp. The TS flag must be
deleted before the CO is released with the deletion of LCK.
while (ACC == FALSE)
{
/* wait until BI is ready */
}
If the BI finds a CO whose SR flag has been set, it reserves
this (ACC = FALSE) and reports it ”ready to send”. It will be
transmitted as soon as no higher-priority telegrams occupy
the bus. After successful transmission, it deletes the flag SR
and sets TS. The setting of ACC re-releases the CO.
Whether an interrupt will be triggered depends on whether
CANxIDX in the GCS contains the value minus one (255)
and transmit interrupts are permitted.
/* CPU has right of access */
LCK = FALSE;
Fig. 25–5: Access to a CO by the user
When the BI is accessing a com. object, it first deletes ACC
and then reads LCK. If LCK is FALSE, it has right of access.
The user should now reserve the CO, reset the flag TS and
delete CANxIDX so that other interrupts can also be
reported. Should he wish to send further data, he can now
enter this.
ACC = FALSE;
if (LCK == FALSE)
{
/* BI has right of access */
}
25.3.2.4. Receive Telegram
ACC = TRUE;
CM = Receive
Fig. 25–6: Access to a CO by the BI
With a receive telegram, data is received. If the EXF flag and
the unmasked bits of the identifier of a received telegram are
the same as those of a receive CO, the telegram will be cop-
ied to the CO. ID, DLC and data bytes are overwritten by the
received ID, DLC and data. Only as many data bytes as the
received DLC specify will be overwritten (max. 8). The DLC
actually received will be entered. A permitted receive CO is
only used when TS has been deleted or OW has been set.
The BI does not wait at a CO until it becomes free.
The BI scans the CA from beginning to end. After a TxTg has
been transmitted, the next TxTg entered is reported ready to
send.
It makes sense to enter the COs in the CA in order of their
priority. The priority is determined by the ID. The lowest ID
has the highest priority. If the first bits of an extended ID are
identical with a standard ID, the standard ID has higher prior-
ity. The CO with the highest priority is at the beginning of the
CA. This ensures that Tx-Tgs with high priority are transmit-
ted first when a rescan is initiated.
Once a telegram has been received and copied to a CO, the
flag TS is set. An interrupt will also be initiated if receive
interrupts are permitted and CANxIDX contains the value
minus one (255).
If the user detects the reception of a telegram (TS set), he
must reserve the CO. Then he can read the data and, before
releasing the CO again, delete TS.
25.3.2.2. Configuration
A CO may be configured only in the inactive and/or locked
mode or when HACK has been set. Otherwise it can lead to
access conflicts between the user and BI.
25.3.2.5. Receive All Telegrams
CM = Rx-All
The communication mode (CM) is determined in the configu-
ration phase. The identifiers are also entered. The flag EXF
must not be overlooked. The flag RSR and DLC determine
whether and how many data bytes will be transmitted in the
telegram. The interrupts can be permitted. In case of a
receive telegram it is necessary under certain circumstances
to set the flags MID and OW. In case of a transmit telegram,
the flag RSC must be adjusted.
If, while searching for an RX-CO, the BI comes across a free
Rx-All-CO, the received telegram will be entered here with-
out regard to ID and EXF.
Rx-All-COs should be applied at the end of the CA.
25.3.2.6. Fetch Telegram
CM = Fetch
A fetch CO is used to request data from another node. This
is done by sending a telegram with the identifier of the
desired data. The remote transmission request flag is set in
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this Tg. No data is therefore sent with it. If another node has
the desired data available, this is transmitted with the same
ID as soon as bus traffic allows.
If a telegram with a DLC greater than 8 is received, this value
will be written into the DLC of the CO, but exactly 8 bytes of
data will be copied.
In this mode, only the reception of the data telegram can trig-
ger an interrupt.
If the DLC of a Tx-CO contains a value greater than 8, this
DLC will be transmitted, but only 8 bytes of data.
The sequence of a fetch cycle is represented for the user in
pseudo-code.
25.3.2.9. Overwrite Mode
The BI normally processes a CO only when the transfer sta-
tus TS has been deleted; i.e. the user has processed the CO
since the last transmission. In the case of COs with which
telegrams are received, the TS flag can be by-passed. If
overwrite (OW) is permitted, the BI may overwrite a previ-
ously received telegram. When accessing data therefore, the
user always receives the most up-to-date data.
if (TS == FALSE && SR == FALSE) /* CO is empty */
{
LCK = TRUE;
/* claim CO */
/* wait until BI released this CO */
while (ACC == FALSE) {/* do anything else */}
SR = TRUE;
TS = FALSE;
LCK = FALSE;
}
/* send this Tg */
/* release CO */
25.3.3. Interrupts
All interrupts are enabled or disabled by the global interrupt
enable flags, GTIE for Tx interrupts, GRIE for Rx interrupts
and EIE for error interrupts in the GCS register. This is the
only location for enabling error interrupts. A Tx interrupt can
be enabled in the corresponding CO with the Tx interrupt
enable flag TIE. An Rx interrupt can be enabled in the corre-
sponding CO with the Rx interrupt enable flag RIE.
The BI now transmits the telegram with the RTR flag set. The
other node receives the Tg, provides the data and returns
the telegram with RTR flag deleted. After the reply telegram
has been received, the BI sets the flag TS. The user waits for
the data.
/* wait for answer */
while (TS == FALSE) {/* do anything else */}
An interrupt can only be initiated when the interrupt index
CANxIDX is empty (minus one). To initiate an interrupt, the
BI enters the number (0...253) of the appropriate CO in the
CANxIDX. When an error interrupt is involved, the number
254 is entered.
LCK = TRUE;
/* claim CO */
/* wait until BI released this CO */
while (ACC == FALSE) {/* do anything else */}
/* copy data */
TS = FALSE;
LCK = FALSE;
The BI attempts to initiate an interrupt immediately after suc-
cessful transfer. If this does not work (CANxIDX not empty),
the interrupt is pending (also error interrupt).
/* release CO */
Instead of waiting for the answer, it is also possible for notifi-
cation to be given by a receive interrupt.
The BI permanently scans the CA. If, while doing so, it finds
a CO whose interrupt condition is satisfied (e.g. TIE and TS
are set), it generates an interrupt. This means that interrupts
not yet reported will not be reported in the sequence of their
occurrence, but in the sequence in which they are discov-
ered later.
25.3.2.7. Provide Telegram
CM = Provide
The interrupt service routine of the user must read the CANx-
IDX. The interrupt source is stored here. If CANxIDX points
to a CO (0...253), the user must reserve this. After this, he
must first delete TS so that this CO does not initiate an inter-
rupt again. Only then he may release CANxIDX (CANxIDX =
255) so that the BI can enter further interrupts.
A provide CO is used to prepare data for fetching. It is the
counterpart of a fetch CO. In a provide CO the RSR flag is
cleared. It will be set and deleted by the BI. The data can be
prepared in two ways:
In the first case, the user does not become active until a
remote frame has been received (Rx interrupt or polling from
RSR). After the CO has then been reserved, the data is writ-
ten, the SR flag is set and the CO is released. The BI
ensures then that the data is transferred back.
25.3.4. Rescan
The normal transmit strategy searches for the next transmit
CO in the CA. If all the transmit COs are ready to send, they
are processed one after the other. This is a democratic strat-
egy.
In the second case, the data has already been entered, SR
has been set and TS deleted before the request. When the
remote frame is received, the user does not need to become
active. Also, no Rx interrupt will be initiated. The data is sim-
ply fetched. In this case the requesting RTR telegram must
contain the correct DLC because, with an RTR telegram too,
a received DLC overwrites the local DLC.
If higher-priority TxTgs are reported in the meantime, these
are not processed until the complete list has been finished.
With rescan, the search for Tx telegrams is started again at
the beginning of the CA. By this means the user can force
the normal strategy to be interrupted and a search to be
made first of all for higher-priority TxTgs. A transmit CO
already reported will of course be transmitted first.
In both cases a Tx interrupt can occur after the data telegram
has been transmitted.
25.3.2.8. Data Length Code
The rescan requirement can be achieved dynamically, when
a transmit CO is reported, by setting the global rescan flag
GRSC.
The data length code is 4 bits long. It can therefore contain
values between 0 and 15. In principle, no more than 8 bytes
can be transmitted. Empty data telegrams (DLC = 0) are also
possible.
It is also possible to configure a rescan strategy statically.
Each Tx-CO has the rescan flag RSC. If it is set, the system
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starts from the beginning with the transmit search after this
CO has been processed. It is possible, for instance, to set
RSC in the low-priority Tx-COs. Each time a low-priority Tx-
CO has been handled, the search continues for higher-prior-
ity objects.
If the BI has received an identifier complete, it starts at the
beginning of the CA with the search for an appropriate Rx-
CO. If a rescan is initiated, the BI also starts from the begin-
ning with the transmit search.
25.3.7.1. Buffers
The user must ensure that each Tx-CO is processed.
Several successive receive COs may be allocated with the
same identifier. The BI stores a received Tg in the first free
Rx-CO. Using this mechanism it is possible to construct a
receive buffer. If RIE is set in the last CO, the CPU is not
informed until the buffer is full.
25.3.5. Time Stamp
The time stamp of a CO shows the user how much time has
elapsed since the transmission of the object. For this pur-
pose, he compares the time stamp with the capture timer
CANxCTIM. Because the time stamp contains the value of
the CANxCTIM at the time of the start of transmission, the
difference is proportional to the time which has elapsed.
25.3.7.2. Basic/Full CAN
For a Basic CAN application, a single Tx-CO will be used. All
outgoing telegrams will be transmitted with this. The user
must receive all Rx-Tgs and must himself decide whether he
needs it (acceptance filtering). For this case it is possible to
use an Rx-All-CO. But it is necessary to ensure that this can
be processed before the next Tg arrives.
The time stamp mechanism also enables network-wide syn-
chronization. A master transmits a Tg. All nodes note the
transmission time (local time). Then the master transmits its
own (global) transmission time. The difference between local
and global time shows by how much one’s own clock (timer)
is wrong.
For this reason, it is a good idea to employ 2 or 3 Rx-All-COs
as buffers after the Tx-CO.
25.3.6. Errors
In the case of a FullCAN application, one uses the built-in
acceptance filtering and sets up a CO specifically for each
desired Rx-Tg and Tx-Tg.
In the error status register (CANxESTR) error messages and
status data are collected which can generate an error inter-
rupt. As long as a flag is set in the CANxESTR, the flag ERS
is also set in the status register. This means that the value
254 is written in CANxIDX and an interrupt is generated
when EIE has been set.
If the CAN-RAM is not big enough, mixed strategies are also
possible. The acceptance filtering, of course, burdens the
CPU with communication tasks.
An error interrupt is deleted by first deleting CANxESTR and
then releasing CANxIDX.
Tx-Obj
Rx-Obj
Rx-Obj
TD:
CM=Send
The 5 flags BIT, STF, CRC, FRM and ACK originate from the
protocol manager. The flag GDM (Good Morning) is not an
error flag. GDM is set when the BI is aroused from the sleep
mode by a dominant bus level.
The flag ECNT (error counter level) indicates that an error
counter has exceeded a limit value. It is set when the trans-
mit error counter exceeds the values 95, 127 and 255 or the
receive error counter exceeds the values 95 and 127.
TD:
CM=
Rec. All
When the BI is in the Bus-Off mode, it no longer actively par-
ticipates in the bus traffic. Nor does it receive telegrams, but
continues to observe the bus. As soon as the BI has
detected 128 x 11 successive recessive bits, it reverts from
the Bus-Off mode to the error-active mode. At the same time
the error counters are cleared.
TD:
CM=
Rec. All
A Bus-Off sequence triggers two interrupts, if the error inter-
rupt is enabled. The first interrupt (ECNT=TRUE) indicates
that the transmit error counter has exceeded the value 255.
This means that the module is in the Bus-Off mode now
(BOFF=TRUE). The receive error counter is used to count
the reception of 128 x 11 successive recessive bits in the
Bus-Off mode. This is the reason for the second interrupt
(ECNT=TRUE), which indicates that the receive error
counter has exceeded the value 95 (warning level). The sec-
ond interrupt can be ignored in Bus-Off mode. The error
interrupt can be disabled during Bus-Off mode to avoid this
second interrupt.
TD:CM = 7 End of Com. Area
Fig. 25–7: Example: CA of a BasicCAN with 2 Rx-buffers
25.3.7. Layout of the CA
The CA contains all COs beginning with the lowest identifier.
The three MSBs must be set in the byte after the last CO
(End of CA).
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Rx-Obj
TD:
Tx-Obj
TD:
CM=
CM=Send
Receive
Tx-Obj
Tx-Obj
Rx-Obj
TD:
CM=Send
TD:
CM=
Rec. All
Rx-Obj
Rx-Obj
TD:
CM=Send
TD:
CM=
Rec. All
TD:
CM=
Receive
TD:
CM=
Rec. All
Rx-Obj
Rx-Obj
TD:
CM=
Rec. All
Rx-Obj
Rx-Obj
TD:
CM=
Rec. All
TD:CM = 7 End of Com. Area
TD:
CM=
Rec. All
Fig. 25–9: Example: CA of a BasicCAN with 4 Rx-buffers
25.3.7.3. Bus Monitor
TD:CM = 7 End of Com. Area
With some Rx-All-COs it is possible to construct a user-
friendly bus monitor. The CPU has merely to observe
whether anything has been received. The contents of the CO
must be stored. The transmission time can be calculated
from the time stamp.
Fig. 25–8: Example: CA of a FullCAN with 2 Rx-objects, 2
Tx-objects, and 2 Rx-buffers
25.3.7.4. Maximum number of COs
The maximum number of COs depends on the size of the
CAN-RAM, the baud rate, the system clock, the BI and the
CPU accesses to the CAN-RAM.
– The BI can handle a maximum of 254 objects. The limiting
factor is the 8-bit register CANxIDX in the GCS. CANxIDX
can contain 256 different values. The values 255 (empty)
and 254 (error) are reserved. The remaining values
0...253 can indicate 254 objects.
– The maximum number of COs is, of course, limited to a
greater extent by the size of the CAN-RAM. The BI can
only access the CAN-RAM. Therefore the CA can only be
applied there.
16 bytes are reserved for each CO. One extra byte for
coding EoCA after the last CO must not be forgotten. The
CAN-RAM area after the EoCA is freely available to the
user. No EoCA is necessary if the CAN-RAM is filled com-
pletely with COs.
There is a maximum number of 32 COs possible in a
CAN-RAM of 512 bytes.
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– The value thus calculated is further limited, however, by
the CPU accesses to the CAN-RAM. Each I/O cycle
required by the CPU to write or read data in the CAN-
RAM is missing from the BI. The BI is halted by CPU
accesses. This reduces the time which the BI has to scan
the CA. Where there is a reduced CPU clock, in particular,
the user should have only limited access to the CAN-
RAM.
CAN RAM Size
Max. Number CO = ----------------------------------------
16
– The next limiting factor can be calculated from the baud
rate and system clock. After the BI has received an identi-
fier, it must be possible for it to scan the entire CA before
the telegram comes to an end.
With the ARM CPU accessing CAN RAM, it is easy to
block the BI’s CAN-RAM access over a long time. The
ARM CPU can make a memory access with each I/O
cycle, leaving nearly no I/O cycles to the BI.
tCA SCAN
Max. Number CO = -----------------------
tCO SCAN
In the above example (8 MHz, 1 MBd), tCA Scan lasts 224
I/O cycles (28 * 8). The BI needs 144 I/O cycles to scan
16 COs leaving 80 I/O cycles to the CPU to process a
telegram. It is not necessary to process more than one
telegram during transmission of one telegram. As long as
the COs are managed via interrupt, 80 I/O cycles should
be more than enough to read or write a CO.
9
tCO SCAN = ----
f0
tCA SCAN = 28 tBit
tBit = ( 3 + TSEG1 + TSEG2 ) tQ
In this worst case scenario the BI needs 288 I/O cycles to
scan 32 COs. This is possible at an input frequency of 8
MHz and up to baud rate of 500 kBd. In a more realistic
estimation (average tCO Scan = 6) the BI needs 192 I/O
cycles to scan 32 COs leaving 32 I/O cycles to the CPU to
process a telegram. This means 1 MBd is possible even
with 32 COs, as long as the COs are managed via inter-
rupt only.
BPR + 1
tQ = --------------------
f0
tCA Scan is the time from having received an ID to the end
of a minimum telegram (11 bit ID, no data), which is at the
BI’s disposal to scan the CA.
tCO Scan is the worst case time needed by the BI to pro-
cess an object (A value of 6 I/O cycles is a more realistic
size than 9).
Due to this, care has to be taken when using free CAN-
RAM (after EoCA). It is not possible here, to make an
assumption about how many accesses a non CAN routine
makes to its data storage.
With an input frequency of 8 MHz and a baud rate (1/tbit)
of 1 MBd, the BI could handle 24 COs. Naturally, this
value needs to be rounded off.
25.4. Bit Timing Logic
In the bit timing logic the transmission speed (baud rate) and
the sample point within one bit will be configured. By shifting
the sample point it is possible to take account of the signal
propagation delay in different buses. Furthermore, the nature
of the sampling and the bit synchronization can also be
defined.
that the edge lies inside this segment. The sync.seg is
always one time quantum long.
Prop.Seg.
This part of a bit is necessary to compensate for delay times
of the network. It is twice the sum of the signal propagation
delay on the bus plus input comparator delay plus output
driver delay.
25.4.1. Baud Rate Pre-scaler
Phase Seg.
The baud rate pre-scaler is a 6-bit counter. It divides the sys-
tem clock down by the factor 1...64. The output is the clock
for the bit timing logic. This clock TQCLK defines the time
quantum (tQ). The time quantum is the smallest time unit into
which a bit is subdivided.
Phase segments 1 and 2 are necessary to compensate
phase differences. They can be lengthened or shortened by
resynchronization.
Sample Point
The bus level is read at this point and interpreted as a
received bit.
25.4.2. Bit Timing
TSEG1
A bit duration consists of a programmable number of TQCLK
cycles. The cycles are split up into the segments SYNCSEG,
TSEG1 and TSEG2.
The CAN implementation combines propagation delay seg-
ment and phase segment 1 to form time segment TSEG1.
TSEG2
TSEG2 corresponds to phase segment 2.
25.4.2.1. Bit Timing Definition
SJW
Sync.Seg.
The synchronization jump width gives the maximum number
of time quanta by which a bit may be lengthened or short-
ened by resynchronization.
It is expected that a bit will begin in the synchronization seg-
ment. If the bit level changes, the resynchronization ensures
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tBit = tSYNCSEG + tTSEG1 + tTSEG2
BPR + 1
tQ = --------------------
f0
tSYNCSEG = 1 tQ
tTSEG1 = (TSEG1 + 1) tQ
tTSEG2 = (TSEG2 + 1) tQ
tSJW = SJW tQ
tBit
1 Timequant
Sample Point
Sync Seg
tSYNCSEG
Prop Seg
Phase Seg1
Phase Seg2
tTSEG2
def. CAN-SPEC
impl. CAN
tTSEG1
Fig. 25–10: Bit Timing Definition
The baud rate is then calculated as follows:
With a baud rate of 1 MBd a bit should be at least 8 tQ long.
In case of a triple sample mode (MSAM = 1), the following
boundary condition must also be observed:
1
BR = -------
tBit
tTSEG1 ≥ tPROP + tSJW + 2tQ
( BPR + 1 ) ( 3 + TSEG1 + TSEG2 )
tBit = ----------------------------------------------------------------------------------------
f0
f0
The triple sample mode offers better immunity to interference
signals. In the single sample mode a higher transmission
speed is possible.
BR = ----------------------------------------------------------------------------------------
( BPR + 1 ) ( 3 + TSEG1 + TSEG2 )
For high baud rates and maximum bus length, neither SYN
nor MSAM may be switched on. Bosch advises against both
adjustment facilities. When an input filter matched to the
baud rate or a bus driver is used, the triple sample mode is
not necessary. If SYN is set, synchronization will also be
made with the soft edge (dominant to recessive) and this will
mean higher demands being imposed on the clock toler-
ances.
25.4.2.2. Bit Timing Configuration
Certain boundary conditions need to be observed when pro-
gramming the bit timing registers. The correct location of the
sample point is especially important with maximum bus
length and at high baud rate.
25.4.2.3. Synchronization
tTSEG2 ≥ 2 tQ
= Information Processing Time
The BTL carries out synchronization at an edge (change of
the bus level) in order to compensate for phase shifts
between the oscillators of the different CAN nodes.
tTSEG2 ≥ tSJW
tTSEG1 ≥ 3 tQ
25.4.2.4. Hard Synchronization
tTSEG1 ≥ tTSEG2
tTSEG1 ≥ tPROP + tSJW
Hard synchronization is carried out at the start of a telegram.
The BTL ensures that the first negative edge is in the sync.
seg.
The information processing time is the internal processing
time. After reception of a bit (sample point) this time is
needed to calculate the next bit for transmission.
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25.4.2.5. Resynchronization
edges lie in the sync. seg. TSJW is the maximum time a bit
can be lengthened or shortened.
Resynchronization takes place during the transmission of a
telegram. If the BTL detects an edge outside the sync. seg., it
can lengthen or shorten the bit. If it detects the edge during
TSEG1, tTSEG1 is lengthened. If it detects the edge during
TSEG2, tTSEG2 is shortened. In this way, it ensures that the
Two forms of resynchronization are possible. In normal oper-
ation, synchronization is carried out only with the negative
edge (recessive to dominant). At low transmission speeds,
synchronization can also be carried out with the rising edge
(SYN = 1).
25.5. Bus Coupling
The bus coupling describes the connection of the internal
signals rx (receive line) and tx (transmit line) to the pins to
the CAN bus.
Table 25–3: Logical Level Receiving
The output pins are push/pull drivers for TLL levels. The
input pins are also designed for TTL levels.
RxD rx
Bus Level
Remarks
Integrated transceivers (Siliconix Si9200, Philips 82C250
etc.) are available for physical coupling in the high-speed
range in compliance with ISO/DIS 11898.
0
0
0
1
1
1
0
1
1
0
0
1
x
0
1
0
1
x
1
1
0
0
1
0
Don’t work
Recessive
Dominant
Dominant
Recessive
Don’t work
For a laboratory system a “minimum bus” can be constructed
by means of a wire-Or circuit.
inverted
direct
To utilize the advantages of differential signal transmission,
an analogue comparator is necessary.
ITX
0
tx
TxD
1
1
+5V
Bus
+5V
REF1
1
RxD
0
CAN
OR
rx
+5V
0
1
REF1
rx
1
RxD
REF0
0
0
OR
Fig. 25–11: Bus Coupling
1
REF0
ITX
tx
0
1
Table 25–2: Logical Level Transmitting
TxD
ITX
0
tx
0
TxD
0
Bus Level
Dominant
Recessive
Recessive
Dominant
Remarks
1
direct
0
1
1
Fig. 25–12: Minimum Bus
1
0
1
inverted
1
1
0
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26. DIGITbus System Description
26.1. Bus Signal and Protocol
The DIGITbus is a single line serial master-slave-bus that
allows clock recovery from the sign stream. Data on the bus
are represented by a pulse width modulated signal. There
are three different signs:
address length is one bit. The minimum data field length is
zero bit.
Telegrams with more than one data field are allowed too. For
instance TTTTAAATDDDDTDDDDDTT is a valid telegram
format on the DIGITbus.
“0”: 25% High Time
“1”: 50% High Time
“T”: 75% High Time
A telegram consisting of an address only is possible too. The
length of the data field is zero in this case.
bit time
T
T
Address
T
T
T
T
T
T
0
1
T
A data field is preceded by an address field and separated
from this by a single “T”. It is followed by one T-Sign. After
reception of two T-Signs the telegram is finished and valid.
A permanent high bus (100% High Time) means the bus is
passive high. The bus is active if there are consecutive T-
Signs, ones or zeros.
In the idle phase (no information exchange) of the bus traffic,
only the bus clock is transmitted.
A permanent low bus (0% High Time) is interpreted as bus
reset or failure indicator. Reasons may be shorts or opens or
even a low level forced by a bus node to indicate an internal
failure or reset condition.
T
T
T
T
T
T
T
T
T
T
T
T
The sign “T” is used to provide a system wide clock for the
bus nodes and to separate the address and data fields and
consecutive telegrams.
After the reception of two consecutive T-Signs all bus nodes
have to be prepared to receive a new telegram starting with
an address field. They are ready to send an address after the
reception of four consecutive T-Signs.
A telegram normally consists of an address and a data field
separated by one “T”. These fields may be as long as neces-
sary. Thus the length of an address or data field may carry
information. The end is marked by a “T”. The end of a tele-
gram is marked by two T-Signs.
The modification of a T-Sign to a zero or one is done by pull-
ing the bus line to low (dominant state) at the right time. This
is done by a master sending an address or a data bit or by a
slave sending a data bit.
In case of reading data from a slave, the master first sends
the address. After receiving the address the slave waits one
T-Sign and then modifies the following T-Signs to zeros and
ones which the master can recognize.
T
T
Address
T
Data
T
T
T
One system implementation may be confined to certain
address and/or data field lengths, thus reducing the hard-
ware or software requirements.
Slaves do not have the possibility to become active on the
bus if they want to communicate a local event or if they need
data from a master. It is a polling bus. Only a master is able
to send an address. The master has to scan the slaves for
their data. But it is possible to transfer data from one slave
directly to another slave. The master has to transmit an
address for which one slave is the source and the second
slave is the destination. Telegrams on the bus are broad-
casted. Each bus node may receive them.
The transmitter of an address has to guarantee that the
address is preceded by four T-Signs at least.
An isolated data field is not possible. Each non “T”
sequence, which is preceded by two or more consecutive T-
Signs must be interpreted as an address. An address field is
valid after the reception of the following “T”. The minimum
26.2. Other Features
There are two possibilities for a slave to signal a local event
to the master. They are called wake-up and bus reset.
level. This will awake the master who has to store this event
in a flag, to start the bus clock and to scan the bus for the
source of this event. The minimum low time of the reset
pulse is 1/16 of the nominal bit time (1/Baudrate).
26.2.1. Wake-up
If the DIGITbus is passive high (permanent high level for
more than one bit period) a slave may pull the bus line to low
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effect the phase correction mechanism allows the bus node
to adjust their internal counters.
26.2.2. Bus Reset
The rising edge of a bit or bus clock is only controlled by the
bus node which generates the bus clock (clock master). No
other bus node may hold down the bus line at that moment.
When the clock master releases the bus line at the end of a
bit, he must watch the bus line. If the bus level does not rise
after at least 1/2 bit time, this must be interpreted as a proto-
col violation. Delay of 1/2 of a bit time is the latest moment
for a master. He can indicate this protocol violation if the ris-
ing edge is delayed 1/8 bit time. Slaves may use this mecha-
nism to signal an exception to the master. They must pull
down the bus for at least 2 bit times. After such an event nor-
mal communication may be impossible until the PLL of bus
nodes have synchronized again.
The master sends a special address to which the slave
answers with a single zero. The master measures the time
between the rising and the falling edge. With this value he
can calculate a phase correction value and transmit it to the
slave. The slave may use it to adjust his internal counter.
The Phase Correction has to be done for each bus node
separately.
26.2.4. Abort Transmission
The Abort Transmission feature is an option that allows the
implementation of some kind of rip cord with the DIGITbus.
On an alarm event, the SW of the sending master bus node
may break the current telegram and send another telegram
instead. The reception of an address/data field can not be
stopped. The transmission of the alarm telegram is delayed
until after the end of the reception in this case. Only the
actual sending bus node can abort the transmission.
26.2.3. Phase Correction
On a physical bus the signal edges may be delayed by the
bus load. An extra delay may be added by different trigger
edges. The bus nodes see the edges at different times. This
cause them to pull the bus line delayed. To compensate this
26.3. Standard Functions
The following standard functions have to be included in
every DIGITbus implementation.
a received address it is not sufficient to compare the value.
The length of the address must be correct too because of the
arbitrary length of the address field.
26.3.1. Send Bus Clock
26.3.5. Send Data
The Bus Clock is the sequence of T-Signs on the DIGITbus.
The rising edges of the bus signal are of constant distance.
Only one bus node may generate this Bus Clock even in a
multi master system. All bus nodes use this stream of T-
Signs to generate telegrams. The bus clock generator knows
two states. “Active Bus” means the transmission of the Bus
Clock. “Passive Bus” means permanent high bus level. “Pas-
sive Bus” may be a low power mode.
Each master must be and some slaves are able to send a
data field. A data field is preceded by an address or data field
and one T-Sign.
26.3.6. Receive Data
Each master must be and some slaves are able to receive a
data field. A data field is preceded by an address or data field
and one T-Sign. It is a good idea to verify the length of a
received data field if possible. But variable length data fields
are possible too.
26.3.2. Receive Bus Clock
Bus nodes which does not generate the bus clock need an
internal clock for their operation. They may use a separate
clock source or derive their clock from the bus clock by a
PLL. Bus nodes which use own clock sources nevertheless
have to synchronize on the bus clock if they want to transmit
or receive data.
26.3.7. Collision Detection
Collision detection together with arbitration is necessary in
multi master systems. It is necessary to avoid the distur-
bance of telegrams if two masters try to send a telegram at
the same time. As long as both transmit the same sign (one
or zero) at the same time, they don’t detect a collision. If one
master is sending a one and the other is sending a zero, a
zero will be seen at the bus. In this case the master whose
one was modified to the zero stops immediately sending. He
should receive this telegram.
26.3.3. Send Address
The Address is the first bit field in a telegram. Only a master
may send this field. The sender must guarantee, that at least
two consecutive T-Signs have been visible on the DIGITbus
before sending this field. Therefore he has to send four T-
Signs. If one of those four transmitted T-signs is disturbed,
only one of the separated telegrams is corrupted for a
receiver. Sending of an address requires synchronization on
the bus clock and, in case of a multi master system, collision
detection and arbitration capability.
The sender has to arbitrate his part of the telegram.
Write telegram: TTTTTAAAATDDDDTTTTT
Read telegram: TTTTTAAAATDDDDTTTTT
The separator (T-Sign) after an address or data field is object
of arbitration too.
In a single master system arbitration loss has to be managed
as a bus error.
26.3.4. Receive Address
Each slave and all multi master capable bus nodes must be
able to receive an address. For a receiver a valid address
field must be preceded by two consecutive T-Signs. To verify
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26.4. Optional Functions
The following optional functions may be designed into a cer-
tain DIGITbus implementation.
26.4.1. Abort Transmission
A master who is controlling the transmission of a telegram
can abort the sending of the address and data field. After
four T-Signs after the last bit he can send another, more
urgent telegram. If he is receiving a data field from a slave,
he must wait until the slave has finished the data field. Then
he can insert a new telegram.
26.4.2. Measure Pulse Width
The capability to measure the pulse width of a high pulse at
the DIGITbus may be used for a phase correction by some
bus nodes. The bus node who generates the bus clock,
sends a data read telegram to another bus node. The other
bus node answers with a data field which consists of a single
zero. The pulse width of this zero is measured by the master.
With this value he can calculate a phase correction value
and transmit it to this bus member, which may adjust its time
slots to the system dependencies.
26.4.3. Correct Phase
Bus nodes which does not generate the bus clock may use
the above described procedure to adjust their phase. They
have to answer to a special address with sending back a
zero. Afterwards they will receive with another special
address a correction value. With this value they can adjust
the point where they pull the bus line to modify a “T” to a one
or a zero.
26.4.4. Generate Wake-up
If the DIGITbus is passive high (no bus clock, always high
level), the clock master may be wake up by pulling the bus
level to low (dominant state) for 1/16 bit time at least. All
nodes without the clock master may be able to do that.
26.4.5. Receive Wake-up
If there is a low pulse of at least 1/64 bit time on a passive
high DIGITbus, the clock master must start to transmit the
bus clock by sending T-Signs. All Masters with a bus clock
generation unit must be able to do so in a system who uses
this feature.
26.4.6. Generate Reset
During active DIGITbus a slave may be allowed to pull down
the bus line longer than up to the end of the actual bit time (2
bit times at least). The rising edge at the end of the bit will be
delayed in this case. This will disturb the bus clock for all bus
nodes.
26.4.7. Receive Reset
The clock master is generating the rising edge at the end of a
bit time. He will detect the above described reset condition
and set a flag if the rising edge is delayed for at least 1/8 of
the bit time.
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27. DIGITbus Master Module
The DIGITbus is a single line serial master-slave-bus that
allows clock recovery from the sign stream. The address and
data field are of arbitrary length.
– Bus clock generation.
– Receive and transmit a telegram with address and data
field.
The DIGITbus Master module is a HW-Module for connect-
ing a single chip controller to the DIGITbus. It generates the
bus clock and manages short telegrams autonomously.
Transmission and reception of long telegrams is supported
by a FIFO each. The DIGITbus Master may be used in a sin-
gle or in a multi master bus system.
– Transmit FIFO and receive FIFO.
– Collision detection and arbitration.
– Abort transmission.
– Sleep mode.
– Bus monitor mode.
– Measure pulse width for phase correction.
– Phase correction.
Features
– Single master in a single master system.
– Clock master in a multi master system.
– Passive master in a multi master system.
– Receive wake-up and bus reset signal.
– Register interface to the CPU.
27.1. Context
Apart from reset and clock line, the interface to the CPU con-
sists of registers connected to the internal address and data
bus. An output signal may be connected to the interrupt con-
troller.
ter. This provides an easy way for the SW to hold the bus
line permanent low or high, or investigate bus level directly,
without support of DIGITbus Master HW.
An open drain output instead of a push/pull output is neces-
sary for the universal port to build a single line wired and bus.
A modified universal port builds the output logic which is con-
nected with its special input and output to the DIGITbus Mas-
+U
Universal Port with
Open Drain Output
DIGITbus
Master
from clock
divider
Port Pin
SI
DIGITbus
rx
tx
ADB
SO
R/W
Other
Transmitter
DB
Reset
Interrupt
Fig. 27–1: Context Diagram
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27.2. Functional Description
27.2.1. 3bit-Prescaler
27.2.8. Collision Detection
The programmable 3bit-Prescaler supplies the module with
clock signals. It scales down the HW option selectable clock
by factor 1, 2, 3 to 8 (see Table 27–2 on page 168). The out-
put is 64 times the bus clock. The desired input frequency
from the clock divider is hardware programmable.
The collision detection logic compares each incoming with
the actual outgoing bit. A difference is signaled to the send
telegram logic. If the module is transmitting, the send tele-
gram logic is stopped immediately and the transmit FIFO and
shift register are flushed.
27.2.2. Internal Clocks
27.2.9. Transmit FIFO
In low power mode the clock supply of the whole module with
exception of the receive bit logic can be stopped. The
receive bit logic needs a clock in low power mode too,
because it must filter and watch the bus line for a wake-up
signal.
The transmit FIFO has five entry addresses. One for the field
length of address or data field, one for a address byte, one
for a data byte, one for more address bytes and one for more
data bytes. The field length has to be written once before the
corresponding field is entered into the FIFO unless the field
length is not a multiple of 8.
27.2.3. Transmit T
An entry into the address register is inserted into the bus
clock after the reception of 4 consecutive T-signs. An entry
into the data register is inserted into the bus clock after the
reception of a non T-sign and one T-sign. Thus it is possible
to append a second data field (maybe acknowledge) after
the reception of a telegram.
The transmit T logic sends a continuous stream of T-signs if
active. It outputs a permanent high if it is inactive.
27.2.4. Transmit Bit
The transmit FIFO may be flushed to abort a transmission. It
is also flushed if the transmit telegram logic is active and a
collision is detected.
Depending on the input signals the transmit bit logic modifies
the T-signs to ones or zeros.
A phase correction can be done by adjusting the start time of
a transmit bit sequence.
27.2.10. Receive FIFO
Other bus behavior than sending zeros, ones or T-signs may
be forced by the SW using the universal port in normal mode
directly. The bus line may be released or pulled low.
The receive FIFO will be filled from the receive shift register.
It has two exit addresses. One for the field length and field
type and one for the bit field. The field length has to be read
before the corresponding field is taken from the FIFO. The
receive FIFO will be frozen if it is full. The receive shift regis-
ter will be over written.
27.2.5. Receive Bit
The receive bit logic samples the bus level at a frequency of
64 times of the bus clock. It filters the input signal and
decodes the input stream to supply the receive telegram
logic with the logical bus signals (0, 1 and T) and the receive
clock. Additional it measures the pulse width of each non T-
sign. It creates a bus reset signal if the active bus is hold
down beyond the end of a bit time. It creates a wake-up sig-
nal if there is a low level on the passive high bus.
27.2.11. Interrupt
Several flags of the status registers are connected by a logi-
cal-or to the interrupt source signal. The interrupt output can
be masked by a flag in the control register.
27.2.6. Send Telegram
The send telegram logic will be enabled by the transmit FIFO
and the receive telegram logic if four consecutive T-signs
were received. It supports the transmit bit logic with the
transmit bit sequence. If it recognizes the begin of a new
field, it waits one bit time (separator T-sign).
27.2.7. Receive Telegram
The receive telegram logic traces the bus and indicates the
state to the status register and other related modules. The
received bit field is written to the receive FIFO. The receive
telegram logic is active all the time. Even if the module is
transmitting a telegram all bits must be received too in a
multi master system, because arbitration may be lost.
Reception of own telegrams can be disabled (in a single
master system).
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CDC 32xxG-B
ADB
DIGITbus
Master
Address
Decoder
R/W
run
HW option
fDB
64 x bus clk
Transmit
T
3-Bit-Prescaler
generate bus clock
DIGITbus
Interrupt
Source
Control/Status
T-Seq.
DB
Phase
Tx Field Length
Tx Addr. Field
&
Tx Data Field
tx
Tx More Addr. Field
Tx More Data Field
wake-up/bus reset
arbitration lost
busy
0-Seq.
1-Seq.
Reset
64 x bus clk
full
Transmit
T
Bit
dat
flush
TxFIFO
TxSR
rise
Transmit
Telegram
Collision
Detection
RxSR
rxclk
Receive
Telegram
rx external only
data lost
Receive
Bit
txclk
rx
T
RxFIFO
dat
empty
64 x bus clk
Rx Field Length
Rx Field
Pulse Width
Fig. 27–2: Block Diagram
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27.3. Registers
The register mnemonic prefix “DG” stands for DIGITbus.
PSC
r/w:
Prescaler
Scaling value
Table 27–1: Register Mapping
Table 27–2: Clock Prescaler
Addr. Mnem.
Offs.
readable
writable
PSC Divide Bus Clock in kHz
by
0
1
2
3
4
5
6
7
DGC0
Control 0
fDB = 4
MHz
fDB = 5
MHz
fDB = 10
MHz
DGC1
Control 1
Status 0
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
1
2
3
4
5
6
7
8
62.5
78.1
39.1
26.0
19.5
15.6
13.0
11.2
9.8
156.25
DGS0
31.25
20.8
15.6
12.5
10.4
8.9
78.1
52.1
39.1
31.25
26.0
22.3
19.5
DGRTMD
DGTL
Rx Length
Tx More Data
Tx Length
DGS1TA
DGTD
Status 1
reserved
Rx Field
Tx Addr.
Tx Data
DGRTMA
Tx More Addr.
An “x” in a writable bit location means that this flag is
reserved. The user has to write a zero to this location for fur-
ther compatibility. An “x” in a readable bit location means that
this flag is reserved. A read from this location results in an
undefined value.
7.8
Note: With an input clock of 5 MHz, the bus clock frequency
of 31.25 kHz and its derivatives (16, 8, 4, 2, 1 kHz) can’t be
achieved. Thus, with a 5 MHz quartz the DIGITbus should be
operated in PLL mode.
DGC0
Control Register 0
7
6
GBC
0
5
ACT
0
4
RXO
0
3
X
x
2
0
1
PSC 2 to 0
0
0
0
DGC1
Control Register 1
r/w
RUN
7
6
5
4
x
x
3
2
0
1
0
0
0
0
Res
r/w
INTE
ENEM ENOF
PHASE
0
0
0
0
Res
RUN
r/w1:
r/w0:
Run
Module clock is active.
Module is not clocked.
INTE
r/w1:
r/w0:
Enable Interrupt
Enable interrupt
Disable interrupt
The module is absolute inactive if RUN is zero. Other flags
are not functional then.
GBC
r/w1:
r/w0:
Generate Bus Clock
Module generates bus clock
No bus clock
ENEM
r/w1:
r/w0:
Enable Not Empty Interrupt
Enable
Disable
ACT
r/w1:
r/w0:
Activate
ENOF
r/w1:
r/w0:
Enable Not Full Interrupt
Enable
Disable
Module is active (reception and transmission).
Module is sleeping (low power mode).
Only the receive bit logic is active in low power mode.
PHASE
Phase Correction Field
RXO
r/w1:
r/w0:
Receive External Only
Don’t receive own telegrams.
Receive all.
r/w:
Transmit phase.
The start of the transmit frame can be selected in increments
of 1/64 of a total bit time related to the rising edge. Values
between 0 and 15 are possible, but only the interval from 0 to
9 results in correct behavior.
Set PHASE to 2 if the DIGITbus is operated as clock master
(GBC = 1). This is necessary to compensate for internal
delay of 2 clocks. Refer to section 27.4.9. for further informa-
tion about phase correction.
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Bit time
Transmitted
Received
RxFIFO
NEM
0
16
32
48
0
0
16
32
48
0
Phase delay
Interrupt
Corrected
4
16
32
48
0
PHASE = Start value of transmit counter.
TxFIFO
EMPTY
NOF
Fig. 27–3: Phase Correction
DGS0
Status Register 0
7
6
x
5
4
3
2
1
0
Interrupt
w
r
x
RDL
x
x
TGV
PV
ERR
x
ARB
Fig. 27–4: Rx- and TxFIFO Timing
NEM
0
NOF
1
0
0
0
x
0
Res
ERR
r1:
r0:
Error
Fatal error.
No error
Clear flag
RDL
r1:
Receive Data Lost
Data lost
w0:
r0:
No data lost
The HW sets this flag either if a dominant level is transmitted
and a recessive level is detected (collision error), or if there
was a wrong edge within a received bit. If a collision error is
detected during transmission, the flag ARB will be set too
and transmission stops immediately. This flag has to be
cleared by the user.
This flag is set if the receive FIFO is full and the shift register
tries to store its contents to the FIFO because a new bit
arrives. In this case the FIFO is frozen but the shift register is
overwritten. It must be interpreted and cleared by the user. It
is cleared by reading an entry from the FIFO.
NEM
r1:
r0:
Rx FIFO is Not Empty
There is at least one entry to read.
Empty.
ARB
r1:
r0:
Arbitration Lost
Arbitration lost.
No arbitration loss.
Clear flag
(see Fig. 27–4 on page 169)
w0:
This flag will be set if a collision is detected during transmis-
sion. It must be cleared by the user. The transmit buffer was
flushed when ARB is true. It is impossible to write to the
transmit FIFO as long as ARB is true. Wait until flag TGV is
true before reloading TxFIFO. This is automatically done if
ARB is evaluated within the TGV interrupt subroutine only.
NOF
r1:
Tx FIFO is Not Full
There is at least one entry free.
Full.
r0:
It generates only an interrupt in the moment when the limit is
passed. It doesn’t generate interrupts when the FIFO is
empty (see Fig. 27–4 on page 169).
The Flags RDL, NEM, NOF, TGV, and PV trigger the inter-
rupt source signal (see Section 27.4.7. on page 173).
TGV
r1:
r0:
Telegram Valid
Telegram valid
Telegram not valid
Clear flag
w0:
DGS1TA
Status 1 & Tx Address Register
This flag will be set if there were received two consecutive T-
signs. It is reset by the HW if a non T-sign is received. It can
be cleared by the user if the related telegram is evaluated.
7
6
5
4
3
2
1
0
w
Transmit Address
PW5 to 0
PV
r1:
Protocol Violation
Wake-up if bus is passive high.
Bus reset if bus is active.
No trouble
r
STATE
0
1
0
0
0
0
0
0
Res
r0:
w0:
Clear flag
The first byte of an address field must be written to DGS1TA.
It must be interpreted and cleared by the user. It is set when
the receive bit logic enters or leaves state passive high or
when it enters the state passive low.
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STATE
r:
Bus State
State of receive bit logic.
Table 27–4: LEN usage, Receive and Transmit Length
LEN
2 1 0
Valid Bit Numbers
7 6 5 4 3 2 1 0
Table 27–3: Receiver States
1
2
3
4
5
6
7
0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
_ _ _ _ _ _ _ x
_ _ _ _ _ _ x x
_ _ _ _ _ x x x
_ _ _ _ x x x x
_ _ _ x x x x x
_ _ x x x x x x
_ x x x x x x x
x x x x x x x x
STATE
0 0
Bus
Passive low
Passive high
Active low
Active high
0 1
1 0
1 1
PW
r:
Pulse Width
Pulse width
The pulse width of the most recently non T-sign is stored in
this register. It is measured in increments of 1/64 of the bus
clock period.
The examples in Table 27–5 illustrate the interpretation of
register DGRTMD. They are valid for an address field (FTYP
= 1) or a data field (FTYP = 0).
DGRTMD
Rx Length & Tx More Data Register
7
6
5
4
3
2
1
0
Table 27–5: DGRTMD Interpretation Examples
w
Transmit More Data
r
RDL
NEM
FTYP EOFLD
x
LEN2 to 0
0
0
x
x
x
x
x
x
Res
More bytes of a data field must be written to DGRTMD.
6
1
0
1
0
Last byte of a field. The six right most bits
belong to the field.
The read part of register DGRTMD is associated with the
front entry in the receive FIFO (the receive field DGRTMA). It
has to be read and interpreted before the corresponding
FIFO entry.
0
A byte of a field. All bits belong to the field. At
least one byte follows.
0
Last byte of a field. Eight bits belong to the
field.
RDL
r1:
Receive Data Lost
Data lost
r0:
No data lost
≠0
Impossible.
The flag RDL from the status register DGS0 is mirrored here.
It is cleared by a read access to register DGRTMA.
NEM
r1:
Receive FIFO is Not Empty
There is at least one entry.
Empty
DGRTMA
Rx Field & Tx More Address Register
r0:
7
6
5
4
3
2
1
0
The flag NEM from the status register DGS0 is mirrored
here. FTYP, EOFLD, LEN and register DGRTMA are not
valid if NEM is false.
w
r
Transmit More Address
Receive Field
FTYP
r1:
r0:
Field Type
Address field
Data field
x
x
x
x
x
x
x
x
Res
More bytes of an address field must be written to DGRTMA.
EOFLD
r1:
r0:
End of Field
Last byte of a field
Not last byte of a field
The bytes of a received field must be read from register
DGRTMA. The meaning of this field (address or data) is
defined by the flag FTYP.
If EOFLD is set, the corresponding FIFO entry is the last part
of the actual field. The next entry, if there is one, belongs to a
new field.
Received bytes of a bit field are right aligned. The last byte of
a long bit field (with the LSB) may be filled partially. To get
the whole bit field right aligned it is necessary to shift all pre-
ceding bytes right.
LEN
r:
Length of Field
Length of valid data bit
The three bit length doesn’t limit the overall length of the cor-
responding field. The length field defines how many bits of
the front entry of the receive FIFO carry valid bits. They are
right aligned (Table 27–4). The real length of the field is
unlimited. The user must count the bytes he fetched from the
FIFO to calculate the real field length.
A read access to this register takes the top entry of the
receive FIFO. Both registers DGRTMA and DGRTMD are
overwritten by the next FIFO entry as result of a read access.
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wait until EMPTY or TGV becomes true before rewriting
TxFIFO. Setting of FLUSH clears TGV at the same time.
DGTL
Transmit Length Register
EMPTY
r1:
r0:
Tx FIFO is Empty
No transmit telegram in FIFO.
Transmit telegram in FIFO.
7
6
FLUSH
0
5
4
3
2
1
0
w
r
x
x
x
x
LEN2 to 0
LEN
w:
Length of Field
Length of address or data field.
x
x
x
x
0
0
0
Res
Res
BUSY EMPTY
x
x
x
x
x
x
These three bits correspond to the first byte of a bit field.
They define how many bits of this byte carry valid information
and should be transmitted (see Table 27–4 on page 170).
DGTL must be written before the first byte of the actual bit
field is written to the FIFO. It has only to be written once for
each bit field. The overall length of the bit field is not limited.
0
1
x
x
x
x
x
x
The Transmit Length Register is associated with the whole
field (address or data) which will be written into the transmit
FIFO. It has to be written before the first entry of the field.
BUSY
r1:
r0:
Transmitter is Busy
Busy.
Idle.
DGTD
Transmit Data Register
This flag is true as long as there is an entry in the TxFIFO or
transmission is not completed. It is set with the first entry into
the TxFIFO and reset after the transmission of the first T sign
after a telegram.
7
6
x
5
4
3
2
1
x
0
x
w
Transmit Data
x
x
x
x
x
Res
FLUSH
w1:
w0:
Flush Tx FIFO
Empty Tx FIFO and abort transmission.
No action.
The first byte of a data field must be written to DGTD.
The first byte of a bit field (with the MSB) which is entered
into DGS1TA or DGTD, may be partially filled. In the follow-
ing bytes all bits must contain valid data.
This flag will be reset by the HW autonomously. After FLUSH
27.4. Principle of Operation
27.4.1. Reset
27.4.2. Initialization
The module reset signal resets all registers and internal HW.
The same does a standby bit in a standby register.
The corresponding port must be configured special out, dou-
ble pull-down.
Setting flag RUN in register DGC0 resets all internal HW and
registers with exception of registers DGC0, DGC1, DGS0
and DGS1TA. These registers are accessible all the time,
they are not reset by any setting of the DIGITbus Master
flags.
After reset and after setting flag DGB in standby register
SR0, the DIGITbus master is inactive. The global enable flag
RUN must be set together with the appropriate prescaler
entry PSC, to activate the module.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
Internal HW are reset to an inactive state (not transmitting,
not receiving). Internal counters are reset to zero. FIFOs and
shift registers are empty. Internal representations of the bus
line are reset to passive bus level (high).
27.4.2.1. Clock Master
The flag GBC (generate bus clock) must be set, if the DIGIT-
bus master should generate the bus clock. The module acts
now as clock master of the connected DIGITbus system. It
outputs a stream of T-signs.
Registers
C0
C1
S1.TSTn
27.4.2.2. Receiver/Transmitter
reset
Setting the flag ACT activates the receive and transmit logic.
From now on all telegrams are received in the receive FIFO.
Writing to the transmit FIFO initiates transmission of a tele-
gram.
Internal
HW
and
remaining
registers
The bus clock (T-signs) must be activated some time before
the first telegram is transmitted. This is necessary, because
other modules may use a PLL for generating the internal
clock from the bus clock. No telegram shall be transmitted
before all modules have locked on the bus clock.
SR0.DGB
R Q
C0.RUN
R Q
reset
reset
Fig. 27–5: Reset Structure
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27.4.2.3. Single Master System
A telegram has been transmitted correctly, if ARB and ERR
are false and EMPTY is true.
In a single master system (no collision possible), you can
suppress reception of transmitted telegrams by setting flag
RXO (receive external only). This unburdens the CPU from
clearing the receive FIFO of those telegrams.
Transmission starts with the first entry in the transmit FIFO.
Consecutive fields should be entered before the transmis-
sion of the preceding field is finished. Take care about possi-
ble interrupts.
27.4.2.4. Multi Master System
27.4.3.1. Transmit FIFO
In a multi master system it is necessary that each transmitted
telegram is received too, because arbitration may be lost and
then the transmitter becomes a receiver. If arbitration was
not lost, the receive FIFO must be read to empty it. The flag
RXO has to be cleared in a multi master system.
SW must ascertain that there is an empty entry in the trans-
mit FIFO before writing to it. Flag NOF (not full) indicates that
there is at least one entry free. Flag EMPTY indicates com-
plete emptiness of transmit FIFO. After reset, FLUSH or ARB
wait until flag TGV is true before rewriting TxFIFO.
Table 27–6: Operating modes
Short telegrams can completely be buffered in the FIFO.
Managing long telegrams is a SW job. The SW must buffer
long telegrams and write the parts in time. The transmit FIFO
is intended to unburden the CPU from immediately reaction
on an NOF interrupt. If an entry becomes free, the SW has
time to write, as long as it needs to transmit two FIFO entries
and the contents of the transmit shift register. This time must
not necessary be the duration for sending 24 bit. May be only
one bit of each remaining FIFO entry has to be send.
RUN
GBC
ACT
RXO
Remarks
0
1
x
x
x
x
x
Standby mode
0
Passive master. Exter-
nal bus clock genera-
tion is necessary.
The transmit FIFO is not intended for telegram tracking. Only
one transmit telegram at a time shall be entered.
1
1
1
1
1
0
x
x
x
0
1
1
x
x
x
0
Clock master
Sleep mode
Active mode
27.4.4. Reception
Every non T sign is shifted into the receive shift register. If it
is full or if a T sign was received, the shift register is stored
into the receive FIFO. This is done until the receive FIFO is
full. In this case, the FIFO is frozen, but the shift register con-
tinues operation. The flag RDL indicates the latter case.
Receive all. (Recom-
mended in multi master
system)
1
x
1
1
Receive external only.
(Recommended in sin-
gle master system)
If the shift register is stored to the receive FIFO because a T
sign was received, the corresponding flag EOFLD is set,
indicating that this is the last entry of a field.
The corresponding flag FTYP is modified at the same time. If
two or more consecutive T signs were received in front of the
actual field, it is set, indicating that this field has to be inter-
preted as an address field. If only one T sign has been
received in front of the actual field, it is cleared, indicating
that it has to be interpreted as a data field.
27.4.3. Transmission
Transmission is initiated by writing a telegram into the trans-
mit FIFO.
If the field length is not a multiple of 8 bit, the total field length
modulo 8 has to be written to register DGTL. This must be
done once for each field and before any entry to registers
DGS1TA, DGTD, DGRTMA or DGRTMD. If the total field
length is a multiple of 8 it is not necessary to write the field
length to register DGTL.
The flag TGV is set if two consecutive T-signs were received.
This is the moment to read status flags and Receive FIFO.
The flags PV and ERR have to be interpreted. Even if an
error occurred, the Receive FIFO must be emptied by read-
ing it because every telegram or fragment is stored there.
Otherwise reception of the next telegram may overflow the
receive FIFO, which is indicated by flag RDL.
The first entry of a field (address or data) has to be written
right aligned to register DGS1TA (address) or DGTD (data).
Further entries of the same field, if it is longer than 8 bit, have
to be written to DGRTMA (more address) or DGRTMD (more
data). A telegram is transmitted MSB first, hence fields have
to be written to transmit FIFO MSB first.
Every time you want to read DGRTMA, it is ingenious to read
DGRTMD first, because DGRTMD and DGRTMA are over-
written with a read access to DGRTMA.
A new address field is transmitted if there were at least 4
consecutive T-signs on the bus. A new data field is transmit-
ted if there was exactly one T-sign. If the last bit of a field
was transmitted and there are no more entries in the transmit
FIFO, the transmitter stops sending. After reception of two
consecutive T-signs the telegram valid flag TGV is set. This
is the signal for the SW to evaluate whether transmission
was correct or whether an arbitration loss or an error can-
celed transmission (flags ARB, PV and ERR). In the latter
case SW must initiate retransmission.
27.4.4.1. Receive FIFO
The receive FIFO contains entries as long as flag NEM is
true.
Short telegrams can be buffered completely in the receive
FIFO. SW must buffer long telegrams and read parts of it in
time.
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27.4.5. Sleep Mode
27.4.9. Correct Phase
Only the receive bit logic is active in sleep mode. Neither
transmission nor reception of telegrams is possible.
The rising edge of the bus signal can be delayed by inner
(sampling and filter) or outer (bus load) influences. This
delayed rising edge resets a 6 bit transmit counter in the
transmit bit logic. The transmit counter pushes the bus line
low when it reaches 15 (transmitting 0) or 31 (transmitting 1).
It releases the bus line when it reaches 55.
A wake-up (passive high to low edge) is signaled by flag PV.
The DIGITbus master is not automatically activated by a
wake-up. This has to be done by SW. The flag PV can be
used to trigger an interrupt.
The transmit counter is reset to a value which contains two
zeros at the most significant position and the four PHASE
bits of the control register DGC1 at the least significant posi-
tion. This allows an adjustment of the transmitted non T
signs between 0 and 15/64 of the whole bit length.
Switching to Sleep Mode while a telegram is transmitted can
cause problems. Hence make sure, that bus clock genera-
tion is switched off only if bus is idle (T-signs).
27.4.6. Abort Transmission
27.4.10. Error
Writing a one to flag FLUSH aborts the transmission of a
telegram after completion of the actual transmitted bit, if the
DIGITbus master is the transmitter. The transmit FIFO is
emptied and another, more urgent telegram can be transmit-
ted. Transmission of the new telegram starts, as soon as 4
consecutive T signs were received after the aborted tele-
gram.
The setting of flag ERR may have one of the following
causes:
– Wrong baud rate of DIGITbus Master or other bus nodes.
– Wrong port configuration of DIGITbus Master.
– Disturbances on bus line.
– HW damaged of DIGITbus Master.
Flag TGV is cleared with a FLUSH. This is the reason why
TGV is set (and interrupt is triggered if enabled) after recep-
tion of 2 T signs, even if no telegram was aborted by FLUSH
because it happened during transmission of T signs.
27.4.11. Precautions
Don’t access DIGITbus registers in CPU Slow and Deep
Slow mode. This can cause interrupts.
Resetting of Flag TGV is the reason why an aborted address
field is marked as data field (FTYP = 0) in the RxFIFO.
If fXTAL is 5 MHz, a bus clock of 31.25 kHz is only in PLL
mode possible (Table 27–2).
It is not possible to abort a telegram or a field which is trans-
mitted by another bus node.
27.4.7. Interrupt
Five flags (RDL, NEM, NOF, TGV, PV) are connected to the
interrupt source output by an or operation. This output can
be enabled globally by flag INTE. The interrupt generation of
two flags (NEM, NOF) can be enabled locally by flags ENEM
and ENOF. A rising edge of a flag triggers the interrupt
source output.
INTE
RDL
DIGITbus
Interrupt
Source
ENEM
NEM
&
&
&
ENOF
NOF
OR
TGV
PV
Fig. 27–6: Interrupt Sources
27.4.8. Measure Pulse Width
The pulse width (high time) of every non T sign is stored with
the falling edge of the bus signal in status register DGS1TA in
the field PW. T signs doesn’t affect PW. It must be read
before the falling edge of the next non T sign.
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CDC 32xxG-B
27.5. Timings
Bus Clock
PRELIMINARY DATA SHEET
D
T
T
T
T
T
A
A
T
D
D
T
T
T
T
Tx stream
txa
Rx stream
D
T
T
T
T
T
A
A
T
D
D
T
T
T
T
TGV
NEM
ARB
collision
Fig. 27–7: Tx Timing
Bus Clock
D
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Tx stream
txa
Rx stream
D
T
T
T
T
T
A
A
T
D
D
T
T
T
T
TGV
NEM
ARB
collision
Fig. 27–8: Rx Timing
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CDC 32xxG-B
28. Audio Module (AM)
The Audio Module AM provides a gong output signal that
may be used to drive a speaker circuit.
Features
– Programmable gong frequency
– Programmable gong duration
– Programmable initial amplitude
– Gong can be stopped and retriggered
The output signal is a square wave signal with selectable
gong frequency.
The gong signal amplitude is defined by the pulse width of a
PWM signal. An internal accumulator is selectable to auto-
matically decrease this pulse width and thus the gong ampli-
tude following an exponential function.
– Generation of an exponentially decreasing gong
amplitude function without CPU interaction
1
/
32
13
13
-
+
Adder
’0x1F’
Data Bus
13
Write AMAS
13
(Start/Stop gong sound)
13
8
5
AMAS
LSBs
Amplitude - Latch (13 Bit)
MSB
Read AMAS
13
8
Data Bus
(Bit 7)
S
R
Q
AMA
COMP Amplitude=0 ?
8
HW Option AC
AM Clock
U 1.3
AM-PWM
FAMClock
AMMCA
0
&
8 Bit - PWM
VDD
&
U 1.4
AM-OUT
AM Trigger
FPWM
8-Bit Counter
&
FGong
CLK
Clear Counter
Set Prescaler-Register
5-Bit Counter
7-Bit Counter
FDecrement
CLK
CLK
Clear Counter
1
1
n
/
/(2 )
2n
Clear Counter
Set Frequency-Register
Set Decrement-Register
3
8
7
Data Bus
Write AMDEC
AMA Write AMF Data Bus
Write AMPRE Data Bus
Fig. 28–1: Block diagram of the audio module
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CDC 32xxG-B
PRELIMINARY DATA SHEET
28.1. Functional Description
The Audio Module output frequency is defined by the follow-
ing formulas:
GDF
Frequency:
ln0,5 – lnAMAS
2
F
----------------------------------------- ----------------
t
d
F
F
1
AMTrigger
AMClock
2(AMF + 1)(AMPRE + 1)
Gong
ln 1 – -----
F
= --------------------------------- = -----------------------------------------------------------------
32
Gong
2(AMF + 1)
Amplitude:
(AMAS + 1)
Ampl. ----------------------------------
(AMPRE + 1)
Every 1st..32nd cycle of the gong sound frequency (depend-
ing on the Gong Duration Factor (AMDEC.GDF)) a new
amplitude value is calculated (FDecrement). The falling edge of
the amplitude decrement frequency FDecrement is latching the
output of the adder into the amplitude latch (13 Bit) and
simultaneously the 8 MSBs into the PWM.
where the maximum amplitude is 1 if AMAS is equal to or
bigger than AMPRE. In the latter case the amplitude remains
constant until the decay mechanism has decreased AMAS
below AMPRE.
During the first low cycle of FGong following the active FDecre-
ment edge the PWM is already running with the newly calcu-
lated amplitude, but takes effect at the output not until the
next high cycle of FGong. FGong is modulating the PWM-out-
put to generate the gong sound frequency, while the
decreasing PWM-value generates an exponential decreas-
ing amplitude.
Duration:
AMF, AMPRE, AMAS and GDF are register values and
described later.
The initial gong sound amplitude is set by writing the Audio
Module Amplitude & Status Register (AMAS), this write also
starts the gong sound. An active audio module is indicated
by the read only Audio Module Active Bit (AMA) in the
AMAS.
As soon as the 8 MSBs of the amplitude latch are reaching
zero, the AMA will be reset, which deactivates the audio
module.
The sound is generated by
blocks of pulses
2 x AMF x AMPRE -> FGong
AMPRE
AMF x AMPRE
AMAS
(PWM)
One block of pulses
Fig. 28–2: Sound generation
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 36).
28.1.1. Hardware Settings
The AM clock frequency FAMClock is set by HW option AC.
28.1.2. Initialization
28.1.3. Start Gong
Prior to entering active mode, proper SW initialization of the
Ports has to be made. The ports have to be configured Spe-
cial Out. Refer to “Ports” for details.
The gong sound is started by writing the initial amplitude
value into AMAS. Simultaneously with the write to AMAS the
Flag Audio Module Active (AMA) is set, which enables the
FAMClock-input.
Three Audio Module Registers have to be set before the
gong sound can be started: the gong prescaler (AMPRE),
the gong sound frequency (AMF) and the gong duration fac-
tor (AMDEC.GDF) register.
28.1.4. Restart Gong
It’s possible to restart the gong sound simply by writing a
new initial amplitude value to AMAS independent of the
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PRELIMINARY DATA SHEET
CDC 32xxG-B
former initial value or the current value of the register. (Note:
The current amplitude value can’t be read out). The new
To stop the gong sound, just write 0x00 into AMAS. The
gong sound then will stop immediately with the writing of
0x00 (also indicated by AMA).
gong sound will start immediately with a low cycle of FGong
.
A continuous tone will never stop automatically. It has to be
stopped by writing 0x00 into AMAS.
28.1.5. Stop Gong
The gong sound will stop automatically as soon as the ampli-
tude value in AMAS reaches zero. This will reset the AMA,
which indicates the inactive audio module.
PWM
Gong
Decrement
Conditions: (F
= 15.625 kHz; F
= 601 Hz; AMDEC value = 2, F
= 150.25Hz)
after 0 s (initial)
A 100 %
zoomed
gong
after 0.146 s (0.68
τ)
B
C
50 %
output
signal
F
PWM
PWM
Pulse
Duty
0
2
3
12
14 15
26
1
13
25
FGong
Factor
after 0.398 s (1.87
τ)
15 %
4 x C
4 x A
4 x B
Gong
Output
Pin
FGong
F
Decrement
start gong
new amplitude (n.a.)
n.a.
n.a.
n.a.
n.a.
time
0.146 s (0.68τ)
0.398 s (1.87τ)
0 s
Fig. 28–3: Example sections of the audio module output signal
Each FDecrement cycle the amplitude is decreased by 1/32.
FDecrement is determined by the value of GDF in the register
28.1.6. Decay of Sound
The decay characteristic used for this gong sound is
described by the following exponential function:
AMDEC and by FGong
:
F
GONG
GDF
n
An A0 (1 - 1/32
)
F
= ---------------------
GDF = 0…5
Decrement
2
with A0 = initial amplitude (AMAS)
An = amplitude after n FDecrement cycles
With GDF settings of 6 and 7 the gong sound amplitude
update frequency FDecrement is zero (continuous tone).
n
= int (t * FDecrement
= number of decrement cycles
)
The time constant τ of the above exponential function is
defined as the time interval within which the amplitude A is
decreasing to 36.8%.
Following the above formula, n can be expressed as
lnA – lnA
n
0
------------------------------
n
1
ln 1 – -----
32
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CDC 32xxG-B
PRELIMINARY DATA SHEET
Given
n
τ
1
0, 368 = 1 – -----
32
the number n of FDecrement cycles needed to reduce the ini-
τ
tial amplitude to 36.8% is
n
32
τ
With an initial amplitude of 0xFF the total time t255->0 needed
to reach zero amplitude in the 8 Bit - AMAS is n = 193 FDecre-
ment cycles, which is approximately 6τ.
With an initial amplitude lower than 0xFF the gong sound
duration is shorter.
That means that τ is correlating with FDecrement. The higher
FDecrement, the shorter is τ.
The total time from a start amplitude A0 to an end amplitude
An is approximately calculated according to following for-
mula.
GDF
lnA – lnA
n
0
2
F
t
------------------------------ --------------------
A → A
1
ln 1 – -----
32
0
n
GONG
To sum up it can be said that the total duration of the gong
sound depends on FGong, set with AMF and AMPRE, the set-
ting of the Gong Duration Factor GDF and the setting of the
initial amplitude AMAS.
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AMAS
(MSB of amplitude latch)
260
240
220
200
180
160
140
120
100
80
36.8%
60
40
13.5%
20
5.0%
1.8%
time
32
72
96 104 112 120 128 136 144 152
168 176 184
200
192
8
16 24
40 48 56 64
80 88
160
1/F
Decrement
1
τ
2τ
3τ
4τ
5τ
6τ
no. F
-cycles
Decrement
CDC 32xxG-B
PRELIMINARY DATA SHEET
28.2. Registers
start, stop, frequency, duration) is the same. The tone is
started by writing an initial value to AMAS, but this value will
only influence the duration of the tone, not its amplitude.
AMAS
Audio Module Amplitude and Status
Register
GDF
Gong sound Duration Factor
Note
7
6
5
4
3
2
1
0
This register sets the gong sound duration in dependence of
FGong. With GDF=0 the amplitude will be decreased every
FGong - cycle, values 1 to 5 will result in a amplitude update
frequency of FGong / 2 to FGong / 32 according to this equa-
tion:
w
Initial Amplitude
r
AMA
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
Res
F
GONG
GDF
Initial Amplitude
F
= ---------------------
GDF = 0…5
Decrement
A write access to this register starts or stops the gong sound,
while the value written is the initial amplitude. Writing the
value 0x0 into this register during an active gong sound
deactivates the gong sound immediately, while writing a
value > 0x0 is restarting the gong sound immediately with
the new Initial Amplitude.
2
A value of 6 or 7 disables decrease of the amplitude, so a
continuous tone with the initial amplitude will be generated
(FDecrement = 0). To stop the continuous tone write a 0x00 to
AMAS or change the gong sound duration factor to let the
tone decay. It’s possible to change GDF during an active
gong sound (AMA = ’1’).
wnn:
w00:
(Re-)Start gong sound with initial amplitude.
Stop gong sound.
AMA
Audio Module Active Flag
Table 28–1: Definition of GDF
This flag indicates an active Audio Module generating a gong
sound.
r1:
r0:
Audio Module is active.
Audio Module is not active.
GDF
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
gong sound duration factor
1
2
AMF
Audio Module Frequency Register
Note
Res
7
6
0
5
4
3
2
1
0
4
w
x
Sound Frequency
8
-
0
0
0
0
0
0
16
With this register the gong sound frequency is programmed.
The PWM frequency is divided by twice the register value
increased by one.
The value which has to be written, resp. the resulting gong
sound frequency is calculated with:
32
continuous tone
F
AMTrigger
AMF = --------------------------------- – 1
2F
GONG
AMPRE
Audio Module Prescaler
It’s possible to write a new gong sound frequency during an
active audio module (AMA = ’1’).
Note
Res
7
6
1
5
4
3
2
1
1
0
1
w
Prescale Value
AMDEC
Audio Module Decrement Register
1
1
1
1
1
Note
Res
7
6
x
-
5
x
-
4
x
-
3
x
-
2
1
GDF
0
0
AMPRE defines the frequency of the trigger input of the
Audio Module. The AM clock input is divided by the Prescale
w
AMMCA
Value plus one to derive the trigger frequency FPWM
.
0
0
0
F
AMClock
AMPRE = ------------------------------ – 1
AMMCA
Audio Module Maximum Constant
Amplitude Flag
F
AMTrigger
w1:
w0:
Activate the AMMCA mode.
Deactivate the AMMCA mode.
AMPRE must be greater than zero.
With the flag AMMCA the Audio Module Maximum Constant
Amplitude mode is selected. If this Flag is set, the gong
sound with the maximum, not decreasing amplitude is avail-
able at the audio module output pin. The only difference
between this tone and a ’normal’ gong sound is the constant,
not decreasing amplitude. The handling of this tone (i.e.
180
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CDC 32xxG-B
29. Hardware Options
29.1. Functional Description
Hardware Options are available in several areas to adapt the
IC function to the host system requirements:
– clock signal selection for most of the peripheral modules
from f0 to f0/217 plus some internal signals (see Table 29–4
on page 183)
– Special Out signal selection for some U- and H-ports
– Rx/Tx polarity selection for SPI and UART modules
Hardware Option setting requires two steps:
1. selection is done by programming dedicated address loca-
tions in the HW Options field (see Section 29.2. on
page 182) with the desired options’ code (see Section 29.3.
on page 183).
2. activation is done by copying the HW Options field to the
corresponding HW Options registers (see Section 29.3. on
page 183) at least once after each reset.
All HW Options except these listed in table 29–1 are SW pro-
gammable.
Table 29–1: Port, Clock and CM Option
Programmability
IC
Type
IC Name
Port
Opt.
Clock
Opt.
CM.WC
M set-
ting
EMU
CDC3205G-A
CDC3205G-B
CDC3207G-B
ROM Part
mask
SW
SW
set to 0
set to 0
set to 0
mask
SW
MCM
Mask
SW
SW
SW
mask
In mask ROM derivatives the clock options and the Watch-
dog, Clock and Supply Monitors are hard wired according to
the HW Options field of the ROM code hex file. Those
options can only be altered by changing a production mask.
To ensure compatible option settings in this IC and mask
ROM derivatives when run with the same ROM code, it is
mandatory to always write the HW Options field to the HW
option registers directly after reset.
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29.2. Listing of Dedicated Addresses of the Hardware Options Field
Please refer to section “Memory and Boot System” for the
dedicated start address of the HW Options field.
Table 29–2: HW Options Field
Offs.
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
Mne.
SMC
SP0C
SP1C
SP2C
P9C
P9P
Options
Table 29–2: HW Options Field
SM, SPI0, SPI1 Pre. & SM Clock
SPI0 I/O & F0SPI Clock
SPI1 I/O & F1SPI Clock
F2SPI Clock
Offs.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Mne.
T0C
T1C
T2C
T3C
T4C
Options
Timer 0 Clock
Timer 1 Clock
Timer 2 Clock
Timer 3 Clock
Timer 4 Clock
PWM 8, 9 Clock
PWM 8, 9 Period
PWM 10, 11 Clock
PWM 10, 11 Period
PWM 0, 1 Clock
P11C
P11P
P1C
P1P
CO00C Clock Out 0: Mux0 Pre. & Clock
CO01C Clock Out 0: Mux1 Clock
CO02C Clock Out 0: Mux2 Clock
PWM 0, 1 Period
PWM 2, 3 Clock
DMAC
CO1C
C0C
C1C
DC
DMA Timer Clock
Clock Out 1: Pre. & Clock
CAPCOM Counter 0 Clock
CAPCOM Counter 1 Clock
DIGITbus Clock
P3C
P3P
PWM 2, 3 Period
PWM 4, 5 Clock
P5C
P5P
PWM 4, 5 Period
PWM 6, 7 Clock
P7C
P7P
LC
LCD Pre. & Clock
AM Clock
PWM 6, 7 Period
AC
PF0C
PFM 0 Clock
PM
CM
Port Mux
Clock Monitor
UA0
UA1
UART0 I/O
UART1 I/O
182
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CDC 32xxG-B
Table 29–4: Clock Option Selection Code
29.3. HW Options Registers and Code
Clock Option
Number
Clock Signal
Selection Code
The mapping of the HW Options registers corresponds
exactly to the HW Options field in the section above. The
order of the HW Options registers description in this section
does not correspond to the order of the HW Options field.
f0
f0
xxx0.0000
xxx0.0001
xxx0.0010
xxx0.0011
xxx0.0100
xxx0.0101
xxx0.0110
xxx0.0111
xxx0.1000
xxx0.1001
xxx0.1010
xxx0.1011
xxx0.1100
xxx0.1101
xxx0.1110
xxx0.1111
xxx1.0000
xxx1.0001
xxx1.0010
xxx1.0011
xxx1.0100
xxx1.0101
xxx1.0110
xxx1.0111
xxx1.1000
xxx1.1001 ...
xxx1.1100
xxx1.1101 ...
xxx1.1111
The emulator IC allow SW programming of the whole regis-
ters. Future mask ROM derivatives don’t allow to write other
clock option values as defined in the HW Options field.
f1
f1
f2
f1/21
The clock options may be programmed to values according
to table 29–4 on page 183.
f3
f1/22
f4
f1/23
Some of the clocks may be pre scaled by a programmable
value. Refer to table 29–3 for possible values.
f5
f1/24
Table 29–3: Clock Prescaler
f6
f1/25
f7
f1/26
PRE
Prescale Value
f8
f1/27
1
x
0
1
0
0
1
1
f9
f1/28
direct
1/1.5
1/2.5
f10
f11
f12
f13
f14
f15
f16
f17
f18
f19
f20
f21
f22 1)
f23
f24
f25, 26, 27
f28
f29, 30
f31
f1/29
f1/210
f1/211
f1/212
f1/213
f1/214
f1/215
f1/216
VSS
T0-OUT
VSS
fSM
fSM/28
fCC0IN
fCC1IN
VSS
f1/21
VSS
f1/29
If the leading “x” in the Clock sampling table are not used
for the purpose of coding other options, they must be
replaced by zeros.
1) Clock option f22 is only available if the Stepper Motor
Module has been enabled by the standby bit.
Micronas
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CDC 32xxG-B
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29.3.1. Timers
P3C
PWM 2, 3 Clock
7
x
x
6
x
x
5
x
x
4
3
2
1
0
0
0
0
0
0
0
0
T0C
Timer 0 Clock
w
Clock Options f0 to f31 (all)
7
x
x
6
x
x
5
x
x
4
3
2
1
0
0
0
0
0
0x0
Res
Res
Res
Res
Res
Res
Res
Res
w
Clock Options f1 to f31
0x01
Res
Res
Res
Res
Res
P3P
PWM 2, 3 Period
7
x
x
6
x
x
5
x
x
4
3
2
1
T1C
Timer 1 Clock
w
Clock Options f0 to f31 (all)
7
x
x
6
x
x
5
x
x
4
3
2
1
0x08
w
Clock Options f0 to f31 (all)
0x0
P5C
PWM 4, 5 Clock
7
x
x
6
x
x
5
x
x
4
3
2
1
T2C
Timer 2 Clock
w
Clock Options f0 to f31 (all)
7
x
x
6
x
x
5
x
x
4
3
2
1
0x0
w
Clock Options f0 to f31 (all)
0x0
P5P
PWM 4, 5 Period
7
x
x
6
x
x
5
x
x
4
3
2
1
T3C
Timer 3 Clock
w
Clock Options f0 to f31 (all)
7
x
x
6
x
x
5
x
x
4
3
2
1
0x08
w
Clock Options f0 to f31 (all)
0x0
P7C
PWM 6, 7 Clock
7
x
x
6
x
x
5
x
x
4
3
2
1
T4C
Timer 4 Clock
w
Clock Options f0 to f31 (all)
7
x
x
6
x
x
5
x
x
4
3
2
1
0x0
w
Clock Options f0 to f31 (all)
0x0
P7P
PWM 6, 7 Period
29.3.2. PWMs
7
x
x
6
x
x
5
x
x
4
3
2
1
The high pulse width of the trigger period must be greater
than the high pulse width of the clock the PWM is provided
with.
w
Clock Options f0 to f31 (all)
0x08
P1C
PWM 0, 1 Clock
P9C
PWM 8, 9 Clock
7
x
x
6
x
x
5
x
x
4
3
2
1
0
7
x
x
6
x
x
5
x
x
4
3
2
1
w
Clock Options f0 to f31 (all)
w
Clock Options f0 to f31 (all)
0x0
Res
0x0
P1P
PWM 0, 1 Period
P9P
PWM 8, 9 Period
7
x
x
6
x
x
5
x
x
4
3
2
1
0
7
x
x
6
x
x
5
x
x
4
3
2
1
w
Clock Options f0 to f31 (all)
w
Clock Options f0 to f31 (all)
0x08
Res
0x08
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29.3.7. Clock Out
CO00C
P11C
PWM 10, 11 Clock
7
6
x
x
5
x
x
4
3
2
1
0
Clock Out 0: Mux0 Pre. & Clock
w
x
Clock Options f0 to f31 (all)
7
x
x
6
5
4
3
2
1
0
x
0x0
Res
w
PRE
Clock Options f0 to f31 (all)
0x0
0x11
Res
P11P
PWM 10, 11 Period
PRE
Prescaler (Table 29–3)
7
6
x
x
5
x
x
4
3
2
1
0
w
x
Clock Options f0 to f31 (all)
CO01C
Clock Out 0: Mux1 Clock
x
0x08
Res
7
6
x
x
5
x
x
4
3
2
1
0
0
0
w
x
Clock Options f0 to f31 (all)
29.3.3. CAPCOMs
x
0x0
Res
Res
Res
C0C
CAPCOM Counter 0 Clock
CO02C
Clock Out 0: Mux2 Clock
7
6
x
x
5
x
x
4
3
2
1
0
7
6
x
x
5
x
x
4
3
2
1
w
x
Clock Options f0 to f31 (all)
w
x
Clock Options f0 to f31 (all)
x
0x0
Res
x
0x0
C1C
CAPCOM Counter 1 Clock
CO1C
Clock Out 1: Pre. & Clock
7
6
x
x
5
x
x
4
3
2
1
0
7
6
5
4
3
2
1
w
x
Clock Options f0 to f31 (all)
w
x
PRE
Clock Options f0 to f31 (all)
x
0x0
Res
x
0x0
0x11
PRE
Prescaler (Table 29–3)
29.3.4. DIGITbus
DC
29.3.8. LCD
DIGITbus Clock
7
x
x
6
x
x
5
x
x
4
3
2
1
0
0
0
LC
LCD Pre. & Clock
w
Clock Options f0 to f31 (all)
7
6
5
4
3
2
1
0
0x0
Res
Res
Res
w
x
PRE
Clock Options f0 to f31 (all)
x
0x0
0x03
Res
29.3.5. DMA
DMAC
PRE
Prescaler (Table 29–3)
DMA Timer Clock
29.3.9. Stepper Motor and SPIs
7
x
x
6
5
x
x
4
3
2
1
w
x
Clock Options f0 to f31 (all)
SMC
SM, SPI0, SPI1 Pre. & SM Clock
x
0x0
7
6
5
4
3
2
1
0
w
x
PRE
Clock Options f0 to f31 (all)
29.3.6. PFM
PF0C
x
0x0
0x0
Res
PFM 0 Clock
PRE
Prescaler (Table 29–3)
7
x
x
6
5
x
x
4
3
2
1
The field PRE of register SMC defines the SPI0 and SPI1
prescaler setting too.
w
x
Clock Options f0 to f31 (all)
x
0x0
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CDC 32xxG-B
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U15
w1:
w0:
U-Port 1.5 outputs
CO1.
CO0Q.
SP0C
SPI0 I/O & F0SPI Clock
7
6
5
x
x
4
3
2
1
0
CC4I
w1:
w0:
CAPCOM4-IN
Input from P0.0.
Input from U5.3.
w SPI0OUT SPI0IN
Clock Options f0 to f31 (all)
0
0
0x0
Res
Res
Res
CACO
w1:
w0:
CAPCOM0, 1, 2-IN
Input from U4.1, U2.4, U2.2.
Input from U3.2, U3.1, U3.0.
SPI0OUT
w1:
w0:
SPI0 Data Output Inverter
Inverted.
Direct.
U06
w1:
w0:
U-Port 0.6 outputs
CC3-OUT.
T4-OUT.
SPI0IN
w1:
w0:
SPI0 Data Input Inverter
Inverted.
Direct.
U20
w1:
U-Port 2.0 outputs
CAN0-TX on U4.2.
CAN0-RX on U4.3.
SCL0 on U2.0.
The clock is pre scaled by SMC.PRE.
SDA0 on U2.1.
SP1C
SPI1 I/O & F1SPI Clock
w0:
CAN0-TX on U2.0 and U4.2.
CAN0-RX on U2.1.
SCL0, SDA0 not usable.
7
6
5
x
x
4
3
2
1
0
w SPI1OUT SPI1IN
Clock Options f0 to f31 (all)
H7
w1:
w0:
H-Port 7 outputs
PWM9, 8, 6, 4.
SME.
0
0
0x0
SPI1OUT
w1:
w0:
SPI1 Data Output Inverter
Inverted.
Direct.
H0
w1:
w0:
H-Port 0 outputs
PWM7, 5, 3, 1.
SMG.
SPI1IN
w1:
w0:
SPI1 Data Input Inverter
Inverted.
Direct.
PINT
w1:
w0:
Port interrupts
Input from P1.2 to 7.
Input from U1.7, U1.6, U1.5, U0.7, U0.5, U0.4.
The clock is pre scaled by SMC.PRE.
29.3.12. Clock Monitor
SP2C
F2SPI Clock
7
6
x
x
5
x
x
4
3
2
1
0
CM
Clock Monitor
w
x
Clock Options f0 to f31 (all)
7
x
x
6
WCM
0
5
x
x
4
x
x
3
x
x
2
x
x
1
x
x
0
x
x
x
0x0
w
Res
The clock is pre scaled by SMC.PRE.
WCM
w1:
Watchdog, Clock and Supply Monitor
Clock & Supply: Always active.
Watchdog: Always active.
29.3.10. Audio Module
w0:
Clock & Supply: deactivatable by SW.
Watchdog: activatable by SW.
AC
AM Clock
7
x
x
6
x
x
5
x
x
4
3
2
1
0
29.3.13. UARTs
UA0
w
Clock Options f0 to f31 (all)
0x0
Res
UART0 I/O
7
U0TX
0
6
U0RX
0
5
x
x
4
x
x
3
x
x
2
x
x
1
x
x
0
x
x
29.3.11. Port Multiplexers
w
Res
PM
Port Mux
U0TX
w1:
w0:
UART0 Tx Output
Inverted.
Direct.
7
U15
0
6
CC4I
0
5
CACO
0
4
U20
1
3
U06
0
2
H7
0
1
H0
0
0
PINT
0
w
Res
U0RX
w1:
UART0 Rx Input
Inverted.
w0:
Direct.
186
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CDC 32xxG-B
UA1
UART1 I/O
7
6
U1RX
0
5
x
x
4
x
x
3
x
x
2
x
x
1
x
x
0
x
x
w
U1TX
0
Res
U1TX
w1:
w0:
UART1 Tx Output
Inverted.
Direct.
U1RX
w1:
w0:
UART1 Rx Input
Inverted.
Direct.
Micronas
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CDC 32xxG-B
30. Register Cross Reference Table
30.1. 8 Bit I/O Region
Table 30–1: Base address 0x00F80000
Offs.
Byte Address
3
Remarks
2
1
0
Module
0xFFC
0x600
0x5FC
0x400
0x3FC
0x200
0x1FC
0x000
5 CAN reserved
CAN 2
CAN RAM
CAN 1
CAN 0
Table 30–2: Base address 0x00F81000
Offs.
Byte Address
3
Remarks
2
1
0
Module
0x1FC
0x0C0
0x0BC
0x094
0x090
0x08C
0x088
0x084
0x080
0x07C
0x054
0x050
0x04C
0x048
0x044
0x040
0x03C
0x014
0x010
0x00C
0x008
0x004
0x000
5 CAN reserved
CAN2
CAN register
CTIM
OCR
BT1
CTIM
ICR
REC
BT3
TEC
BT2
IDM
IDX
ESTR
STR
CTR
CAN1
CTIM
OCR
BT1
CTIM
ICR
REC
BT3
TEC
BT2
IDM
IDX
ESTR
STR
CTR
CAN0
CTIM
OCR
BT1
CTIM
ICR
REC
BT3
TEC
BT2
IDM
IDX
ESTR
STR
CTR
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Table 30–3: Base address 0x00F90000 (formerly 1F00)
Offs.
Byte Address
3
Remarks
2
1
0
Module
0x0FC
0x0F8
0x0F4
0x0F0
0x0EC
0x0B0
0x0AC
0x0A8
0x0A4
0x0A0
0x09C
0x080
0x07C
0x078
0x074
0x070
0x06C
0x068
0x064
0x060
0x05C
0x058
0x054
0x050
0x04C
0x048
0x044
0x040
0x03C
0x030
0x02C
0x028
0x024
0x020
0x01C
0x018
0x014
0x010
0x00C
0x008
0x004
0x000
TST2
TST1
TST3
TSTAD3
DGS1TA
DGC1
TST4
TSTAD2
DGTL
DGC0
Test
TST5
DGRTMA
DGRTMD
DGTD
DGS0
DIGITBus
64 byte
32 byte
ANAA
AD0
ADC
AD1
UA0IF
UA0CA
UA0C
UA0IM
UA0D
UART0
UA0BR1
UA0BR0
CCC0H
CC3I
CCC0L
CC3M
CC2M
CC1M
CC0M
CAPCOM0
CC3H
CC2H
CC1H
CC0H
CC3L
CC2L
CC1L
CC0L
CC3
CC2
CC1
CC0
8 byte
CC2I
CC1I
CC0I
CSW1
Core Logic
SMVCMP
TIM2
SMVCOS
Stepper Motor
Module VDO
SMVSIN
TIM4
SMVC
TIM3
TIM1
Timer
TIM0H
TIM0L
Timer0
CCC1H
CC5I
CCC1L
CC5M
CC4M
CAPCOM1
CC5H
CC4H
CC5L
CC4L
CC5
CC4I
CC4
16 byte
AMDEC
IRPM1
AMF
AMAS
AMPRE
Audio Module
Port Interrupt
IRPM0
8 byte
UA1IF
UA1CA
UA1C
UA1IM
UA1D
UART1
UA1BR1
UA1BR0
CO0SEL
SPI0D
Core Logic
SPI
SPI1M
SR1
SPI1D
SPI0M
Core Logic
SR0
ANAU
CSW0
190
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 30–4: Base address 0x00F90100 (formerly 1E00)
Offs.
Byte Address
3
Remarks
2
1
0
Module
0x0FC
0x0F0
0x0EC
0x0E8
0x0E4
0x0E0
0x0DC
0x0D8
0x0D4
0x0D0
0x0CC
0x0C8
0x0C4
0x0C0
0x0BC
0x060
0x05C
0x054
0x050
0x04C
0x048
0x044
0x040
0x03C
0x020
0x01C
0x018
0x014
0x010
0x00C
0x008
0x004
0x000
16 byte
HW Options
UA1
PM
UA0
CM
P7P
P7C
P5P
P5C
P1C
P9C
SMC
DC
P3P
P3C
P1P
P11P
SP2C
PF0C
C1C
P11C
SP1C
AC
P9P
SP0C
LC
C0C
CO01C
T2C
CO1C
CO00C
T1C
DMAC
T4C
T0C
CO02C
T3C
96 byte
PFM
PFM0
PWMC
PWM11
PWM7
PWM3
PWM
PWM10
PWM6
PWM2
PWM9
PWM5
PWM1
PWM8
PWM4
PWM0
32 byte
I2C1
I2C
I2CM1
I2CRS1
I2CWD11
I2CRD1
I2CWP11
I2CWS11
I2CWP01
I2CWS01
I2CWD01
I2C0
I2CM0
I2CRS0
I2CWD10
I2CRD0
I2CWP10
I2CWS10
I2CWP00
I2CWS00
I2CWD00
Micronas
Nov. 28, 2002; 6251-546-1PD
191
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 30–5: Base address 0x00F90400
Offs.
Byte Address
3
Remarks
2
1
0
Module
0x0FC
0x0F8
0x0F4
0x0F0
0x0EC
0x0E8
0x0E4
0x0E0
0x0DC
0x0D8
0x0D4
0x0D0
0x0CC
0x0C8
0x0C4
0x0C0
0x0BC
0x0B8
0x0B4
0x0B0
0x0AC
0x090
0x084
0x080
0x074
0x070
0x064
0x060
0x054
0x050
0x044
0x040
0x034
0x030
0x024
0x020
0x014
0x010
0x004
0x000
HxPIN
HxD
H-Port7
H-Port6
H-Port5
H-Port4
H-Port3
H-Port2
H-Port1
H-Port0
H-Ports
HxLVL
HxLVL
HxLVL
HxLVL
HxLVL
HxLVL
HxLVL
HxLVL
HxNS
HxNS
HxNS
HxNS
HxNS
HxNS
HxNS
HxNS
HxTRI
HxTRI
HxTRI
HxTRI
HxTRI
HxTRI
HxTRI
HxTRI
HxPIN
HxD
HxPIN
HxD
HxPIN
HxD
HxPIN
HxD
HxPIN
HxD
HxPIN
HxD
HxPIN
HxD
P-Ports
U-Ports
P2LVL
P1LVL
P0LVL
P2IE
P1IE
P0IE
P2PIN
P1PIN
P0PIN
P-Port 2
P-Port1
P-Port 0
reserved
UxMODE
UxDPM
UxPIN
UxNS
UxPIN
UxNS
UxPIN
UxNS
UxPIN
UxNS
UxPIN
UxNS
UxPIN
UxNS
UxPIN
UxNS
UxPIN
UxNS
UxPIN
UxNS
UxLVL
UxTRI
UxLVL
UxTRI
UxLVL
UxTRI
UxLVL
UxTRI
UxLVL
UxTRI
UxLVL
UxTRI
UxLVL
UxTRI
UxLVL
UxTRI
UxLVL
UxTRI
UxSLOW
UxD
U-Port 8
U-Port 7
U-Port 6
U-Port 5
U-Port 4
U-Port 3
U-Port 2
U-Port 1
U-Port 0
UxMODE
UxDPM
UxSLOW
UxD
UxMODE
UxDPM
UxSLOW
UxD
UxMODE
UxDPM
UxSLOW
UxD
UxMODE
UxDPM
UxSLOW
UxD
UxMODE
UxDPM
UxSLOW
UxD
UxMODE
UxDPM
UxSLOW
UxD
UxMODE
UxDPM
UxSLOW
UxD
UxMODE
UxDPM
UxSLOW
UxD
192
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 30–6: Base address 0x00F90500
Offs.
Byte Address
3
Remarks
180 Bytes
reserved
2
1
0
Module
0x0FC
0x050
0x04C
0x048
0x044
0x040
0x03C
0x030
0x02C
0x028
0x024
0x020
0x01C
0x014
0x010
0x00C
0x008
0x004
0x000
reserved
GBus
GC
GD
reserved
Core Logic
WSR
IOC
Clock, PLL, ERM
ERMC
PLLC
reserved
LCD
ULCDLD
reserved for Patch
Micronas
Nov. 28, 2002; 6251-546-1PD
193
CDC 32xxG-B
PRELIMINARY DATA SHEET
30.2. 32 Bit I/O Region
Table 30–7: Base address 0x00FFFD00
Offs.
Byte Address
3
Remarks
2
1
0
Module
0x0FC
0x004
0x000
252 bytes
reserved
Core Logic
CR
Control Register
Table 30–8: Base address 0x00FFFE00
Offs.
Byte Address
3
Remarks
2
1
0
Module
0x0FC
0x020
0x018
0x010
0x008
0x004
0x000
rsvd
Channel 4 to 31
DMA
DC3M
DC2M
DC1M
Channel 3
Channel 2
Channel 1
Control
DST
DVB
Table 30–9: Base address 0x00FFFF00
Offs.
Byte Address
3
Remarks
2
1
0
Module
0x0FC
0x0F4
0x0F0
0x0EC
0x0C8
0x0C4
0x0C0
0x0BC
0x040
0x03C
0x028
0x024
:
12 bytes reserved
IRQ and FIQ
Interrupt Control-
ler
CRF
PRF
FIQ registers
40 bytes reserved
VTB
IRQ registers
PESRC
PEPRIO
AFP
CRI
128 bytes
reserved
Interrupt source
nodes
ISN39
:
ISN38
:
ISN37
:
ISN36
:
0x004
0x000
ISN7
ISN3
ISN6
ISN2
ISN5
ISN1
ISN4
ISN0
194
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
31. Register Quick Reference
Due to HW constraints some multi-byte registers must be
accessed byte by byte only. Postfixes (_m_n) may be
attached to such register mnemonics if necessary, where “m”
stands for the access size in bit (m = 8 or 16) and “n” stands
for the byte or half word offset (n = 0, 1, 2, 3).
Table 31–1: Possible Postfixes
Postfix
_8_0
Access Size
Byte Offset
Byte 0 (LSB)
Byte 1
Byte
The I/O area is organized in little endian format, thus the
LSB, independent of the flag CR.ENDIAN setting, is always
stored at the low address.
_8_1
_8_2
Byte 2
_8_3
Byte 3 (MSB)
Low half word
High half word
_16_0
_16_1
Half word
Table 31–2: Analog Section (Base addr. 0xF90000)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
AD0
ADC Register 0
0x0A8
13.7.
r
EOC
x
x
x
x
TEST
AN1
AN0
w
TSAMP
REF
CHANNEL
0
0
0
0
0
0
0
0
Res
AD1
ADC Register 1
0x0A9
r
AN9
x
AN8
x
AN7
x
AN6
x
AN5
x
AN4
x
AN3
x
AN2
BUF
0
w
Res
Res
ANAA
Analog AVDD Regis- 0x0AC
ter
r/w EP06
P06
WAIT
x
x
x
x
BVE
0
0
Micronas
Nov. 28, 2002; 6251-546-1PD
195
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–3: Analog Input Ports (Base addr. 0xF90400)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
P0PIN
P1PIN
P2PIN
P0IE
Port x Pin Register
0x0B0
0x0B4
0x0B8
0x0B1
0x0B5
0x0B9
12.1.
r
r/w
r/w
P7
P6
P5
P4
P3
P2
P1
P0
1
1
1
1
1
1
1
1
Res
Res
Res
Port x Input Enable
Register
I7
I6
I5
I4
I3
I2
I1
I0
P1IE
0
0
0
0
0
0
0
0
I
P2IE
P0LVL
P1LVL
P2LVL
Port x Level Register 0x0B3
A7
A6
A5
A4
A3
A2
A1
A0
0x0B7
0x0BB
0
0
0
0
0
0
0
0
Table 31–4: Audio Module (Base addr. 0xF90000)
Mnemonic
AMPRE
AMAS
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
Audio Module Pres-
caler
0x02C
28.2.
w
Prescale Value
1
1
1
1
1
1
1
1
Res
Audio Module Ampli- 0x02D
tude & Status Regis-
ter
w
r
Initial Amplitude
AMA
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
Res
Res
Res
AMF
Audio Module Fre-
quency Register
0x02E
w
w
x
Sound Frequency
-
0
0
0
0
0
0
0
0
AMDEC
Audio Module Decre- 0x02F
ment Register
AMMCA
x
x
x
x
GDF
0
-
-
-
-
0
0
196
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 31–5: Capture-Compare-Unit 0 (Base addr. 0xF90000)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
CC0M
CC1M
CC2M
CC3M
CC0I
CAPCOM 0 Mode
Register
0x06C
0x070
0x074
0x078
0x06D
0x071
0x075
0x079
17.2.
r/w MCAP MCMP MOFL
FOL
OAM
IAM
0
0
0
0
0
0
0
0
Res
CAPCOM 0 Interrupt
Register
r/w
CAP
CMP
OFL
LAC
RCR
x
x
x
CC1I
0
0
0
0
0
0
0
0
Res
CC2I
CC3I
CC0L
CC1L
CC2L
CC3L
CC0H
CC1H
CC2H
CC3H
CCC0L
CAPCOM 0 Capture/ 0x06E
Compare Register
r
Read low byte of capture register and lock it.
Write low byte of compare register and lock it.
low byte
0x072
0x076
0x07A
w
1
1
1
1
1
1
1
1
Res
CAPCOM 0 Capture/ 0x06F
Compare Register
r
Read high byte of capture register and unlock it.
Write high byte of compare register and unlock it.
high byte
0x073
0x077
0x07B
0x07C
w
1
1
1
1
1
1
1
1
Res
CAPCOM Counter 0
low byte
r
r
Read low byte and lock CCC
0
0
0
0
0
0
0
0
0
0
0
0
Res
Res
CCC0H
CAPCOM Counter 0
high byte
0x07D
Read high byte and unlock CCC
0
0
0
0
Micronas
Nov. 28, 2002; 6251-546-1PD
197
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–6: Capture-Compare-Unit 1 (Base addr. 0xF90000)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
CC4M
CC5M
CAPCOM Mode
Register
0x040
0x044
17.2.
r/w MCAP MCMP MOFL
FOL
OAM
IAM
0
0
0
0
0
0
0
0
Res
Res
CC4I
CC5I
CAPCOM Interrupt
Register
0x041
0x045
r/w
CAP
CMP
OFL
LAC
RCR
x
x
x
0
0
0
0
0
0
0
0
CC4L
CC5L
CAPCOM Capture/
Compare Register
low byte
0x042
0x046
r
Read low byte of capture register and lock it.
Write low byte of compare register and lock it.
w
1
1
1
1
1
1
1
1
Res
CC4H
CC5H
CAPCOM Capture/
Compare Register
high byte
0x043
0x047
r
Read high byte of capture register and unlock it.
Write high byte of compare register and unlock it.
w
1
0
0
1
0
0
1
1
1
1
1
0
0
1
0
0
Res
Res
Res
CCC1L
CCC1H
CAPCOM Counter 1
low byte
0x048
0x049
r
r
Read low byte and lock CCC
0
0
0
0
CAPCOM Counter 1
high byte
Read high byte and unlock CCC
0
0
0
0
198
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 31–7: Controller Area Network Registers (Base addr. 0xF81000)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
CAN0CTR
CAN1CTR
CAN2CTR
CAN0STR
CAN1STR
CAN2STR
CAN0ESTR
CAN1ESTR
CAN2ESTR
CAN0IDX
CAN1IDX
CAN2IDX
CAN0IDM
CAN1IDM
CAN2IDM
Control Register
0x000
0x040
0x080
0x001
0x041
0x081
25.2.
r/w
HLT
SLP
GRSC
EIE
GRIE
GTIE
rsvd
rsvd
1
0
0
0
0
0
x
x
Res
Res
Res
Res
Status Register
r
HACK BOFF
EPAS
ERS
rsvd
rsvd
rsvd
rsvd
1
0
0
0
x
x
x
x
Error Status Register 0x002
r/w GDM
CTOV
ECNT
BIT
STF
CRC
FRM
ACK
0x042
0x082
0
0
0
0
0
0
0
0
Interrupt Index Reg-
ister
0x003
0x043
0x083
0x004
0x044
0x084
r/w
Interrupt Index
1
1
1
1
1
1
1
1
Identifier Mask Reg-
ister
r/w
r/w
r/w
r/w
0
Identifier Mask Bits 4 to 0
x
x
x
3
Identifier Mask Bits 12 to 5
Identifier Mask Bits 20 to 13
Identifier Mask Bits 28 to 21
2
1
0
0
0
0
0
0
0
0
Res
CAN0BT1
CAN1BT1
CAN2BT1
CAN0BT2
CAN1BT2
CAN2BT2
CAN0BT3
CAN1BT3
CAN2BT3
CAN0ICR
CAN1ICR
CAN2ICR
Bit Timing Register 1 0x008
r/w MSAM
SYN
BPR
0x048
0
0
0
0
0
0
0
0
Res
0x088
Bit Timing Register 2 0x009
r/w
r/w
r/w
rsvd
TSEG2
TSEG1
0x049
0
0
0
0
0
0
0
0
0
0
Res
Res
Res
0x089
Bit Timing Register 3 0x00A
rsvd
rsvd
rsvd
rsvd
rsvd
SJW
0x04A
0x08A
x
x
x
x
x
0
Input Control Regis-
ter
0x00B
0x04B
0x08B
rsvd
rsvd
rsvd
rsvd
rsvd
XREF
REF1
REF0
x
x
x
x
x
0
0
0
Micronas
Nov. 28, 2002; 6251-546-1PD
199
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–7: Controller Area Network Registers (Base addr. 0xF81000)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
CAN0OCR
CAN1OCR
CAN2OCR
CAN0TEC
CAN1TEC
CAN2TEC
CAN0REC
CAN1REC
CAN2REC
CAN0CTIM
CAN1CTIM
CAN2CTIM
Output Control Reg-
ister
0x00C
0x04C
0x08C
0x00D
0x04D
0x08D
0x00E
0x04E
0x08E
0x00F
0x04F
0x08F
25.2.
r/w
rsvd
rsvd
rsvd
rsvd
rsvd
rsvd
rsvd
ITX
x
x
x
x
x
x
x
0
Res
Res
Res
Transmit Error
Counter
r
r
Counter Bit 7 to 0
0
0
0
0
0
0
0
0
0
0
0
0
Receive Error
Counter
x
Counter Bit 6 to 0
x
0
0
0
Capture Timer
r
r
Timer Bit 15 to 8
Timer Bit 7 to 0
1
0
0
0
0
0
0
0
0
0
Res
Table 31–8: Core Logic 32 Bit (Base addr. 0xFFFD00)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
CR
Control Register
0x000
6.1.
r/w
x
x
x
x
x
x
x
x
x
x
3
r/w STPCLK RESLNG
r/w EB2 TFT
r/w JTAG ENDIAN
Value of memory location 0x20 to 0x23
x
x
TSTTOG
PSA
2
TETM
EB1
EBW
EASY
MFM
1
MAP
IBOOT IROM
IRAM
ICPU
0
Res
200
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 31–9: Core Logic 8 Bit (Base addr. 0xF90000)
Mnemonic
CSW0
ANAU
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
Clock, Supply and
Watchdog Register 0
0x000
6.
w
FHR
x
x
x
x
x
x
CMA
0
x
x
x
x
x
x
1
Res
Analog UVDD Regis- 0x004
ter
r/w
EAL
x
LS
x
x
FVE
VE
0
0
0
0
0
SR0
Standby Register 0
0x008
r/w
r/w
r/w
r/w
I2C1
TIM2
LCD
SM
I2C0
TIM3
x
x
x
x
x
DGB
x
CAN2
CCC1
TIM1
CAN1
x
3
TIM4
UART1
x
2
PSLW UART0
ADC
SPI1
XTAL
SPI0
1
x
x
x
CAN0
CCC0
0
0x00000100
Res
SR1
Standby Register 1
0x00C
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3
2
x
PFM0 PWM11 PWM9 PWM7 PWM5 PWM3 PWM1
1
IRQ
FIQ
x
x
x
CPUM
0
0x00000001
Res
CO0SEL
CSW1
Clock Out 0 Selec-
tion
0x014
0x060
w
x
x
x
x
x
x
CO01
CO00
x
x
x
x
x
x
0
0
Res
Clock, Supply and
Watchdog Register 1
w
r
Watchdog Time and Trigger Value
1
1
1
1
1
1
1
1
Res
Res
TST
x
x
FHR
CLM
PIN
POR WDRES
-
-
-
0
0
0
0
0
Micronas
Nov. 28, 2002; 6251-546-1PD
201
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–10: Core Logic 8 Bit (Base addr. 0xF90500)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
PLLC
PLL Control
0x020
0x024
6.
r/w
ACT
LCK
PLLM
x
PMF
x
x
x
x
0
0
0
0
Res
ERMC
ERM Control
r/w
r/w
r/w
TSEL
3
x
x
x
x
x
x
x
x
x
x
x
2
EOM
TOL
1
r/w INPH
SUP
0
0x00000000
Res
IOC
I/O Control
0x028
0x02C
w
x
x
x
x
x
IOP
x
x
x
x
x
0
0
0
Res
Res
WSR
Wait State Register
w
NWS
SWS
0x00
202
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 31–11: DIGITbus (Base addr. 0xF90000)
Mnemonic
Register Name
Control Register 0
Control Register 1
Status Register 0
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
DGC0
0x0F0
0x0F1
0x0F2
27.3.
r/w
RUN
GBC
ACT
RXO
X
PSC 2 to 0
0
0
0
0
x
0
0
0
Res
Res
DGC1
r/w INTE
ENEM ENOF
x
PHASE
0
0
0
x
0
0
0
0
DGS0
w
r
x
RDL
x
x
NEM
0
x
NOF
1
TGV
PV
ERR
x
ARB
0
0
0
x
0
Res
DGRTMD
DGTL
Rx Length & Tx More 0x0F3
Data Register
w
r
Transmit More Data
RDL
NEM
FTYP EOFLD
x
LEN2 to 0
0
0
x
x
x
x
x
x
Res
Tx Length Register
0x0F4
0x0F5
w
r
x
FLUSH
x
x
x
LEN2 to 0
x
0
x
x
x
0
0
0
Res
Res
BUSY EMPTY
x
x
x
x
x
x
0
1
x
x
x
x
x
x
DGS1TA
Status 1 & Tx
w
r
Transmit Address
PW5 to 0
Address Register
STATE
0
x
1
x
0
x
0
0
0
0
x
0
x
Res
Res
DGTD
Tx Data Register
0x0F6
0x0F7
w
Transmit Data
x
x
x
DGRTMA
Rx Field & Tx More
Address Register
w
r
Transmit More Address
Receive Field
x
x
x
x
x
x
x
x
Res
Micronas
Nov. 28, 2002; 6251-546-1PD
203
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–12: DMA (Base addr. 0xFFFE00)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
DVB
DMA Vector Base
0x000
20.2.
r/w
r/w
r/w
r/w
0
0
0
0
0
0
0
0
3
A23 to A16
A15 to A8
2
1
A7
0
x
0
x
0
0
0
0
0
0
0x0000
0x00
Res
DST
DMA Status
0x004
r/w
DE
SRC
0
Res
DC1M
DC2M
DC3M
DMA Channel x
Mode
0x008
0x010
0x018
r/w
r/w
P
DMAT
x
TRIG
1
EN
x
x
BYP
0x0000
DIR
MAS
0
Res
Table 31–13: FIQ Interrupt Logic (Base addr. 0xFFFF00)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
PRF
Pending Register
FIQ
0x0F0
0x0F1
10.2.
r/w
r/w
x
x
x
x
x
x
x
P
x
x
x
x
x
x
x
0
Res
CRF
Control Register FIQ
GE
x
x
x
SEL
0
x
x
x
0
0
0
0
Res
Table 31–14: Graphic Bus Interface (Base addr. 0xF90500)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
GD
Graphic Bus Data
Register
0x040
0x044
21.2.
r/w
r/w
Data
0
0x00
Res
GC
Graphic Bus Control
Register
TIM
E
BSY
SEQ
DTA
0
0x00
Res
204
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 31–15: Hardware Options Registers (Base addr. 0xF90100)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
T0C
Timer 0 Clock
0x0C0
29.3.
w
w
x
x
x
Clock Options f1 to f31
x
x
x
0x01
Res
T1C
Timer 1 to 4 Clock
0x0C1
0x0C2
0x0C3
0x0C4
0x0C5
x
x
x
Clock Options f0 to f31 (all)
T2C
x
x
x
0x0
Res
T3C
T4C
CO00C
Clock Out0: Mux0
Pre. & Clock
w
w
w
w
w
x
PRE
Clock Options f0 to f31 (all)
x
0x0
0x11
Res
Res
Res
Res
Res
CO01C
CO02C
Clock Out0: Mux1 to
Mux3 Clock
0x0C6
0x0C7
x
x
x
Clock Options f0 to f31 (all)
x
x
x
0x0
DMAC
DMA Timer Clock
0x0C8
x
x
x
Clock Options f0 to f31 (all)
x
x
x
0x0
CO1C
Clock Out1: Pre. &
Clock
0x0C9
x
PRE
Clock Options f0 to f31 (all)
x
0x0
0x11
C0C
C1C
DC
CAPCOM Counter
Clocks
0x0CA
0x0CB
0x0CC
0x0CD
x
x
x
Clock Options f0 to f31 (all)
x
x
x
0x0
DIGITbus Clock
LC
LCD Pre. & Clock
w
w
w
w
x
PRE
Clock Options f0 to f31 (all)
x
0x0
0x03
Res
Res
Res
Res
Res
AC
AM Clock
0x0CE
0x0CF
0x0D0
0x0D1
x
x
x
Clock Options f0 to f31 (all)
x
x
x
0x0
PF0C
SMC
SP0C
PFM 0 Clock
x
x
x
Clock Options f0 to f31 (all)
x
x
x
0x0
SM, SPI0, SPI1 Pre.
& SM Clock
x
PRE
Clock Options f0 to f31 (all)
x
0x0
0x0
SPI0 I/O & F0SPI
Clock
w SPI0OUT SPI0IN
x
Clock Options f0 to f31 (all)
0
0
x
0x0
Micronas
Nov. 28, 2002; 6251-546-1PD
205
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–15: Hardware Options Registers (Base addr. 0xF90100)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
SP1C
SPI1 I/O & F1SPI
Clock
0x0D2
0x0D3
29.3.
w SPI1OUT SPI1IN
x
Clock Options f0 to f31 (all)
0
0
x
0x0
Res
Res
Res
SP2C
F2SPI Clock
PWM Clock
w
w
x
x
x
Clock Options f0 to f31 (all)
x
x
x
0x0
P9C
P11C
P1C
P3C
P5C
P7C
P9P
P11P
P1P
P3P
P5P
P7P
PM
0x0D4
0x0D6
0x0D8
0x0DA
0x0DC
0x0DE
0x0D5
0x0D7
0x0D9
0x0DB
0x0DD
0x0DF
0x0E9
x
x
x
Clock Options f0 to f31 (all)
x
x
x
0x0
PWM Period
w
x
x
x
Clock Options f0 to f31 (all)
x
x
x
0x08
Res
Port Multiplexer
Clock Monitor
UARTs
w
w
w
w
U15
CC4I
CACO
U20
U06
H7
H0
PINT
0
0
0
1
0
0
0
0
Res
Res
Res
Res
CM
0x0EA
0x0EC
0x0ED
x
WCM
x
x
x
x
x
x
x
0
x
x
x
x
x
x
UA0
UA1
U0TX
U0RX
x
x
x
x
x
x
0
0
x
x
x
x
x
x
U1TX
U1RX
x
x
x
x
x
x
0
0
x
x
x
x
x
x
206
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 31–16: High Current Ports (Base addr. 0xF90400)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
H0D
High Current Port
Data Register
0x0C0
0x0C8
0x0D0
0x0D8
0x0E0
0x0E8
0x0F0
0x0F8
0x0C1
0x0C9
0x0D1
0x0D9
0x0E1
0x0E9
0x0F1
0x0F9
0x0C2
0x0CA
0x0D2
0x0DA
0x0E2
0x0EA
0x0F2
0x0FA
12.5.
r/w
r/w
r/w
x
x
x
x
D3
D2
D1
D0
H1D
x
x
x
x
0
0
0
0
Res
Res
Res
H2D
H3D
H4D
H5D
H6D
H7D
H0TRI
H1TRI
H2TRI
H3TRI
H4TRI
H5TRI
H6TRI
H7TRI
H0NS
H1NS
H2NS
H3NS
H4NS
H5NS
H6NS
H7NS
High Current Port
Tristate Register
x
x
x
x
T3
T2
T1
T0
x
x
x
x
0
0
0
0
High Current Port
Normal/Special Reg-
ister
x
x
x
x
S3
S2
S1
S0
x
x
x
x
0
0
0
0
Micronas
Nov. 28, 2002; 6251-546-1PD
207
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–16: High Current Ports (Base addr. 0xF90400)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
H0LVL
H1LVL
H2LVL
H3LVL
H4LVL
H5LVL
H6LVL
H7LVL
H0PIN
H1PIN
H2PIN
H3PIN
H4PIN
H5PIN
H6PIN
H7PIN
High Current Port
Level Register
0x0C3
0x0CB
0x0D3
0x0DB
0x0E3
0x0EB
0x0F3
0x0FB
12.5.
r/w
x
x
x
x
A3
A2
A1
A0
x
x
x
x
0
0
0
0
Res
High Current Port Pin 0x0C4
Register
0x0CC
r
x
x
x
x
P3
P2
P1
P0
x
x
x
x
0
0
0
0
Res
0x0D4
0x0DC
0x0E4
0x0EC
0x0F4
0x0FC
208
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 31–17: I2C-Bus Master Interfaces (Base addr. 0xF90100)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
I2CWS00
I2CWS01
I2C Write Start Reg-
ister 0
0x000
0x010
24.2.
w
w
w
w
w
w
r
I2C Address
0x00
Res
I2CWS10
I2CWS11
I2C Write Start Reg-
ister 1
0x001
0x011
I2C Address
0x00
Res
Res
Res
Res
Res
Res
I2CWD00
I2CWD01
I2C Write Data Reg-
ister 0
0x002
0x012
I2C Data
0x00
I2CWD10
I2CWD11
I2C Write Data Reg-
ister 1
0x003
0x013
I2C Data
0x00
I2CWP00
I2CWP01
I2C Write Stop Reg-
ister 0
0x004
0x014
I2C Data
0x00
I2CWP10
I2CWP11
I2C Write Stop Reg-
ister 1
0x005
0x015
I2C Data
0x00
I2CRD0
I2CRD1
I2C Read Data Reg-
ister
0x006
0x016
I2C Data
0x00
I2CRS0
I2CRS1
I2C Read Status
Register
0x007
0x017
r
x
OACK AACK DACK BUSY
WFH
RFE
x
0
0
0
0
0
0
0
0
Res
Res
I2CM0
I2CM1
I2C Mode Register
0x00B
0x01B
w
DGL
SPEED
1
0x02
Micronas
Nov. 28, 2002; 6251-546-1PD
209
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–18: Interrupt Controller Unit (Base addr. 0xFFFF00)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
ISN0
Interrupt Source
Node Register 0
0x000
9.3.
r/w
M
P
E
x
PRIO
0
x
0
x
0
0
0
0
Res
:
:
:
ISN39
Interrupt Source
Node Register 39
0x027
CRI
Control Register IRQ 0x0C0
r/w
r/w
r
GE
TE
x
x
x
x
x
x
0
0
x
x
x
x
x
x
Res
Res
Res
Res
AFP
Actual and Forced
Priority Register
0x0C1
0x0C2
0x0C3
0x0C4
APRIO
FPRIO
0
0
0
0
0
0
0
0
0
0
0
PEPRIO
PESRC
VTB
Priority Encoder Pri-
ority output
x
x
x
x
Priority
x
x
x
x
0
0
Priority Encoder
Source output
r
x
x
Source
x
x
0
0
0
0
0
Vector Table Base
r/w
r/w
r/w
r/w
0
0
0
0
0
0
0
0
0
0
3
Address bit 23 to 16
Address bit 15 to 9
2
0
0
1
0
0
0
0
0
0
0x00000000
Res
Table 31–19: LCD (Base addr. 0xF90500)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
ULCDLD
Universal Port LCD
Load Register
0x010
19.2.
w
LCDSLV
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
Res
210
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 31–20: Port Interrupts (Base addr. 0xF90000)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
IRPM0
Interrupt Port Mode
Register 0
0x02A
0x02B
11.
r/w
r/w
PIT3
PIT2
PIT1
PIT5
PIT0
0
0
0
0
0
0
0
0
0
0
0
0
Res
Res
IRPM1
Interrupt Port Mode
Register 1
x
x
x
x
PIT4
x
x
x
x
Table 31–21: Pulse Frequency Modulator (Base addr. 0xF90100)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
PFM0
Pulse Width and
Period Length Regis-
ter
0x050
16.2.
w
w
w
w
INV
x
x
x
x
x
x
x
3
Pulse Width
2
Period Length (High Byte)
Period Length (Low Byte)
0x00
1
0
Res
Micronas
Nov. 28, 2002; 6251-546-1PD
211
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–22: Pulse Width Modulator (Base addr. 0xF90100)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
PWMC
PWM Register
0x040
0x041
0x042
0x043
0x044
0x045
0x046
0x047
0x048
0x049
0x04A
0x04B
0x04F
15.2.
w
Pulse width value
0
0
0
0
0
0
0
0
Res
PWM Control Regis-
ter
w
x
x
P1611
P169
P167
P165
P163
P161
x
x
0
0
0
0
0
0
Res
Table 31–23: Serial Synchronous Peripheral Interfaces (Base addr. 0xF90000)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
SPI0D
SPI1D
SPI Data Register
SPI Mode Register
0x010
0x012
22.2.
r/w
r/w
Bit 7 to 0 of Rx/Tx Data
0
0
0
0
0
0
0
0
0
0
0
0
Res
Res
SPI0M
SPI1M
0x011
0x013
BIT8
LEN9 RXSEL INTERN
SCLK
CSF
0
0
0
0
212
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 31–24: Stepper Motor VDO (Base addr. 0xF90000)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
SMVC
Stepper Motor VDO,
Control Register
0x05A
0x05B
18.2.
w
x
x
SEL
x
QUAD
x
x
0
0
0
x
0
0
Res
SMVSIN
Stepper Motor VDO,
Sine Register
r
x
x
x
x
x
x
x
BUSY
w
8bit Sine Value
0
0
0
0
0
0
0
0
0
0
Res
Res
Res
SMVCOS
SMVCMP
Stepper Motor VDO,
Cosine Register
0x05C
0x05D
w
8bit Cosine Value
0
0
0
0
0
0
Stepper Motor VDO,
Back-Up Compara-
tor Register
r/w
x
ACRF ACRD ACRB ACRG ACRE ACRC ACRA
x
0
0
0
0
0
0
0
Table 31–25: Test Registers (Base addr. 0xF90000)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
TSTAD2
TSTAD3
TST5
Test Register AD2
Test Register AD3
Test Register 5
Test Register 4
Test Register 3
Test Register 1
Test Register 2
0x0F8
0x0F9
0x0FB
0x0FC
0x0FD
0x0FE
0x0FF
6.5.
w
For testing purposes only
0
0
0
0
0
0
0
0
Res
TST4
TST3
TST1
TST2
Micronas
Nov. 28, 2002; 6251-546-1PD
213
CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–26: Timer (Base addr. 0xF90000)
Mnemonic
Register Name
Offs
Register Configuration
Section
7
6
5
4
3
2
1
0
TIM0L
Timer 0 low byte
0x04E
14.
r
Read low byte of down-counter and latch high byte
Write low byte of reload value and reload down-counter
w
1
1
1
1
1
1
1
1
Res
TIM0H
Timer 0 high byte
0x04F
r
Latched high byte of down-counter
High byte of reload value
w
1
0
1
0
1
1
1
1
1
0
1
0
Res
Res
TIM1
TIM2
TIM3
TIM4
Timer 1 Register
Timer 2 Register
Timer 3 Register
Timer 4 Register
0x054
0x055
0x056
0x057
w
Reload value
0
0
0
0
214
Nov. 28, 2002; 6251-546-1PD
Micronas
PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 31–27: Universal Asynchronous Receiver Transmitters (Base addr. 0xF90000)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
UA0D
UA1D
UART Data Register
0x0A0
0x018
23.3.
r
Receive register
Transmit register
w
x
x
x
x
x
x
x
x
Res
UA0C
UA1C
UART Control and
Status Register
0x0A1
0x019
r
RBUSY BRKD
FRER
OVRR
PAER EMPTY FULL TBUSY
0
x
x
0
x
1
0
0
Res
Res
w
x
x
x
x
STPB
ODD
PAR
LEN
x
x
x
x
0
0
0
0
UA0BR0
UA1BR0
UART Baudrate Reg- 0x0A2
ister low byte
w
Bit 7 to 0 of Baud Rate
0x01A
0
0
0
0
0
0
0
0
Res
Res
Res
Res
Res
UA0BR1
UA1BR1
UART Baudrate Reg- 0x0A3
ister high byte
w
x
x
x
Bit 12 to 8 of Baud Rate
0x01B
-
-
-
0
0
0
0
0
UA0IM
UA1IM
UART Interrupt Mask 0x0A4
Register
0x01C
w
x
x
x
x
x
ADR
BRK
RCVD
-
-
-
-
-
0
0
0
UA0CA
UA1CA
UART Compare
Address Register
0x0A5
0x01D
w
Bit 7 to 0 of address
0
0
0
0
0
0
0
0
UA0IF
UA1IF
UART Interrupt Flag
Register
0x0A6
0x01E
r
Test
Test
Test
Test
Test
ADR
BRK
RCVD
-
-
-
-
-
x
0
0
Micronas
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CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–28: Universal Ports (Base addr. 0xF90400)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
U0D
Universal Port Data/
Segment 0 Register
0x000
0x010
0x020
0x030
0x040
0x050
0x060
0x070
0x080
0x001
0x011
0x021
0x031
0x041
0x051
0x061
0x071
0x081
0x002
0x012
0x022
0x032
0x042
0x052
0x062
0x072
0x082
12.3.
r/w
D7
D6
D5
D4
D3
D2
D1
D0
Port
U1D
r/w SG7_0 SG6_0 SG5_0 SG4_0 SG3_0 SG2_0 SG1_0 SG0_0 LCD
U2D
0
0
0
0
0
0
0
0
Res
U3D
U4D
U5D
U6D
U7D
U8D
U0TRI
U1TRI
U2TRI
U3TRI
U4TRI
U5TRI
U6TRI
U7TRI
U8TRI
U0NS
U1NS
U2NS
U3NS
U4NS
U5NS
U6NS
U7NS
U8NS
Universal Port
Tristate/Segment 1
Register
r/w
T7
T6
T5
T4
T3
T2
T1
T0
Port
r/w SG7_1 SG6_1 SG5_1 SG4_1 SG3_1 SG2_1 SG1_1 SG0_1 LCD
1
1
1
1
1
1
1
1
Res
Universal Port Nor-
mal-Special/Seg-
ment 2 Register
r/w
S7
S6
S5
S4
S3
S2
S1
S0
Port
r/w SG7_2 SG6_2 SG5_2 SG4_2 SG3_2 SG2_2 SG1_2 SG0_2 LCD
Res
0
0
0
0
0
0
0
0
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PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 31–28: Universal Ports (Base addr. 0xF90400)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
U0DPM
U1DPM
U2DPM
U3DPM
U4DPM
U5DPM
U6DPM
U7DPM
U8DPM
U0SLOW
U1SLOW
U2SLOW
U3SLOW
U4SLOW
U5SLOW
U6SLOW
U7SLOW
U8SLOW
U0LVL
Universal Port Dou-
ble Pull-Down Mode/
Segment 3 Register
0x003
0x013
0x023
0x033
0x043
0x053
0x063
0x073
0x083
0x004
0x014
0x024
0x034
0x044
0x054
0x064
0x074
0x084
0x005
0x015
0x025
0x035
0x045
0x055
0x065
0x075
0x085
12.3.
r/w
D7
D6
D5
D4
D3
D2
D1
D0
Port
r/w SG7_3 SG6_3 SG5_3 SG4_3 SG3_3 SG2_3 SG1_3 SG0_3 LCD
0
0
0
0
0
0
0
0
Res
Universal Port Slow
Mode Register
r/w
S7
S6
S5
S4
S3
S2
S1
S0
0
0
0
0
0
0
0
0
Res
Universal Port Level
Register
r/w
A7
A6
A5
A4
A3
A2
A1
A0
U1LVL
0
0
0
0
0
0
0
0
Res
U2LVL
U3LVL
U4LVL
U5LVL
U6LVL
U7LVL
U8LVL
Micronas
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CDC 32xxG-B
PRELIMINARY DATA SHEET
Table 31–28: Universal Ports (Base addr. 0xF90400)
Mnemonic
Register Name
Offs.
Register Configuration
Section
7
6
5
4
3
2
1
0
U0PIN
Universal Port Pin
Register
0x006
0x016
0x026
0x036
0x046
0x056
0x066
0x076
0x086
0x007
0x017
0x027
0x037
0x047
0x057
0x067
0x077
0x087
12.3.
r
P7
P6
P5
P4
P3
P2
P1
P0
U1PIN
x
x
x
x
x
x
x
x
Res
U2PIN
U3PIN
U4PIN
U5PIN
U6PIN
U7PIN
U8PIN
U0MODE
U1MODE
U2MODE
U3MODE
U4MODE
U5MODE
U6MODE
U7MODE
U8MODE
Universal Port Mode
Register
r/w
L7
L6
L5
L4
L3
L2
L1
L0
0
0
0
0
0
0
0
0
Res
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PRELIMINARY DATA SHEET
CDC 32xxG-B
32. Control Register and Memory Interface
32.1. Control Register CR
When exiting Reset, the device will start up in a configuration
defined by the CR setting. For details on how to set the CR
see chapter “Core Logic”.
Emu Bus configured for external Flash
memory.
Pin signals FBUSQ, BWQ0 to 3 and CE1Q
are disabled and pulled low weakly.
In CPU SLOW mode pin signal CE0Q
activates flash memory only for 1/128th of
access cycle.
Emu Bus configured for standard external
Memory. CE0Q always enables memory
for full access cycle.
A full description of the functionality of all CR bits is given
below. Among others, the CR allows to configure the mem-
ory interface for connection to a variety of external memo-
ries.
r/w0:
CR
Control Register
EBW
Emu Bus Width (Emu/MCM parts only,
Table 32–1)
Emu Bus configured for 16bit wide external
Offs
7
6
5
4
3
2
x
1
x
0
r/w1:
r/w
x
x
x
x
x
x
3
2
1
0
memory.
Bits CR.PSA, CR.STPCLK and CR.RESLNG
are forced to one and bit CR.TSTTOG is
forced to zero.
Emu Bus configured for 32bit wide external
memory.
r/w STPCLK RESLNG
r/w EB2 TFT
r/w JTAG ENDIAN
x
x
x
TSTTOG
EASY
x
PSA
TETM
EB1
EBW
MFM
r/w0:
MAP
IBOOT IROM
IRAM
ICPU
Value of memory location 0x20 to 0x23
Res
EASY
Emu Bus in Asynchronous Mode
(Table 32–1)
(Emu/MCM parts only)
Emu Bus configured for asynchronous
external memory.
Emu Bus configured for synchronous
external memory.
The upper half word of register CR is loaded from location
0x22/0x23 only if flag EBW is at zero. If EBW is at one, the
upper half word is initialized to 0xFFFB.
r/w1:
r/w0:
STPCLK
r/w1:
r/w0:
Stop Clock (Emu parts only)
Timers are stopped in debug mode.
Timers are working during debug mode.
In synchronous mode the address bus (A) and chip enable
(CExQ) latches are transparent.
Timers are stopped with a resolution of 1/f0.
Table 32–1: Emu bus configuration for some commonly
used external memories
RESLNG
r/w1:
Reset Pulse Length
Pulse length is 8/FXTAL
r/w0:
Pulse length is 2048/FXTAL
This bit specifies the length of the reset pulse which is output
at pin RESETQ following an internal reset. If pin TEST is 1
the first reset after power on is short. The following resets are
as programmed by RESLNG. If pin TEST is 0 all resets are
long.
External Memory Type
Program Mem-
ory (CE0Q)
Data or BOOT
Memory (CE1Q)
1
0
0
0
1
1
0
0
1
0
1
1
32-Bit sync SRAM (e.g.
TSTTOG
TEST2 Pin Toggle (Table 32–8)
MT55L256L32F)
This bit is used for test purposes only. If TSTTOG is true in IC
active mode, pin TEST2 can toggle the Multi Function pins
between Bus mode and normal mode.
32-Bit async Flash
(e.g. 2 x Am29F400BT)
PSA
r/w1:
r/w0:
Program Storage Access
16bit access.
32bit access.
16-Bit async.
don’t use
Flash
(e.g.
Am29F400BT)
This bit allows, in EMU parts, to set the data bus access
width to ROM, BootROM and Flash program storage.
EB2
r/w1:
r/w0:
External Bus Flag 2 (Table 32–1)
0
0
0
1
0
1
1
1
32-Bit async Flash
(e.g. 2 x Am29LV400BT)
CE0Q and CE1Q select two external chips.
OEQ and WEQ select one external chip
connected to CE0Q (don’t use CE1Q).
16-Bit async.
don’t use
Flash
(e.g.
Am29LV400BT)
TFT
Trace Bus Full Trace (Emu parts only,
Table 32–2)
TETM
EB1
Trace Bus ETM (Emu parts only, Table 32–2)
MFM
Multi Function pin Mode (Tables 32–8)
External Bus Flag 1 (Emu/MCM parts only,
Table 32–1)
r/w1:
Power saving mode of memory interface.
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CDC 32xxG-B
PRELIMINARY DATA SHEET
JTAG
r/w1:
r/w0
Application JTAG Interface
Enabled if TEST2 pin is high (Fig. 32–2)
Disabled
IBOOT
IROM
IRAM
Internal Boot ROM (Tables 32–4, 32–7)
Internal ROM (Table 32–5)
Internal RAM (Tables 32–6, 32–7)
ENDIAN
r/w1:
r/w0:
Endian setting ARM Core
Little endian.
Big endian.
ICPU
r/w1:
r/w0:
Internal CPU
Enable internal CPU.
Disable internal CPU
Don’t change this flag dynamically
MAP
Mapping (Table 32–3)
ICPU
Data Bus
0
Test Bus
Mux
1
CPU
Ports
MFM0
≥1
IRAM
&
MFM1
&
predecram
MFM0
MFM1
RAM
&
&
IRAM
predecram
IROM
&
&
&
≥1
IROM
TESTTOG
TEST2 Pin
&
predecrom
predecrom
IBOOT
≥1
ROM
external access
predecboot
predecio
IBOOT
&
predecboot
Boot
Emu only
≥1
TFT
&
MFM0
MFM1
EMUTRI
EMUTRI
TETM
Addr. & Ctrl.
Mem Ifc
ETM
0
TFT
&
Trace Bus
Mux
1
Analyzer
Fig. 32–1: Bus Interfaces
CR.JTAG
Table 32–2: TETM and TFT Usage
Appl. JTAG
interface
TEST2
Trace Bus
Mode
D0 to D31 active
ETM
&
Emu. JTAG
interface
nTRST
1
1
1
Disabled (Gnd)
(Except for
for external mem-
ory access only
Off
Emu only
DBGACK, nRE-
SET, FSYS)
Fig. 32–2: Enabling JTAG Interfaces
0
1
1
0
Analyzer
ETM
always
Off
On
for external mem-
ory access only
0
0
ETM
always
On
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PRELIMINARY DATA SHEET
CDC 32xxG-B
Table 32–3: MAP usage
Table 32–8: TSTTOG and MFM usage in ROM/Flash parts
MAP
Mapping Effect
MFM
Multi Function Pins
1
0
0
1
0
0
1
x
1
0
mirrors RAM base offset 0xC0.0000 to 0
maps ROM/Flash base offset 0x20.0000 to 0
mirrors Boot ROM base offset 0xF0.0000 to 0
0
0
1
0
1
0
1
x
0
1
x
0
1
x
0
1
x
Bus mode 0
Bus mode 0
Port mode
Bus mode 1
Bus mode 1
Port mode
Bus mode 2
Bus mode 2
Port mode
Port mode
Table 32–4: IBOOT usage
MFM selected Boot ROM source
QFP128 Emu
0
1
1
0
1
1
0
x
1
x
0
0
x
0
1
x
external via Multi Function pins in Bus
mode
0
1
disable Boot ROM
internal Boot ROM
ext. via Emu bus
1
x
Table 32–5: IROM usage
selected ROM/Flash source
QFP128 Emu
external via Multi Function pins in Bus mode
0
1
internal ROM/Flash
external via Emu bus
Table 32–6: IRAM usage
MFM selected RAM source
QFP128
1
0
x
1
x
0
Emu
0
x
0
1
x
external via Multi Function pins in Bus
mode
disable RAM
internal RAM
ext. via Emu bus
1
Table 32–7: CE1Q Selections
CE1Q selects
RAM
Boot ROM
internal
0
1
1
x
0
1
external
internal
external
No external access
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32.2. External Memory Interface
32.2.1. Interfacing examples
EVDD = 5V is required for the following interfacing examples.
5V
RESET#
CE#
OE#
WE#
CE0Q
OEQ
BYTE#
RY/BY#
WEQ/RWQ
Flash-EEPROM
256k x 16
A[17:0]
A[18:8], AICU[7:2], AMCS1
D[15:0]
DQ[15:0]
GND
Fig. 32–3: Asynchronous Flash EEPROM (e.g. Am29F400B) as program memory
BWQ0
BWQ1
BWQ2
BWQ3
5V
CExQ
OEQ
CE#
WE#
OE#
CE#
WE#
OE#
CE#
WE#
OE#
CE#
WE#
OE#
A[18:0]
I/O[7:0]
A[18:0]
I/O[7:0]
A[18:0]
I/O[7:0]
A[18:0]
I/O[7:0]
GND
A[20:8], AICU[7:2]
D[31:0]
D[31:24]
D[23:16]
D[15:8]
D[7:0]
Fig. 32–4: Asynchronous SRAM (e.g. KM684002B) as emulation program memory
3V3
CLK
CKE
MODE
ZZ
FBUSQ
CE0Q
CE#
R/W#
BW#[d:a]
WEQ/RWQ
BWQ[3:0]
CE2
SSRAM
256k x 32
CE2#
OE#
SA, SA1,SA0
A[19:8], AICU[7:2]
D[31:0]
DQ[d:a]
ADV/LD#
GND
Fig. 32–5: Synchronous SRAM (e.g. MT55L256L32F) as emulation program memory
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CDC 32xxG-B
3V3
CLK
CKE
MODE
ZZ
FBUSQ
CE1Q
CE#
R/W#
BW#[d:a]
WEQ/RWQ
BWQ[3:0]
CE2
SSRAM
256k x 32
CE2#
OE#
SA, SA1,SA0
A[19:8], AICU[7:2]
D[31:0]
DQ[d:a]
ADV/LD#
GND
Fig. 32–6: Synchronous SRAM (e.g. MT55L256L32F) as emulation RAM or boot memory
32.2.2. External Trace Interfacing
For a mapping of the IC pins to external trace tools see the
Specification of the Evaluation Board Kit (EVB).
32.2.3. Memory Interface Characteristics
Table 32–9: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.5V<EVDDn<5.5V,
TCASE= 0 to 35°C, CL = 70pF
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
DFBUSQ
FBUSQ High to Low Ratio
47.5
52.5
%
PLL mode
Synchronous SRAM
t
t
t
t
t
t
t
sync Address Setup Time
0
ns
ns
ns
ns
ns
ns
ns
13ns ADB to Pad, 4ns Pad to DB
sAS
sync Address Hold Time
sync Chip Enable Setup
sync Data Setup Read Time
sync Data Hold Read Time
sync Data Setup Write Time
sync Data drive Tristate
0
sAH
0
20
15
sCES
sDSR
sDHR
sDSW
sDDT
25
0
0
0
Asynchronous SRAM
t
t
t
t
t
t
t
async Address Setup Time
0
0
10
10
ns
ns
ns
ns
ns
ns
ns
aAS
async Address Hold Time
async Chip Enable Setup
async Output Enable Setup
async Byte Write Setup
async Data Setup Read
async Data Hold Read Time
0
aAH
aCES
aOES
aBWS
aDSR
aDHR
0
0
25
0
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CDC 32xxG-B
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Table 32–9: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.5V<EVDDn<5.5V,
TCASE= 0 to 35°C, CL = 70pF
Symbol
Parameter
Min.
Typ.
Max.
Unit
ns
Test Conditions
t
async Data Setup Write
async Data drive Tristate
0
15
aDSW
t
0
ns
aDDT
Table 32–10: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V,
3V<EVDDn=FVDD<3.6V, TCASE= -40 to 85°C, CL = 10pF
Symbol
Asynchronous Flash
async Address Setup Time
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
t
0
ns
12ns ADB to Pad, 5ns Pad to DB
aAS
FSYS
nWAIT
FBUSQ
A
t
t
t
t
sAS
sCES
sAS
sAS
t
t
t
t
t
sAH
sAH
sAH
sAH
A1
A2
A3
CExQ
WEQ/RWQ
BWQ[3:0]
D[31:0]
t
t
t
sDDT
sDSW
sDSR
sDHR
D1
D2
D3
6)
6)
6)
6)
read data
read data
write data
Fig. 32–7: Sync SRAM Timing, 0 Wait States
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PRELIMINARY DATA SHEET
CDC 32xxG-B
FSYS
nWAIT
FBUSQ
t
t
sAS
t
sAH
A1
A2
A
sCES
t
sAH
CExQ
WEQ/RWQ
BWQ[3:0]
D[31:0]
t
t
sDSR
sDHR
D1
D2
6)
6)
read data, no wait state
6)
read data, 1 wait state
write data
Fig. 32–8: Sync SRAM Timing, Read with Wait State, followed by a Write Cycle
FSYS
nWAIT
FBUSQ
t
t
t
t
sAS
sCES
sAS
sAS
t
sAH
A1
A2
A
t
t
t
sAH
sAH
sAH
CExQ
WEQ/RWQ
BWQ[3:0]
D[31:0]
t
t
sDSW
sDDT
D1
D2
write data, 1 wait state
6)
6)
read data
6)
write data, no wait state
Fig. 32–9: Sync SRAM Timing, Write with Wait State, followed by a Read Cycle
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CDC 32xxG-B
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FSYS
nWAIT
FBUSQ
CExQ
t
aCES
t
aAH
t
aAS
t
aAH
A1
A2
A3
A4
A
t
t
aAH
aOES
OEQ
t
t
aAH
aBWS
BWQ[3:0],
WEQ/RWQ
t
t
t
t
aDDT
aDSW
aDSR
aDHR
D[31:0]
D1
D2
D3
D4
6)
6)
6)
6)
6)
write data
read data
read data
write data
Fig. 32–10: Async SRAM/Flash Timing, 0 Wait States
FSYS
nWAIT
FBUSQ
t
t
aCES
t
t
t
aAH
aAH
aAH
CExQ
A
aAS
A1
A2
t
aOES
OEQ
BWQ[3:0], WEQ/RWQ
t
t
aDHR
aDSR
D[31:0]
6)
D1
D2
6)
read data, 1 wait state
6)
write data
read data, no wait state
Fig. 32–11: Async SRAM/Flash Timing, Read with Wait State, followed by a Write Cycle
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CDC 32xxG-B
FSYS
nWAIT
FBUSQ
t
t
aCES
t
aAH
CExQ
A
aAS
t
aAH
A1
A2
OEQ
t
t
aAH
aBWS
BWQ[3:0],
WEQ/RWQ
t
t
aDSW
aDDT
D[31:0]
D1
D2
write data, 1 wait state
6)
6)
read data
6)
write data, no wait state
Fig. 32–12: Async SRAM/Flash Timing, Write with Wait State, followed by a Read Cycle
6) During the high level of FBUSQ the previous data bus levels are weakly held. Thus the data bus is defined when the bus drivers
are tristate and FBUSQ is high. See section ‘Electrical Characteristics’ for the weak hold currents for pull-down (Ipd) and for pull-
up (Ipu).
fast mode
slow mode
FSYSint
FBUSQint
CE0Q
WEQ/RWQ
OEQ
Fig. 32–13: CE0Q Timing in PLL/FAST and SLOW/DEEP SLOW modes (CR.EB2 set to 0, CR.EB1 and CR.EASY set to 1)
CE0Q is used for low power mode. Input data are latched
with the rising edge of CE0Q and are weakly held as long as
CE0Q stays high.
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PRELIMINARY DATA SHEET
CDC 32xxG-B
33. Differences
This chapter describes differences of this document to pre-
decessor document “CDC32xxG-B V3.0 Automotive Control-
ler Family Hardware Manual, CDC3205G-B Automotive Con-
troller Specification“ (6251-546-4AI)
#
1
2
Section
Description
Introduction
Example Mask ROM Part replaced by CDC3272G-B, T
Absolute Maximum Ratings: editorial corrections.
extended.
CASE
Electrical Characteristics
Recommended Operating Conditions: editorial corrections.
Characteristics:
various editorial changes,
changed definition: UI
, UI
, BV
, BI
, t
, most ADC parameters, R of quartz
DDs
DDd
DD_ro
DD_rlim BVDD_su 1
changed value: T
range, UI
, UI
, HI
, V -V , I , I , V (H-Ports), V (H-Ports), I
,
CASE
DDs
DDd
DDq
ilhc ihlc pd pu ol
oh
shf
I
, I
, V
, t
, AV -AV , t
, C , dt
shs shsd
REFINT ACDEL
lh
hl UCDEL i PLL
added parameters: I
DD_rlimr
3
CPU and Clock System
CPU mode switching changed.
PWM, PFM and CAPCOM: operability during CPU-Active modes corrected.
ERM table replaced by version from Errata V3.6, F
ERM deactivation procedure corrected.
max. reduced.
SYS
4
5
Core Logic
I2C
Description of the Watchdog module clarified.
Reset Logic Block Diagram clarified.
Block diagram corrected.
Initialization corrected.
Description of Write-FIFO half full interrupt corrected.
Read-FIFO behavior clarified.
Description of DACK flag clarified.
Table 32-1 corrected.
6
7
Control Register and Mem-
ory Interface
Differences
Chapter added.
Micronas
Nov. 28, 2002; 6251-546-1PD
229
CDC 32xxG-B
PRELIMINARY DATA SHEET
34. Data Sheet History
1. Preliminary Data Sheet: “CDC 32xxG-B Automotive
Controller Family User Manual, CDC 3205G-B Auto-
motive Controller”, Nov. 28, 2002, 6251-546-1PD. First
release of the preliminary data sheet.
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com
Printed in Germany
Order No. 6251-546-1PD
230
Nov. 28, 2002; 6251-546-1PD
Micronas
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