CLLE1AX7R0G1R5MT [TDK]
CAPACITOR, CERAMIC;
| 型号： | CLLE1AX7R0G1R5MT |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | CAPACITOR, CERAMIC |
| 文件： | 总26页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPECIFICATION
SPEC. No.
DATE :
Upon the acceptance of this spec.
previous spec. (C2004-1306-023)
shall be abolished.
CUSTOMER’S PRODUCT NAME
TDK PRODUCT NAME
CLLC1A, CLLE1A Series
Please sign and return this specification to your local TDK representatives. If orders are placed
without this returned documentation, we must consider you found the specification acceptable.
THIS SPECIFICATION IS RECEIVED
DATE:
YEAR
MONTH
DAY
TDK-EPC Corporation
1-13-1, Nihonbashi, Chuo-ku, Tokyo
103-0027, Japan
ENGINEERING
ISSUED
CHECKED
APPROVED
DATE
DATE
DATE
Sales Office
Sales Tel.
(
)
PRODUCT CLASSIFICATION
CODE
040320
REV 0.3 201012
1. SCOPE
This specification is applicable to chip type multilayer ceramic capacitors with a priority over other
relevant specifications. Production places defined in this specification shall be TDK-EPC Corporation
Japan, TDK (Suzhou) Co., Ltd, TDK-EPC HONG KONG LIMITED, TDK (Malaysia) Sdn. Bhd, and TDK
Components U.S.A. Inc.
EXPLANATORY NOTE:
This specification warrants the quality of the TDK ceramic chip capacitors. The product should be
evaluated and confirmed in your product before use. If the use of the product exceeds the bounds of
this specification, we can not guarantee its quality and reliability.
2. CODE CONSTRUCTION
(Example)
CLLC1A
CLLE1A
(1)
X7S
X7S
(2)
0G
0G
(3)
105
475
(4)
M
M
(5)
T
T
(6)
1. Type
L
T
CL
W
P
C
Please refer to product list for the dimension of each product. See Section 8 for inside structure
and material.
2. Temperature Characteristics (Details are shown in Section 7, No.6)
3. Rated Voltage
Symbol
1A
Rated Voltage
DC 10 V
0J
DC 6.3 V
0G
DC 4 V
4. Rated Capacitance
Stated in three digits and in units of pico farads (pF).
The first and second digits identify the first and second significant figures of the capacitance; the
third digit identifies the multiplier.
R is designated for a decimal point.
Example 105
→
1,000,000pF
1 of 25
5. Capacitance tolerance
6. Packaging
Symbol
M
Tolerance
± 20 %
Symbol
Packaging
Bulk
B
T
Taping
3. RATED CAPACITANCE AND CAPACITANCE TOLERANCE
1. Standard combination of rated capacitance and tolerances
Temperature
Capacitance tolerance
Characteristics
Rated capacitance
E – 6 series
X7R
M (± 20 %)
X7S
2. Capacitance Step in E series
E series
E- 6
Capacitance Step
2.2 3.3
1.0
1.5
4.7
6.8
4. OPERATING TEMPERATURE RANGE
Min. operating
Temperature
Max. operating
Temperature
Reference
Temperature
T.C.
X7R
-55°C
X7S
125°C
25°C
5. STORING CONDITION AND TERM
5 to 40°C at 20 to 70%RH
6 months Max.
6. INDUSTRIAL WASTE DISPOSAL
Dispose this product as industrial waste in accordance with the local Industrial Waste Laws.
2 of 25
7. PERFORMANCE
No.
1
Item
Performance
Test or inspection method
External Appearance No defects which may affect
performance.
Inspect with magnifying glass.
(3X magnifications)
2
3
Insulation Resistance 100MΩ·μF min.
Apply rated voltage for 60s.
Measure 8 terminal electrodes at the same
time.
Withstand test voltage without
insulation breakdown or other
damage.
Voltage Proof
2.5 times of rated voltage
Above DC voltage shall be applied for
1~5s.
Charge / discharge current shall not
exceed 50mA.
Measure 8 terminal electrodes at the same
time.
4
Capacitance
Within the specified tolerance at
1000hrs age (Per IEC-384-9).
Measuring
frequency
Measuring
voltage
WV
10V
1.0±0.2Vrms.
0.5±0.2Vrms.
1kHz±10%
6.3V and
under
Measure 8 terminal electrodes at the same
time.
5
6
Dissipation Factor
Characteristics
See No.4 in this table for measuring
condition.
T.C.
X7R
X7S
D.F.
0.10 max.
Temperature
Capacitance shall be measured by the
steps shown in the following table after
thermal equilibrium is obtained for each
step.
Capacitance Change (%)
No DC voltage applied
Characteristics
of Capacitance
X7R : ±15
X7S : ±22
Capacitance change shall be calculated by
the value of the reference temperature in
Step 3.
Step
Temperature(°C)
25 ± 2
1
2
3
4
-55 ± 2
25 ± 2
125 ± 2
3 of 25
(7. Performance, continued)
No. Item
7 Robustness of
Terminations
Performance
Test or inspection method
No sign of termination coming off, Reflow solder the capacitors on P.C.
breakage of ceramic, or other
abnormal signs.
board (shown in Appendix 1 and 2) and
apply a pushing force of for 10±1s.
2N
P.C. board
Capacitor
8
Solderability
All terminations shall exhibit a
continuous solder coating free
from defects for a minimum of
75% of the surface area of any
individual termination. Anomalies
Completely soak both terminations in
solder at 235±5°C for 2±0.5s.
Solder : H63A (JIS Z 3282)
other than dewetting, non-wetting, Flux : Isopropyl alcohol (JIS K 8839)
and pin holes are not cause for
rejection.
Rosin(JIS K 5902) 25% solid
solution.
A section
9
Resistance External
No cracks are allowed and
Completely soak both terminations in
solder at 260±5°C for 5±1s.
to solder
heat
appearance terminations shall be covered at
least 60% with new solder.
Capacitance
Preheating condition
Temp. : 150±10°C
Time : 1 to 2min.
Change from the
Characteristics
value before test
X7R
± 7.5 %
X7S
Flux : Isopropyl alcohol (JIS K 8839)
Rosin (JIS K 5902) 25% solid
solution.
D.F.
Meet the initial spec.
Meet the initial spec.
Solder : H63A (JIS Z 3282)
Insulation
Resistance
Leave the capacitor in ambient
conditions for 24±2h before
measurement.
4 of 25
(7. Performance, continued)
No. Item
10 Vibration External
Performance
Test or inspection method
No mechanical damage.
Reflow solder the specimen on P.C.
board (shown in Appendix 1 and 2)
before testing.
appearance
Capacitance
Change from the
Characteristics
Vibrate the specimen with amplitude of
1.5mm p-p sweeping the frequencies
from 10Hz to 55Hz and back to 10Hz in
a minute.
value before test
X7R
X7S
± 7.5 %
D.F.
Meet the initial spec.
Repeat this cycle for 2h each in 3
perpendicular directions (6h in total).
11 Temperature External
cycle appearance
Capacitance
No mechanical damage.
Reflow solder the capacitor on P.C.
board (shown in Appendix 1 and 2)
before testing.
Change from the
Characteristics
Expose the specimens in the condition
step 1 through 4 and repeat 5 times
consecutively.
value before test
X7R
X7S
± 7.5 %
Leave the specimen in ambient
conditions for the following time before
measurement.
D.F.
Meet the initial spec.
Meet the initial spec.
Insulation
Resistance
Voltage
proof
Step Temperature(°C) Time (min.)
No insulation breakdown or other
damage.
-55±3
25
1
2
3
4
30 ± 3
2 - 5
125± 2
25
30 ± 2
2 - 5
5 of 25
(7. Performance, continued)
No.
Item
External
Performance
Test or inspection method
12 Moisture
No mechanical damage.
Reflow solder the capacitor on P.C.
board (shown in Appendix 1 and 2)
before testing.
Resistance appearance
(Steady
State)
Capacitance
Change from the
Characteristics
Leave at temperature 40 ± 2°C, 90 to
95%RH for 500 +24,0h.
value before test
X7R
X7S
± 12.5 %
Leave the specimen in ambient
conditions for 24±2h before the
measurement.
D.F.
Characteristics
X7R/X7S :
200% of initial spec. max.
10MΩ·μF min.
Insulation
Resistance
13 Moisture
External
No mechanical damage.
Reflow solder the capacitor on P.C.
board (shown in Appendix 1 and 2)
before testing.
Resistance appearance
Capacitance
Change from the
Apply the rated voltage at temperature
40±2°C, and 90 to 95%RH for
500+24,0h
Characteristics
value before test
X7R
X7S
± 12.5 %
Charge/discharge current shall not
exceed 50mA.
D.F.
Characteristics
X7R/X7S :
Leave the capacitor in ambient
conditions for 48 ± 4h before
measurement.
200% of initial spec. max.
Insulation
Resistance
5MΩ·μF min.
Voltage conditioning:
Voltage treats the specimen under
testing temperature and voltage for 1
hour.
Leave the capacitor in ambient
conditions for 24 ± 2h before
measurement.
Use this measurement for initial value.
6 of 25
(7. Performance, continued)
No.
Item
External
Performance
Test or inspection method
14 Life
No mechanical damage.
Reflow solder the capacitor on P.C.
board (shown in Appendix 1 and 2)
before testing.
appearance
Capacitance
Change from the
Characteristics
Apply the rated voltage at 125±2°C for
1,000 +48,0h
value before test
X7R
X7S
± 15 %
Charge/discharge current shall not
exceed 50mA.
D.F.
Characteristics
X7R/X7S :
Leave the specimen in ambient
conditions for 24±2h before
measurement.
200% of initial spec. max.
Insulation
10MΩ·μF min.
Voltage conditioning:
Resistance
Voltage treats the capacitor under
testing temperature and voltage for 1
hour.
Leave the specimen in ambient
conditions for 48±4h before
measurement as initial value.
7 of 25
Appendix 1
CLLC1A
PC Board
50.0
41.25
50.0
41.25
3.0
2.5
4.0
1.5
1.1
0.8
1.1
0.8
0.6
0.6
0.4
0.19
(Unit: mm)
1. Material: Glass Epoxy (As per JIS C6484 GE4)
2. Thickness: 0.8mm
Copper (Thickness: 0.035mm)
Solder resist
8 of 25
Appendix 2
CLLE1A
PC Board
50.0
41.25
1.5
50.0
41.25
3.0
2.5
4.0
19.0
10.0
2.0
20.0
18.0
20.0
20.0
10.0
7.0
7.0
5.0
5.0
4.0
15.0
1.5
1.1
1.5
1.1
0.85
0.85
0.5 pitch
0.7
8.3
8.3
0.1
1.05
1.05
0.9
0.9
0.3
0.4
0.4
(Unit: mm)
1. Material: Glass Epoxy (As per JIS C6484 GE4)
2. Thickness: 1.6mm
Copper (Thickness: 0.035mm)
Solder resist
9 of 25
8. INSIDE STRUCTURE AND MATERIAL
A’
B’
B
A
3
A − A’
B − B’
4
5
2
1
MATERIAL
No.
1
NAME
Dielectric
Electrode
BaTiO3
Ni
2
3
Cu
Termination
4
Ni
5
Sn
9. EQUIVALENT CIRCUIT
8)
–
7)
+
6)
–
5)
+
+ 1) 3) 5) 7)
– 2) 4) 6) 8)
+
1)
–
2)
+
3)
–
4)
8 terminals are connected and
measured at the same time.
10 of 25
12. Caution
No.
Process
Condition
1.1 Storage
Operating
1. The capacitor must be stored in an ambient temperature of 5 to 40°C with a relative
Condition
humidity of 20 to 70%RH. The product should be used within 6 months upon receipt.
(Storage,
2. The capacitor must be operated and stored in an environment free of condensation and
corrosive gases such as hydrogen sulphide, hydrogen sulphate, chlorine, ammonia and
sulfur.
Transportation)
3. Avoid storing in sun light and falling of dew.
4. Do not use capacitor under high humidity and high/low atmospheric pressure which
may compromise product reliability.
5. Capacitor should be tested for solderability when stored for long periods of time.
1.2 Handling in transportation
In case of the transportation, the performance of the capacitor may be deteriorated
depending on the transportation condition. (Refer to JEITA RCR-2335B 9.2 “Handling
in transportation”)
2.1 Operating temperature
2
Circuit design
Operating temperature should be followed strictly within this specification.
1. Do not use capacitors above the maximum allowable operating temperature.
2. Surface temperature including self heating should be below maximum operating
temperature.
(Due to dielectric loss, capacitors will heat itself when AC is applied. Especially at high
frequencies around its SRF, the heat might be so extreme that it may damage itself or the
product it’s mounted on. Please design the circuit so that the maximum temperature of
the capacitors (including the self heating) will be below the maximum allowable operating
temperature. Temperature rise at capacitor surface shall be below 20°C)
3. The electrical characteristics of the capacitor will vary depending on the temperature. The
capacitor should be selected and designed after taking temperature into consideration.
2.2 Operating voltage
1.
Operating voltage across the terminals should be below the rated voltage.
When AC and DC are super imposed, V0-P must be below the rated voltage. (Reference
figures 1 and 2 below).
AC or pulse with overshooting, VP-P must be below the rated voltage. (Reference
figures 3, 4, and 5 below).
When the voltage is started/stopped to the circuit an irregular voltage may be generated
for a transit period because of resonance or switching. Be sure to use the capacitor
within rated voltage during these Irregular voltage periods.
Voltage
(1) DC voltage
(2) DC+AC voltage
(3) AC voltage
Positional
Measurement
(Rated voltage)
V0-P
V0-P
VP-P
0
0
0
Voltage
(4) Pulse voltage (A) (5) Pulse voltage (B)
Positional
Measurement
VP-P
VP-P
0
(Rated voltage)
0
11 of 25
(10. Caution, continued)
No.
2
Process
Condition
Circuit design
(continued)
2.2 Operating Voltage (continued)
2. Even below the rated voltage, if repetitive high AC frequency or pulsed voltage is
applied, the reliability of the capacitors may be reduced.
3. The effective capacitance will vary depending on applied DC and AC voltages.
The capacitor should be selected after considering the voltage affect.
2.3 Frequency
When Class 2 capacitors are used in AC and/or pulsed voltages, the capacitor
may self vibrate and generate audible sound (piezoelectric affect).
3
Designing
P.C. Board
The amount of solder at the terminations has a direct effect on the reliability of the
capacitors.
1. The greater the amount of solder, the higher the stress on the chip capacitor, and
the more likely that it will break. When designing a P.C. board, determine the shape
and size of the solder lands to have proper amount of solder on the terminations.
2. Avoid using common solder land for multiple terminations and provide individual
solder land for each termination instead.
3. Size and recommended land dimensions provided below:
B
A
P
D
C
Recommended Land Dimensions (mm)
Type
CLLC1A
CLLE1A
(CC0603)
(CC0805)
Symbol
A
0.25
0.4
1.2
0.4
0.4
0.3
B
C
D
P
0.3 ~ 0.6
1.3 ~ 1.8
0.5 ~ 0.8
0.5
12 of 25
(10. Caution, continued)
No.
3
Process
Designing
Condition
4. Recommended chip capacitor layout is provided below:
P.C. board
(continued)
Disadvantage against
bending stress
Advantage against
bending stress
Perforation or slit
Perforation or slit
Mounting
face
Break P.C. board with
mounted side up.
Break P.C. board with
mounted side down.
Mount perpendicularly to
perforation or slit
Mount in parallel with
perforation or slit
Perforation or slit
Perforation or slit
Chip
arrangement
(Direction)
Closer to slit is higher stress
Away from slit is less stress
ℓ1
ℓ2
Distance
from slit
(ℓ1 < ℓ2
)
(ℓ1 < ℓ2)
13 of 25
(10. Caution, continued)
No.
3
Process
Condition
Designing
P.C. board
(continued)
5. Mechanical stress varies according to location of chip capacitor on the P.C. board.
E
D
Perforation
C
A
B
Slit
The relative stress applied to these capacitors during depaneling is in the following
order:
A > B = C > D > E
4.1 Stress from mounting head
4
Mounting
If the mounting head is adjusted too low, it may induce excessive stress on the chip
capacitors and result in cracking. Please take following precautions:
1. Adjust the bottom dead center of the mounting head to reach the P.C. board surface
and but not contact it.
2. Adjust the mounting head pressure to be 1 to 3N of static weight.
3. To minimize the impact energy from mounting head, it is important to provide support
from the bottom side of the P.C. board. See following examples.
Not recommended
Recommended
Crack
Single sided
mounting
Support pin
Double-sides
mounting
Solder
peeling
Crack
Support pin
When the centering jaw is worn, mechanical impact on the capacitor may occur and damage
the product. Please control the closing dimension of the centering jaw and provide sufficient
preventive maintenance and/or replacement if necessary.
14 of 25
(10. Caution, continued)
No.
5
Process
Soldering
Condition
5.1 Flux selection
Although highly-activated flux gives better solderability, substances which Increase
activity may also degrade the insulation of the chip capacitor. To avoid such
degradation, the following is recommended.
1. It is recommended to use a mildly activated rosin flux (less than 0.1wt%
chlorine).
2. Excessive flux must be avoided. Please provide proper amount of flux.
3. When water-soluble flux is used, sufficient washing is necessary.
5.2 Recommended soldering profile by various methods
Reflow soldering
Soldering
Preheating
Natural cooling
Peak
Temp
∆T
0
Over 60 sec.
Peak Temp time
Manual soldering
(Solder iron)
300
∆T
Preheating
0
3sec. (As short as possible)
5.3 Recommended soldering peak temp and duration
Peak temp
Duration
Pb-Sn Solder
230°C max.
260°C max.
20 sec. max.
10 sec. max.
Lead Free
Solder
Recommended solder compositions
Sn-37Pb (Pb-Sn solder)
Sn-3.0Ag-0.5Cu (Lead Free Solder)
15 of 25
(10. Caution, continued)
No.
5
Process
Soldering
(continued)
Condition
5.4 Avoiding thermal shock
1. Preheating condition
Soldering
Temp. (°C)
Reflow soldering
Manual soldering
∆T ≤ 150
∆T ≤ 150
2. Cooling condition
Natural cooling using air is recommended. If the chips are dipped into a solvent for
cleaning, the temperature difference (∆T) must be less than 100°C.
5.5 Amount of solder
Excessive solder will induce higher tensile force on the chip capacitor during
temperature changes and may result in chip cracking. In sufficient solder may
detach the capacitor from the P.C. board.
5.6 Amount of solder
Excessive solder will induce higher tensile force in chip capacitor when
temperature changes and it may result in chip cracking. Insufficient solder may
detach the capacitor from the P.C. board.
Higher tensile force on the
chip capacitor may cause
cracking.
Excessive
solder
Maximum amount
Adequate
solder
Minimum amount
Small solder fillet may
Insufficient
solder
cause contact failure or not
hold the chip capacitor to
the P.C. board.
5.7 Solder repair by solder iron
1. Selection of the soldering iron tip
Tip temperatures of solder iron varies by its type, P.C. board material and solder
land size. Higher temperatures may provide quicker operation, however heat shock
may cause a crack in the chip capacitor. Please confirm the tip temperature
before soldering and keep the peak temperature and time in accordance with
following recommended condition. (Please preheat the chip capacitors with the
condition in 5.4 to avoid the thermal shock.)
Recommended solder iron condition (Pb-Sn Solder and Lead Free Solder)
Temp. (°C)
Duration (sec.)
Wattage (W)
Shape (mm)
300 max.
3 max.
20 max.
Ø 3.0 max.
16 of 25
(10. Caution, continued)
No.
5
Process
Condition
Soldering
(continued)
2. Direct contact of the soldering iron with ceramic dielectric of the chip capacitor may
cause cracking. Do not touch the ceramic dielectric and the terminations by solder
iron.
5.8 Sn-Zn solder
Sn-Zn solder affects product reliability.
Please contact TDK in advance when utilize Sn-Zn solder.
5.9 Countermeasure for tombstone
The misalignment between the mounted positions of the capacitors and the land
patterns should be minimized. The tombstone phenomenon may occur especially
when the capacitors are mounted (in longitudinal direction) in the same direction of
the reflow soldering. (Refer to JEITA RCR-2335B Annex A “Recommendations to
prevent the tombstone phenomenon”)
6
Cleaning
1. If an unsuitable cleaning fluid is used, flux residue or some foreign articles may stick
to the chip capacitor surface and deteriorate the insulation resistance.
2. If cleaning condition is not suitable, it may deteriorate the chip capacitor’s insulation
resistance.
2.1 Insufficient washing
1. Lead wire and terminal electrodes may be corroded by Halogen in the flux.
2. Halogen in the flux may adhere on the surface of capacitor, and lower the
insulation resistance.
3. Water soluble flux has higher tendency to have above mentioned problems (1)
and (2).
2.2 Excessive washing
1. Excessive washing may damage the coating material of coated capacitor and
deteriorate it.
2. When ultrasonic cleaning is used, excessively high energy output can affect the
connection between the ceramic chip capacitor's body and the terminal electrode.
To avoid this, the following is recommended.
Power: 20W/ℓmax.
Frequency: 40kHz max.
Washing time: 5 minutes max.
2.3 If the cleaning fluid is contaminated, of Halogen concentration can increases, and
bring the same result as insufficient cleaning.
7
Coating and
molding of the
P.C. Board
1. When the P.C. board is coated, please verify the impact on the capacitor.
2. Please carefully verify that there is no harmful decomposing or reaction gas
emission during curing which may damage the chip capacitor.
3. Please verify the curing temperature.
17 of 25
(10. Caution, continued)
No.
8
Process
Condition
Handling after
chip mounted
1. Please pay attention not to bend or distort the P.C. board after soldering, otherwise
the chip capacitor may crack.
Bend
Twist
2. When functional check of the P.C. board is performed, higher pin pressure tends to
be used for fear of loose contact. But if the pressure is excessive and bends the
P.C. board, it may crack the chip capacitor or peel the termination. Please adjust
the pins accordingly to ensure the P.C. Board is not flexed.
Item
Not recommended
Recommended
Termination
Support pin
Board
bending
Check pin
Check pin
9
Handling of loose
chip capacitor
1. The chip capacitor may crack if dropped, especially large case sizes. Please
handle with care and do not use if dropped.
Crack
Floor
18 of 25
(10. Caution, continued)
No.
9
Process
Condition
Handling of loose
chip capacitor
(continued)
2. When stacking the P.C. board for storage or handling after soldering, the corner of
the P.C. Board may hit the chip capacitor of a neighboring board to cause a crack.
P.C. Board
Crack
10 Capacitance
aging
Class 2 capacitors have an aging characteristic, which is a decrease in capacitance
over time due to crystalline changes that occur in ferroelectric ceramics. Careful
consideration should be done in case of a time constant circuit.
11 Estimated life
and estimated
failure rate of
capacitors
The estimated life and (failure rate) depend on the temperature and voltage. This can
be calculated by the equation described in JEITA RCR-2335B Annex 6 “Calculation of
the estimated lifetime and the failure rate. “ The risk can be decreased by reducing the
temperature and the voltage but the failure rate can not be guaranteed.
12
Others
The products listed on this specification sheet are intended for use in general
electronic equipment (AV equipment, telecommunications equipment, home
appliances, amusement equipment, computer equipment, personal equipment, office
equipment, measurement equipment, industrial robots) under a normal operation and
use condition.
The products are not designed or warranted to meet the requirements of the
applications listed below, whose performance and/or quality require a more stringent
level of safety or reliability, or whose failure, malfunction or trouble could cause serious
damage to society, person or property. Please understand that TDK is not responsible
for any damage or liability caused by use of this product in any of the applications
below or for any other use exceeding the range or conditions set forth in this
specification sheet:
Aerospace/Aviation equipment. Transportation equipment (cars, electric trains, ships,
etc.) Medical equipment. Power-generation control equipment. Atomic energy-related
equipment. Seabed equipment. Transportation control equipment. Public
information-processing equipment. Military equipment. Electric heating apparatus,
burning equipment. Disaster prevention/crime prevention equipment. Safety
equipment. Other applications that are not considered general-purpose applications.
When using this product in general-purpose applications, you are kindly requested to
take into consideration securing protection circuit/equipment or providing backup
circuits, etc., to ensure higher safety.
19 of 25
11. Packaging label
Packaging shall be done to protect the components from the damage during transportation and
storing, and a label which has the following information shall be attached.
1) Inspection No.
2) TDK P/N
3) Customer's P/N
4) Quantity
*Composition of Inspection No.
Example
M
0
A
–
ΟΟ
–
ΟΟΟ
(a) (b) (c)
(d)
(e)
a) Line code
b) Last digit of the year
c) Month and A for January and B for February and so on. (Skip I)
d) Inspection Date of the month.
e) Serial No. of the day
12. Bulk packaging quantity
Total number of components in a plastic bag for bulk packaging: 1,000pcs.
20 of 25
13. TAPE PACKAGING SPECIFICATION
1. CONSTRUCTION AND DIMENSION OF TAPING
1. Dimensions of carrier tape
Dimensions of plastic tape shall be according to Appendix 3.
2. Trailer and leader of carrier tape
Blank
Chips
Blank
160mm min.
160mm min.
Leader
Drawing direction
400mm min.
3. Dimensions of taping reel
Dimensions of 178mm diameter reel shall be according to Appendix 4.
Dimensions of 330mm diameter reel shall be according to Appendix 5.
4. Structure of taping
Top cover tape
Pitch hole
Cavity (Chip insert)
Plastic carrier tape
2. CHIP QUANTITY
Chip quantity (pcs.)
Taping
Material
Type
Ø178mm reel
Ø330mm reel
CLLC1A
[CC0603]
Plastic
4,000
4,000
10,000
CLLE1A
[CC0805]
Plastic
10,000
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3. PERFORMANCE SPECIFICATIONS
1. Peel back cover (top cover tape)
0.05-0.7N. (See the following figure.)
Direction of pulling
Top cover tape
Carrier tape
0~15°
Direction of pulling
2. Carrier tape shall be flexible enough to be wound around a minimum radius of 30mm with
components in tape.
3. The number of components missing shall be less than 0.1%
4. Components shall not stick to top cover tape.
5. The top cover tape shall not protrude beyond the edges of the carrier tape not shall cover the
sprocket holes.
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Appendix 3
Plastic tape
Cavity (Chip insert)
Pitch hole
J
E
D
A
C
B
t
Q
H
G
F
K
(Unit: mm)
F
Symbol
A
B
C
D
E
Type
CLLC1A
1.1 ± 0.2
1.9 ± 0.2
2.3 ± 0.2
8.0 ± 0.3
3.5 ± 0.05
1.75 ± 0.1
4.0 ± 0.1
CLLE1A
1.5 ± 0.2
G
Symbol
H
J
K
t
Q
Type
CLLC1A
CLLE1A
+ 0.1
2.0 ± 0.05
4.0 ± 0.1
Ø1.5
0
2.5 max.
0.3 max.
Ø0.5 min.
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Appendix 4
Reel material: Polystyrene
W2
E
C
B
D
r
W1
A
(Unit: mm)
W1
Symbol
A
B
C
D
E
Dimension Ø178 ± 2.0
Ø60 ± 2.0
Ø13 ± 0.5
Ø21 ± 0.8
2.0 ± 0.5
9.0 ± 0.3
Symbol
W2
r
Dimension
13.0 ± 1.4
1.0
Appendix 5
Reel material: Polystyrene
E
C
B
D
r
t
W
A
(Unit: mm)
W
Symbol
A
B
C
D
E
Ø382 max.
(Nominal Ø330)
Dimension
Ø50 min.
Ø13 ± 0.5
Ø21 ± 0.8
2.0 ± 0.5
10.0 ± 1.5
Symbol
t
r
Dimension
2.0 ± 0.5
1.0
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END PAGE
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