DK-42351 [TDK]
加速度传感器;
| 型号： | DK-42351 |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | 加速度传感器 传感器 |
| 文件： | 总100页 (文件大小：2073K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IIM-42351 Datasheet
High-performance 3-Axis SmartIndustrial™ Accelerometer
MEMS Device for Industrial Applications
GENERAL DESCRIPTION
APPLICATIONS
•
•
•
•
Industrial tilt sensing
Power tools
Platform stabilization
Robotics
The IIM-42351 is a 3-axis accelerometer packaged in
a small 2.5 mm x 3 mm x 0.91 mm (14-pin LGA)
package.
The IIM-42351 includes multiple capabilities to
enable easy, robust, and accurate inertial and
inclination measurements in Industrial applications:
FEATURES
•
Digital-output X-, Y-, and Z-axis accelerometer
with programmable full-scale range of ±2g, ±4g,
±8g and ±16g
User-programmable interrupts
I3CSM / I2C / SPI slave host interface
Digital-output temperature sensor
External clock input supports highly accurate
clock input from 31 kHz to 50 kHz
Small and thin package:
2.5 mm x 3 mm x 0.91 mm (14-pin LGA)
20,000g shock tolerant
MEMS structure hermetically sealed and bonded
at wafer level
RoHS and Green compliant
•
•
Low noise: 70 µg/√Hz
Low power: 0.3 mA with all 3-axes delivering full
performance
•
•
•
•
•
•
Output data rate up to 8 kHz
Highly accurate external clock input to increase
ODR accuracy, reduce system level sensitivity
error, improve measurement impacts from
device-to-device variation.
•
•
2K-byte FIFO that can lower the traffic on the
serial bus interface, and reduce power
consumption by allowing the system processor
to burst read sensor data and then go into a low-
power mode
•
•
•
•
•
Wake-on-motion interrupt for low power
operation of applications processor
Operating temperature range: -40°C to 105°C
TYPICAL OPERATING CIRCUIT
AP_CS
The host interface can be configured to support
I3CSM slave, I2C slave, or SPI slave modes. The I3CSM
interface supports speeds up to 12.5 MHz (data rates
up to 12.5 Mbps in SDR mode, 25 Mbps in DDR
mode), the I2C interface supports speeds up to 1
MHz, and the SPI interface supports speeds up to
24 MHz.
14
13
12
AP_SDO
RESV
RESV
11
1
2
10 RESV
IIM-42351
INT2 / FSYNC
/ CLKIN
RESV
3
4
9
8
1.71 – 3.6VDC
The device features an operating voltage range from
3.6V down to 1.71V.
INT1 / INT
VDD
5
6
7
C1, 0.1 µF
C2, 2.2 µF
ORDERING INFORMATION
PART NUMBER
TEMPERATURE
PACKAGE
1.71 – 3.6VDC
IIM-42351†
−40°C to +105°C
14-pin LGA
C3, 10 nF
†Denotes RoHS and Green-compliant package
Application Schematic (SPI Interface to Host)
LONGEVITY COMMITMENT
To provide the best service for customers developing products with a long-life cycle we have designed and engineered products with
longevity in mind. These products are designed for harsher environments and are tested and manufactured to higher accuracy and
stability. https://invensense.tdk.com/longevity/
InvenSense, Inc. reserves the right to change
specifications and information herein without
notice unless the product is in mass
InvenSense, a TDK Group Company
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 988–7339
Document Number: DS-000441
Revision: 1.2
Release Date: 03/24/2022
production and the datasheet has been
designated by InvenSense in writing as subject
to a specified Product / Process Change
Notification Method regulation.
invensense.tdk.com
IIM-42351
TABLE OF CONTENTS
General Description............................................................................................................................................ 1
Ordering Information ......................................................................................................................................... 1
Applications........................................................................................................................................................ 1
Features.............................................................................................................................................................. 1
Typical Operating Circuit .................................................................................................................................... 1
Introduction........................................................................................................................................................ 8
1.1 Purpose and Scope .................................................................................................................................. 8
1.2 Product Overview .................................................................................................................................... 8
1.3 Applications ............................................................................................................................................. 8
Features.............................................................................................................................................................. 9
2.1 Accelerometer Features .......................................................................................................................... 9
2.2 Motion Features ...................................................................................................................................... 9
2.3 Additional Features.................................................................................................................................. 9
Electrical Characteristics................................................................................................................................... 10
3.1 Accelerometer Specifications ................................................................................................................10
3.2 Electrical Specifications ......................................................................................................................... 11
3.3 I2C Timing Characterization ...................................................................................................................13
3.4 SPI Timing Characterization – 4-Wire SPI Mode....................................................................................14
3.5 SPI Timing Characterization – 3-Wire SPI Mode....................................................................................15
3.6 RTC (CLKIN) Timing Characterization.....................................................................................................16
3.7 Absolute Maximum Ratings...................................................................................................................17
Applications Information.................................................................................................................................. 18
4.1 Pin Out Diagram and Signal Description................................................................................................18
4.2 Typical Operating Circuit........................................................................................................................ 19
4.3 Bill of Materials for External Components.............................................................................................20
4.4 System Block Diagram ........................................................................................................................... 21
4.5 Overview................................................................................................................................................ 21
4.6 Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning .......................................21
4.7 I3CSM, I2C and SPI Host Interface............................................................................................................21
4.8 Self-Test ................................................................................................................................................. 21
4.9 Clocking.................................................................................................................................................. 22
1
2
3
4
4.10
4.11
4.12
4.13
4.14
Sensor Data Registers........................................................................................................................ 22
Interrupts........................................................................................................................................... 22
Digital-Output Temperature Sensor..................................................................................................22
Bias and LDOs .................................................................................................................................... 22
Charge Pump ..................................................................................................................................... 22
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IIM-42351
4.15
Standard Power Modes.....................................................................................................................23
5
6
Signal Path ........................................................................................................................................................ 24
5.1 Summary of Parameters Used to Configure the Signal Path .................................................................24
5.2 Anti-Alias Filter ...................................................................................................................................... 24
5.3 User Programmable Offset ....................................................................................................................27
5.4 UI Filter Block......................................................................................................................................... 27
5.5 ODR And FSR Selection .......................................................................................................................... 30
FIFO................................................................................................................................................................... 32
6.1 Packet Structure .................................................................................................................................... 32
6.2 FIFO Header ........................................................................................................................................... 34
6.3 Maximum FIFO Storage ......................................................................................................................... 34
6.4 FIFO Configuration Registers .................................................................................................................35
Programmable Interrupts................................................................................................................................. 36
APEX Motion Functions .................................................................................................................................... 37
8.1 APEX ODR Support................................................................................................................................. 37
8.2 DMP Power Save Mode ......................................................................................................................... 38
8.3 Pedometer Programming ...................................................................................................................... 38
8.4 Tilt Detection Programming...................................................................................................................39
8.5 Freefall Detection Programming............................................................................................................40
8.6 Tap Detection Programming..................................................................................................................41
8.7 Wake on Motion Programming .............................................................................................................42
8.8 Significant Motion Detection Programming..........................................................................................42
Digital Interface ................................................................................................................................................ 44
9.1 I3CSM, I2C and SPI Serial Interfaces.........................................................................................................44
9.2 I3CSM Interface ....................................................................................................................................... 44
9.3 I2C Interface ........................................................................................................................................... 44
9.4 I2C Communications Protocol ................................................................................................................44
9.5 I2C Terms................................................................................................................................................ 47
9.6 SPI Interface........................................................................................................................................... 47
Assembly .......................................................................................................................................................... 49
7
8
9
10
10.1
10.2
Orientation of Axes ........................................................................................................................... 49
Package Dimensions.......................................................................................................................... 50
11
12
Part Number Package Marking......................................................................................................................... 52
Use Notes ......................................................................................................................................................... 53
12.1
12.2
12.3
Accelerometer Mode Transitions......................................................................................................53
Accelerometer Low Power (LP) Mode Averaging Filter Setting ........................................................53
Settings for I2C, I3CSM, and SPI Operation..........................................................................................53
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IIM-42351
12.4
12.5
12.6
12.7
12.8
Anti-Alias Filter Operation.................................................................................................................53
external clock input effect on odr .....................................................................................................54
INT_ASYNC_RESET Configuration......................................................................................................54
FIFO Timestamp Interval Scaling .......................................................................................................54
Supplementary Information for FIFO_HOLD_LAST_DATA_EN..........................................................54
13
Register Map .................................................................................................................................................... 56
13.1
13.2
13.3
13.4
13.5
13.6
User Bank 0 Register Map .................................................................................................................56
User Bank 1 Register Map .................................................................................................................57
User Bank 2 Register Map .................................................................................................................57
User Bank 3 Register Map .................................................................................................................57
User Bank 4 Register Map .................................................................................................................58
Register Values Modification.............................................................................................................58
14
User Bank 0 Register Map – Descriptions.........................................................................................................59
14.1
DEVICE_CONFIG ................................................................................................................................ 59
DRIVE_CONFIG .................................................................................................................................. 59
INT_CONFIG....................................................................................................................................... 60
FIFO_CONFIG..................................................................................................................................... 60
TEMP_DATA1 .................................................................................................................................... 60
TEMP_DATA0 .................................................................................................................................... 61
ACCEL_DATA_X1................................................................................................................................ 61
ACCEL_DATA_X0................................................................................................................................ 61
ACCEL_DATA_Y1................................................................................................................................ 61
ACCEL_DATA_Y0................................................................................................................................ 61
ACCEL_DATA_Z1................................................................................................................................ 62
ACCEL_DATA_Z0................................................................................................................................ 62
TMST_FSYNCH................................................................................................................................... 62
TMST_FSYNCL.................................................................................................................................... 62
INT_STATUS....................................................................................................................................... 63
FIFO_COUNTH ................................................................................................................................... 63
FIFO_COUNTL.................................................................................................................................... 63
FIFO_DATA......................................................................................................................................... 63
APEX_DATA0 ..................................................................................................................................... 64
APEX_DATA1 ..................................................................................................................................... 64
APEX_DATA2 ..................................................................................................................................... 64
APEX_DATA3 ..................................................................................................................................... 64
APEX_DATA4 ..................................................................................................................................... 65
APEX_DATA5 ..................................................................................................................................... 65
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.12
14.13
14.14
14.15
14.16
14.17
14.18
14.19
14.20
14.21
14.22
14.23
14.24
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Document Number: DS-000441
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IIM-42351
14.25
14.26
14.27
14.28
14.29
14.30
14.31
14.32
14.33
14.34
14.35
14.36
14.37
14.38
14.39
14.40
14.41
14.42
14.43
14.44
14.45
14.46
14.47
14.48
14.49
14.50
14.51
14.52
INT_STATUS2..................................................................................................................................... 65
INT_STATUS3..................................................................................................................................... 66
SIGNAL_PATH_RESET ........................................................................................................................ 66
INTF_CONFIG0................................................................................................................................... 66
INTF_CONFIG1................................................................................................................................... 68
PWR_MGMT0.................................................................................................................................... 68
ACCEL_CONFIG0................................................................................................................................ 69
TEMP_FILT_CONFIG .......................................................................................................................... 69
ACCEL_FILT_CONFIG.......................................................................................................................... 70
ACCEL_CONFIG1................................................................................................................................ 70
TMST_CONFIG................................................................................................................................... 71
APEX_CONFIG0.................................................................................................................................. 71
SMD_CONFIG .................................................................................................................................... 72
FIFO_CONFIG1................................................................................................................................... 72
FIFO_CONFIG2................................................................................................................................... 72
FIFO_CONFIG3................................................................................................................................... 73
FSYNC_CONFIG.................................................................................................................................. 73
INT_CONFIG0..................................................................................................................................... 74
INT_CONFIG1..................................................................................................................................... 74
INT_SOURCE0.................................................................................................................................... 75
INT_SOURCE1.................................................................................................................................... 75
INT_SOURCE3.................................................................................................................................... 76
INT_SOURCE4.................................................................................................................................... 76
FIFO_LOST_PKT0 ............................................................................................................................... 76
FIFO_LOST_PKT1 ............................................................................................................................... 77
SELF_TEST_CONFIG ........................................................................................................................... 77
WHO_AM_I ....................................................................................................................................... 77
REG_BANK_SEL.................................................................................................................................. 78
15
User Bank 1 Register Map – Descriptions.........................................................................................................79
15.1
15.2
15.3
15.4
15.5
15.6
15.7
SENSOR_CONFIG0 ............................................................................................................................. 79
TMSTVAL0 ......................................................................................................................................... 79
TMSTVAL1 ......................................................................................................................................... 79
TMSTVAL2 ......................................................................................................................................... 79
INTF_CONFIG4................................................................................................................................... 80
INTF_CONFIG5................................................................................................................................... 80
INTF_CONFIG6................................................................................................................................... 80
16
User Bank 2 Register Map – Descriptions.........................................................................................................81
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IIM-42351
16.1
16.2
16.3
16.4
16.5
16.6
ACCEL_CONFIG_STATIC2...................................................................................................................81
ACCEL_CONFIG_STATIC3...................................................................................................................81
ACCEL_CONFIG_STATIC4...................................................................................................................81
XA_ST_DATA...................................................................................................................................... 81
YA_ST_DATA...................................................................................................................................... 82
ZA_ST_DATA...................................................................................................................................... 82
17
18
User Bank 3 Register Map – Descriptions.........................................................................................................83
17.1
17.2
PU_PD_CONFIG1 ............................................................................................................................... 83
PU_PD_CONFIG2 ............................................................................................................................... 84
User Bank 4 Register Map – Descriptions.........................................................................................................85
18.1
FDR_CONFIG...................................................................................................................................... 85
APEX_CONFIG1.................................................................................................................................. 85
APEX_CONFIG2.................................................................................................................................. 86
APEX_CONFIG3.................................................................................................................................. 87
APEX_CONFIG4.................................................................................................................................. 88
APEX_CONFIG5.................................................................................................................................. 89
APEX_CONFIG6.................................................................................................................................. 90
APEX_CONFIG7.................................................................................................................................. 91
APEX_CONFIG8.................................................................................................................................. 91
APEX_CONFIG9.................................................................................................................................. 91
APEX_CONFIG10................................................................................................................................ 92
ACCEL_WOM_X_THR......................................................................................................................... 92
ACCEL_WOM_Y_THR......................................................................................................................... 93
ACCEL_WOM_Z_THR......................................................................................................................... 93
INT_SOURCE6 .................................................................................................................................... 93
INT_SOURCE7.................................................................................................................................... 94
INT_SOURCE8.................................................................................................................................... 94
INT_SOURCE9.................................................................................................................................... 95
INT_SOURCE10.................................................................................................................................. 95
OFFSET_USER4 .................................................................................................................................. 95
OFFSET_USER5 .................................................................................................................................. 96
OFFSET_USER6 .................................................................................................................................. 96
OFFSET_USER7 .................................................................................................................................. 96
OFFSET_USER8 .................................................................................................................................. 96
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10
18.11
18.12
18.13
18.14
18.15
18.16
18.17
18.18
18.19
18.20
18.21
18.22
18.23
18.24
19
20
21
SmartIndustrial Family...................................................................................................................................... 97
Reference ......................................................................................................................................................... 98
Revision History................................................................................................................................................ 99
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Revision: 1.2
IIM-42351
Table of Figures
Figure 1. I2C Bus Timing Diagram.................................................................................................................................13
Figure 2. 4-Wire SPI Bus Timing Diagram ....................................................................................................................14
Figure 3. 3-Wire SPI Bus Timing Diagram ....................................................................................................................15
Figure 4. RTC Timing Diagram......................................................................................................................................16
Figure 5. Pin Out Diagram for IIM-42351 2.5 mm x 3.0 x 0.91 mm LGA......................................................................19
Figure 6. IIM-42351 Application Schematic (I3CSM / I2C Interface to Host) .................................................................19
Figure 7. IIM-42351 Application Schematic (SPI Interface to Host).............................................................................20
Figure 8. IIM-42351 System Block Diagram.................................................................................................................21
Figure 9. IIM-42351 Signal Path...................................................................................................................................24
Figure 10. FIFO Packet Structure .................................................................................................................................32
Figure 11. Maximum FIFO Storage ..............................................................................................................................35
Figure 12. START and STOP Conditions .......................................................................................................................45
Figure 14. Complete I2C Data Transfer ........................................................................................................................45
Figure 15. Typical SPI Master/Slave Configuration......................................................................................................48
Figure 16. Orientation of Axes of Sensitivity and Polarity of Rotation........................................................................49
Table of Tables
Table 1. Accelerometer Specifications ........................................................................................................................10
Table 2. D.C. Electrical Characteristics.........................................................................................................................11
Table 3. A.C. Electrical Characteristics.........................................................................................................................12
Table 4. I2C Timing Characteristics...............................................................................................................................13
Table 5. 4-Wire SPI Timing Characteristics (24-MHz Operation).................................................................................14
Table 6. 3-Wire SPI Timing Characteristics (24-MHz Operation).................................................................................15
Table 7. RTC Timing Characteristics.............................................................................................................................16
Table 8. Absolute Maximum Ratings ...........................................................................................................................17
Table 9. Signal Descriptions.........................................................................................................................................18
Table 10. Bill of Materials ............................................................................................................................................20
Table 11. Standard Power Modes for IIM-42351 ........................................................................................................23
Table 12. Parameters used to control the signal path.................................................................................................24
Table 13. I2C Terms......................................................................................................................................................47
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Document Number: DS-000441
Revision: 1.2
IIM-42351
1 INTRODUCTION
1.1 PURPOSE AND SCOPE
This document is a product specification, providing a description, specifications, and design related information on
the IIM-42351, a 3-axis accelerometer device targeted at Industrial applications. The device is housed in a small
2.5x3x0.91 mm 14-pin LGA package.
1.2 PRODUCT OVERVIEW
The IIM-42351 is a 3-axis accelerometer in a small 2.5x3x0.91 mm (14-pin LGA) package. It also features a 2K-byte
FIFO that can lower the traffic on the serial bus interface and reduce power consumption by allowing the system
processor to burst read sensor data and then go into a low-power mode. IM-42351, with its 3-axis integration,
enables manufacturers to eliminate the costly and complex selection, qualification, and system level integration of
discrete devices, guaranteeing optimal motion performance for consumers.
The accelerometer supports four programmable full-scale range settings from ±2g to ±16g. It includes multiple
capabilities to enable tri-axial inclination measurements in Industrial applications:
•
•
Low noise: 70 µg/√Hz
Low power: 0.3 mA with all 3-axes delivering full performance
IIM-42351 also supports external clock input for highly accurate 31 kHz to 50k Hz clock, that helps to reduce
system level sensitivity error, reduce ODR sensitivity to temperature and device to device variation.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts. The device features I3CSM, I2C, and SPI serial interfaces, a VDD
operating range of 1.71V to 3.6V, and a separate VDDIO operating range of 1.71V to 3.6V.
The host interface can be configured to support I3CSM slave, I2C slave, or SPI slave modes. The I3CSM interface
supports speeds up to 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), the I2C
interface supports speeds up to 1 MHz, and the SPI interface supports speeds up to 24 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers
with companion CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a
footprint and thickness of 2.5 mm x 3 mm x 0.91 ;mm (14-pin LGA), to provide a very small yet high performance
low cost package. The device provides high robustness by supporting 20,000g shock reliability.
1.3 APPLICATIONS
•
•
•
Tilt sensing
Platform stabilization
Robotics
Page 8 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
2 FEATURES
2.1 ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in IIM-42351 includes a wide range of features:
•
Digital-output X-, Y-, and Z-axis accelerometer with programmable full-scale range of ±2g, ±4g, ±8g and
±16g
•
•
•
•
Low Noise (LN) and Low Power (LP) power modes support
User-programmable interrupts
Wake-on-motion interrupt for low power operation of applications processor
Self-test
2.2 MOTION FEATURES
IIM-42351 includes the following motion features, also known as APEX (Advanced Pedometer and Event Detection
– neXt gen)
•
•
•
•
•
•
Pedometer: tracks step count, also issues step detect interrupt
Tilt Detection: issues an interrupt when the tilt angle exceeds 35° for more than a programmable time
Freefall Detection: triggers an interrupt when device freefall is detected and outputs freefall duration
Tap Detection: issues an interrupt when a tap is detected, along with the tap count
Wake on Motion: detects motion when accelerometer data exceeds a programmable threshold.
Significant Motion Detection: detects significant motion if Wake on Motion events are detected during a
programmable time window
2.3 ADDITIONAL FEATURES
IIM-42351 includes the following additional features:
•
External clock input supports highly accurate clock input from 31 kHz to 50 kHz, helps to reduce system
level sensitivity error
•
•
•
2K byte FIFO buffer enables the applications processor to read the data in bursts
User-programmable digital filters for accelerometer, and temperature sensor
User configurable internal pull-up/pull-downs included on I/O interfaces to reduce system costs
associated with external pull-ups/pull-downs
•
12.5 MHz I3CSM (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode) / 1 MHz I2C / 24 MHz SPI
slave host interface
•
•
•
•
•
Digital-output temperature sensor
Smallest and thinnest LGA package for portable devices: 2.5 mm x 3 mm x 0.91 mm (14-pin LGA)
20,000g shock tolerant
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
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Document Number: DS-000441
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IIM-42351
3 ELECTRICAL CHARACTERISTICS
3.1 ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of Section 3.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ACCELEROMETER SENSITIVITY
ACCEL_FS_SEL =0
ACCEL_FS_SEL =1
ACCEL_FS_SEL =2
ACCEL_FS_SEL =3
±16
±8
g
g
2
2
Full-Scale Range
2
±4
g
2
±2
g
2, 5
2
ADC Word Length
Output in two’s complement format
ACCEL_FS_SEL =0
16
bits
LSB/g
LSB/g
LSB/g
LSB/g
%
2,048
4,096
8,192
16,384
±0.5
±0.005
±0.1
±1
2
ACCEL_FS_SEL =1
Sensitivity Scale Factor
2
ACCEL_FS_SEL =2
2
ACCEL_FS_SEL =3
Component-level
Sensitivity Scale Factor Initial Tolerance
Sensitivity Change vs. Temperature
Nonlinearity
1
3
3
3
-40°C to +105°C
%/ºC
%
Best Fit Straight Line, ±2g
Cross-Axis Sensitivity
%
ZERO-G OUTPUT
Initial Tolerance
Board-level, all axes
-40°C to +105°C
±20
mg
3
3
Zero-G Level Change vs. Temperature
±0.15
mg/ºC
OTHER PARAMETERS
Noise Power Spectral Density
Total RMS
@ 10Hz
70
µg/√Hz
°/s-rms
Hz
1
4
2
Bandwidth = 100 Hz
ODR < 1kHz
ODR ≥ 1kHz
0.70
5
500
Low-Pass Filter Response
42
3979
Hz
ms
Hz
2
3
2
Accelerometer Startup Time
Output Data Rate
From sleep mode to valid data
10
1.5625
8000
Table 1. Accelerometer Specifications
Notes:
1. Tested in production.
2. Guaranteed by design.
3. Derived from validation or characterization of parts, not tested in production.
4. Calculated from Power Spectral Density.
5. 20-bits data format supported in FIFO, see section 6.1.
Page 10 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
3.2 ELECTRICAL SPECIFICATIONS
D.C. Electrical Characteristics
Typical Operating Circuit of Section 3.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
SUPPLY VOLTAGES
MIN
TYP
MAX
UNITS
NOTES
VDD
1.71
1.71
1.8
1.8
3.6
3.6
V
V
1
1
VDDIO
SUPPLY CURRENTS
3-Axis Accelerometer
At 25°C
0.28
7.5
mA
µA
2
2
Low-Noise Mode
Full-Chip Sleep Mode
TEMPERATURE RANGE
Specified Temperature Range
Performance parameters are not applicable
beyond Specified Temperature Range
-40
+105
°C
2
Table 2. D.C. Electrical Characteristics
Notes:
1. Guaranteed by design.
2. Derived from validation or characterization of parts, not tested in production.
Page 11 of 100
Document Number: DS-000441
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IIM-42351
A.C. Electrical Characteristics
Typical Operating Circuit of Section 3.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLIES
Monotonic ramp. Ramp rate is 10% to 90% of
the final value
Supply Ramp Time
0.01
3
ms
1
1
mV
peak-peak
Power Supply Noise
Up to 10 kHz
10
TEMPERATURE SENSOR
Operating Range
25°C Output
ADC Resolution
ODR
Room Temperature Offset
Stabilization Time
Sensitivity
Ambient
-40
105
°C
LSB
bits
Hz
°C
µs
2
3
2
2
3
2
1
1
0
16
With Filter
25°C
25
-5
8000
5
14000
Untrimmed
132.48
2.07
LSB/°C
LSB/°C
Sensitivity for FIFO data
POWER-ON RESET
I2C ADDRESS
1
ms
Start-up time for register read/write
From power-up
1
1
1
AP_AD0 = 0
AP_AD0 = 1
1101000
1101001
I2C ADDRESS
DIGITAL INPUTS (FSYNC, SCLK, SDI, CS)
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
0.7*VDDIO
V
V
0.3*VDDIO
< 10
100
pF
nA
Input Leakage Current
DIGITAL OUTPUT (SDO, INT1, INT2)
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT, INT Low-Level Output Voltage
RLOAD=1 MΩ;
RLOAD=1 MΩ;
0.9*VDDIO
V
V
V
0.1*VDDIO
0.1
OPEN=1, 0.3 mA sink
Current
Output Leakage Current
tINT, INT Pulse Width
OPEN=1
100
nA
µs
int_tpulse_duration= 0, 1 (100us, 8us ) ;
I2C I/O (SCL, SDA)
8
100
VIL, LOW-Level Input Voltage
-0.5 V
0.3*VDDIO
V
V
VIH, HIGH-Level Input Voltage
0.7*VDDIO
VDDIO +
0.5 V
Vhys, Hysteresis
0.1*VDDIO
V
V
VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current
3 mA sink current
0
0.4
1
VOL=0.4 V
VOL=0.6 V
3
6
mA
mA
Output Leakage Current
100
nA
ns
tof, Output Fall Time from VIHmax to VILmax
Cb bus capacitance in pf
20+0.1Cb
300
INTERNAL CLOCK SOURCE
Clock Frequency Initial Tolerance
CLKSEL=`2b00; 25°C
-3
+3
±3
%
%
1
1
Frequency Variation over Temperature
CLKSEL=`2b00; -40°C to +85°C
Table 3. A.C. Electrical Characteristics
Notes:
1. Expected results based on design, will be updated after characterization. Not tested in production.
2. Guaranteed by design.
3. Production tested.
Page 12 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
3.3 I2C TIMING CHARACTERIZATION
Typical Operating Circuit of Section 3.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERS
CONDITIONS
I2C FAST-MODE PLUS
MIN
TYPICAL
MAX
UNITS
NOTES
I2C TIMING
fSCL, SCL Clock Frequency
1
MHz
1
1
tHD.STA, (Repeated) START Condition Hold Time
0.26
0.5
0.26
0.26
0
µs
tLOW, SCL Low Period
µs
µs
µs
µs
ns
ns
ns
µs
1
1
1
1
1
1
1
1
tHIGH, SCL High Period
tSU.STA, Repeated START Condition Setup Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
50
120
120
Cb bus cap. from 10 to 400 pF
Cb bus cap. from 10 to 400 pF
tf, SDA and SCL Fall Time
0.5
0.5
tSU.STO, STOP Condition Setup Time
tBUF, Bus Free Time Between STOP and START
Condition
µs
1
Cb, Capacitive Load for each Bus Line
tVD.DAT, Data Valid Time
< 400
pF
µs
µs
1
1
1
0.45
0.45
tVD.ACK, Data Valid Acknowledge Time
Table 4. I2C Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
tf
tSU.DAT
t
r
SDA
SCL
70%
30%
70%
30%
continued below at
9th clock cycle
A
tf
t
r
t
VD.DAT
70%
30%
70%
30%
tHD.DAT
t
HD.STA
1/fSCL
t
LOW
1st clock cycle
S
t
HIGH
tBUF
SDA
SCL
70%
30%
A
t
SU.STO
tSU.STA
tHD.STA
t
VD.ACK
70%
30%
9th clock cycle
S
P
Sr
Figure 1. I2C Bus Timing Diagram
Page 13 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
3.4 SPI TIMING CHARACTERIZATION – 4-WIRE SPI MODE
Typical Operating Circuit of Section 3.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
NOTES
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING
fSPC, SCLK Clock Frequency
tLOW, SCLK Low Period
tHIGH, SCLK High Period
tSU.CS, CS Setup Time
Default
24
MHz
ns
1
1
1
1
1
1
1
1
1
1
17
17
39
18
13
8
ns
ns
tHD.CS, CS Hold Time
ns
tSU.SDI, SDI Setup Time
tHD.SDI, SDI Hold Time
ns
ns
tVD.SDO, SDO Valid Time
tHD.SDO, SDO Hold Time
tDIS.SDO, SDO Output Disable Time
Cload = 20 pF
Cload = 20 pF
21.5
28
ns
3.5
ns
ns
Table 5. 4-Wire SPI Timing Characteristics (24-MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
CS
70%
30%
tFall
tRise
t
HD;CS
t
SU;CS
70%
t
HIGH
1/fCLK
SCLK
30%
tSU;SDI
tHD;SDI
tLOW
70%
30%
SDI
LSB IN
MSB IN
tDIS;SDO
t
VD;SDO
t
HD;SDO
70%
30%
SDO
MSB OUT
LSB OUT
Figure 2. 4-Wire SPI Bus Timing Diagram
Page 14 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
3.5 SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE
Typical Operating Circuit of Section 3.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
NOTES
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING
fSPC, SCLK Clock Frequency
tLOW, SCLK Low Period
Default
24
MHz
ns
1
1
1
1
1
1
1
1
1
1
17
17
39
5
tHIGH, SCLK High Period
ns
tSU.CS, CS Setup Time
ns
tHD.CS, CS Hold Time
ns
tSU.SDIO, SDIO Input Setup Time
tHD.SDIO, SDIO Input Hold Time
tVD.SDIO, SDIO Output Valid Time
tHD.SDIO, SDIO Output Hold Time
tDIS.SDIO, SDIO Output Disable Time
13
8
ns
ns
Cload = 20 pF
Cload = 20 pF
18.5
28
ns
3.5
ns
ns
Table 6. 3-Wire SPI Timing Characteristics (24-MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
CS
70%
30%
tFall
tRise
t
HD;CS
t
SU;CS
70%
t
HIGH
1/fCLK
SCLK
30%
tSU;SDIO
tHD;SDIO
t
LOW
70%
30%
I
LSB IN
MSB IN
tDIS;SDIO
t
VD;SDIO
t
HD;SDIO
70%
30%
O
MSB OUT
LSB OUT
Figure 3. 3-Wire SPI Bus Timing Diagram
Page 15 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
3.6 RTC (CLKIN) TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
NOTES
PARAMETERS
RTC (CLKIN) TIMING
CONDITIONS
MIN
TYP
MAX
UNITS
FRTC, RTC Clock Frequency
tHIGHRTC, RTC Clock High Period
tRISERTC, RTC Clock Rise Time
tFALLRTC, RTC Clock Fall Time
Default
31
1
32
50
kHz
µs
1
1
1
1
5
500
500
ns
5
ns
Table 7. RTC Timing Characteristics
Notes:
1. Based on characterization. Not tested in production.
Figure 4. RTC Timing Diagram
Page 16 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
3.7 ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the
absolute maximum ratings conditions for extended periods may affect device reliability. Prolonged exposure to
acceleration ranges beyond ±60g may affect device reliability.
PARAMETER
RATING
-0.5V to 4V
Supply Voltage, VDD
Supply Voltage, VDDIO
-0.5V to 4V
Input Voltage Level (FSYNC, SCL, SDA)
Acceleration (Any Axis, unpowered)
Operating Temperature Range
Storage Temperature Range
-0.5V to VDDIO + 0.5V
20,000g for 0.2 ms
-40°C to 105°C
-40°C to 125°C
2 kV (HBM);
500V (CDM)
JEDEC Class II (2), 125°C
±100 mA
Electrostatic Discharge (ESD) Protection
Latch-up
Table 8. Absolute Maximum Ratings
Page 17 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
PIN NUMBER
PIN NAME
PIN DESCRIPTION
PIN STATUS
By default, pull-up/pull-down is disabled. Pull-up can
be enabled by setting PIN1_PU_EN = 1 (register 0x0Eh
in Bank 3). Pull-down can be enabled by setting
PIN1_PD_EN = 1 (register 0x0Eh in Bank 3). Note that
both pull-up and pull-down must not be simultaneously
enabled for the same pin.
AP_SDO: AP SPI serial data output (4-wire mode);
AP_AD0: AP I3CSM / I2C slave address LSB
1
AP_SDO / AP_AD0
By default, pull-up is disabled. Pull-up can be enabled
by setting PIN2_PU_EN = 1 (register 0x06h in Bank 3).
2
3
RESV
RESV
No Connect or Connect to GND
No Connect or Connect to GND
By default, pull-up is disabled. Pull-up can be enabled
by setting PIN3_PU_EN = 1 (register 0x06h in Bank 3).
INT1: Interrupt 1 (Note: INT1 can be push-pull or open
drain)
INT: All interrupts mapped to pin 4
By default, pull-down is disabled. Pull-down can be
enabled by setting PIN4_PD_EN = 1 (register 0x06h in
Bank 3).
4
INT1 / INT
5
6
VDDIO
GND
IO power supply voltage
Power supply ground
By default, pull-up is disabled. Pull-up can be enabled
by setting PIN7_PU_EN = 1 (register 0x06h in Bank 3)
and it can be disabled by setting PIN7_PU_EN = 0.
7
8
RESV
VDD
Connect to GND
Power supply voltage
INT2: Interrupt 2 (Note: INT2 can be push-pull or open
By default, pull-down is disabled.
drain)
Pull-down can be enabled by setting PIN9_PD_EN = 1
(register 0x06h in Bank 3).
9
INT2 / FSYNC / CLKIN
FSYNC: Frame sync input; Connect to GND if FSYNC not
used
CLKIN: External Clock Input
By default, pull-up is enabled.
Pull-up can be disabled by setting PIN10_PU_EN = 0
and it can be enabled by setting PIN10_PU_EN = 1
(register 0x06h in Bank 3).
10
11
RESV
RESV
No Connect or Connect to GND
No Connect or Connect to GND
By default, pull-up is enabled.
Pull-up can be disabled by setting PIN11_PU_EN = 0
and it can be enabled by setting PIN11_PU_EN = 1
(register 0x06h in Bank 3).
By default, pull-up is enabled. Pull-up can be disabled
by setting PIN12_PU_EN = 0 (register 0x0Eh in Bank 3).
Pull-down can be enabled by setting PIN12_PD_EN = 1
(register 0x0Eh in Bank 3). Note that both pull-up and
pull-down must not be simultaneously enabled for the
same pin.
AP SPI Chip select (AP SPI interface); Connect to VDDIO if
using AP I3CSM / I2C interface
12
13
14
AP_CS
By default, pull-up/pull-down is disabled. Pull-up can
be enabled by setting PIN13_PU_EN = 1 (register 0x0Eh
in Bank 3). Pull-down can be enabled by setting
PIN13_PD_EN = 1 (register 0x0Eh in Bank 3). Note that
both pull-up and pull-down must not be simultaneously
enabled for the same pin.
AP_SCL: AP I3CSM / I2C serial clock; AP_SCLK: AP SPI serial
clock
AP_SCL / AP_SCLK
By default, pull-up/pull-down is disabled. Pull-up can
be enabled by setting PIN14_PU_EN = 1 (register 0x0Eh
in Bank 3). Pull-down can be enabled by setting
PIN14_PD_EN = 1 (register 0x0Eh in Bank 3). Note that
both pull-up and pull-down must not be simultaneously
enabled for the same pin.
AP_SDA: AP I3CSM / I2C serial data; AP_SDIO: AP SPI serial
data I/O (3-wire mode); AP_SDI: AP SPI serial data input (4-
wire mode)
AP_SDA / AP_SDIO /
AP_SDI
Table 9. Signal Descriptions
Page 18 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
+Z
IIM-42351
/
+Y
+X
Figure 5. Pin Out Diagram for IIM-42351 2.5 mm x 3.0 x 0.91 mm LGA
4.2 TYPICAL OPERATING CIRCUIT
VDDIO
12
14
13
AP_AD0
RESV
RESV
11
1
2
10 RESV
IIM-4
2
351
INT2 / FSYNC
RESV
3
4
9
8
/ CLKIN
1.71 – 3.6VDC
INT1 / INT
VDD
5
6
7
C1, 0.1 µF
C2, 2.2 µF
1.71 – 3.6VDC
C3, 10 nF
Figure 6. IIM-42351 Application Schematic (I3CSM / I2C Interface to Host)
Note: I2C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required.
Page 19 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
AP_CS
14
13
12
AP_SDO
RESV
RESV
11
1
2
10 RESV
IIM-42351
/ CLKIN
INT2 / FSYNC
RESV
3
4
9
8
1.71 – 3.6VDC
INT1 / INT
VDD
5
6
7
C1, 0.1 µF
C2, 2.2 µF
1.71 – 3.6VDC
C3, 10 nF
Figure 7. IIM-42351 Application Schematic (SPI Interface to Host)
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS
COMPONENT
VDD Bypass Capacitors
LABEL
SPECIFICATION
X7R, 0.1µF ±10%
X7R, 2.2µF ±10%
QUANTITY
C1
C2
1
1
VDDIO Bypass Capacitor
C3
X7R, 10nF ±10%
1
Table 10. Bill of Materials
Page 20 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
4.4 SYSTEM BLOCK DIAGRAM
IIM-42351
Figure 8. IIM-42351 System Block Diagram
Note: The above block diagram is an example. Please refer to the pin-out (section 3.1) for other configuration options.
4.5 OVERVIEW
The IIM-42351 is comprised of the following key blocks and functions:
•
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
o
20-bits data format support in FIFO for high-data resolution (see section 6 for details)
•
•
•
•
•
•
•
•
•
•
I3CSM, I2C and SPI serial communications interfaces to Host
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes
4.6 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The IIM-42351 includes a 3-Axis MEMS accelerometer. Acceleration along a particular axis induces displacement of
a proof mass in the MEMS structure, and capacitive sensors detect the displacement. The IIM-42351 architecture
reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is
placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale
factor is calibrated at the factory and is nominally independent of supply voltage. The full-scale range of the digital
output can be adjusted to ±2g, ±4g, ±8g and ±16g.
4.7 I3CSM, I2C AND SPI HOST INTERFACE
The IIM-42351 communicates to the application processor using an I3CSM, I2C, or SPI serial interface. The IIM-42351
always acts as a slave when communicating to the application processor.
4.8 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each
measurement axis can be activated by means of the accelerometer self-test registers.
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The
output signal is used to observe the self-test response.
The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED
When the value of the self-test response is within the specified min/max limits of the product specification, the
part has passed self-test. When the self-test response exceeds the min/max values, the part is deemed to have
failed self-test.
Page 21 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
4.9 CLOCKING
The IIM-42351 has a flexible clocking scheme, allowing the internal clock source to be used for the internal
synchronous circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various control
circuits and registers.
The internal clock for IIM-42351 is generated by a relaxation oscillator. A highly accurate external clock may be
used rather than the internal clock sources, if greater clock accuracy is desired. The CLKIN pin on IIM-42351
provides the ability to input an external clock. External clock input supports highly accurate clock input from 31 kHz
to 50k Hz, resulting in improvement of the following:
a) ODR uncertainty due to process, temperature, and design limitations. This uncertainty can be as high as
±8% in internal clock mode. The CLKIN, assuming a 50 ppm or better 32.768 kHz source, will improve the
ODR accuracy from ±80,000 ppm to ±50 ppm in RCOSC mode.
b) Sophisticated systems can estimate ODR inaccuracy to some extent, but not to the extent improved by
using CLKIN.
c) System-level clock/sensor synchronization. When using CLKIN, the accelerometer is on the same clock as
the host. There is no need to continually re-synchronize the sensor data as the sensor sample points and
period are known to be in exact alignment with the common system clock.
d) Other applications that benefit from CLKIN include navigation, robotics.
4.10 SENSOR DATA REGISTERS
The sensor data registers contain the latest accelerometer, and temperature measurement data. They are read-
only registers and are accessed via the serial interface. Data from these registers may be read anytime.
4.11 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the
interrupt pins configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that
can trigger an interrupt are (1) new data is available to be read (from the FIFO and Data registers); (2)
accelerometer event interrupts; (3) FIFO watermark; (4) FIFO overflow. The interrupt status can be read from the
Interrupt Status register.
4.12 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the IIM-42351 die temperature. The readings from
the ADC can be read from the FIFO or the Sensor Data registers.
Temperature data value from the sensor data registers can be converted to degrees centigrade by using the
following formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25
FIFO_TEMP_DATA, temperature data stored in FIFO, can be 8-bit or 16-it quantity. The 8-bit of temperature data
stored in FIFO is limited to -40°C to 85°C range, while the 16-bit representation can support the full operating
temperature range. It can be converted to degrees centigrade by using the following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25
4.13 BIAS AND LDOS
The bias and LDO section generate the internal supply and the reference voltages and currents required by the
IIM-42351.
4.14 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
Page 22 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
4.15 STANDARD POWER MODES
The following table lists the user-accessible power modes for IIM-42351.
MODE
NAME
ACCEL
Off
Off
1
2
3
4
Sleep Mode
Standby Mode
Accelerometer Low-Power Mode
Accelerometer Low-Noise Mode
Duty-Cycled
On
Table 11. Standard Power Modes for IIM-42351
Page 23 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
5 SIGNAL PATH
The following figure shows a block diagram of the signal path for IIM-42351.
Decimation
Filter
ADC
(32kHz)
UI Interface
Anti-Alias
Filter (AAF)
Filter (AAF)
User
User
Anti-Alias
UI Filter Block
(order, BW, ODR)
Sensor
Registers
0
1
Programmable
Programmable
Offset
Offset
FSR Selection
AAF_DIS
Figure 9. IIM-42351 Signal Path
The signal path starts with ADCs for the accelerometer. Other components of the signal path are described below
in further detail.
5.1 SUMMARY OF PARAMETERS USED TO CONFIGURE THE SIGNAL PATH
The following table shows the parameters that can control the signal path.
PARAMETER NAME
ACCEL_AAF_DIS
DESCRIPTION
Disables the Accelerometer Anti Alias Filter
Three parameters required to program the accelerometer AAF. This is a 2nd order filter
with programmable low pass filter. This is a user programmable filter which can be used
to select the desired BW. This filter allows trading off RMS noise vs. latency for a given
ODR.
ACCEL_AAF_DELT
ACCEL_AAF_DELTSQR
ACCEL_AAF_BITSHIFT
Table 12. Parameters used to control the signal path
5.2 ANTI-ALIAS FILTER
To program the anti-alias filter for a required bandwidth, use the table below to map the bandwidth to register
values as shown:
1. Register bank 2, register 0x03h, bits 6:1, ACCEL_AAF_DELT: Code from 1 to 63 that allows
programming the bandwidth for accelerometer anti-alias filter
2. Register bank 2, register 0x04h, bits 7:0 and Bank 2, register 0x05h, bits 3:0,
ACCEL_AAF_DELTSQR: Square of the delt value for accelerometer
3. Register bank 2, register 0x05h, bits 7:4, ACCEL_AAF_BITSHIFT: Bitshift value for accelerometer
used in hardware implementation
Page 24 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
3DB BANDWIDTH (HZ)
42
ACCEL_AAF_DELT
ACCEL_AAF_DELTSQR
ACCEL_AAF_BITSHIFT
1
1
15
13
12
11
10
10
9
84
2
4
126
3
9
170
4
16
213
5
25
258
6
36
303
7
49
348
8
64
9
394
9
81
9
441
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
100
122
144
170
196
224
256
288
324
360
400
440
488
528
576
624
680
736
784
848
896
960
1024
1088
1152
1232
1296
1376
1440
1536
1600
8
488
8
536
8
585
8
634
7
684
7
734
7
785
7
837
7
890
6
943
6
997
6
1051
1107
1163
1220
1277
1336
1395
1454
1515
1577
1639
1702
1766
1830
1896
1962
2029
2097
2166
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
4
4
4
4
Page 25 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
3DB BANDWIDTH (HZ)
2235
ACCEL_AAF_DELT
ACCEL_AAF_DELTSQR
1696
ACCEL_AAF_BITSHIFT
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
2306
1760
2377
1856
2449
1952
2522
2016
2596
2112
2671
2208
2746
2304
2823
2400
2900
2496
2978
2592
3057
2720
3137
2816
3217
2944
3299
3008
3381
3136
3464
3264
3548
3392
3633
3456
3718
3584
3805
3712
3892
3840
3979
3968
The anti-alias filter can be selected or bypassed for the accelerometer by using the parameter ACCEL_AAF_DIS in
register bank 2, register 0x03h, bit 0 as shown below.
ACCEL_AAF_DIS
FUNCTION
0
1
Enable accelerometer anti-aliasing filter
Disable accelerometer anti-aliasing filter
Page 26 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
5.3 USER PROGRAMMABLE OFFSET
Accelerometer offsets can be programmed by the user by using registers OFFSET_USER4, through OFFSET_USER8,
in bank 0, registers 0x7Bh through 0x7Fh (bank 4) as shown below.
REGISTER ADDRESS
REGISTER NAME
BITS
3:0
FUNCTION
Reserved
0x7Bh
OFFSET_USER4
Upper bits of X-accel offset programmed by user. Max
value is ±1g, resolution is 0.5 mg.
7:4
Lower bits of X-accel offset programmed by user. Max
value is ±1g, resolution is 0.5 mg.
Lower bits of Y-accel offset programmed by user. Max
value is ±1g, resolution is 0.5 mg.
Upper bits of Y-accel offset programmed by user. Max
value is ±1g, resolution is 0.5 mg.
Upper bits of Z-accel offset programmed by user. Max
value is ±1g, resolution is 0.5 mg.
0x7Ch
0x7Dh
OFFSET_USER5
OFFSET_USER6
7:0
7:0
3:0
7:4
7:0
0x7Eh
OFFSET_USER7
OFFSET_USER8
Lower bits of Z-accel offset programmed by user. Max
value is ±1g, resolution is 0.5 mg.
0x7Fh
5.4 UI FILTER BLOCK
The UI filter block can be programmed to select filter order and bandwidth for accelerometer.
Accelerometer filter order can be selected by programming the parameter ACCEL_UI_FILT_ORD in register bank 0,
register 0x53h, bits 4:3, as shown below.
ACCEL_UI_FILT_ORD
FILTER ORDER
00
01
10
11
1st order
2nd order
3rd order
Reserved
Accelerometer filter 3dB bandwidth can be selected by programming the parameter ACCEL_UI_FILT_BW in register
bank 0, register 0x52h, bits 7:4, as shown below. The values shown in bold correspond to low noise and the values
shown in italics correspond to low latency. User can select the appropriate setting based on the application
requirements for power and latency. Corresponding Noise Bandwidth (NBW) and Group Delay values are also
shown.
1st Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3DB BANDWIDTH (HZ) FOR ACCEL_UI_FILT_ORD=0 (1ST ORDER FILTER)
ACCEL_UI_FILT_BW
ACCEL_ODR
ODR(HZ)
8000
4000
2000
1000
500
0
1
2
3
4
5
6
7
14
15
3
4
2096.30
1048.10
524.00
5
6
498.30 227.20 188.90 111.00 92.40 59.60 48.80 23.90 262.00 2096.30
15
7
249.10 113.60
94.40
75.50
75.50
75.50
55.50 46.20 29.80 24.40 11.90 131.00 1048.10
200
99.60
49.80
24.90
90.90
90.90
90.90
44.40 37.00 23.80 19.50
44.40 37.00 23.80 19.50
44.40 37.00 23.80 19.50
9.60 104.80
9.60 104.80
9.60 104.80
419.20
209.60
104.80
8
100
9
50
Page 27 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
10
11
25
12.50
90.90
90.90
75.50
75.50
44.40 37.00 23.80 19.50
44.40 37.00 23.80 19.50
9.60 104.80
9.60 104.80
52.40
52.40
12.5
12.50
NBW BANDWIDTH (HZ) FOR ACCEL_UI_FILT_ORD=0 (1ST ORDER FILTER)
ACCEL_UI_FILT_BW
ACCEL_ODR
ODR(HZ)
8000
4000
2000
1000
500
0
1
2
3
4
5
6
7
14
15
3
4
2204.6
1102.2
551.1
5
6
551.1
280.5
112.2
56.1
230.8
115.4
92.4
92.4
92.4
92.4
92.4
196.3
98.2
78.5
78.5
78.5
78.5
78.5
126.5 108.9
75.8
37.9
30.3
30.3
30.3
30.3
30.3
64.1
32.1
25.7
25.7
25.7
25.7
25.7
34.1
17.1
13.7
13.7
13.7
13.7
13.7
275.6
137.8
110.3
110.3
110.3
110.3
110.3
2204.6
1102.2
440.9
220.5
110.3
55.2
15
7
63.3
50.6
50.6
50.6
50.6
50.6
54.5
43.6
43.6
43.6
43.6
43.6
200
8
100
9
50
28.1
10
11
25
14.1
12.5
14.1
55.2
GROUP DELAY @DC (MS) FOR ACCEL_UI_FILT_ORD=0 (1ST ORDER FILTER)
ACCEL_UI_FILT_BW
ACCEL_ODR
ODR(HZ)
8000
4000
2000
1000
500
0
1
2
3
4
5
6
7
14
15
3
4
0.3
0.5
0.9
5
6
0.6
1.8
2.0
2.8
3.1
6.1
7.6
7.6
7.6
7.6
7.6
4.1
8.1
4.7
9.3
8.1
16.2
20.3
20.3
20.3
20.3
20.3
1.5
0.2
0.4
1.0
1.9
3.8
7.5
7.5
15
7
1.1
2.7
3.6
4.4
4.4
4.4
4.4
4.4
4.0
5.0
5.0
5.0
5.0
5.0
5.5
6.8
6.8
6.8
6.8
6.8
3.0
3.8
3.8
3.8
3.8
3.8
200
10.2
10.2
10.2
10.2
10.2
11.7
11.7
11.7
11.7
11.7
8
100
5.3
9
50
10.5
21.0
21.0
10
11
25
12.5
2nd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3DB BANDWIDTH (HZ) FOR ACCEL_UI_FILT_ORD=1 (2ND ORDER FILTER)
ACCEL_UI_FILT_BW
ACCEL_ODR
ODR(HZ)
8000
4000
2000
1000
500
0
1
2
3
4
5
6
7
14
15
3
4
2096.3
1048.1
524.0
5
6
493.3 230.7 191.6 117.5
97.1 59.6 48.0 21.3 262.0 2096.3
48.5 29.8 24.0 10.6 131.0 1048.1
15
246.7 115.3
95.8
58.8
Page 28 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
7
8
200
100
50
98.7
49.3
24.7
12.3
12.3
92.3
92.3
92.3
92.3
92.3
76.6
76.6
76.6
76.6
76.6
47.0
47.0
47.0
47.0
47.0
38.8 23.8 19.2
38.8 23.8 19.2
38.8 23.8 19.2
38.8 23.8 19.2
38.8 23.8 19.2
8.5 104.8
8.5 104.8
8.5 104.8
8.5 104.8
8.5 104.8
419.2
209.6
104.8
52.4
9
10
11
25
12.5
52.4
NBW BANDWIDTH (HZ) FOR ACCEL_UI_FILT_ORD=1 (2ND ORDER FILTER)
ACCEL_UI_FILT_BW
ACCEL_ODR
ODR(HZ)
8000
4000
2000
1000
500
0
1
2
3
4
5
6
7
14
15
3
4
2204.6
1102.2
551.1
5
6
551.1 223.7 189.9 122.7 102.8 64.7 52.5 23.7 275.6 2204.6
15
7
259.6 111.9
95.0
76.0
76.0
76.0
76.0
76.0
61.4
49.1
49.1
49.1
49.1
49.1
51.4 32.4 26.3 11.9 137.8 1102.2
200
103.9
52.0
26.0
13.0
13.0
89.5
89.5
89.5
89.5
89.5
41.2 25.9 21.0
41.2 25.9 21.0
41.2 25.9 21.0
41.2 25.9 21.0
41.2 25.9 21.0
9.5 110.3
9.5 110.3
9.5 110.3
9.5 110.3
9.5 110.3
440.9
220.5
110.3
55.2
8
100
9
50
10
11
25
12.5
55.2
GROUP DELAY @DC (MS) FOR ACCEL_UI_FILT_ORD=1 (2ND ORDER FILTER)
ACCEL_UI_FILT_BW
ACCEL_ODR
ODR(HZ)
8000
4000
2000
1000
500
0
1
2
3
4
5
6
7
14
15
3
4
0.3
0.5
0.9
5
6
0.7
2.1
2.4
3.2
3.7
5.2
6.1 12.0
1.5
0.2
0.4
1.0
1.9
3.8
7.5
7.5
15
7
1.3
3.3
4.1
5.1
5.1
5.1
5.1
5.1
4.7
5.8
5.8
5.8
5.8
5.8
6.4
8.0
8.0
8.0
8.0
8.0
7.3 10.4 12.2 24.0
9.1 12.9 15.3 30.0
9.1 12.9 15.3 30.0
9.1 12.9 15.3 30.0
9.1 12.9 15.3 30.0
9.1 12.9 15.3 30.0
3.0
3.8
3.8
3.8
3.8
3.8
200
8
100
6.5
9
50
12.9
25.7
25.7
10
11
25
12.5
3rd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3DB BANDWIDTH (HZ) FOR ACCEL_UI_FILT_ORD=2 (3RD ORDER FILTER)
ACCEL_UI_FILT_BW
ACCEL_ODR
ODR(HZ)
8000
0
1
2
3
4
5
6
7
14
15
3
4
2096.3
1048.1
4000
Page 29 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
5
6
2000
1000
500
200
100
50
524.0
492.9 234.7 195.8 118.9
97.9 60.8 46.8 25.2 262.0
48.9 30.4 23.4 12.6 131.0
39.2 24.3 18.7 10.1 104.8
39.2 24.3 18.7 10.1 104.8
39.2 24.3 18.7 10.1 104.8
39.2 24.3 18.7 10.1 104.8
39.2 24.3 18.7 10.1 104.8
2096.3
1048.1
419.2
209.6
104.8
52.4
15
7
246.4 117.4
97.9
78.3
78.3
78.3
78.3
78.3
59.5
47.6
47.6
47.6
47.6
47.6
98.6
49.3
24.6
12.3
12.3
93.9
93.9
93.9
93.9
93.9
8
9
10
11
25
12.5
52.4
NBW BANDWIDTH (HZ) FOR ACCEL_UI_FILT_ORD=2 (3RD ORDER FILTER)
ACCEL_UI_FILT_BW
ACCEL_ODR
ODR(HZ)
8000
4000
2000
1000
500
0
1
2
3
4
5
6
7
14
15
3
4
2204.6
1102.2
551.1
5
6
551.1 221.3 188.5 120.1 100.0 62.9 48.6 26.4 275.6
2204.6
1102.2
440.9
220.5
110.3
55.2
15
7
252.0 110.7
94.3
75.4
75.4
75.4
75.4
75.4
60.1
48.1
48.1
48.1
48.1
48.1
50.0 31.5 24.3 13.2 137.8
40.0 25.2 19.5 10.6 110.3
40.0 25.2 19.5 10.6 110.3
40.0 25.2 19.5 10.6 110.3
40.0 25.2 19.5 10.6 110.3
40.0 25.2 19.5 10.6 110.3
200
100.8
50.4
25.2
12.6
12.6
88.6
88.6
88.6
88.6
88.6
8
100
9
50
10
11
25
12.5
55.2
GROUP DELAY @DC (MS) FOR ACCEL_UI_FILT_ORD=2 (3RD ORDER FILTER)
ACCEL_UI_FILT_BW
ACCEL_ODR
ODR(HZ)
8000
4000
2000
1000
500
0
1
2
3
4
5
6
7
14
15
3
4
0.3
0.5
0.9
5
6
0.8
2.3
2.7
4.0
4.6
6.6
8.2 14.1
1.5
0.2
0.4
1.0
1.9
3.8
7.5
7.5
15
7
1.6
4.0
4.6
5.8
5.8
5.8
5.8
5.8
5.4
6.8
6.8
6.8
6.8
6.8
7.9
9.8
9.8
9.8
9.8
9.8
9.2 13.2 16.3 28.1
11.4 16.5 20.4 35.2
11.4 16.5 20.4 35.2
11.4 16.5 20.4 35.2
11.4 16.5 20.4 35.2
11.4 16.5 20.4 35.2
3.0
3.8
3.8
3.8
3.8
3.8
200
8
100
8.0
9
50
15.9
31.8
31.8
10
11
25
12.5
5.5 ODR AND FSR SELECTION
Accelerometer ODR can be selected by programming the parameter ACCEL_ODR in register bank 0, register 0x50h,
bits 3:0 as shown below.
ACCEL_ODR
ACCELEROMETER ODR VALUE
Reserved
0000
Page 30 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
Reserved
Reserved
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
8kHz (LN mode)
4kHz (LN mode)
2kHz (LN mode)
1kHz (LN mode) (default)
200Hz (LP or LN mode)
100Hz (LP or LN mode)
50Hz (LP or LN mode)
25Hz (LP or LN mode)
12.5Hz (LP or LN mode)
Reserved
Reserved
Reserved
500Hz (LP or LN mode)
Accelerometer FSR can be selected by programming the parameter ACCEL_FS_SEL in register bank 0, register
0x50h, bits 7:5 as shown below.
ACCEL_FS_SEL
ACCELEROMETER FSR VALUE
000
001
010
011
100
101
110
111
16g
8g
4g
2g
Reserved
Reserved
Reserved
Reserved
Page 31 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
6 FIFO
The IIM-42351 contains a 2 kB FIFO register that is accessible via the serial interface. The FIFO configuration
register determines which data is written into the FIFO. Possible choices include accelerometer data, temperature
readings, and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO.
6.1 PACKET STRUCTURE
The following figure shows the 8 and 16-byte FIFO packet structures supported in IIM-42351. Base data format for
accelerometer is 16-bits per element. 20-bits data format support is included in one of the packet structures.
When 20-bits data format is used, accelerometer data consists of 18-bits of actual data and the two lowest order
bits are always set to 0. When 20-bits data format is used, the only FSR settings that are operational is ±16g for
accelerometer, even if the FSR selection register settings are configured for other FSR values. The accelerometer
sensitivity scale factor value is and 8192 LSB/g.
Header
(1 byte)
Header
(1 byte)
Header
(1 byte)
Accelerometer Data
(6 bytes)
Accelerometer Data
(6 bytes)
Accelerometer Data
(6 bytes)
Temperature Data
(1 byte)
Reserved
Reserved
Packet 1
Temperature Data
(1 byte)
Temperature Data
(2 bytes)
TimeStamp
(2 bytes)
TimeStamp
(2 bytes)
Packet 2
20-bit Extension
(3 bytes)
Packet 3
Figure 10. FIFO Packet Structure
Due to limitation on the number of bits, 8-bit Temperature data stored in FIFO is limited to -40°C to 85°C range.
Either 16-bit Temperature data format (FIFO packet 3) or the value from the sensor data registers (TEMP_DATA)
must be used to support a temperature measurements range of -40° to 105°C.
The rest of this sub-section describes how individual data is packaged in the different FIFO packet structures.
Page 32 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
Packet 1: Individual data is packaged in Packet 1 as shown below.
BYTE
CONTENT
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
FIFO Header
Accel X [15:8]
Accel X [7:0]
Accel Y [15:8]
Accel Y [7:0]
Accel Z [15:8]
Accel Z [7:0]
Temperature [7:0]
Packet 2: Individual data is packaged in Packet 2 as shown below.
BYTE
CONTENT
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
FIFO Header
Accel X [15:8]
Accel X [7:0]
Accel Y [15:8]
Accel Y [7:0]
Accel Z [15:8]
Accel Z [7:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Temperature[7:0]
TimeStamp[15:8]
TimeStamp[7:0]
Packet 3: Individual data is packaged in Packet 3 as shown below.
Byte
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Content
FIFO Header
Accel X [19:12]
Accel X [11:4]
Accel Y [19:12]
Accel Y [11:4]
Accel Z [19:12]
Accel Z [11:4]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Temperature[15:8]
Temperature[7:0]
Page 33 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
0x0F
0x10
0x11
0x12
TimeStamp[15:8]
TimeStamp[7:0]
Accel X [3:0]
Reserved
Reserved
Accel Y [3:0]
0x13
Accel Z [3:0]
Reserved
6.2 FIFO HEADER
The following table shows the structure of the 1 byte FIFO header.
BIT FIELD
ITEM
DESCRIPTION
1: FIFO is empty
0: Packet contains sensor data
7
HEADER_MSG
0xx: Reserved
6:4
HEADER_PACKET_FORMAT
100: Packet contains packet 1 format (accel + temp)
101: Reserved
110: Packet contains packet 2 format (accel + temp + timestamp)
111: Packet contains packet 3 format (hires accel + temp + timestamp)
*See detail packet structure at section 6.1
00: Packet does not contain timestamp or FSYNC time data
01: Reserved
10: Packet contains ODR Timestamp
3:2
HEADER_TIMESTAMP_FSYNC
11: Packet contains FSYNC time, and this packet is flagged as first ODR after FSYNC (only if
FIFO_TMST_FSYNC_EN is 1)
1: The ODR for accel is different for this accel data packet compared to the previous accel
packet
0: The ODR for accel is the same as the previous packet with accel
1
0
HEADER_ODR_ACCEL
-
Reserved
6.3 MAXIMUM FIFO STORAGE
The maximum number of packets that can be stored in FIFO is a variable quantity depending on the use case. As
shown in Figure 11, the physical FIFO size is 2048 bytes. A number of bytes equal to the packet size selected (see
section 5.1) is reserved to prevent reading a packet during write operation. Additionally, a read cache 2 packets
wide is available.
When there is no serial interface operation, the read cache is not available for storing packets, being fed by the
serial interface clock.
When serial interface operation happens, depending on the operation length and the packet size chosen, either 1
or 2 of the packet entries in read cache may become available for storing packets. In that case the total storage
available is up to the maximum number of packets that can be accommodated in 2048 bytes + 1 packet size,
depending on the packet size used.
Due to the non-deterministic nature of system operation, driver memory allocation should always be the largest
size of 2080 bytes.
Page 34 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
2 Packet Size
FIFO 2048 Bytes
Read Cache
2048 Bytes – 1 packet size
1 Packet Size
Reserved to prevent reading a
packet during write operation
Figure 11. Maximum FIFO Storage
6.4 FIFO CONFIGURATION REGISTERS
The following control bits in bank 0, register 0x5Fh determine what data is placed into the FIFO. The values of
these bits may change while the FIFO is being filled without corruption of the FIFO.
BIT
NAME
FUNCTION
0: Default setting; Sensor data have regular resolution
1: Sensor data in FIFO will have extended resolution enabling the 20 Bytes
packet
4
FIFO_HIRES_EN
0: FIFO will only contain ODR timestamp information
1: FIFO can also contain FSYNC time and FSYNC tag for one ODR after an
FSYNC event
00: Disable packet goes to FIFO
01: Enable Packet 1 goes to FIFO
3
FIFO_TMST_FSYNC_EN
FIFO_PACKET_EN
1: 0
10: Reserved
11: Enable Packet 2 goes to FIFO when FIFO_HIRES_EN=0
Enable Packet 3 goes to FIFO when FIFO_HIRES_EN=1
Configuration register settings above impact FIFO header and FIFO packet size as follows:
FIFO_TMST_
FSYNC_EN
FIFO_HIRES_EN
FIFO_PACKET_EN
HEADER
PACKET SIZE
1
1
0
0
0
0
0
1
0
1
X
X
2’b_11
2’b_11
2’b_11
2’b_11
2’b_01
2’b_00
8’b_0111_10xx
8’b_0111_11xx
8’b_0110_10xx
8’b_0110_11xx
8’b_0100_00xx
No FIFO writes
20 Bytes
20 Bytes
16 Bytes
16 Bytes
8 Bytes
No FIFO writes
Page 35 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
7 PROGRAMMABLE INTERRUPTS
The IIM-42351 has a programmable interrupt system that can generate an interrupt signal on the INT pins. Status
flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. There are two
interrupt outputs. Any interrupt may be mapped to either interrupt pin as explained in the register section. The
following configuration options are available for the interrupts
•
•
•
INT1 and INT2 can be push-pull or open drain
Level or pulse mode
Active high or active low
Additionally, IIM-42351 includes In-band Interrupt (IBI) support for the I3CSM interface.
Page 36 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
8 APEX MOTION FUNCTIONS
The APEX (Advanced Pedometer and Event Detection – neXt gen) features of IIM-42631 consist of:
•
•
Pedometer: Tracks Step count and issues a Step Detect Interrupt
Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 degrees for more than a programmable
time.
•
•
•
Freefall Detection: Triggers an interrupt when device freefall is detected and outputs freefall duration.
Tap Detection: Issues an interrupt when Tap is detected, along with a register containing the Tap Count.
Wake on Motion (WoM): Detects motion when accelerometer samples exceed a programmable
threshold. This motion event can be used to enable chip operation from sleep mode.
Significant Motion Detector (SMD): Detects motion if WoM events are detected during a programmable
time window (2s or 4s).
•
8.1 APEX ODR SUPPORT
APEX algorithms are designed to work with the accelerometer, for a variety of ODR settings. However, there is a
minimum ODR required for each algorithm. The following table shows the relationship between the available
accelerometer ODRs and the operation of the APEX algorithms. In order to allow more flexible operation where we
can control the ODR of the APEX algorithms independent of the accelerometer ODR, we allow for an additional
selection determined by the field DMP_ODR (DMP stands for Digital Motion ProcessorTM, an architectural
component of APEX). The tables below shows how DMP_ODR should be configured in relation to the
accelerometer ODR and the expected performance.
ACCEL ODR DMP_ODR
PEDOMETER
TILT DETECTION
FREEFALL DETECTION
< 25 Hz
≥ 25 Hz
≥ 5 0Hz
100 Hz
500Hz
X
Disabled
Disabled
Disabled
0 (25 Hz)
2 (50 Hz)
3 (100 Hz)
1 (500Hz)
Low Power
Normal
Low Power
Normal
Low Power
Low Power
High Performance
Normal (50Hz)
Disabled
Normal
(50 Hz)
High Performance
High Performance
(50 Hz)
ACCEL ODR
TAP DETECTION
200 Hz
500 Hz
1 kHz
Low Power
Normal
High Performance
Disabled
> 1 kHz
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If the accelerometer ODR is set below the minimum DMP ODR (25 Hz), the APEX features cannot be enabled.
When the accelerometer ODR needs to be set differently from the DMP ODR, only the integer multiple of DMP
ODR for accelerometer sensor ODR is suitable to use with DMP. For example, when the accelerometer ODR is set
as 200 Hz, the APEX features can be enabled with choices of 25 Hz, or 50 Hz, depending on the DMP_ODR register
setting.
DMP ODR should not be changed on the fly. The following sequence should be followed for changing the DMP
ODR:
1. Disable Pedometer, and Tilt Detection if they are enabled
2. Change DMP ODR
3. Set DMP_INIT_EN for one cycle (Register 0x4Bh in Bank 0)
4. Unset DMP_INIT_EN (Register 0x4Bh in Bank 0)
5. Enable APEX features of interest
8.2 DMP POWER SAVE MODE
DMP Power Save Mode can be enabled or disabled by DMP_POWER_SAVE (Register 0x56h in Bank 0). When the
DMP Power Save Mode is enabled, APEX features are enabled only when WOM is detected. WOM must be
explicitly enabled for the DMP to work in this mode. When WOM is not detected the APEX features are on pause.
If the user does not want to use DMP Power Save Mode they may set DMP_POWER_SAVE = 0, and use APEX
functions without WOM detection.
8.3 PEDOMETER PROGRAMMING
•
Pedometer configuration parameters
1. LOW_ENERGY_AMP_TH_SEL (Register 0x40h in Bank 4)
2. PED_AMP_TH_SEL (Register 0x41h in Bank 4)
3. PED_STEP_CNT_TH_SEL (Register 0x41h in Bank 4)
4. PED_HI_EN_TH_SEL (Register 0x42h in Bank 4)
5. PED_SB_TIMER_TH_SEL (Register 0x42h in Bank 4)
6. PED_STEP_DET_TH_SEL (Register 0x42h in Bank 4)
7. SENSITIVITY_MODE (Register 0x48h in Bank 4)
8. There are 2 ODR and 2 sensitivity modes
ACCEL ODR (DMP_ODR)
25 Hz (0)
NORMAL
SLOW WALK
low power
low power and slow walk
slow walk
50 Hz (2)
high performance
•
•
Initialize Sensor in a typical configuration
1. Set accelerometer ODR to 50 Hz (Register 0x50h in Bank 0)
2. Set accelerometer to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Eh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Set DMP ODR = 50 Hz and turn on Pedometer feature (Register 0x56h in Bank 0)
4. Wait 1 millisecond
Initialize APEX hardware
1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0)
2. Wait 1 millisecond
3. Set LOW_ENERGY_AMP_TH_SEL to 10 (Register 0x40h in Bank 4)
4. Set PED_AMP_TH_SEL to 8 (Register 0x41h in Bank 4)
5. Set PED_STEP_CNT_TH_SEL to 5 (Register 0x41h in Bank 4)
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6. Set PED_HI_EN_TH_SEL to 1 (Register 0x42h in Bank 4)
7. Set PED_SB_TIMER_TH_SEL to 4 (Register 0x42h in Bank 4)
8. Set PED_STEP_DET_TH_SEL to 2 (Register 0x42h in Bank 4)
9. Set SENSITIVITY_MODE to 0 (Register 0x48h in Bank 4)
10. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
11. Wait 50 milliseconds
12. Enable STEP detection, source for INT1 by setting bit 5 in register INT_SOURCE6 (Register 0x4Dh
in Bank 4) to 1. Or if INT2 is selected for STEP detection, enable STEP detection source by setting
bit 5 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1.
13. As freefall and pedometer share the same output register, they cannot run concurrently. Disable
freefall by setting FF_ENABLE to 0 (Register 0x56h in Bank 0)
14. Turn on Pedometer feature by setting PED_ENABLE to 1 (Register 0x56h in Bank 0)
•
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for STEP_DET_INT
2. If the step count is equal to or greater than 65535 (uint16), the STEP_CNT_OVF_INT (Register
0x38h in Bank 0) will be set to 1. Example:
.
.
.
Take 1 step =>output step count = 65533 (real step count is 65533)
Take 1 step => output step count = 65534 (real step count is 65534)
Take 1 step => output step count = 0 and interrupt is fired (real step count is 65535+0=
65535)
.
Take 1 step => output step count = 1 (real step count is 65535+1=65536)
3. Read the step count in STEP_CNT (Register 0x31h and 0x32h in Bank 0)
4. Read the step cadence in STEP_CADENCE (Register 0x33h in Bank 0)
5. Read the activity class in ACTIVITY_CLASS (Register 0x34h in Bank 0)
8.4 TILT DETECTION PROGRAMMING
•
Tilt Detection configuration parameters
1. TILT_WAIT_TIME (Register 0x43h in Bank 4)
This parameter configures how long of a delay after tilt is detected before interrupt is triggered
Default is 2 (4 s).
Range is 0 = 0 s, 1 = 2 s, 2 = 4 s, 3 = 6 s
For example, setting TILT_WAIT_TIME = 2 is equivalent to 4 seconds for all ODRs
•
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 9 for 50 Hz or 10 for 25 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Set DMP ODR (Register 0x56h in Bank 0)
DMP_ODR = 0 for 25 Hz, 2 for 50 Hz
4. Wait 1 millisecond
•
Initialize APEX hardware
1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0)
2. Wait 1 millisecond
3. Set TILT_WAIT_TIME (Register 0x43h in Bank 4) if default value does not meet needs
4. Wait 1 millisecond
5. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
6. Enable Tilt Detection, source for INT1 by setting bit 3 in register INT_SOURCE6 (Register 0x4Dh in
Bank 4) to 1. Or if INT2 is selected for Tilt Detection, enable Tilt Detection source by setting bit 3
in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1.
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7. Wait 50 milliseconds
8. Turn on Tilt Detection feature by setting TILT_ENABLE to 1 (Register 0x56h in Bank 0)
•
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for TILT_DET_INT
8.5 FREEFALL DETECTION PROGRAMMING
Freefall Detection detects device freefall. It uses a low-g and a high-g detector to detect freefall start and
freefall end. It provides a trigger indicating freefall event and the freefall duration. The duration is given in
number of samples and can be converted to freefall distance in meters by applying the following formula:
FF_DISTANCE = 0.5 * 9.81 * (FF_DUR * DMP_ODR_S)^2
Note: DMP_ODR_S is the duration of DMP_ODR expressed in seconds.
•
Freefall Detection configuration parameters
1. LOWG_PEAK_TH_SEL (Register 0x44h in Bank 4)
2. LOWG_TIME_TH_SEL (Register 0x44h in Bank 4)
3. LOWG_PEAK_TH_HYST_SEL (Register 0x43h in Bank 4)
4. HIGHG_PEAK_TH_SEL (Register 0x45h in Bank 4)
5. HIGHG_TIME_TH_SEL (Register 0x45h in Bank 4)
6. HIGHG_PEAK_TH_HYST_SEL (Register 0x43h in Bank 4)
7. FF_MIN_DURATION_CM (Register 0x49h in Bank 4)
8. FF_MAX_DURATION_CM (Register 0x49h in Bank 4)
9. FF_DEBOUNCE_DURATION (Register 0x49h in Bank 4)
•
•
Initialize Sensor in a typical configuration
1. Set Accel ODR to 500 Hz (Register 0x50h in Bank 0)
2. Set AVG filtering to 1 sample to minimize power consumption (Register 0x52h in Bank 0)
ACCEL_UI_FILT_BW = 1
3. Set Accel to Low Power mode (Register 0x4E in Bank 0)
ACCEL_MODE[1:0] = 2
4. Set DMP ODR = 500 Hz (Register 0x56 in Bank 0)
DMP_ODR[1:0] = 1
Initialize APEX hardware
1. Set LOWG_PEAK_TH_SEL (Register 0x44h in Bank 4)
2. Set LOWG_TIME_TH_SEL (Register 0x44h in Bank 4)
3. Set LOWG_PEAK_TH_HYST_SEL (Register 0x43 in Bank4)
4. Set HIGHG_PEAK_TH_SEL (Register 0x45h in Bank 4)
5. Set HIGHG_TIME_TH_SEL (Register 0x45h in Bank 4)
6. Set HIGHG_PEAK_TH_HYST_SEL (Register 0x43h in Bank4)
7. Set FF_DEBOUNCE_DURATION (Register 0x49h in Bank 4)
8. Set FF_MIN_DURATION_CM (Register 0x49h in Bank 4)
9. Set FF_MAX_DURATION_CM (Register 0x49h in Bank 4)
10. Set DMP_MEM_RESET_EN to 1 if DMP is started for the first time after reset (Register 0x4Bh in
Bank 0)
11. Wait 1 millisecond
12. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
13. Enable FREEFALL detection, source for INT1 by setting bit 1 in register INT_SOURCE6 (Register
0x4Dh in Bank 4) to 1. Or if INT2 is selected for FREEFALL detection, enable FREEFALL detection
source by setting bit 1 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1.
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14. Wait 50 milliseconds
15. As freefall and pedometer share the same output register, they cannot run concurrently. Disable
pedometer by setting PED_ENABLE to 0 (Register 0x56h in Bank 0)
16. Set FF_ENABLE to 1 (Register 0x56h in Bank 0)
•
•
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for FF_DET_INT
2. Read the freefall duration (Registers 0x31h and 0x32h in Bank 0)
Note: As freefall and pedometer share the same output register, they cannot be run concurrently.
8.6 TAP DETECTION PROGRAMMING
•
Tap Detection configuration parameters
1. TAP_TMAX (Register 0x47h in Bank 4)
2. TAP_TMIN (Register 0x47h in Bank 4)
3. TAP_TAVG (Register 0x47h in Bank 4)
4. TAP_MIN_JERK_THR (Register 0x46h in Bank 4)
5. TAP_MAX_PEAK_TOL (Register 0x46h in Bank 4)
6. TAP_ENABLE (Register 0x56h in Bank 0)
•
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 15 for 500 Hz (ODR of 200Hz or 1kHz may also be used)
2. Set power modes and filter configurations as shown below
.
For ODR up to 500Hz, set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and ACCEL_LP_CLK_SEL = 0, (Register 0x4Dh in Bank 0) for low power
mode
Set filter settings as follows: ACCEL_DEC2_M2_ORD = 2 (Register 0x53h in Bank 0);
ACCEL_UI_FILT_BW = 4 (Register 0x52h in Bank 0)
•
For ODR of 1kHz, set Accel to Low Noise mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 1
Set filter settings as follows: ACCEL_UI_FILT_ORD = 2 (Register 0x53h in Bank 0);
ACCEL_UI_FILT_BW = 0 (Register 0x52h in Bank 0)
3. Wait 1 millisecond
•
Initialize APEX hardware
1. Set TAP_TMAX to 2 (Register 0x47h in Bank 4)
2. Set TAP_TMIN to 3 (Register 0x47h in Bank 4)
3. Set TAP_TAVG to 3 (Register 0x47h in Bank 4)
4. Set TAP_MIN_JERK_THR to 17 (Register 0x46h in Bank 4)
5. Set TAP_MAX_PEAK_TOL to 2 (Register 0x46h in Bank 4)
6. Wait 1 millisecond
7. Enable TAP source for INT1 by setting bit 0 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to
1. Or if INT2 is selected for TAP, enable TAP source by setting bit 0 in register INT_SOURCE7
(Register 0x4Eh in Bank 4) to 1.
8. Wait 50 milliseconds
9. Turn on TAP feature by setting TAP_ENABLE to 1 (Register 0x56h in Bank 0)
•
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for TAP_DET_INT
2. Read the tap count in TAP_NUM (Register 0x7Bh in Bank 0)
3. Read the tap axis in TAP_AXIS (Register 0x7Bh in Bank 0)
4. Read the polarity of tap pulse in TAP_DIR (Register 0x7Bh in Bank 0)
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8.7 WAKE ON MOTION PROGRAMMING
•
Wake on Motion configuration parameters
1. WOM_X_TH (Register 0x4Ah in Bank 4)
2. WOM_Y_TH (Register 0x4Bh in Bank 4)
3. WOM_Z_TH (Register 0x4Ch in Bank 4)
4. WOM_INT_MODE (Register 0x57h in Bank 0)
5. WOM_MODE (Register 0x57h in Bank 0)
6. SMD_MODE (Register 0x57h in Bank 0)
•
•
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 9 for 50 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Wait 1 millisecond
Initialize APEX hardware
1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4)
2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4)
3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4)
4. Wait 1 millisecond
5. Enable all 3 axes as WOM sources for INT1 by setting bits 2:0 in register INT_SOURCE1 (Register
0x66h in Bank 0) to 1. Or if INT2 is selected for WOM, enable all 3 axes as WOM sources by
setting bits 2:0 in register INT_SOURCE4 (Register 0x69h in Bank 0) to 1.
6. Wait 50 milliseconds
7. Turn on WOM feature by setting WOM_INT_MODE to 0, WOM_MODE to 1, SMD_MODE to 1
(Register 0x56h in Bank 0)
•
Output registers
1. Read interrupt register (Register 0x37h in Bank 0) for WOM_X_INT
2. Read interrupt register (Register 0x37h in Bank 0) for WOM_Y_INT
3. Read interrupt register (Register 0x37h in Bank 0) for WOM_Z_INT
8.8 SIGNIFICANT MOTION DETECTION PROGRAMMING
•
•
Significant Motion Detection configuration parameters
1. WOM_X_TH (Register 0x4Ah in Bank 4)
2. WOM_Y_TH (Register 0x4Bh in Bank 4)
3. WOM_Z_TH (Register 0x4Ch in Bank 4)
4. WOM_INT_MODE (Register 0x57h in Bank 0)
5. WOM_MODE (Register 0x57h in Bank 0)
6. SMD_MODE (Register 0x57h in Bank 0)
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 9 for 50 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Wait 1 millisecond
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•
Initialize APEX hardware
1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4)
2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4)
3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4)
4. Wait 1 millisecond
5. Enable SMD source for INT1 by setting bit 3 in register INT_SOURCE1 (Register 0x66h in Bank 0)
to 1. Or if INT2 is selected for SMD, enable SMD source by setting bit 3 in register INT_SOURCE4
(Register 0x69h in Bank 0) to 1.
6. Wait 50 milliseconds
7. Turn on SMD feature by setting WOM_INT_MODE to 0, WOM_MODE to 1, SMD_MODE to 3
(Register 0x56h in Bank 0)
•
Output registers
1. Read interrupt register (Register 0x37h in Bank 0) for SMD_INT
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9 DIGITAL INTERFACE
9.1 I3CSM, I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the IIM-42351 can be accessed using I3CSM at 12.5 MHz (data rates up to
12.5 Mbps in SDR mode, 25 Mbps in DDR mode), I2C at 1 MHz or SPI at 24 MHz. SPI operates in 3-wire or 4-wire
mode. Pin assignments for serial interfaces are described in Section 3.1.
9.2 I3CSM INTERFACE
I3CSM is a new 2-wire digital interface comprised of the signals serial data (SDA) and serial clock (SCLK). I3CSM is
intended to improve upon the I2C interface, while preserving backward compatibility.
I3CSM carries the advantages of I²C in simplicity, low pin count, easy board design, and multi-drop (vs. point to
point), but provides the higher data rates, simpler pads, and lower power of SPI. I3CSM adds higher throughput for
a given frequency, in-band interrupts (from slave to master), dynamic addressing.
IIM-42351 supports the following features of I3CSM
:
•
•
•
•
•
•
•
SDR data rate up to 12.5Mbps
DDR data rate up to 25Mbps
Dynamic address allocation
In-band Interrupt (IBI) support
Support for asynchronous timing control mode 0
Error detection (CRC and/or Parity)
Common Command Code (CCC)
The IIM-42351 always operates as an I3CSM slave device when communicating to the system processor, which thus
acts as the I3CSM master. I3CSM master controls an active pullup resistance on SDA, which it can enable and disable.
The pullup resistance may be a board level resistor controlled by a pin, or it may be internal to the I3CSM master.
9.3 I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are
open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or a
slave. The master device puts the slave address on the bus, and the slave device with the matching address
acknowledges the master.
The IIM-42351 always operates as a slave device when communicating to the system processor, which thus acts as
the master. SDA and SCL lines typically need pull-up resistors to VDDIO. The maximum bus speed is 1 MHz.
The slave address of the IIM-42351 is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is determined
by the logic level on pin AP_AD0. This allows two IIM-42351s to be connected to the same I2C bus. When used in
this configuration, the address of one of the devices should be b1101000 (pin AP_AD0 is logic low) and the address
of the other should be b1101001 (pin AP_AD0 is logic high).
9.4 I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as
a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be
busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the
SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
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SDA
SCL
S
P
START condition
STOP condition
Figure 12. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data
transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge
signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA
and holding it low during the HIGH portion of the acknowledge clock pulse.
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by
an 8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to
the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave
device. Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the
SDA line LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the
master with a STOP condition (P), thus freeing the communications line. However, the master can generate a
repeated START condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to
HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place
when SCL is low, with the exception of start and stop conditions.
SDA
SCL
1 – 7
8
9
1 – 7
8
9
1 – 7
8
9
S
P
START
STOP
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
condition
condition
Figure 13. Complete I2C Data Transfer
To write the internal IIM-42351 registers, the master transmits the start condition (S), followed by the I2C address
and the write bit (0). At the 9th clock cycle (when the clock is high), the IIM-42351 acknowledges the transfer. Then
the master puts the register address (RA) on the bus. After the IIM-42351 acknowledges the reception of the
register address, the master puts the register data onto the bus. This is followed by the ACK signal, and data
transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master
can continue outputting data rather than transmitting a stop signal. In this case, the IIM-42351 automatically
increments the register address and loads the data to the appropriate register. The following figures show single
and two-byte write sequences.
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Single-Byte Write Sequence
Master
Slave
S
AD+W
RA
DATA
DATA
P
ACK
ACK
ACK
ACK
ACK
Burst Write Sequence
Master
Slave
S
AD+W
RA
DATA
P
ACK
ACK
To read the internal IIM-42351 registers, the master sends a start condition, followed by the I2C address and a
write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the IIM-42351,
the master transmits a start signal followed by the slave address and read bit. As a result, the IIM-42351 sends an
ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from
master. The NACK condition is defined such that the SDA line remains high at the 9th clock cycle. The following
figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
RA
RA
S
AD+R
AD+R
NACK
P
ACK
ACK
ACK
ACK
ACK
DATA
Burst Read Sequence
Master
Slave
S
AD+W
S
ACK
NACK
P
ACK DATA
DATA
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9.5 I2C TERMS
SIGNAL
DESCRIPTION
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
S
AD
W
Write bit (0)
R
Read bit (1)
ACK
NACK
RA
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
IIM-42351 internal register address
DATA
P
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 13. I2C Terms
9.6 SPI INTERFACE
The IIM-42351 supports 3-wire or 4-wire SPI for the host interface. The IIM-42351 always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO), the Serial Data Input
(SDI), and the Serial Data IO (SDIO) are shared among the Slave devices. Each SPI slave device requires its own Chip
Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active
at a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices
are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interfere
with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 24 MHz
5. SPI read operations are completed in 16 or more clock cycles (two or more bytes). The first byte
contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte
contains the Read/Write bit and indicates the Read (1) operation. The following 7 bits contain the
Register Address. In cases of multiple-byte Reads, data is two or more bytes:
SPI Address format
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
SPI Data format
MSB
LSB
D7
D6 D5 D4 D3 D2 D1 D0
6. SPI write operations are completed in 16 clock cycles (two bytes). The first byte contains the SPI
Address, and the second byte contains the SPI data. The first bit of the first byte contains the
Read/Write bit and indicates the Write (0) operation. The following 7 bits contain the Register Address.
7. Supports Single or Burst Reads and Single Writes.
Page 47 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
SCLK
SDIO
SPI Master
SPI Slave 1
CS1
CS2
nCS
SCLK
SDIO
SPI Slave 2
nCS
Figure 14. Typical SPI Master/Slave Configuration
Page 48 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
10 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS)
accelerometer packaged in LGA package.
10.1 ORIENTATION OF AXES
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1
identifier (•) in the figure.
+Z
+Y
+Z
+Y
+X
+X
Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation
Page 49 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
10.2 PACKAGE DIMENSIONS
14 Lead LGA (2.5x3x0.91) mm NiAu pad finish
Page 50 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
DIMENSIONS IN MILLIMETERS
SYMBOLS
MIN
0.85
NOM
0.91
0.105
0.8
MAX
0.97
REF
Total Thickness
Substrate Thickness
Mold Thickness
A
A1
A2
REF
D
E
2.5
3
BSC
BSC
0.3
Body Size
Lead Width
Lead Length
W
0.2
0.25
L
e
n
0.425
0.475
0.5
14
0.525
BSC
Lead Pitch
Lead Count
D1
1.5
BSC
Edge Pin Center to Center
E1
SD
aaa
bbb
ddd
1
0.25
0.1
0.2
0.08
BSC
BSC
Body Center to Contact Pin
Package Edge Tolerance
Mold Flatness
Coplanarity
Page 51 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
11 PART NUMBER PACKAGE MARKING
The part number package marking for IIM-42351 devices is summarized below:
PART NUMBER
IIM-42351
PART NUMBER PACKAGE MARKING
I4351
TOP VIEW
I4351
Part Number
X X XX X X
YYWW
Lot Traceability Code
Y Y = Year Code
W W = Work Week
Page 52 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
12 USE NOTES
12.1 ACCELEROMETER MODE TRANSITIONS
When transitioning from accelerometer Low Power (LP) mode to accelerometer Low Noise (LN) mode, if ODR is
6.25 Hz or lower, software should change ODR to a value of 12.5 Hz or higher, because accelerometer LN mode
does not support ODR values below 12.5 Hz.
When transitioning from accelerometer LN mode to accelerometer LP mode, if ODR is greater than 500 Hz,
software should change ODR to a value of 500 Hz or lower, because accelerometer LP mode does not support ODR
values above 500 Hz.
12.2 ACCELEROMETER LOW POWER (LP) MODE AVERAGING FILTER SETTING
Software drivers provided with the device use Averaging Filter setting of 16x. This setting is recommended for
meeting Android noise requirements in LP mode, and to minimize accelerometer offset variation when
transitioning from LP to Low Noise (LN) mode. 1x averaging filter can be used by following the setting configuration
shown in section 14.38.
12.3 SETTINGS FOR I2C, I3CSM, AND SPI OPERATION
Upon bootup the device comes up in SPI mode. The following settings should be used for I2C, I3CSM, and SPI
operation.
Scenario 1: INT1/INT2 pins are used for interrupt assertion in I3CSM mode.
REGISTER FIELD
I2C DRIVER
SETTING
I3CSM DRIVER
SETTING
SPI DRIVER
SETTING
I3C_EN (bit 4, register INTF_CONFIG6, address 0x7C, bank 1)
1
1
1
I3C_SDR_EN (bit 0, register INTF_CONFIG6, address 0x7C, bank
0
1
1
1)
I3C_DDR_EN (bit 1, register INTF_CONFIG6, address 0x7C, bank
0
0
1
1
0
0
0
3
1
0
0
5
1)
I3C_BUS_MODE (bit 6, register INTF_CONFIG4, address 0x7A,
bank 1)
I2C_SLEW_RATE (bits 5:3, register DRIVE_CONFIG, address
0x13, bank 0)
SPI_SLEW_RATE (bits 2:0, register DRIVE_CONFIG, address
0x13, bank 0)
Scenario 2: IBI is used for interrupt assertion in I3CSM mode.
REGISTER FIELD
I2C DRIVER
SETTING
I3CSM DRIVER
SETTING
SPI DRIVER
SETTING
I3C_EN (bit 4, register INTF_CONFIG6, address 0x7C, bank 1)
1
1
1
I3C_SDR_EN (bit 0, register INTF_CONFIG6, address 0x7C, bank
0
1
1
1)
I3C_DDR_EN (bit 1, register INTF_CONFIG6, address 0x7C, bank
0
0
1
1
1
0
0
5
1
0
0
5
1)
I3C_BUS_MODE (bit 6, register INTF_CONFIG4, address 0x7A,
bank 1)
I2C_SLEW_RATE (bits 5:3, register DRIVE_CONFIG, address
0x13, bank 0)
SPI_SLEW_RATE (bits 2:0, register DRIVE_CONFIG, address
0x13, bank 0)
12.4 ANTI-ALIAS FILTER OPERATION
Use of Anti-Alias Filter is supported only for Low Noise (LN) mode operation. The host is responsible for keeping
the UI path in LN mode while Anti-Alias Filter are turned on.
Page 53 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
12.5 EXTERNAL CLOCK INPUT EFFECT ON ODR
ODR values supported by the device scale with external clock frequency, if external clock input is used. The ODR
values shown in the datasheet are supported with external clock input frequency of 32 kHz. For any other external
clock input frequency, these ODR values will scale by a factor of (External clock value in kHz/32). For example, if an
external clock frequency of 32.768 kHz is used, instead of ODR value of 500 Hz, it will be 500 * (32.768/32) =
512 Hz.
12.6 INT_ASYNC_RESET CONFIGURATION
For register INT_CONFIG1 (bank 0 register 0x64) bit 4 INT_ASYNC_RESET, user should change setting to 0 from
default setting of 1, for proper INT1 and INT2 pin operation.
12.7 FIFO TIMESTAMP INTERVAL SCALING
When RTC_MODE =1 (bank 0 register 0x4D bit2) and register INTF_CONFIG5 (bank 1 register 0x7B) bit 2:1
(PIN9_FUNCTION) is set to 10 for CLKIN input;
THEN
Timestamp interval reported in FIFO requires scaling by a factor of 32.768/30. For example, when ODR = 1 kHz, the
true timestamp interval should be 1000 µs. But the value in FIFO toggles between 915 and 916 µs. After scaling
915.5 * 32.768/30 = 1000 µs.
ELSE
Timestamp interval reported in FIFO requires scaling by a factor of 32/30. For example when ODR = 1 kHz, the true
timestamp interval should be 1000 µs. But the value in FIFO toggles between 937 and 938 µs. After scaling 937.5 *
32/30 = 1000 µs.
12.8 SUPPLEMENTARY INFORMATION FOR FIFO_HOLD_LAST_DATA_EN
This section contains supplementary information for using register field FIFO_HOLD_LAST_DATA_EN (bit 7) of
register INTF_CONFIG0 (address 0x4C, bank 0) .
The following table shows the values in FIFO:
16-BIT FIFO
PACKET
FIFO_HOLD_LAST_DATA_EN
20-BIT FIFO PACKET
Every Other Even number in {-524256 to +524284}
Example: {-524256, -524252, -524248, -524244
…..+524280, +524284}
All values in:
{-32766 to
+32767}
Valid sample
0 (Insert Invalid code)
Invalid
sample
-524288
-32768
All values in:
{-32768 to
+32767}
Every Other Even number in {-524288 to +524284 }
Example: {-524288, -524284, -524280 …..+524280,
+524284}
Valid sample
1 (“copy last valid” mode:
No invalid code insertion)
Invalid
sample
Copy last valid sample
The following table shows the values in sense registers on reset:
FIFO_HOLD_LAST_DATA_EN = 0
FIFO_HOLD_LAST_DATA_EN = 1
POWER ON RESET
Accel /Temperature Sensor = -32768
TILL FIRST SAMPLE
Accel/Temperature Sensor = 0
The following table shows the values in sense registers after first sample is received. As shown in table, the
combination of FIFO_HOLD_LAST_DATA_EN and FSYNC Tag determine the range of values read for valid samples
and invalid samples.
Page 54 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
FSYNC ENABLED ON ONE SENSOR
FSYNC TAG
DISABLED
OTHER SENSOR NOT
SELECTED FOR FSYNC
TAGGING
FIFO_HOLD_LAST_DATA_EN
SENSOR SELECTED FOR FSYNC TAG
FSYNC TAGGED
FSYNC NOT
TAGGED
0 (Insert Invalid
code)
All values in:
{-32766 to
+32767}
All ODD values in:
All EVEN values
All values in:
{-32766 to +32767}
Valid
sample
{-32765 to +32767} in:
{-32766 to
+32766}
Invalid
sample
Valid
Registers do not receive invalid samples. Registers hold last valid sample until new one
arrives
1 (“copy last
valid” mode: No
invalid code
insertion)
All values in:
{-32768 to
+32767}
All ODD values in:
{-32767 to +32767} in:
{-32768 to
+32766}
All EVEN values
sample
All values in:
{-32768 to +32767}
Invalid
sample
Registers do not receive invalid samples. Registers hold last valid sample until new one
arrives
Page 55 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
13 REGISTER MAP
This section lists the register map for the IIM-42351, for user banks 0, 1, 2, 4.
13.1 USER BANK 0 REGISTER MAP
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SOFT_RESET_
CONFIG
11
13
14
17
19
20
DEVICE_CONFIG
DRIVE_CONFIG
INT_CONFIG
R/W
R/W
R/W
-
SPI_MODE
-
-
I2C_SLEW_RATE
SPI_SLEW_RATE
INT2_DRIVE_
CIRCUIT
INT2_POLARI
TY
INT1_DRIVE_
CIRCUIT
INT1_POLARI
TY
-
INT2_MODE
INT1_MODE
16
1D
1E
1F
20
21
22
23
24
2B
2C
22
29
30
31
32
33
34
35
36
43
44
FIFO_CONFIG
TEMP_DATA1
R/W
FIFO_MODE
-
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
TEMP_DATA[15:8]
TEMP_DATA0
TEMP_DATA[7:0]
ACCEL_DATA_X[15:8]
ACCEL_DATA_X[7:0]
ACCEL_DATA_Y[15:8]
ACCEL_DATA_Y[7:0]
ACCEL_DATA_Z[15:8]
ACCEL_DATA_Z[7:0]
TMST_FSYNC_DATA[15:8]
TMST_FSYNC_DATA[7:0]
ACCEL_DATA_X1
ACCEL_DATA_X0
ACCEL_DATA_Y1
ACCEL_DATA_Y0
ACCEL_DATA_Z1
ACCEL_DATA_Z0
TMST_FSYNCH
TMST_FSYNCL
UI_FSYNC_IN
T
RESET_DONE
_INT
DATA_RDY_I
NT
FIFO_THS_IN
FIFO_FULL_I
NT
AGC_RDY_IN
T
2D
45
INT_STATUS
R/C
-
-
T
2E
2F
30
31
32
33
34
35
36
37
46
47
48
49
50
51
52
53
54
55
FIFO_COUNTH
FIFO_COUNTL
FIFO_DATA
R
FIFO_COUNT[15:8]
R
FIFO_COUNT[7:0]
FIFO_DATA
R
APEX_DATA0
APEX_DATA1
APEX_DATA2
APEX_DATA3
APEX_DATA4
APEX_DATA5
INT_STATUS2
SYNCR
STEP_CNT[7:0] / FF_DUR[7:0]
STEP_CNT[15:8] / FF_DUR[15:8]
STEP_CADENCE
SYNCR
R
R
-
DMP_IDLE
ACTIVITY_CLASS
R
-
TAP_NUM
TAP_AXIS
TAP_DIR
R
-
-
DOUBLE_TAP_TIMING
R/C
-
SMD_INT
WOM_Z_INT
-
WOM_Y_INT
FF_DET_INT
WOM_X_INT
TAP_DET_INT
STEP_DET_IN
T
STEP_CNT_O
VF_INT
TILT_DET_IN
T
38
4B
56
75
INT_STATUS3
R/C
DMP_INIT_E
N
DMP_MEM_
RESET_EN
ABORT_AND
_RESET
TMST_STROB
E
SIGNAL_PATH_RESET
W/C
-
-
FIFO_FLUSH
-
FIFO_HOLD_L
AST_DATA_E
N
FIFO_COUNT
_REC
FIFO_COUNT
_ENDIAN
SENSOR_DAT
A_ENDIAN
4C
4D
76
77
INTF_CONFIG0
INTF_CONFIG1
R/W
R/W
-
UI_SIFS_CFG
ACCEL_LP_CL
K_SEL
-
RTC_MODE
CLKSEL
4E
50
51
52
53
78
80
81
82
83
PWR_MGMT0
ACCEL_CONFIG0
R/W
R/W
R/W
R/W
R/W
-
TEMP_DIS
IDLE
-
-
ACCEL_MODE
ACCEL_FS_SEL
TEMP_FILT_BW
-
-
ACCEL_ODR
TEMP_FILT_CONFIG
ACCEL_FILT_CONFIG
ACCEL_CONFIG1
-
ACCEL_UI_FILT_BW
-
-
ACCEL_UI_FILT_ORD
ACCEL_DEC2_M2_ORD
-
TMST_TO_RE
GS_EN
TMST_DELTA
_EN
TMST_FSYNC
_EN
54
56
57
84
86
87
TMST_CONFIG
APEX_CONFIG0
SMD_CONFIG
R/W
R/W
R/W
-
TMST_RES
-
TMST_EN
DMP_POWE
R_SAVE
TAP_ENABLE
PED_ENABLE
TILT_ENABLE
FF_ENABLE
DMP_ODR
WOM_INT_
MODE
-
WOM_MODE
SMD_MODE
FIFO_RESUM
E_PARTIAL_R
D
FIFO_WM_G
T_TH
FIFO_HIRES_
FIFO_TMST_F
SYNC_EN
FIFO_TEMP_
EN
5F
95
FIFO_CONFIG1
R/W
-
FIFO_PACKET_EN
EN
Page 56 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
60
61
96
97
FIFO_CONFIG2
FIFO_CONFIG3
R/W
R/W
FIFO_WM[7:0]
-
FIFO_WM[11:8]
FSYNC_UI_FL
AG_CLEAR_S
EL
FSYNC_POLA
RITY
62
98
FSYNC_CONFIG
R/W
-
FSYNC_UI_SEL
-
63
64
99
INT_CONFIG0
INT_CONFIG1
R/W
R/W
-
UI_DRDY_INT_CLEAR
INT_TDEASSE INT_ASYNC_
FIFO_THS_INT_CLEAR
FIFO_FULL_INT_CLEAR
INT_TPULSE_
DURATION
100
-
-
-
RT_DISABLE
RESET
UI_FSYNC_IN
T1_EN
RESET_DONE
_INT1_EN
UI_DRDY_INT
1_EN
FIFO_THS_IN
T1_EN
FIFO_FULL_I
NT1_EN
UI_AGC_RDY
_INT1_EN
65
66
68
69
101
102
104
105
INT_SOURCE0
INT_SOURCE1
INT_SOURCE3
INT_SOURCE4
R/W
R/W
R/W
R/W
I3C_PROTOC
OL_ERROR_I
NT1_EN
SMD_INT1_E
N
WOM_Z_INT
1_EN
WOM_Y_INT
1_EN
WOM_X_INT
1_EN
-
-
-
-
-
UI_FSYNC_IN
T2_EN
RESET_DONE
_INT2_EN
UI_DRDY_INT
2_EN
FIFO_THS_IN
T2_EN
FIFO_FULL_I
NT2_EN
UI_AGC_RDY
_INT2_EN
I3C_PROTOC
OL_ERROR_I
NT2_EN
SMD_INT2_E
N
WOM_Z_INT
2_EN
WOM_Y_INT
2_EN
WOM_X_INT
2_EN
6C
6D
108
109
FIFO_LOST_PKT0
FIFO_LOST_PKT1
R
R
FIFO_LOST_PKT_CNT[15:8]
FIFO_LOST_PKT_CNT[7:0]
ACCEL_ST_P
OWER
70
112
SELF_TEST_CONFIG
R/W
EN_AZ_ST
-
EN_AY_ST
EN_AX_ST
-
-
-
75
76
117
118
WHO_AM_I
R
WHOAMI
REG_BANK_SEL
R/W
BANK_SEL
13.2 USER BANK 1 REGISTER MAP
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
03
62
63
64
03
98
SENSOR_CONFIG0
TMSTVAL0
R/W
R
-
ZA_DISABLE
YA_DISABLE
XA_DISABLE
TMST_VALUE[7:0]
99
TMSTVAL1
R
TMST_VALUE[15:8]
100
TMSTVAL2
R
-
TMST_VALUE[19:16]
SPI_AP_4WIR
I3C_BUS_MO
DE
7A
7B
7C
122
123
124
INTF_CONFIG4
INTF_CONFIG5
INTF_CONFIG6
R/W
R/W
R/W
-
-
-
E
-
PIN9_FUNCTION
-
I3C_IBI_BYTE
-
I3C_EN
I3C_IBI_EN
I3C_DDR_EN
I3C_SDR_EN
_EN
13.3 USER BANK 2 REGISTER MAP
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ACCEL_AAF_
DIS
03
03
ACCEL_CONFIG_STATIC2
R/W
-
ACCEL_AAF_DELT
04
05
3B
3C
3D
04
05
59
60
61
ACCEL_CONFIG_STATIC3
ACCEL_CONFIG_STATIC4
XA_ST_DATA
R/W
R/W
R/W
R/W
R/W
ACCEL_AAF_DELTSQR[7:0]
ACCEL_AAF_BITSHIFT
ACCEL_AAF_DELTSQR[11:8]
XA_ST_DATA
YA_ST_DATA
ZA_ST_DATA
YA_ST_DATA
ZA_ST_DATA
13.4 USER BANK 3 REGISTER MAP
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
PU_PD_CONFIG1
PU_PD_CONFIG2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN11_PU_E
N
PIN10_PU_E
N
06
0E
06
14
R/W
R/W
PIN7_PU_EN
PIN1_PD_EN
-
PIN9_PD_EN
PIN3_PU_EN
PIN2_PU_EN
PIN4_PD_EN
PIN12_PU_E
N
PIN12_PD_E
N
PIN14_PU_E
N
PIN14_PD_E
N
PIN13_PU_E
N
PIN13_PD_E
N
PIN1_PU_EN
Page 57 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
13.5 USER BANK 4 REGISTER MAP
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
09
40
41
42
43
44
45
46
47
09
64
65
66
67
68
69
70
71
FDR_CONFIG
APEX_CONFIG1
APEX_CONFIG2
APEX_CONFIG3
APEX_CONFIG4
APEX_CONFIG5
APEX_CONFIG6
APEX_CONFIG7
APEX_CONFIG8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FDR_SEL
LOW_ENERGY_AMP_TH_SEL
PED_AMP_TH_SEL
DMP_POWER_SAVE_TIME_SEL
PED_STEP_CNT_TH_SEL
PED_STEP_DET_TH_SEL
TILT_WAIT_TIME_SEL
PED_SB_TIMER_TH_SEL
PED_HI_EN_TH_SEL
HIGHG_PEAK_TH_HYST_SEL
LOWG_PEAK_TH_HYST_SEL
LOWG_PEAK_TH_SEL
HIGHG_PEAK_TH_SEL
TAP_MIN_JERK_THR
LOWG_TIME_TH_SEL
HIGHG_TIME_TH_SEL
TAP_MAX_PEAK_TOL
TAP_TMIN
-
TAP_TMAX
TAP_TAVG
SENSITIVITY_
MODE
48
72
APEX_CONFIG9
R/W
-
49
4A
4B
4C
73
74
75
76
APEX_CONFIG10
ACCEL_WOM_X_THR
ACCEL_WOM_Y_THR
ACCEL_WOM_Z_THR
R/W
R/W
R/W
R/W
FF_MIN_DURATION_CM
FF_MAX_DURATION_CM
WOM_X_TH
FF_DEBOUNCE_DURATION
WOM_Y_TH
WOM_Z_TH
STEP_DET_IN
T1_EN
STEP_CNT_O
FL_INT1_EN
TILT_DET_IN
T1_EN
FREEFALL_DE
T_INT1_EN
TAP_DET_INT
1_EN
4D
4E
4F
77
78
79
INT_SOURCE6
INT_SOURCE7
INT_SOURCE8
R/W
R/W
R/W
-
-
-
-
-
STEP_DET_IN
T2_EN
STEP_CNT_O
FL_INT2_EN
TILT_DET_IN
T2_EN
FREEFALL_DE
T_INT2_EN
TAP_DET_INT
2_EN
FSYNC_IBI_E
N
UI_DRDY_IBI
_EN
FIFO_THS_IBI
FIFO_FULL_IB
I_EN
AGC_RDY_IBI
_EN
_EN
I3C_PROTOC
OL_ERROR_I
BI_EN
WOM_Z_IBI_
EN
WOM_Y_IBI_
EN
WOM_X_IBI_
EN
50
51
80
81
INT_SOURCE9
INT_SOURCE10
R/W
R/W
-
SMD_IBI_EN
-
STEP_DET_IB
I_EN
STEP_CNT_O
FL_IBI_EN
TILT_DET_IBI
_EN
FREEFALL_DE
T_IBI_EN
TAP_DET_IBI
_EN
-
-
7B
7C
7D
7E
7F
123
124
125
126
127
OFFSET_USER4
OFFSET_USER5
OFFSET_USER6
OFFSET_USER7
OFFSET_USER8
R/W
R/W
R/W
R/W
R/W
ACCEL_X_OFFUSER[11:8]
Reserved
ACCEL_X_OFFUSER[7:0]
ACCEL_Y_OFFUSER[7:0]
ACCEL_Z_OFFUSER[11:8]
ACCEL_Y_OFFUSER[11:8]
ACCEL_Z_OFFUSER[7:0]
Detailed register descriptions are provided in the sections that follow. Please note the following regarding Clock
Domain for each register:
•
Clock Domain: SCLK_UI means that the register is controlled from the UI interface
Register fields marked as Reserved must not be modified by the user. The Reset Value of the register can be used
to determine the default value of reserved register fields, and unless otherwise noted this default value must be
maintained even if the values of other register fields are modified by the user.
13.6 REGISTER VALUES MODIFICATION
The only register settings that user can modify during sensor operation are for ODR selection, FSR selection, and
sensor mode changes (register parameters ACCEL_ODR, ACCEL_FS_SEL, ACCEL_MODE). User must not modify any
other register values during sensor operation. The following procedure must be used for other register values
modification.
•
•
•
Turn Accel Off
Modify register values
Turn Accel On
Page 58 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14 USER BANK 0 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 0.
Note: The device powers up in sleep mode.
14.1 DEVICE_CONFIG
Name: DEVICE_CONFIG
Address: 17 (11h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
7:5
4
NAME
-
SPI_MODE
FUNCTION
Reserved
SPI mode selection
0: Mode 0 and Mode 3 (default)
1: Mode 1 and Mode 2
Reserved
Software reset configuration
0: Normal (default)
1: Enable reset
3:1
0
-
SOFT_RESET_CONFIG
After writing 1 to this bitfield, wait 1ms for soft reset to be effective, before
attempting any other register access
14.2 DRIVE_CONFIG
Name: DRIVE_CONFIG
Address: 19 (13h)
Serial IF: R/W
Reset value: 0x05
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:6
-
Reserved
Controls slew rate for output pin 14 in I2C mode only
000: 20ns-60ns
001: 12ns-36ns
010: 6ns-18ns
011: 4ns-12ns
5:3
I2C_SLEW_RATE
100: 2ns-6ns
101: < 2ns
110: Reserved
111: Reserved
Controls slew rate for output pin 14 in SPI or I3CSM mode, and for all other output
pins
000: 20ns-60ns
001: 12ns-36ns
010: 6ns-18ns
011: 4ns-12ns
100: 2ns-6ns
101: < 2ns
2:0
SPI_SLEW_RATE
110: Reserved
111: Reserved
Page 59 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.3 INT_CONFIG
Name: INT_CONFIG
Address: 20 (14h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:6
-
Reserved
INT2 interrupt mode
0: Pulsed mode
1: Latched mode
INT2 drive circuit
0: Open drain
5
4
3
2
1
0
INT2_MODE
INT2_DRIVE_CIRCUIT
INT2_POLARITY
INT1_MODE
1: Push pull
INT2 interrupt polarity
0: Active low (default)
1: Active high
INT1 interrupt mode
0: Pulsed mode
1: Latched mode
INT1 drive circuit
0: Open drain
INT1_DRIVE_CIRCUIT
INT1_POLARITY
1: Push pull
INT1 interrupt polarity
0: Active low (default)
1: Active high
14.4 FIFO_CONFIG
Name: FIFO_CONFIG
Address: 22 (16h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:6
FIFO_MODE
00: Bypass Mode (default)
01: Stream-to-FIFO Mode
10: STOP-on-FULL Mode
11: STOP-on-FULL Mode
Reserved
5:0
-
14.5 TEMP_DATA1
Name: TEMP_DATA1
Address: 29 (1Dh)
Serial IF: SYNCR
Reset value: 0x80
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
TEMP_DATA[15:8]
Upper byte of temperature data
Page 60 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.6 TEMP_DATA0
Name: TEMP_DATA0
Address: 30 (1Eh)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
TEMP_DATA[7:0]
Lower byte of temperature data
Temperature data value from the sensor data registers can be converted to degrees centigrade by using the
following formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25
FIFO_TEMP_DATA, temperature data stored in FIFO, can be 8-bit or 16-it quantity. The 8-bit of temperature data
stored in FIFO is limited to -40C to 85C range, while the 16-bit representation can support the full operating
temperature range. It can be converted to degrees centigrade by using the following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25
14.7 ACCEL_DATA_X1
Name: ACCEL_DATA_X1
Address: 31 (1Fh)
Serial IF: SYNCR
Reset value: 0x80
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
ACCEL_DATA_X[15:8]
Upper byte of Accel X-axis data
14.8 ACCEL_DATA_X0
Name: ACCEL_DATA_X0
Address: 32 (20h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
ACCEL_DATA_X[7:0]
Lower byte of Accel X-axis data
14.9 ACCEL_DATA_Y1
Name: ACCEL_DATA_Y1
Address: 33 (21h)
Serial IF: SYNCR
Reset value: 0x80
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
ACCEL_DATA_Y[15:8]
Upper byte of Accel Y-axis data
14.10ACCEL_DATA_Y0
Name: ACCEL_DATA_Y0
Address: 34 (22h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
ACCEL_DATA_Y[7:0]
Lower byte of Accel Y-axis data
Page 61 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.11ACCEL_DATA_Z1
Name: ACCEL_DATA_Z1
Address: 35 (23h)
Serial IF: SYNCR
Reset value: 0x80
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
ACCEL_DATA_Z[15:8]
Upper byte of Accel Z-axis data
14.12ACCEL_DATA_Z0
Name: ACCEL_DATA_Z0
Address: 36 (24h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
ACCEL_DATA_Z[7:0]
Lower byte of Accel Z-axis data
14.13TMST_FSYNCH
Name: TMST_FSYNCH
Address: 43 (2Bh)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Stores the upper byte of the time delta from the rising edge of FSYNC to the latest
ODR until the UI Interface reads the FSYNC tag in the status register
7:0
TMST_FSYNC_DATA[15:8]
14.14TMST_FSYNCL
Name: TMST_FSYNCL
Address: 44 (2Ch)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Stores the lower byte of the time delta from the rising edge of FSYNC to the latest
ODR until the UI Interface reads the FSYNC tag in the status register
7:0
TMST_FSYNC_DATA[7:0]
Page 62 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.15INT_STATUS
Name: INT_STATUS
Address: 45 (2Dh)
Serial IF: R/C
Reset value: 0x10
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
This bit automatically sets to 1 when a UI FSYNC interrupt is generated. The bit clears
to 0 after the register has been read.
Reserved
This bit automatically sets to 1 when software reset is complete. The bit clears to 0
after the register has been read.
6
5
4
UI_FSYNC_INT
-
RESET_DONE_INT
This bit automatically sets to 1 when a Data Ready interrupt is generated. The bit
clears to 0 after the register has been read.
This bit automatically sets to 1 when the FIFO buffer reaches the threshold value. The
bit clears to 0 after the register has been read.
This bit automatically sets to 1 when the FIFO buffer is full. The bit clears to 0 after
the register has been read.
This bit automatically sets to 1 when an AGC Ready interrupt is generated. The bit
clears to 0 after the register has been read.
3
2
1
0
DATA_RDY_INT
FIFO_THS_INT
FIFO_FULL_INT
AGC_RDY_INT
14.16FIFO_COUNTH
Name: FIFO_COUNTH
Address: 46 (2Eh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
High Bits, count indicates the number of records or bytes available in FIFO according
to FIFO_COUNT_REC setting.
Note: Must read FIFO_COUNTL to latch new data for both FIFO_COUNTH and
FIFO_COUNTL.
7:0
FIFO_COUNT[15:8]
14.17FIFO_COUNTL
Name: FIFO_COUNTL
Address: 47 (2Fh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Low Bits, count indicates the number of records or bytes available in FIFO according
to FIFO_COUNT_REC setting.
7:0
FIFO_COUNT[7:0]
Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL.
14.18FIFO_DATA
Name: FIFO_DATA
Address: 48 (30h)
Serial IF: R
Reset value: 0xFF
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
FIFO_DATA
FIFO data port
Page 63 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.19APEX_DATA0
Name: APEX_DATA0
Address: 49 (31h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
STEP_CNT[7:0]
Pedometer Output: Lower byte of Step Count measured by pedometer
14.20APEX_DATA1
Name: APEX_DATA1
Address: 50 (32h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
STEP_CNT[15:8]
Pedometer Output: Upper byte of Step Count measured by pedometer
14.21APEX_DATA2
Name: APEX_DATA2
Address: 51 (33h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Pedometer Output: Walk/run cadence in number of samples. Format is u6.2. e.g. At
50Hz ODR and 2Hz walk frequency, the cadence is 25 samples. The register will
output 100.
7:0
STEP_CADENCE
14.22APEX_DATA3
Name: APEX_DATA3
Address: 52 (34h)
Serial IF: R
Reset value: 0x04
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:3
-
Reserved
0: Indicates DMP is running
1: Indicates DMP is idle
Pedometer Output: Detected activity
00: Unknown
2
DMP_IDLE
1:0
ACTIVITY_CLASS
01: Walk
10: Run
11: Reserved
Page 64 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.23APEX_DATA4
Name: APEX_DATA4
Address: 53 (35h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:5
-
Reserved
Tap Detection Output: Number of taps in the current Tap event
00: No tap
4:3
TAP_NUM
01: Single tap
10: Double tap
11: Reserved
Tap Detection Output: Represents the accelerometer axis on which tap energy is
concentrated
00: X-axis
01: Y-axis
10: Z-axis
11: Reserved
2:1
0
TAP_AXIS
TAP_DIR
Tap Detection Output: Polarity of tap pulse
0: Current accelerometer value – Previous accelerometer value is a positive value
1: Current accelerometer value – Previous accelerometer value is a negative value or
zero
14.24APEX_DATA5
Name: APEX_DATA5
Address: 54 (36h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:6
-
Reserved
DOUBLE_TAP_TIMING measures the time interval between the two taps when
double tap is detected. It counts every 16 accelerometer samples as one unit
between the 2 tap pulses. Therefore, the value is related to the accelerometer
ODR.
5:0
DOUBLE_TAP_TIMING
Time in seconds = DOUBLE_TAP_TIMING * 16 / ODR
For example, if the accelerometer ODR is 500 Hz, and the DOUBLE_TAP_TIMING
register reading is 6, the time interval value is 6*16/500 = 0.192 seconds.
14.25INT_STATUS2
Name: INT_STATUS2
Address: 55 (37h)
Serial IF: R/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
7:4
3
2
1
NAME
-
SMD_INT
WOM_Z_INT
WOM_Y_INT
WOM_X_INT
FUNCTION
Reserved
Significant Motion Detection Interrupt, clears on read
Wake on Motion Interrupt on Z-axis, clears on read
Wake on Motion Interrupt on Y-axis, clears on read
Wake on Motion Interrupt on X-axis, clears on read
0
Page 65 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.26INT_STATUS3
Name: INT_STATUS3
Address: 56 (38h)
Serial IF: R/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
7:6
5
4
3
NAME
-
STEP_DET_INT
STEP_CNT_OVF_INT
TILT_DET_INT
-
FUNCTION
Reserved
Step Detection Interrupt, clears on read
Step Count Overflow Interrupt, clears on read
Tilt Detection Interrupt, clears on read
Reserved
2
1
0
FF_DET_INT
TAP_DET_INT
Freefall Interrupt, clears on read
Tap Detection Interrupt, clears on read
14.27SIGNAL_PATH_RESET
Name: SIGNAL_PATH_RESET
Address: 75 (4Bh)
Serial IF: W/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
7
NAME
-
FUNCTION
Reserved
6
5
4
DMP_INIT_EN
DMP_MEM_RESET_EN
-
When this bit is set to 1, the DMP is enabled
When this bit is set to 1, the DMP memory is reset
Reserved
When this bit is set to 1, the signal path is reset by restarting the ODR counter and
signal path controls
When this bit is set to 1, the time stamp counter is latched into the time stamp
register. This is a write on clear bit.
3
2
ABORT_AND_RESET
TMST_STROBE
1
0
FIFO_FLUSH
-
When set to 1, FIFO will get flushed.
Reserved
14.28INTF_CONFIG0
Name: INTF_CONFIG0
Address: 76 (4Ch)
Serial IF: R/W
Reset value: 0x30
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Setting 0 corresponds to the following:
Sense Registers from Power on Reset till first sample:
•
Invalid Samples Value: -32768
Sense Registers after first sample received:
Sense Registers Valid Sample Values:
7
FIFO_HOLD_LAST_DATA_EN
•
o
o
o
Range limited from -32766 to +32767 when FSYNC tag is disabled,
or for sensor not selected for FSYNC tag
Range limited from -32765 to +32767 (odd values) for sensor
selected for FSYNC tag, and FSYNC is tagged
Range limited from -32766 to +32766 (even values) for sensor
selected for FSYNC tag, but FSYNC is not tagged
Page 66 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
•
Sense Registers Invalid Sample Values:
o
-32768 when FSYNC tag is disabled, or for sensor not selected for
FSYNC tag, or for sensor selected for FSYNC tag but FSYNC is not
tagged
o
-32767 for sensor selected for FSYNC tag, and FSYNC is tagged
FIFO:
•
•
Invalid Sample Value: -32768
Valid Sample Values: -32766 to +32767
Setting 1 corresponds to the following:
Sense Registers from Power on Reset till first sample:
•
Invalid Samples Value: 0
Sense Registers after first sample received:
•
Sense Registers Valid Sample Values:
o
o
o
Range limited from -32768 to +32767 when FSYNC tag is disabled,
or for sensor not selected for FSYNC tag
Range limited from -32767 to +32767 (odd values) for sensor
selected for FSYNC tag, and FSYNC is tagged
Range limited from -32768 to +32766 (even values) for sensor
selected for FSYNC tag, but FSYNC is not tagged
•
Sense Registers Invalid Sample Values:
o
Registers hold last valid sample until new one arrives
FIFO:
•
•
Invalid Sample Value: Copy last valid sample
Valid Sample Values: -32768 to +32767
0: FIFO count is reported in bytes
6
5
FIFO_COUNT_REC
1: FIFO count is reported in records (1 record = 16 bytes for header + accel + temp
sensor data + time stamp, or 8 bytes for header + accel + temp sensor data)
0: FIFO count is reported in Little Endian format
1: FIFO count is reported in Big Endian format (default)
0: Sensor data is reported in Little Endian format
1: Sensor data is reported in Big Endian format (default)
Reserved
FIFO_COUNT_ENDIAN
4
SENSOR_DATA_ENDIAN
-
3:2
0x: Reserved
10: Disable SPI
1:0
UI_SIFS_CFG
11: Disable I2C
Invalid Data Generation: FIFO/Sense Registers may contain invalid data under the following conditions:
a) From power on reset to first ODR sample of any sensor (accel, temp sensor)
b) When any sensor is disabled (accel, temp sensor)
c) When accel is enabled with different ODRs. In this case, the sensor with lower ODR will generate invalid
samples when it has no new data.
Invalid data can take special values or can hold last valid sample received. For -32768 to be used as a flag for
invalid accel samples, the valid accel sample range is limited in such case as well. Bit 7 of INTF_CONFIG0 controls
what values invalid (and valid) samples can take as shown above.
Page 67 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.29INTF_CONFIG1
Name: INTF_CONFIG1
Address: 77 (4Dh)
Serial IF: R/W
Reset value: 0x90
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:4
-
Reserved
0: Accelerometer LP mode uses Wake Up oscillator clock
1: Accelerometer LP mode uses RC oscillator clock
0: No input RTC clock is required
1: RTC clock input is required
00: Always select internal RC oscillator
01: Reserved
3
2
ACCEL_LP_CLK_SEL
RTC_MODE
1:0
CLKSEL
10: Reserved
11: Disable all clocks
14.30PWR_MGMT0
Name: PWR_MGMT0
Address: 78 (4Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:6
-
Reserved
0: Temperature sensor is enabled (default)
1: Temperature sensor is disabled
5
TEMP_DIS
If this bit is set to 1, the RC oscillator is powered on even if Accel is powered off.
Nominally this bit is set to 0, so when Accel is powered off,
the chip will go to OFF state, since the RC oscillator will also be powered off
00: default
4
IDLE
3:2
Reserved
00: Turns accelerometer off (default)
01: Turns accelerometer off
10: Places accelerometer in Low Power (LP) Mode
1:0
ACCEL_MODE
11: Places accelerometer in Low Noise (LN) Mode
When transitioning from OFF to any of the other modes, do not issue any register
writes for 200µs.
Page 68 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.31ACCEL_CONFIG0
Name: ACCEL_CONFIG0
Address: 80 (50h)
Serial IF: R/W
Reset value: 0x03
Clock Domain: SCLK_UI
BIT
7:5
4
NAME
FUNCTION
Full scale select for accelerometer UI interface output
000: ±16g (default)
001: ±8g
010: ±4g
011: ±2g
100: Reserved
101: Reserved
110: Reserved
111: Reserved
ACCEL_FS_SEL
Reserved
Reserved
Accelerometer ODR selection for UI interface output
0000: Reserved
0001: Reserved
0010: Reserved
0011: 8kHz (LN mode)
0100: 4kHz (LN mode)
0101: 2kHz (LN mode)
0110: 1kHz (LN mode) (default)
0111: 200Hz (LP or LN mode)
1000: 100Hz (LP or LN mode)
1001: 50Hz (LP or LN mode)
1010: 25Hz (LP or LN mode)
1011: 12.5Hz (LP or LN mode)
1100: 6.25Hz (LP mode)
1101: 3.125Hz (LP mode)
1110: 1.5625Hz (LP mode)
1111: 500Hz (LP or LN mode)
3:0
ACCEL_ODR
14.32 TEMP_FILT_CONFIG
Name: TEMP_FILT_CONFIG
Address: 81 (51h)
Serial IF: R/W
Reset value: 0x16
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Sets the bandwidth of the temperature signal DLPF
000: DLPF BW = 4000Hz; DLPF Latency = 0.125ms (default)
001: DLPF BW = 170Hz; DLPF Latency = 1ms
010: DLPF BW = 82Hz; DLPF Latency = 2ms
011: DLPF BW = 40Hz; DLPF Latency = 4ms
100: DLPF BW = 20Hz; DLPF Latency = 8ms
101: DLPF BW = 10Hz; DLPF Latency = 16ms
110: DLPF BW = 5Hz; DLPF Latency = 32ms
111: DLPF BW = 5Hz; DLPF Latency = 32ms
Reserved
7:5
TEMP_FILT_BW
4
3:2
1:0
-
-
-
Reserved
Reserved
Page 69 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.33 ACCEL_FILT_CONFIG
Name: ACCEL_FILT_CONFIG
Address: 82 (52h)
Serial IF: R/W
Reset value: 0x11
Clock Domain: SCLK_UI
BIT
7:4
3:0
NAME
FUNCTION
LN Mode:
Bandwidth for Accel LPF
0 BW=ODR/2
1 BW=max(400Hz, ODR)/4 (default)
2 BW=max(400Hz, ODR)/5
3 BW=max(400Hz, ODR)/8
4 BW=max(400Hz, ODR)/10
5 BW=max(400Hz, ODR)/16
6 BW=max(400Hz, ODR)/20
7 BW=max(400Hz, ODR)/40
8 to 13: Reserved
ACCEL_UI_FILT_BW
14 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2 runs at
max(400Hz, ODR)
15 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2 runs at
max(200Hz, 8*ODR)
LP Mode:
0 Reserved
1 1x AVG filter (default)
2 to 5 Reserved
6 16x AVG filter
7 to 15 Reserved
Reserved
-
14.34ACCEL_CONFIG1
Name: ACCEL_CONFIG1
Address: 83 (53h)
Serial IF: R/W
Reset value: 0x0D
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:5
-
Reserved
Selects order of ACCEL UI filter
00: 1st Order
4:3
ACCEL_UI_FILT_ORD
01: 2nd Order
10: 3rd Order
11: Reserved
Order of Accelerometer DEC2_M2 filter
00: Reserved
2:1
0
ACCEL_DEC2_M2_ORD
-
01: Reserved
10: 3rd order
11: Reserved
Reserved
Page 70 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.35TMST_CONFIG
Name: TMST_CONFIG
Address: 84 (54h)
Serial IF: R/W
Reset value: 0x23
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:5
-
Reserved
0: TMST_VALUE[19:0] read always returns 0s
1: TMST_VALUE[19:0] read returns timestamp value
Time Stamp resolution: When set to 0 (default), time stamp resolution is 1 µs. When
set to 1, resolution is 16µs
Time Stamp delta enable: When set to 1, the time stamp field contains the
measurement of time since the last occurrence of ODR.
Time Stamp register FSYNC enable (default). When set to 1, the contents of the
Timestamp feature of FSYNC is enabled. The user also needs to select
FIFO_TMST_FSYNC_EN in order to propagate the timestamp value to the FIFO.
0: Time Stamp register disable
4
3
2
TMST_TO_REGS_EN
TMST_RES
TMST_DELTA_EN
1
0
TMST_FSYNC_EN
TMST_EN
1: Time Stamp register enable (default)
14.36APEX_CONFIG0
Name: APEX_CONFIG0
Address: 86 (56h)
Serial IF: R/W
Reset value: 0x82
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
0: DMP power save mode not active
1: DMP power save mode active (default)
7
DMP_POWER_SAVE
0: Tap Detection not enabled
1: Tap Detection enabled when accelerometer ODR is set to one of the ODR values
6
5
TAP_ENABLE
PED_ENABLE
supported by Tap Detection (200 Hz, 500 Hz, 1 kHz)
0: Pedometer not enabled
1: Pedometer enabled
0: Tilt Detection not enabled
1: Tilt Detection enabled
Reserved
0: Freefall Detection not enabled
1: Freefall Detection enabled
00: 25Hz
4
3
2
TILT_ENABLE
-
FF_ENABLE
01: 500Hz
10: 50Hz
1:0
DMP_ODR
11: 100Hz
Page 71 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.37SMD_CONFIG
Name: SMD_CONFIG
Address: 87 (57h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:4
-
Reserved
0: Set WoM interrupt on the OR of all enabled accelerometer thresholds
1: Set WoM interrupt on the AND of all enabled accelerometer threshold
0: Initial sample is stored. Future samples are compared to initial sample
1: Compare current sample to previous sample
00: SMD disabled
3
2
WOM_INT_MODE
WOM_MODE
01: WOM mode
10: SMD short (1 sec wait) An SMD event is detected when two WOM are detected 1
sec apart
1:0
SMD_MODE
11: SMD long (3 sec wait) An SMD event is detected when two WOM are detected 3
sec apart
14.38FIFO_CONFIG1
Name: FIFO_CONFIG1
Address: 95 (5Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
0: Partial FIFO read disabled, requires re-reading of the entire FIFO
1: FIFO read can be partial, and resume from last read point
Trigger FIFO watermark interrupt on every ODR (DMA write) if FIFO_COUNT ≥
FIFO_WM_TH
6
5
FIFO_RESUME_PARTIAL_RD
FIFO_WM_GT_TH
0: Default setting; Sensor data have regular resolution
1: Sensor data in FIFO will have extended resolution enabling the 20 Bytes
packet
Must be set to 1 for all FIFO use cases when FSYNC is used
Enable temperature sensor packets to go to FIFO
0
4
FIFO_HIRES_EN
3
2
1
0
FIFO_TMST_FSYNC_EN
FIFO_TEMP_EN
Reserved
FIFO_ACCEL_EN
Enable accelerometer packets to go to FIFO
14.39FIFO_CONFIG2
Name: FIFO_CONFIG2
Address: 96 (60h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Lower bits of FIFO watermark. Generate interrupt when the FIFO reaches or
exceeds FIFO_WM size in bytes or records according to FIFO_COUNT_REC setting.
FIFO_WM_EN must be zero before writing this register. Interrupt only fires once.
This register should be set to non-zero value, before choosing this interrupt
source.
7:0
FIFO_WM[7:0]
Page 72 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.40FIFO_CONFIG3
Name: FIFO_CONFIG3
Address: 97 (61h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:4
-
Reserved
Upper bits of FIFO watermark. Generate interrupt when the FIFO reaches or
exceeds FIFO_WM size in bytes or records according to FIFO_COUNT_REC setting.
FIFO_WM_EN must be zero before writing this register. Interrupt only fires once.
This register should be set to non-zero value, before choosing this interrupt
source.
3:0
FIFO_WM[11:8]
Note: Do not set FIFO_WM to value 0.
14.41FSYNC_CONFIG
Name: FSYNC_CONFIG
Address: 98 (62h)
Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
000: Do not tag FSYNC flag
001: Tag FSYNC flag to TEMP_OUT LSB
101: Tag FSYNC flag to ACCEL_XOUT LSB
110: Tag FSYNC flag to ACCEL_YOUT LSB
111: Tag FSYNC flag to ACCEL_ZOUT LSB
Reserved
0: FSYNC flag is cleared when UI sensor register is updated
1: FSYNC flag is cleared when UI interface reads the sensor register LSB of FSYNC
tagged axis
6:4
FSYNC_UI_SEL
3:2
1
-
FSYNC_UI_FLAG_CLEAR_SEL
0: Start from Rising edge of FSYNC pulse to measure FSYNC interval
1: Start from Falling edge of FSYNC pulse to measure FSYNC interval
0
FSYNC_POLARITY
Page 73 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.42INT_CONFIG0
Name: INT_CONFIG0
Address: 99 (63h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:6
-
Reserved
Data Ready Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
01: Clear on Status Bit Read
5:4
3:2
1:0
UI_DRDY_INT_CLEAR
FIFO_THS_INT_CLEAR
FIFO_FULL_INT_CLEAR
10: Clear on Sensor Register Read
11: Clear on Status Bit Read AND on Sensor Register read
FIFO Threshold Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
01: Clear on Status Bit Read
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read AND on FIFO data 1 byte read
FIFO Full Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
01: Clear on Status Bit Read
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read AND on FIFO data 1 byte read
14.43INT_CONFIG1
Name: INT_CONFIG1
Address: 100 (64h)
Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
Interrupt pulse duration
6
5
INT_TPULSE_DURATION
INT_TDEASSERT_DISABLE
0: Interrupt pulse duration is 100µs. Use only if ODR < 4kHz. (Default)
1: Interrupt pulse duration is 8 µs. Required if ODR ≥ 4kHz, optional for ODR < 4kHz.
Interrupt de-assertion duration
0: The interrupt de-assertion duration is set to a minimum of 100 µs. Use only if ODR
< 4kHz. (Default)
1: Disables de-assert duration. Required if ODR ≥ 4kHz, optional for ODR < 4kHz.
User should change setting to 0 from default setting of 1, for proper INT1 and INT2
pin operation
4
INT_ASYNC_RESET
-
3:0
Reserved
Page 74 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.44INT_SOURCE0
Name: INT_SOURCE0
Address: 101 (65h)
Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
0: UI FSYNC interrupt not routed to INT1
1: UI FSYNC interrupt routed to INT1
Reserved
6
5
4
UI_FSYNC_INT1_EN
-
0: Reset done interrupt not routed to INT1
1: Reset done interrupt routed to INT1
0: UI data ready interrupt not routed to INT1
1: UI data ready interrupt routed to INT1
0: FIFO threshold interrupt not routed to INT1
1: FIFO threshold interrupt routed to INT1
0: FIFO full interrupt not routed to INT1
1: FIFO full interrupt routed to INT1
0: UI AGC ready interrupt not routed to INT1
1: UI AGC ready interrupt routed to INT1
RESET_DONE_INT1_EN
3
2
1
0
UI_DRDY_INT1_EN
FIFO_THS_INT1_EN
FIFO_FULL_INT1_EN
UI_AGC_RDY_INT1_EN
14.45INT_SOURCE1
Name: INT_SOURCE1
Address: 102 (66h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
0: I3CSM protocol error interrupt not routed to INT1
1: I3CSM protocol error interrupt routed to INT1
Reserved
6
5:4
3
I3C_PROTOCOL_ERROR_INT1_EN
-
0: SMD interrupt not routed to INT1
1: SMD interrupt routed to INT1
0: Z-axis WOM interrupt not routed to INT1
1: Z-axis WOM interrupt routed to INT1
0: Y-axis WOM interrupt not routed to INT1
1: Y-axis WOM interrupt routed to INT1
0: X-axis WOM interrupt not routed to INT1
1: X-axis WOM interrupt routed to INT1
SMD_INT1_EN
2
1
0
WOM_Z_INT1_EN
WOM_Y_INT1_EN
WOM_X_INT1_EN
Page 75 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.46INT_SOURCE3
Name: INT_SOURCE3
Address: 104 (68h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
0: UI FSYNC interrupt not routed to INT2
1: UI FSYNC interrupt routed to INT2
Reserved
6
5
4
UI_FSYNC_INT2_EN
-
0: Reset done interrupt not routed to INT2
1: Reset done interrupt routed to INT2
0: UI data ready interrupt not routed to INT2
1: UI data ready interrupt routed to INT2
0: FIFO threshold interrupt not routed to INT2
1: FIFO threshold interrupt routed to INT2
0: FIFO full interrupt not routed to INT2
1: FIFO full interrupt routed to INT2
0: UI AGC ready interrupt not routed to INT2
1: UI AGC ready interrupt routed to INT2
RESET_DONE_INT2_EN
3
2
1
0
UI_DRDY_INT2_EN
FIFO_THS_INT2_EN
FIFO_FULL_INT2_EN
UI_AGC_RDY_INT2_EN
14.47INT_SOURCE4
Name: INT_SOURCE4
Address: 105 (69h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
I3C_PROTOCOL_ERROR_INT2
_EN
-
0: I3CSM protocol error interrupt not routed to INT2
1: I3CSM protocol error interrupt routed to INT2
Reserved
6
5:4
3
0: SMD interrupt not routed to INT2
1: SMD interrupt routed to INT2
0: Z-axis WOM interrupt not routed to INT2
1: Z-axis WOM interrupt routed to INT2
0: Y-axis WOM interrupt not routed to INT2
1: Y-axis WOM interrupt routed to INT2
0: X-axis WOM interrupt not routed to INT2
1: X-axis WOM interrupt routed to INT2
SMD_INT2_EN
2
1
0
WOM_Z_INT2_EN
WOM_Y_INT2_EN
WOM_X_INT2_EN
14.48FIFO_LOST_PKT0
Name: FIFO_LOST_PKT0
Address: 108 (6Ch)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
FIFO_LOST_PKT_CNT[7:0]
Low byte, number of packets lost in the FIFO
Page 76 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.49FIFO_LOST_PKT1
Name: FIFO_LOST_PKT1
Address: 109 (6Dh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
FIFO_LOST_PKT_CNT[15:8]
High byte, number of packets lost in the FIFO
14.50SELF_TEST_CONFIG
Name: SELF_TEST_CONFIG
Address: 112 (70h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
Set to 1 for accel self-test
Otherwise set to 0; Set to 0 after self-test is completed
6
ACCEL_ST_POWER
5
4
3
2
1
0
EN_AZ_ST
EN_AY_ST
EN_AX_ST
Reserved
Reserved
Reserved
Enable Z-accel self-test
Enable Y-accel self-test
Enable X-accel self-test
0
0
0
14.51WHO_AM_I
Name: WHO_AM_I
Address: 117 (75h)
Serial IF: R
Reset value: 0x6C
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
WHOAMI
Register to indicate to user which device is being accessed
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default
value of the register is 0x6C. This is different from the I2C address of the device as seen on the slave I2C controller
by the applications processor.
Page 77 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
14.52REG_BANK_SEL
Note: This register is accessible from all register banks
Name: REG_BANK_SEL
Address: 118 (76h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: ALL
BIT
NAME
FUNCTION
7:3
-
Reserved
Register bank selection
000: Bank 0 (default)
001: Bank 1
010: Bank 2
011: Bank 3
2:0
BANK_SEL
100: Bank 4
101: Reserved
110: Reserved
111: Reserved
Page 78 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
15 USER BANK 1 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 1.
15.1 SENSOR_CONFIG0
Name: SENSOR_CONFIG0
Address: 03 (03h)
Serial IF: R/W
Reset value: 0xB8
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:3
-
Reserved
0: Z accelerometer is on
1: Z accelerometer is disabled
0: Y accelerometer is on
1: Y accelerometer is disabled
0: X accelerometer is on
1: X accelerometer is disabled
2
1
0
ZA_DISABLE
YA_DISABLE
XA_DISABLE
15.2 TMSTVAL0
Name: TMSTVAL0
Address: 98 (62h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
When TMST_STROBE is programmed, the current value of the internal counter is
latched to this register. Allows the full 20-bit precision of the time stamp to be read
back.
7:0
TMST_VALUE[7:0]
15.3 TMSTVAL1
Name: TMSTVAL1
Address: 99 (63h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
When TMST_STROBE is programmed, the current value of the internal counter is
latched to this register. Allows the full 20-bit precision of the time stamp to be read
back.
7:0
TMST_VALUE[15:8]
15.4 TMSTVAL2
Name: TMSTVAL2
Address: 100 (64h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:4
-
Reserved
When TMST_STROBE is programmed, the current value of the internal counter is
latched to this register. Allows the full 20-bit precision of the time stamp to be read
back.
3:0
TMST_VALUE[19:16]
Page 79 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
15.5 INTF_CONFIG4
Name: INTF_CONFIG4
Address: 122 (7Ah)
Serial IF: R/W
Reset value: 0x03
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
0: Device is on a bus with I2C and I3CSM devices
1: Device is on a bus with I3CSM devices only
Reserved
6
5:2
1
I3C_BUS_MODE
-
0: AP interface uses 3-wire SPI mode
1: AP interface uses 4-wire SPI mode (default)
Reserved
SPI_AP_4WIRE
-
0
15.6 INTF_CONFIG5
Name: INTF_CONFIG5
Address: 123 (7Bh)
Serial IF: R/W
Reset value: 0x20
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:3
-
Reserved
Selects among the following functionalities for pin 9
00: INT2
2:1
0
PIN9_FUNCTION
-
01: FSYNC
10: CLKIN
11: Reserved
Reserved
15.7 INTF_CONFIG6
Name: INTF_CONFIG6
Address: 124 (7Ch)
Serial IF: R/W
Reset value: 0x5F
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:5
-
Reserved
0: I3CSM slave not enabled
1: I3CSM slave enabled
4
3
2
1
0
I3C_EN
0: I3CSM IBI payload function not enabled
1: I3CSM IBI payload function enabled
0: I3CSM IBI function not enabled
1: I3CSM IBI function enabled
0: I3CSM DDR mode not enabled
1: I3CSM DDR mode enabled
0: I3CSM SDR mode not enabled
1: I3CSM SDR mode enabled
I3C_IBI_BYTE_EN
I3C_IBI_EN
I3C_DDR_EN
I3C_SDR_EN
Page 80 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
16 USER BANK 2 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 2.
16.1 ACCEL_CONFIG_STATIC2
Name: ACCEL_CONFIG_STATIC2
Address: 03 (03h)
Serial IF: R/W
Reset value: 0x7E
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
0: Enable accelerometer anti-aliasing filter
1: Disable accelerometer anti-aliasing filter
6:1
0
ACCEL_AAF_DELT
ACCEL_AAF_DIS
16.2 ACCEL_CONFIG_STATIC3
Name: ACCEL_CONFIG_STATIC3
Address: 04 (04h)
Serial IF: R/W
Reset value: 0x80
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
7:0
ACCEL_AAF_DELTSQR[7:0]
16.3 ACCEL_CONFIG_STATIC4
Name: ACCEL_CONFIG_STATIC4
Address: 05 (05h)
Serial IF: R/W
Reset value: 0x3F
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
7:4
ACCEL_AAF_BITSHIFT
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
3:0
ACCEL_AAF_DELTSQR[11:8]
16.4 XA_ST_DATA
Name: XA_ST_DATA
Address: 59 (3Bh)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
XA_ST_DATA
X-accel self-test data
Page 81 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
16.5 YA_ST_DATA
Name: YA_ST_DATA
Address: 60 (3Ch)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
YA_ST_DATA
Y-accel self-test data
16.6 ZA_ST_DATA
Name: ZA_ST_DATA
Address: 61 (3Dh)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:0
ZA_ST_DATA
Z-accel self-test data
Page 82 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
17 USER BANK 3 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 3.
17.1 PU_PD_CONFIG1
Name: PU_PD_CONFIG1
Address: 06 (06h)
Serial IF: R/W
Reset value: 0x88
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Pull-up control for pin 11
0: Pull-up is disabled
1: Pull-up is enabled
7
PIN11_PU_EN
Pull-up control for pin 7 if triple interface mode is used. Must be set to 0 if
single/dual interface mode is used.
0: Pull-up is disabled
1: Pull-up is enabled
Reserved
Pull-down control for pin 9 in single/dual interface mode. Must be set to 0 if triple
interface mode is used.
0: Pull-down is disabled
6
5
4
PIN7_PU_EN
-
PIN9_PD_EN
1: Pull-down is enabled
Pull-up control for pin 10
0: Pull-up is disabled
1: Pull-up is enabled
Pull-up control for pin 3
0: Pull-up is disabled
1: Pull-up is enabled
Pull-up control for pin 2
0: Pull-up is disabled
3
2
1
0
PIN10_PU_EN
PIN3_PU_EN
PIN2_PU_EN
PIN4_PD_EN
1: Pull-up is enabled
Pull-down control for pin 4
0: Pull-down is disabled
1: Pull-down is enabled
Page 83 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
17.2 PU_PD_CONFIG2
Name: PU_PD_CONFIG2
Address: 14 (0Eh)
Serial IF: R/W
Reset value: 0x20
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Pull-up control for pin 1. See bit 6 description for pull-down control for pin 1. Note
that both pull-up and pull-down must not be simultaneously enabled for the same
pin.
7
PIN1_PU_EN
0: Pull-up is disabled
1: Pull-up is enabled
Pull-down control for pin 1. See bit 7 description for pull-up control for pin 1. Note
that both pull-up and pull-down must not be simultaneously enabled for the same
6
5
4
3
2
1
0
PIN1_PD_EN
PIN12_PU_EN
PIN12_PD_EN
PIN14_PU_EN
PIN14_PD_EN
PIN13_PU_EN
PIN13_PD_EN
pin.
0: Pull-down is disabled
1: Pull-down is enabled
Pull-up control for pin 12. See bit 4 description for pull-down control for pin 12. Note
that both pull-up and pull-down must not be simultaneously enabled for the same
pin.
0: Pull-up is disabled
1: Pull-up is enabled
Pull-down control for pin 12. See bit 5 description for pull-up control for pin 12. Note
that both pull-up and pull-down must not be simultaneously enabled for the same
pin.
0: Pull-down is disabled
1: Pull-down is enabled
Pull-up control for pin 14. See bit 2 description for pull-down control for pin 14. Note
that both pull-up and pull-down must not be simultaneously enabled for the same
pin.
0: Pull-up is disabled
1: Pull-up is enabled
Pull-down control for pin 14. See bit 3 description for pull-up control for pin 14. Note
that both pull-up and pull-down must not be simultaneously enabled for the same
pin.
0: Pull-down is disabled
1: Pull-down is enabled
Pull-up control for pin 13. See bit 0 description for pull-down control for pin 13. Note
that both pull-up and pull-down must not be simultaneously enabled for the same
pin.
0: Pull-up is disabled
1: Pull-up is enabled
Pull-down control for pin 13. See bit 1 description for pull-up control for pin 13. Note
that both pull-up and pull-down must not be simultaneously enabled for the same
pin.
0: Pull-down is disabled
1: Pull-down is enabled
Page 84 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
18 USER BANK 4 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 4.
18.1 FDR_CONFIG
Name: FDR_CONFIG
Address: 09 (09h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
FIFO packet rate decimation factor. Sets the number of discarded FIFO packets.
Valid range is 0 to 127. User must disable sensors when initializing FDR_SEL value or
making changes to it.
0000000: Decimation is disabled, all packets are sent to FIFO
0000001: 1 packet out of 2 is sent to FIFO
0000010: 1 packet out of 3 is sent to FIFO
0000011: 1 packet out of 4 is sent to FIFO
…
6:0
FDR_SEL
1111111: 1 packet out of 128 is sent to FIFO
18.2 APEX_CONFIG1
Name: APEX_CONFIG1
Address: 64 (40h)
Serial IF: R/W
Reset value: 0xA2
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Pedometer Low Energy mode amplitude threshold selection
Use default value 1010b
7:4
LOW_ENERGY_AMP_TH_SEL
When the DMP is in power save mode, it is awakened by the WOM and will wait for
a certain duration before going back to sleep. This bitfield configures this duration.
0000: 0 seconds
0001: 4 seconds
0010: 8 seconds (default)
0011: 12 seconds
0100: 16 seconds
0101: 20 seconds
0110: 24 seconds
0111: 28 seconds
1000: 32 seconds
1001: 36 seconds
1010: 40 seconds
1011: 44 seconds
1100: 48 seconds
1101: 52 seconds
1110: 56 seconds
1111: 60 seconds
3:0
DMP_POWER_SAVE_TIME_SEL
Page 85 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
18.3 APEX_CONFIG2
Name: APEX_CONFIG2
Address: 65 (41h)
Serial IF: R/W
Reset value: 0x85
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Pedometer amplitude threshold selection
Use default value 1000b
Pedometer step count detection window
Use default value 0101b
0000: 0 steps
7:4
PED_AMP_TH_SEL
0001: 1 step
0010: 2 steps
0011: 3 steps
0100: 4 steps
0101: 5 steps (default)
0110: 6 steps
0111: 7 steps
3:0
PED_STEP_CNT_TH_SEL
1000: 8 steps
1001: 9 steps
1010: 10 steps
1011: 11 steps
1100: 12 steps
1101: 13 steps
1110: 14 steps
1111: 15 steps
Page 86 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
18.4 APEX_CONFIG3
Name: APEX_CONFIG3
Address: 66 (42h)
Serial IF: R/W
Reset value: 0x51
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Pedometer step detection threshold selection
Use default value 010b
000: 0 steps
001: 1 step
010: 2 steps (default)
011: 3 steps
7:5
PED_STEP_DET_TH_SEL
100: 4 steps
101: 5 steps
110: 6 steps
111: 7 steps
Pedometer step buffer timer threshold selection
Use default value 100b
000: 0 samples
001: 1 sample
010: 2 samples
011: 3 samples
100: 4 samples (default)
101: 5 samples
110: 6 samples
111: 7 samples
Pedometer high energy threshold selection
Use default value 01b
4:2
1:0
PED_SB_TIMER_TH_SEL
PED_HI_EN_TH_SEL
Page 87 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
18.5 APEX_CONFIG4
Name: APEX_CONFIG4
Address: 67 (43h)
Serial IF: R/W
Reset value: 0xA4
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Configures duration of delay after tilt is detected before interrupt is triggered
00: 0s
01: 2s
7:6
TILT_WAIT_TIME_SEL
10: 4s (default)
11: 6s
This threshold is added to the LOWG peak threshold after the initial threshold is
met. The threshold values corresponding to parameter values are shown below:
000: 31mgee
001: 63mgee
010: 94mgee
011: 125mgee
5:3
LOWG_PEAK_TH_HYST_SEL
100: 156mgee (default)
101: 188mgee
110: 219mgee
111: 250mgee
This threshold is added to the HIGHG peak threshold after the initial threshold is
met. The threshold values corresponding to parameter values are shown below:
000: 31mgee
001: 63mgee
010: 94mgee
2:0
HIGHG_PEAK_TH_HYST_SEL
011: 125mgee
100: 156mgee (default)
101: 188mgee
110: 219mgee
111: 250mgee
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18.6 APEX_CONFIG5
Name: APEX_CONFIG5
Address: 68 (44h)
Serial IF: R/W
Reset value: 0x8C
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
This parameter defines the threshold for accelerometer values below which the
algorithm considers it has entered low-g state. The threshold values corresponding
to parameter values are shown below:
00000: 31mgee
00001: 63mgee
00010: 94mgee
00011: 125mgee
00100: 156mgee
00101: 188mgee
00110: 219mgee
00111: 250mgee
01000: 281mgee
01001: 313mgee
01010: 344mgee
01011: 375mgee
01100: 406mgee
01101: 438mgee
01110: 469mgee
7:3
LOWG_PEAK_TH_SEL
01111: 500mgee
10000: 531mgee
10001: 563mgee (default)
10010: 594mgee
10011: 625mgee
10100: 656mgee
10101: 688mgee
10110: 719mgee
10111: 750mgee
11000: 781mgee
11001: 813mgee
11010: 844mgee
11011: 875mgee
11100: 906mgee
11101: 938mgee
11110: 969mgee
11111: 1000mgee
This parameter defines the number of samples for which the device should stay in
low-g before triggering interrupt.
2:0
LOWG_TIME_TH_SEL
Number of samples = LOWG_TIME_TH_SEL + 1
Default value is 4 (i.e. 5 samples)
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18.7 APEX_CONFIG6
Name: APEX_CONFIG6
Address: 69 (45h)
Serial IF: R/W
Reset value: 0x5C
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
This parameter defines the threshold for accelerometer values above which the
algorithm considers it has entered high-g state. The threshold values corresponding
to parameter values are shown below:
00000: 250mgee
00001: 500mgee
00010: 750mgee
00011: 1000mgee
00100: 1250mgee
00101: 1500mgee
00110: 1750mgee
00111: 2000mgee
01000: 2250mgee
01001: 2500mgee
01010: 2750mgee
01011: 3000mgee (default)
01100: 3250mgee
01101: 3500mgee
01110: 3750mgee
7:3
HIGHG_PEAK_TH_SEL
01111: 4000mgee
10000: 4250mgee
10001: 4500mgee
10010: 4750mgee
10011: 5000mgee
10100: 5250mgee
10101: 5500mgee
10110: 5750mgee
10111: 6000mgee
11000: 6250mgee
11001: 6500mgee
11010: 6750mgee
11011: 7000mgee
11100: 7250mgee
11101: 7500mgee
11110: 7750mgee
11111: 8000mgee
This parameter defines the number of samples for which the device should stay in
high-g before triggering interrupt.
2:0
HIGHG_TIME_TH_SEL
Number of samples = HIGHG_TIME_TH_SEL + 1
Default value is 4 (i.e. 5 samples)
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18.8 APEX_CONFIG7
Name: APEX_CONFIG7
Address: 70 (46h)
Serial IF: R/W
Reset value: 0x45
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Tap Detection minimum jerk threshold
Use default value 010001b
Tap Detection maximum peak tolerance
Use default value 01b
7:2
TAP_MIN_JERK_THR
1:0
TAP_MAX_PEAK_TOL
18.9 APEX_CONFIG8
Name: APEX_CONFIG8
Address: 71 (47h)
Serial IF: R/W
Reset value: 0x5B
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7
-
Reserved
Tap measurement window (number of samples)
Use default value 10b
Tap energy measurement window (number of samples)
Use default value 11b
Single tap window (number of samples)
Use default value 011b
6:5
4:3
2:0
TAP_TMAX
TAP_TAVG
TAP_TMIN
18.10APEX_CONFIG9
Name: APEX_CONFIG9
Address: 72 (48h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:1
-
Reserved
0: Low power mode at accelerometer ODR 25Hz; High performance mode at
accelerometer ODR ≥ 50Hz
1: Low power and slow walk mode at accelerometer ODR 25Hz; Slow walk mode at
accelerometer ODR ≥ 50Hz
0
SENSITIVITY_MODE
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18.11APEX_CONFIG10
Name: APEX_CONFIG10
Address: 73 (49h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
This parameter defines the minimum freefall length that the algorithm should
report. Freefalls smaller than this value are ignored. Freefall lengths corresponding
to parameter values are shown below:
000: 13cm (default)
001: 19cm
010: 28cm
7:5
FF_MIN_DURATION_CM
011: 38cm
100: 50cm
101: 64cm
110: 78cm
111: 95cm
This parameter defines the maximum freefall length that the algorithm should
report. Freefalls longer than this value are ignored. Freefall lengths corresponding
to parameter values are shown below:
000: 113cm (default)
001: 154cm
010: 201cm
4:2
FF_MAX_DURATION_CM
011: 255cm
100: 314cm
101: 380cm
110: 452cm
111: 531cm
This parameter defines the time during which low-g and high-g events are not taken
into account after a high-g event. It helps to avoid detecting bounces as free fall.
Debounce durations corresponding to parameter values are shown below:
00: 0s (default)
01: 1s
1:0
FF_DEBOUNCE_DURATION
10: 2s
11: 3s
18.12ACCEL_WOM_X_THR
Name: ACCEL_WOM_X_THR
Address: 74 (4Ah)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Threshold value for the Wake on Motion Interrupt for X-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g :
1g]; Resolution 1g/256=~3.9mg
7:0
WOM_X_TH
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18.13ACCEL_WOM_Y_THR
Name: ACCEL_WOM_Y_THR
Address: 75 (4Bh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Threshold value for the Wake on Motion Interrupt for Y-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g :
1g]; Resolution 1g/256=~3.9mg
7:0
WOM_Y_TH
18.14ACCEL_WOM_Z_THR
Name: ACCEL_WOM_Z_THR
Address: 76 (4Ch)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Threshold value for the Wake on Motion Interrupt for Z-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g :
1g]; Resolution 1g/256=~3.9mg
7:0
WOM_Z_TH
18.15INT_SOURCE6
Name: INT_SOURCE6
Address: 77 (4Dh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:6
-
Reserved
0: Step detect interrupt not routed to INT1
1: Step detect interrupt routed to INT1
0: Step count overflow interrupt not routed to INT1
1: Step count overflow interrupt routed to INT1
0: Tilt detect interrupt not routed to INT1
1: Tile detect interrupt routed to INT1
5
4
STEP_DET_INT1_EN
STEP_CNT_OFL_INT1_EN
3
2
1
TILT_DET_INT1_EN
-
Reserved
0: Freefall detect interrupt not routed to INT1
1: Freefall detect interrupt routed to INT1
0: Tap detect interrupt not routed to INT1
1: Tap detect interrupt routed to INT1
FREEFALL_DET_INT1_EN
0
TAP_DET_INT1_EN
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18.16INT_SOURCE7
Name: INT_SOURCE7
Address: 78 (4Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:6
-
Reserved
0: Step detect interrupt not routed to INT2
1: Step detect interrupt routed to INT2
0: Step count overflow interrupt not routed to INT2
1: Step count overflow interrupt routed to INT2
0: Tilt detect interrupt not routed to INT2
1: Tile detect interrupt routed to INT2
5
4
STEP_DET_INT2_EN
STEP_CNT_OFL_INT2_EN
3
2
1
TILT_DET_INT2_EN
-
Reserved
0: Freefall detect interrupt not routed to INT2
1: Freefall detect interrupt routed to INT2
0: Tap detect interrupt not routed to INT2
1: Tap detect interrupt routed to INT2
FREEFALL_DET_INT2_EN
0
TAP_DET_INT2_EN
18.17INT_SOURCE8
Name: INT_SOURCE8
Address: 79 (4Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:6
-
Reserved
0: FSYNC interrupt not routed to IBI
1: FSYNC interrupt routed to IBI
Reserved
5
4
3
FSYNC_IBI_EN
-
0: UI data ready interrupt not routed to IBI
1: UI data ready interrupt routed to IBI
0: FIFO threshold interrupt not routed to IBI
1: FIFO threshold interrupt routed to IBI
0: FIFO full interrupt not routed to IBI
1: FIFO full interrupt routed to IBI
0: AGC ready interrupt not routed to IBI
1: AGC ready interrupt routed to IBI
UI_DRDY_IBI_EN
2
1
0
FIFO_THS_IBI_EN
FIFO_FULL_IBI_EN
AGC_RDY_IBI_EN
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18.18INT_SOURCE9
Name: INT_SOURCE9
Address: 80 (50h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
0: I3CSM protocol error interrupt not routed to IBI
1: I3CSM protocol error interrupt routed to IBI
Reserved
7
I3C_PROTOCOL_ERROR_IBI_EN
6:5
4
-
0: SMD interrupt not routed to IBI
1: SMD interrupt routed to IBI
0: Z-axis WOM interrupt not routed to IBI
1: Z-axis WOM interrupt routed to IBI
0: Y-axis WOM interrupt not routed to IBI
1: Y-axis WOM interrupt routed to IBI
0: X-axis WOM interrupt not routed to IBI
1: X-axis WOM interrupt routed to IBI
Reserved
SMD_IBI_EN
3
2
WOM_Z_IBI_EN
WOM_Y_IBI_EN
1
0
WOM_X_IBI_EN
-
18.19INT_SOURCE10
Name: INT_SOURCE10
Address: 81 (51h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
7:6
-
Reserved
0: Step detect interrupt not routed to IBI
1: Step detect interrupt routed to IBI
0: Step count overflow interrupt not routed to IBI
1: Step count overflow interrupt routed to IBI
0: Tilt detect interrupt not routed to IBI
1: Tile detect interrupt routed to IBI
Reserved
0: Freefall detect interrupt not routed to IBI
1: Freefall detect interrupt routed to IBI
0: Tap detect interrupt not routed to IBI
1: Tap detect interrupt routed to IBI
5
4
STEP_DET_IBI_EN
STEP_CNT_OFL_IBI_EN
3
2
1
TILT_DET_IBI_EN
-
FREEFALL_DET_IBI_EN
0
TAP_DET_IBI_EN
18.20OFFSET_USER4
Name: OFFSET_USER4
Address: 123 (7Bh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
7:4
3:0
NAME
FUNCTION
Upper bits of X-accel offset programmed by user. Max value is ±1g, resolution is
0.5mg.
ACCEL_X_OFFUSER[11:8]
Reserved
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18.21OFFSET_USER5
Name: OFFSET_USER5
Address: 124 (7Ch)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Lower bits of X-accel offset programmed by user. Max value is ±1g, resolution is
0.5mg.
7:0
ACCEL_X_OFFUSER[7:0]
18.22OFFSET_USER6
Name: OFFSET_USER6
Address: 125 (7Dh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Lower bits of Y-accel offset programmed by user. Max value is ±1g, resolution is
0.5mg.
7:0
ACCEL_Y_OFFUSER[7:0]
18.23OFFSET_USER7
Name: OFFSET_USER7
Address: 126 (7Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Upper bits of Z-accel offset programmed by user. Max value is ±1g, resolution is
0.5mg.
7:4
ACCEL_Z_OFFUSER[11:8]
Upper bits of Y-accel offset programmed by user. Max value is ±1g, resolution is
0.5mg.
3:0
ACCEL_Y_OFFUSER[11:8]
18.24OFFSET_USER8
Name: OFFSET_USER8
Address: 127 (7Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT
NAME
FUNCTION
Lower bits of Z-accel offset programmed by user. Max value is ±1g, resolution is
0.5mg.
7:0
ACCEL_Z_OFFUSER[7:0]
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19 SMARTINDUSTRIAL FAMILY
TDK’s SmartIndustrial™ portfolio of 6-axis IMU and 3-axis Accelerometer products delivers the precise motion,
vibration and inclination measurements that industrial applications need. These products offer the ability to take
precise measurements in harsh environments with vibration and wide temperature variations.
TDK’s broad portfolio of Industrial Motion Sensing solutions offers customers a range of performance and cost
choices, enabling a wide variety of Industrial navigation, stabilization, and monitoring applications.
By combining its innovative MEMS Motion Sensor technologies with its expertise of Industrial applications, TDK
offers unique capabilities such as Fault-tolerant motion sensing solution.
Page 97 of 100
Document Number: DS-000441
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IIM-42351
20 REFERENCE
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:
• Manufacturing Recommendations
o
o
o
o
Assembly Guidelines and Recommendations
PCB Design Guidelines and Recommendations
MEMS Handling Instructions
ESD Considerations
o
Reflow Specification
o
Storage Specifications
o
o
o
Package Marking Specification
Tape & Reel Specification
Reel & Pizza Box Label
o
Packaging
o
Representative Shipping Carton Label
• Compliance
o
o
o
Environmental Compliance
DRC Compliance
Compliance Declaration Disclaimer
Page 98 of 100
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Revision: 1.2
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21 REVISION HISTORY
REVISION DATE
REVISION
DESCRIPTION
01/07/2021
1.0
Initial release
Updated formatting
02/25/2022
03/24/2022
1.1
1.2
Updated longevity info
Updated table 1 MIN ODR typo, added Total rms specification
Updated table 2 minor typo
Updated table 3 power supply
Page 99 of 100
Document Number: DS-000441
Revision: 1.2
IIM-42351
https://invensense.tdk.com/longevity/
This information furnished by InvenSense or its affiliates (“TDK InvenSense”) is believed to be accurate and reliable. However, no responsibility
is assumed by TDK InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use.
Specifications are subject to change without notice. TDK InvenSense reserves the right to make changes to this product, including its circuits
and software, in order to improve its design and/or performance, without prior notice. TDK InvenSense makes no warranties, neither expressed
nor implied, regarding the information and specifications contained in this document. TDK InvenSense assumes no responsibility for any claims
or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is
not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or
otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied.
Trademarks that are registered trademarks are the property of their respective companies. TDK InvenSense sensors should not be used or sold
in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life
threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear
instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2021—2022 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps,
DMP, AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and
product names may be trademarks of the respective companies with which they are associated.
©2021—2022 InvenSense. All rights reserved.
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