FS1412-0600-AL [TDK]
µPOL™嵌入式DC-DC转换器;
| 型号： | FS1412-0600-AL |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | µPOL™嵌入式DC-DC转换器 DC-DC转换器 |
| 文件： | 总39页 (文件大小：2784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FS1412 µPOL™
DATASHEET
12A Rated µPOL™ Buck Regulator with Integrated Inductor
and Digital Power System Management
Features
Description
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•
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µPOL™ package with output inductor included
The FS1412 is an easy-to-use, fully integrated and
highly efficient micro-point-of-load (µPOL™) voltage
regulator. The on-chip pulse-width modulation
(PWM) controller and integrated MOSFETs, plus
incorporated inductor and capacitors, result in an
extremely compact and accurate regulator. The
low-profile package is suitable for automated
assembly using standard surface-mount equipment.
Small size: 5.8mm x 4.9mm x 1.6mm
Continuous 12A load capability
Plug and play: no external compensation required
Programmable operation using I2C and PMBus™
Wide input voltage range: 4.5–16V
Adjustable output voltage: 0.6–1.8V
Enabled input, programmable under-voltage
lock-out (UVLO) circuit
Developed by a cross-functional engineering team, the
design exemplifies best practice and uses class-leading
technologies. From early in the integrated circuit
design phase, designers worked with application and
packaging engineers to select compatible
technologies and implement them in ways that
reduce compromise. The ability to program aspects
of the FS1412’s operation using the I2C and PMBus™
protocols is unique in this class of product.
Developing and optimizing all these elements
together has yielded the smallest, most efficient
and fully featured 12A µPOL™ currently available.
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•
•
•
•
Open-drain power-good indicator
Built-in protection features
Operating temperature from -40°C to +125°C
Lead-free and halogen-free
Compliant with EU REACH and RoHS
Applications
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Telecom, wireless and 5G applications
Networking and datacenter applications
Storage applications
Industrial applications
Distributed point-of-load power architectures
Computing peripheral voltage regulation
General DC-DC conversion
The built-in protection features include soft-start
protection, over-voltage protection, thermally
compensated over-current protection with hiccup
mode, thermal shut-down with auto-recovery.
PVIN = 12V, VOUT = 1.8V
No airflow, all losses included
Page 1
Rev 2.5, July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Pin configuration
Figure 1 Pin layout (top view)
Figure 2 Pin layout (bottom view)
Pin functions
Pin
Number
Name Description
1
2
SW2
VIN
Test pin
Input voltage. Input for the internal LDO regulator.
En
Enable. Switches the FS1412 on and off. Can be used with two external resistors to set an external
UVLO (Figure 5).
3
4
5
PVCC
VCC
Input supply for the drivers. Connect to VCC on the application board.
Supply voltage. May be an input bias for an external VCC voltage or the output of the internal LDO regulator.
Feedback voltage to the device. Connect to VOUT on the application board using an external resistor
divider to set desired output voltage.
6
VFB
Signal ground. Serves as the ground for the internal reference and control circuitry. Connect pins to the
7,22
8
AGnd
VOUT
PG
PGnd plane through vias.
Regulator output voltage. Place output capacitors and a 100Ω resistor between VOUT and PGnd.
Power Good status. Open drain of an internal MOSFET.
Pull up to VCC – Pin 5 or an external bias voltage with a 49.9kΩ resistor.
9
10
11
ADDR Address. Connect to AGnd through a resistor to program FS1412 address.
SYNC Synchronize device with external clock. Connect to AGnd if unused.
I2C/PMBus™ Serial Input/Output line. Pull up to bus voltage with 4.99kΩ resistor. Connect to AGnd if
unused.
12
SDA
13
14
15
SCL
I2C/PMBus™ Clock line. Pull up to bus voltage with 4.99kΩ resistor. Connect to AGnd if unused.
ALERT SMBAlert# line. Pull up to bus voltage with 4.99kΩ resistor.
SW1
An optional external capacitor may be connected between SW1 and Cb.
Power Ground. Serves as a separate ground for the MOSFETs. Connect to the power ground plane in
the application.
16,20,21 PGnd
17
Cb
An optional external capacitor may be connected between Cb and SW1.
18,19
PVIN
Power input voltage. Input for the MOSFETs.
Page 2
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Block diagram
Figure 3 FS1412 µPOL™
Typical application
Figure 4 Applications circuit for using an external resistor to set the output voltage
Page 3
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Absolute maximum ratings
Warning: Stresses beyond those shown may cause permanent damage to the FS1412.
Note:
Functional operation of the FS1412 is not implied under these or any other conditions beyond those stated in
the FS1412 specification.
Reference
Range
PVIN, VIN, En to PGnd, Cb to SW1
VCC to PGnd (Note 1)
-0.3V to 18V
-0.3V to 6V
SW1, SW2
-0.3V to 15V
Fb, Sync, Addr, SCL, SDA, SALERT to AGnd (Note1)
PG to AGnd (Note 1)
-0.3V to VCC
-0.3V to VCC
PGnd to AGnd
ESD Classification (HBM JESD22-A114)
Moisture Sensitivity Level
-0.3V to +0.3V
Class 1C
MSL 3 (per JEDEC J-STD-020D)
Thermal Information
Range
Junction-to-Ambient Thermal Resistance ƟJA
Junction to PCB Thermal Resistance ƟJ-PCB
Storage Temperature Range
20.5°C/W
5.5°C/W
-55°C to 150°C
-40°C to 150°C
Junction Temperature Range
Note:
ƟJA : FS1412 evaluation board and JEDEC specifications JESD 51-2A
ƟJ-c (bottom) : JEDEC specification JESD 51-8
Page 4
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Order information
Package details
The FS1412 uses a µPOL™ 5.8mm x 4.9mm package delivered in tape-and-reel format, with either 250 or 3900
devices on a reel.
Part Number
FS1412-0600-AS
FS1412-0600-AL
VOUT
0.60
0.60
Quantity per Reel
250
3900
Package Description
22-pin LGA SiP (5.8mm x 4.9mm)
22-pin LGA SiP (5.8mm x 4.9mm)
Package Code
P24
P24
For more information on the tape-and-reel specification, go to:
https://product.tdk.com/en/products/power/switching-power/micro-pol/designtool.html
Page 5
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Recommended operating conditions
Definition
Symbol
PVIN
PVIN
VIN
Min
6*VOUT
6*VOUT
4.5
Max
16
Units
Input Voltage Range with External VCC (Note 3, Note 5)
Input Voltage Range with Internal LDO (Note 4, Note 5)
Bias Input Voltage Range (Note 4)
Supply Voltage Range (Note 2)
16
16
V
VCC
4.5
5.5
Output Voltage Range
VOUT
IO
TJ
0.6
0
-40
1.8
12
125
Continuous Output Current Range
Operating Junction Temperature
A
°C
Electrical characteristics
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply over: 6*VOUT <PVIN <16V, 4.5V < VIN < 16V, 0°C < T < 125°C
Typical values are specified at TA = 25°C
Parameter
Symbol
Conditions
Min Typ Max Unit
Supply Current
VIN Supply Current (Standby)
VIN Supply Current (Dynamic)
Soft-Start
IIN (STANDBY)
IIN (DYN)
Enable low
En high, VIN = 12V, FSW =470kHz
7
16
8
18
mA
Default (Note 7), VOUT = 0.6V,
TON_RISE=2ms
V/m
s
Soft-Start Rate
SSRATE
0.17 0.28 0.37
0.6
Output Voltage
VOUT (default)
range
V
V
Output Voltage Range
0.6
1.8
Resolution
5
mV
TJ = 25°C, VOUT = 0.6V
-40°C < TJ < 125°C (Note 6)
±0.75
Accuracy
%
-1
+1
On-Time Timer Control
On Time
Minimum On-Time
TON
TON(MIN)
PVIN = 12V, VOUT = 0.6V, FSW = 470kHz 185 211 235
ns
(Note 7)
50
Internal Low Drop-Out (LDO) Regulator
5.5V ≤ VIN ≤ 16V, 0 – 40mA
4.5V ≤ VIN < 5.5V, 0 – 40mA
0 – 40mA
4.89 5.2
4.19 4.26
5.4
LDO Regulator Output Voltage
VCC
VLD
V
Load Regulation
Thermal Shut-Down
Thermal Shut-Down
Hysteresis
0.19
Default
(Note 7)
(Note 7)
145
25
°C
Page 6
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply over: 6*VOUT <PVIN <16V, 4.5V < VIN < 16V, 0°C < T < 125°C
Typical values are specified at TA = 25°C
Parameter
Symbol
Conditions
Min Typ Max Unit
Under-Voltage Lock-Out
VCC Start Threshold
VCC Stop Threshold
VCC_UVLO(START)
VCC_UVLO(STOP)
En(HIGH)
VCC Rising Trip Level
VCC Falling Trip Level
Ramping Up
4.0 4.2
3.6 3.8
1.05 1.20 1.34
0.92 1.00 1.11
4.4
4.1
V
Enable Threshold
En(LOW)
Ramping Down
150
Input Impedance
Current Limit
REN
500 1000
0
kΩ
IOC (default)
IOC (range)
TBLK(HICCUP)
TJ = 25°C
14.5 16
10
17.5
16
Current Limit Threshold
A
Hiccup Blanking Time
20
ms
Over-Voltage Protection
VOVP (default)
VOVP (range)
VOVP (resolution)
OVP Detect (Note 7)
115 120 125
Output Over-Voltage Protection
Threshold
105
120 Fb%
5
5
Output Over-voltage Protection Delay TOVPDEL
µs
Power Good (PG)
Power Good Upper Threshold
Power Good Hysteresis
Power Good Sink Current
Telemetry
VPG(UPPER) (default) VOUT Rising
85 90
95
Fb%
VPG(LOWER)
IPG
VOUT Falling
PG = 0.5V, En = 2V
7
9
mA
PVIN=12V, -40°C < TJ < 125°C
-2
-5
-18
-20
2
5
18
20
Input voltage reporting accuracy
PVIN_report_err
%
5V<PVIN<16V, -40°C < TJ <125°C
VOUT = VFB =0.6V, -40°C < TJ < 125°C
-40°C < TJ <125°C (Note 7)
Output voltage reporting accuracy
Temperature reporting accuracy
VOUT_report_err
T_report_err
mV
°C
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply over: 6*VOUT < PVIN = VIN < 16V, 0°C < T < 125°C
Typical values are specified at TA = 25°C
Parameter
Symbol Conditions
Fast-mode
Fast-mode Plus
Unit
(Note 7 for all
parameters)
I2C parameters
Min
Max
Min
Max
I2C bus voltage
VBUS
VIL
VIH
1.8
−0.5
0.7VBUS
0.05VBUS
5.5
0.3VBUS
1.8
−0.5
0.7VBUS
0.05VBUS
5.5
0.3VBUS
LOW-level input voltage
HIGH-level input voltage
Hysteresis
V
V
VHYS
(open-drain or open-
VOL1 collector) at 3mA sink
LOW-level output voltage 1
0
0.4
0
0.4
current; VDD > 2 V,
Page 7
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply over: 6*VOUT < PVIN = VIN < 16V, 0°C < T < 125°C
Typical values are specified at TA = 25°C
Parameter
Symbol Conditions
Fast-mode
Fast-mode Plus
Unit
(Note 7 for all
parameters)
I2C parameters
Min
Max
Min
Max
(open-drain or open-
LOW-level output voltage 2
VOL2 collector) at 2mA sink
0
0.2VBUS
0
0.2VBUS
current; VDD ≤ 2 V,
VOL = 0.4 V,
VOL = 0.6 V
TOF From VIHmin to VILmax
3
6
-
-
3
6
-
-
LOW-level output current
Output fall time
Pulse width of spikes that
must be suppressed by the
input filter
IOL
mA
ns
20 × (VBUS/5.5 V) 250 20 × (VBUS/5.5 V) 125
TSP
0
50
0
50
Input current each I/O pin
Capacitance for each I/O pin
SCL clock frequency
II
CI
FSCL
−10
-
0
10
10
400
−10
-
0
10
10
μA
pF
1000 kHz
Hold time (repeated) START
condition
LOW period of the SCL clock
HIGH period of the SCL clock
After this time, the first
clock pulse is generated
THD;STA
0.6
-
0.26
-
-
TLOW
THIGH
1.3
0.6
-
-
0.5
0.26
-
μs
Set-up time for a repeated
START condition
Data hold time
TSU;STA
0.6
-
0.26
-
THD;DAT I2C-bus devices
TSU;DAT
0
100
-
-
0
50
-
-
Data set-up time
Rise time of SDA and SCL
signals
Fall time of SDA and SCL signals
TR
TF
20
300
-
120
ns
20 × (VDD/5.5 V) 300 20 × (VDD/5.5 V) 120
Set-up time for STOP condition TSU;STO
0.6
-
0.26
-
μs
Bus free time between a
STOP and START condition
TBUF
1.3
-
0.5
-
Capacitive load for each bus line CBUS
-
-
-
400
0.9
0.9
-
-
-
-
550
0.45
0.45
-
pF
Data valid time
TVD;DAT
μs
Data valid acknowledge time TVD;ACK
Noise margin at the LOW level
Noise margin at the HIGH level
SDA timeout
VNL
VNH
TTO
0.1VDD
0.2VDD
200
0.1VDD
0.2VDD
200
For each connected device,
including hysteresis
V
-
-
μs
For supported PMBus™ commands, see page 37.
Page 8
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Notes
1
2
3
4
5
6
PGnd pin and AGnd pin are connected together
Must not exceed 6V
VIN is connected to VCC to bypass the internal Low Drop-Out (LDO) regulator
VIN is connected to PVIN (for single-rail applications with PVIN=VIN=4.5V–16V)
Maximum switch node voltage should not exceed 15V
Hot and cold temperature performance is assured by correlation using
statistical quality control, but not tested in production; performance at 25°C is
tested and guaranteed in production environment
7
Guaranteed by design but not tested in production
Page 9
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Temperature characteristics
Output Voltage: 0.6V
Output Voltage: 0.8V
Output Voltage: 1.0V
Output Voltage: 1.2V
Output Voltage: 1.5V
Output Voltage: 1.8V
Page 10
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Enable Start Threshold
VCC Start Threshold
On Time
Enable Stop Threshold
VCC Stop Threshold
Off Time
Page 11
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Soft-Start Rate
VIN Supply Current (Dynamic)
Page 12
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Efficiency characteristics
Typical efficiency
PVIN = 12V,VOUT = 1V, IO = 0–12A, room temperature, no air flow, all losses included
Typical power loss
PVIN = 12V,VOUT = 1V, IO = 0–12A, room temperature, no air flow, all losses included
Page 13
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Typical load regulation
PVIN = 12V,VOUT = 1V, IO = 0–12A, room temperature, no air flow, all losses included
Page 14
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Applications information
Overview
Bias voltage
The FS1412 is an easy-to-use, fully integrated and
highly efficient DC/DC regulator. Aspects of its
operation, including output voltage and system
optimization parameters, can be programmed
The FS1412 has an integrated Low Drop-Out (LDO)
regulator, providing the DC bias voltage for the
internal circuitry. The typical LDO regulator output
voltage is 5.2V. For internally biased single-rail
operation, the VIN pin should be connected to the
PVIN pin (Figure 5). If an external bias voltage is
used, the VIN pin should be connected to the VCC
pin to bypass the internal LDO regulator (Figure 6).
There is a separate pin to provide bias for the
drivers (PVCC); this should be connected to VCC in
the application circuit.
using the I2C/PMBus™ protocol. It uses
a
proprietary modulator to deliver fast transient
responses. The modulator has internal stability
compensation so that it can be used in a wide
range of applications, with various types of output
capacitors, without loop stability issues.
The FS1412 is a versatile device offering great
flexibility for configuration and system monitoring
using the I2C/PMBus™ interface. At the same time,
it allows standalone operation without any digital
interface by making it easy for the designer to
configure output voltages using simple resistor
divider changes, and to monitor the system using
the Power Good output.
The supply voltage (internal or external) rises with
VIN and does not need to be enabled using the En
pin. Consequently, I2C/PMBus™ communication
can begin as soon as:
•
•
•
•
VCC_UVLO start threshold is exceeded
Memory contents are loaded
Initialization is complete
Address offset is read
Operation and topology
Note:
Until initialization is complete, a small leakage
current (≈3.4µA) will flow from the device into
the output. This may significantly pre-bias the
output voltage in applications with long
VIN/VCC rise times. To prevent this, a small
load capable of sinking 3.4µA should be
connected in such applications.
The FS1412 uses an interleaved buck converter
topology. It shows reduced voltage stresses on the
internal power devices, resulting in smaller size
and switching losses comparable to an equivalently
rated conventional interleaved buck converter.
Another advantage is a natural current-sharing
mechanism between the two phases.
The I2C bus may be pulled up either to VCC or to a
system I2C bus voltage. The FS1412 offers two
ranges for the I2C bus voltage, defined by the user
register bit Bus_voltage_sel.
Register
Bits
Name/Description
0x7A
[2]
Bus_voltage_sel
0:1.8–2.5V, 1: 3.3–5V
Page 15
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
I2C base address and offsets
The FS1412 has user registers to set its I2C base
address and PMBus™ base address. The default I2C
base address is 0x08, and the default PMBus™
base address is 0x70. An offset of 0–15 is then
defined by connecting the ADDR pin to the AGnd
pin, either directly or through a resistor. An
address detector reads the resistance of the
connection at startup and uses it to set the offset,
which is added to the base I2C address to set the
address at which the I2C master device will
communicate with the FS1412. The same offset is
added to the base PMBus™ address to determine
the PMBus™ address at which PMBus™
communication will be established.
To select offsets of 0–15, connect the pins as follows:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
– 0Ω (short ADDR to AGnd)
Figure 5 Single supply configuration: internal LDO
regulator, adjustable PVIN_UVLO
+1 – 1.13kΩ
+2 – 1.87kΩ
+3 – 2.61kΩ
+4 – 3.4kΩ
+5 – 4.12kΩ
+6 – 4.87kΩ
+7 – 5.62kΩ
+8 – 6.34kΩ
+9 – 7.15kΩ
+10 – 7.87kΩ
+11 – 8.66kΩ
+12 – 9.31kΩ
+13 – 10.2kΩ
+14 – 11kΩ
+15 – 12.1kΩ
Note:
Do not use the 7-bit address 0x0C; this
corresponds to the Alert Response Address in
the SMBus™ protocol.
Figure 6 Using an external bias voltage
Page 16
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Soft-start and target output voltage
The FS1412 has an internal digital soft-start circuit
to control output voltage rise-time and limit current
surge at start-up. When VCC exceeds its start
threshold (VCC_UVLO(START)), the FS1412 exits reset
mode; this initiates loading of the contents of the
non-volatile memory into the working registers and
calculates the address offset as described above.
Once initialization is complete, the internal soft
start begins to ramp towards the set reference
voltage at a rate determined by the TON_RISE
registers (corresponding to the TON_RISE
command), provided these conditions are met:
a) A valid enable signal is recognized (as defined
by the Enable pin, Operation register,
ON_OFF_CONFIG register, input voltage PVIN,
and PVIN UVLO threshold corresponding to the
VIN_ON registers).
Figure 7 Theoretical operational waveforms
during soft-start
Over-current protection (OCP) and over-voltage
protection (OVP) are enabled during soft-start to
protect the FS1412 from short circuits and excess
voltages respectively.
b) The internal pre-charge circuit has ensured
that, when the device starts to switch, it does
so with balanced PVIN/2 voltages across all FETs.
During initial start-up, the FS1412 operates with a
minimum of high-drive (HDrv) pulses until the
output voltage increases (see Switching frequency
and minimum values for on-time, off-time on page
19). On-time is increased until VOUT reaches the
target value defined by the VOUT_COMMAND
registers. For proper start-up operation of the
FS1412, fitting a 100Ω resistor in parallel with the
output capacitors (COUT) is recommended. A
minimum wait time of 600*COUT is recommended
between successive power or Enable cycling
operations. For example, with the recommended
100Ω resistor across four 47µF output capacitors, a
new Enable assertion should not happen for a
minimum of 78ms after disabling the FS1412.
Page 17
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
A resistor divider may be used with a standard
FS1412-0600 device to set the desired output
voltage (Figure 8). This gives system designers the
flexibility to design all the power rails in the system
across the entire output voltage range (0.6–1.8V)
using a single part.
VOUT (V)
0.72V
0.85V
0.9V
0.95V
1V
RBOTTOM (kΩ)
21
9.76
8.06
6.81
5.9
1.05V
1.1V
1.2V
1.5V
1.8V
5.23
4.75
3.92
2.55
1.91
Instead of an external resistor divider, the output
voltage can be set using I2C/PMBus™ commands
(see page 24) or the corresponding user registers.
The table below lists VOUT_COMMAND codes to
set the voltages shown above. FS1412 supports
this command with a resolution of 1/256V.
VOUT (V) VOUT_COMMAND VOUT (V) VOUT_COMMAND
0.65
0.70
0.72
0.75
0.78
0.80
0.85
0.88
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
00A7
00B4
00B9
00C0
00C8
00CD
00DA
00E2
00E7
00F4
0100
010D
011A
0127
0134
0140
014D
015A
0167
0174
0127
0180
018D
019A
01A7
01B4
01C0
01CD
Figure 8 Setting the output voltage with an
external resistor divider
The equation below describes the appropriate
resistor divider selection to set the output voltage
using a FS1412 programmed to 0.6V.
푅푇푂푃
푅퐵푂푇푇푂푀
=
1.7975푉 − 1.0639 − 0.00894푅ꢀꢁꢂ
표
where, RTOP and RBOT are in kΩ. It is recommended
that system designers place a capacitor (CFF in
Figure 18) of 47pF to 470pF in parallel with RTOP
,
for which a value of 4.12kΩ is recommended. The
recommended value for RBOTTOM depends on the
output voltage, as shown in the table below. It is
also recommended that designers validate these
values in their own applications.
Shut-down mechanisms
The FS1412 has two shut-down mechanisms:
•
Hard shut-down or decay according to load
A valid hard-disable is recognized (as defined
by the Enable pin, Operation register,
ON_OFF_CONFIG register, input voltage PVIN,
Page 18
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
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Data and specifications subject to change without notice.
FS1412 µPOL™
and PVIN UVLO threshold corresponding to the
VIN_ON registers). Both drivers switch off and
soft-start is pulled down instantaneously.
When output voltage is set by programming the
VOUT_COMMAND user registers, rather than using
an external resistor divider, mode b) should be
used. To do this, the user must also enable the PLL
(phase-locked loop), which is disabled by default,
and cycle the Enable pin. This automatically sets
the switching frequency to factory-programmed
values shown in the table below. The PLL
modulates the on-time to maintain a constant
switching frequency irrespective of the load.
•
Soft-Stop or controlled ramp down
A valid soft-off request is recognized (as
defined by the Enable pin, Operation register
and ON_OFF_CONFIG register). Then, following
a delay corresponding to the TOFF_DELAY
registers, the SS signal falls to 0 in a time
defined by the TOFF_FALL registers; the drivers
are disabled only when it reaches 0. The output
voltage follows the SS signal down to 0.
VOUT range (V)
FSW (MHz)
0.50
VOUT < 0.65
0.65 < VOUT < 1.10
1.10 < VOUT < 1.32
1.32 < VOUT < 1.80
1.00
1.25
1.50
By default, the device is configured for hard shut-
down. Shut-down with PVIN is always a hard shut-
down.
Therefore, with either method, system designers
need not concern themselves with selecting the
switching frequency and have one fewer design
task to manage.
Switching frequency and minimum
values for on-time, off-time and PVIN
The switching frequency of the FS1412 depends on
the output voltage. There are two possible modes
of operation:
When input voltage is high relative to target
output voltage, the Control MOSFETs are switched
on for shorter periods. The shortest period for
which it can reliably be switched on is defined by
minimum on-time (TON(MIN)). During start-up, when
the output voltage is very small, the FS1412
operates with minimum on-time.
a) Pseudo constant-frequency COT mode (default)
b) PLL-modulated COT mode
For the default output voltage of 0.6V, the
switching frequency is nominally 470kHz, and the
device operates in mode a). In this mode, when
the output voltage is set using an external resistor
divider, the switching frequency automatically
adjusts to the appropriate value:
The maximum conversion ratio, on the other hand,
is determined by two factors:
a) When input voltage is low relative to target
output voltage, the Control MOSFET is
switched on for longer periods. The shortest
period for which it can be switched off is
defined by minimum off-time (TOFF(MIN)). The
Synchronous MOSFET stays on during this
period and its current is detected for over-
current protection. This dictates the minimum
input voltage that can still allow the device to
regulate its output at the target voltage.
푉푂푈푇
퐹
푠푤
= 470푘퐻푧 ×
0.6
Page 19
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Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
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Data and specifications subject to change without notice.
FS1412 µPOL™
b) To maintain balanced switching amplitudes in
both phases, this topology requires there to be
no overlap between the high sides of the two
phases (unlike a conventional buck topology).
This effectively imposes theoretical maximums
of 50% on the duty cycle of each phase and 25%
on the conversion ratio; in practice, allowing for
circuit delays and dead-times, the conversion
ratio must not exceed 16% at full load.
The maximum conversion ratio is affected by both
system efficiency and load transient requirements.
It is recommended that system designers validate
the values in their own applications.
Enable (En) pin
The Enable (En) pin has several functions:
Figure 9 En pin used to monitor other rails
for sequencing purposes
•
In the default setting of the ON_OFF_CONFIG
command, it is used to switch the FS1412 on and
off. It has a precise threshold, which is internally
monitored by the UVLO circuit. If it is left floating,
an internal 1MΩ resistor pulls it down to prevent
the FS1412 being switched on unintentionally.
It can be used to implement a precise input
voltage UVLO. The input of the En pin is derived
from the PVIN voltage by a set of resistive
Over-current protection (OCP)
Over-current protection (OCP) is provided by
sensing the current through the RDS(on) of the
Synchronous MOSFET. When this current exceeds
the OCP threshold, a fault condition is generated.
This method provides several benefits:
•
dividers, REN1 and REN2 (Figure 5). Users can
program the UVLO threshold voltage by selecting
different ratios. A useful feature that stops the
FS1412 regulating when PVIN is lower than the
desired voltage, this may be used for finer
control over the PVIN UVLO voltage levels than is
provided by the VIN_ON/VIN_OFF commands.
It can be used to monitor other rails for a
specific power sequencing scheme (Figure 9).
•
Provides accurate over-current protection
without reducing converter efficiency
(the current sensing is lossless)
Reduces cost by eliminating a current-sense
resistor
•
•
Reduces any layout-related noise issues.
•
The OCP threshold is defined by the IOUT_OC_
FAULT_LIMIT command (or the corresponding user
registers). The over-current limit may be programmed
in 0.5A steps, up to a maximum of 16A. The minimum
recommended over-current threshold is 10A.
The OCP threshold is internally compensated so
that it remains almost constant at different
ambient temperatures.
Page 20
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Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
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Data and specifications subject to change without notice.
FS1412 µPOL™
When the current exceeds the OCP threshold, the
PG and SS signals are pulled low. The Synchronous
MOSFET remains on until the current falls to 0,
then the FS1412 enters hiccup mode (Figure 10).
Both the Control MOSFET and the Synchronous
MOSFET remain off for the hiccup-blanking time.
After this time, the FS1412 tries to restart. If an
over-current fault is still detected, the preceding
actions are repeated. The FS1412 remains in
hiccup mode until the over-current fault is
remedied. The FS1412 can be re-programmed to
enter a latched shut-down mode on encountering
an over-current fault.
VOUT_OV_FAULT_LIMIT
(% of VOUT_COMMAND) (% of VOUT_COMMAND)
100 < setting ≤ 105.4
105.4 < setting ≤ 110.1
110.1 < setting ≤ 114.8
114.8 < setting ≤ 100.1
Actual OVP Threshold
105
110
115
120
The default setting is 120%. All the MOSFETs are
switched off immediately and the PG pin is pulled
low.
The MOSFETs remain latched off until reset by
cycling either VCC or En. Figure 11 shows a timing
diagram for over-voltage protection.
Figure 11 Illustration of latched OVP
The FS1412 provides output over-voltage and
under-voltage warnings, as well as output under-
voltage fault protection. These are set by three
commands, respectively: VOUT_OV_WARN_LIMIT,
VOUT_UV_WARN_LIMIT and VOUT_UV_FAULT_LIMIT
(or the corresponding user registers). The
mechanism for these thresholds is different from
the over-voltage protection mechanism: the former
rely on a digital comparison of the digitized and
processed VOUT telemetry to the thresholds,
whereas the latter relies on an all-analog signal
path and an internal high-speed comparator.
Figure 10 Illustration of OCP in hiccup mode
Over-voltage protection (OVP)
Over-voltage protection (OVP) is provided by
sensing the voltage at the FB pin. When FB exceeds
the output OVP threshold for longer than the
output OVP delay (typically 5μs), a fault condition
is generated.
The OVP threshold is defined by the VOUT_OV_
FAULT_LIMIT command (or the corresponding user
registers). This command allows the over-voltage
level to be set relative to the output voltage, with a
resolution of 1/256V. However, internally, these
are rounded to one of four settings as shown in the
table below.
Page 21
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Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
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Data and specifications subject to change without notice.
FS1412 µPOL™
Over-temperature protection (OTP)
Power Good (PG)
Temperature sensing is provided inside the
FS1412. The OTP threshold is defined by the lower
of two thresholds:
Power Good (PG) behavior is defined by the user
register
POWER_GOOD_ON
bits
PGControl
and
by
When
the
the
command.
PGControl bit is set, the PMBus™ command may
be used to set the upper power good threshold
relative to the output voltage, with a resolution of
1/256V. However, internally, these are rounded to
one of four settings as shown in the table below.
a) A fixed threshold set internally to 145°C. The
comparison with this threshold is analog. If the
temperature exceeds the threshold, the device
stops switching with all MOSFETs off until the
temperature drops below the threshold, after
which it restarts automatically.
POWER_GOOD_ON
Actual Power Good Threshold
(% of VOUT_COMMAND) (% of VOUT_COMMAND)
b) A programmable threshold set to a resolution
of 1°C using the OT_FAULT_LIMIT command
(or the corresponding user registers). When
set lower than the fixed analog threshold
96.1 < threshold ≤ 85.1
79.6 < threshold ≤ 85.1
85.1 < threshold ≤ 89.8
89.81 < threshold ≤ 96.1
80
85
90
95
(145°C),
the
programmable
threshold
determines the temperature at which the
device trips, making a digital comparison of
reported temperature (READ_TEMPERATURE)
and OT_FAULT_LIMIT. When the reported
temperature exceeds the programmable
threshold, the device either continues power
conversion (default) or goes into a latched
The default is 90%, so the PG signal will be asserted
when the voltage at the Fb pin exceeds 90% of the
VOUT_COMMAND setting (default 0.6V).
Hysteresis of 5% is applied to this, giving a lower
threshold. When the voltage at the Fb pin drops below
this lower threshold, the PG signal is pulled low.
shutdown,
a
behavior
selected
by
reprogramming the OT_FAULT_RESPONSE
PMBus command (or corresponding registers).
Recovery requires either cycling Enable or the
Operation command.
PGControl bit set to 1 (default)
Figure 12 shows PG behavior in this situation.
By default, the FS1412 relies on the fixed analog
threshold with its auto-restart fault response. In
this default configuration, the digital threshold is
set to 150°C, and the fault response is set to ignore.
Figure 12 PG signal when PGControl bit=1
Page 22
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Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
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Data and specifications subject to change without notice.
FS1412 µPOL™
The behavior is the same at start-up and during
normal operation. The PG signal is asserted when:
In normal operation, the PG signal behaves in the
same way as when the PGControl bit is 1.
At start-up, however, the PG signal is asserted after
Fb is within 2% of target output voltage, not when
Fb exceeds the upper PG threshold.
•
•
En and VCC are both above their thresholds
No fault has occurred
(including over-current, over-voltage and
over-temperature)
VOUT is within the target range
(determined by continuously monitoring
whether FB is above the PG threshold)
FS1412 also integrates an additional PMOS in
parallel to the NMOS internally connected to the
PG pin (Figure 3). This PMOS allows the PG signal
to stay at logic low, even if VCC is low and the PG
pin is pulled up to an external voltage not VCC.
•
PGControl bit set to 0
Figure 13 shows PG behavior in this situation.
Figure 13 PG signal when PGControl bit=0
Page 23
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Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
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Data and specifications subject to change without notice.
FS1412 µPOL™
Output voltage and output capacitor
Design example
Let us now consider a simple design example, using
the FS1412 for the following design parameters:
The FS1412 is trimmed at the factory to provide a
0.6V output in closed loop. When not using
I2C/PMBus™ and instead employing a resistor
divider, as in the application example here, we will
choose the resistor values in accordance with the
discussion on page 18. Therefore, RTOP = 4.12kΩ,
RBOTTOM = 5.9 kΩ and CFF = 220pF.
•
•
•
•
•
•
•
PVIN = VIN = 12V
VOUT = 1.0V
FSW = 800kHz
COUT = 4 x 47μF
CIN = 3 x 22μF
The design requires minimal output capacitance to
meet the target output voltage ripple and target
maximum output voltage deviation under load
transient conditions.
Ripple Voltage = ± 1% * VOUT
ΔVOUT(MAX) = ±3% * VOUT
(for 50% load transient @ 40A/μs)
Input capacitor
For the FS1412, the minimum number of output
capacitors required to achieve target peak-to-peak
VOUT ripple is:
The input capacitor selected for this design must:
•
Handle the peak and root mean square (RMS)
input currents required by the FS1412
Have low equivalent series resistance and
inductance (ESR and ESL) to reduce input
voltage ripple
(ퟏ − 푫)
ퟖ푪푭푺푾
푬푺푳 × 푭푺푾 × (ퟏ − 푫)ퟐ
(
)
+ 푬푺푹 ퟏ − 푫 +
푫
푵푴푰푵 = ퟓ. ퟖ ×
∆푉푂푈푇푟푖푝푝푙푒(푝ꢊ푝)
•
where:
•
•
•
NMIN = minimum number of output capacitors
D = duty cycle
C = equivalent capacitance of each output
capacitor
MLCCs (multi-layer ceramic capacitors) are ideal.
Typically, in 0805 case size, they can handle 2A
RMS current with less than 5°C temperature rise.
•
•
FSW = switching frequency
ESR = equivalent series resistance of each
output capacitor
For the FS1412 converter topology operating at
duty cycle D and output current IO, the RMS value
of the input current is:
•
•
ESL = equivalent series inductance of each
output capacitor
∆푉푂푈푇푟푖푝푝푙푒(푝ꢊ푝)
퐼ꢃ푀푆 = 0.5 × 퐼ꢄ 퐷(1 − 퐷)
√
2×ꢅ
ꢆꢇꢈ
In this application, IO = 12A and 퐷 =
= 0.166
푃ꢅ
= target peak-to-peak VOUT ripple
ꢉ푁
Therefore, IRMS = 2.23A and we can select three
22μF 25V ceramic capacitors for the input
capacitors (C2012X5R1E226M125AC from TDK).
This design uses C2012X5R0J476M125AC from
TDK; this is a 47μF MLCC, 0805 case size, rated at
6.3V. At 1.0V, accounting for DC bias and AC ripple
derating, it has an equivalent capacitance of 33μF
(C). Equivalent series resistance is 3mΩ (ESR) and
equivalent series inductance is 0.44nH (ESL).
If the FS1412 is not located close to the 12V power
supply, a bulk capacitor (68–330μF) may be used in
addition to the ceramic capacitors.
Putting these parameters into the equation gives:
For VIN, which is the input to the LDO, it is
recommended to use a 1μF capacitor very close to
the pin. The VIN pin should be connected to PVIN
through a 2.7Ω resistor. Together, the 2.7Ω resistor
and 1μF capacitor filter noise on PVIN.
NMIN = 2.27
Page 24
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Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
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Data and specifications subject to change without notice.
FS1412 µPOL™
To meet the maximum voltage deviation ΔVomax
under a ∆퐼표 load transient, the minimum required
number of output capacitors is:
It should be noted that even in the absence of a
target VOUT ripple or target maximum voltage
deviation under load transient, at least one 22μF
capacitor is still required in order to ensure stable
operation without excessive jitter.
ퟎ. ퟏퟗퟔ × ∆푰ퟐ풐
4 × ∆푉
× 퐹 × 퐶
푠푤
표푚푎푥
Up to eight 47μF capacitors may be used in the
design. If more capacitance is required, it is
recommended to use a high value capacitor with
relatively high ESR (>3mΩ).
where:
•
•
•
•
∆퐼표 = load step
∆푉푂푈푇푚푎푥 = target maximum voltage deviation
= switching frequency
C = equivalent capacitance of each output
capacitor
퐹
푠푤
A 100 ohm resistor should be added in parallel
with the output capacitors.
Figure 15 to Figure 16 show peak-to-peak voltage
deviation as a function of slew rate for different
output voltages and load currents.
Again, using C = 33μF, it can be seen that the
minimum number of output capacitors required is
2.22.
Figure 17 shows the minimum required output
capacitance as a function of the output voltage.
For an output voltage of 1V, the minimum
capacitor requirement is dictated by the load
transient specifications (< ±3% VOUT). For output
voltages above 1V, the output voltage ripple
specification dominates (< ±1%).
In our design intended for space-constrained
applications,
therefore,
we
use
four
C2012X5R0J476M125AC capacitors.
It should be noted here that the calculation for the
minimum number of output capacitors under a
load transient makes some assumptions:
a) No ESR or ESL
VCC and PVCC capacitor selection
b) Converter can saturate its duty cycle instantly
c) No latency
FS1412 uses on-package capacitors for VCC as well
as PVCC to ensure effective high-frequency
bypassing. However, especially for applications
that use an external VCC supply, it is recommended
that system designers place 2.2μF/0603/X7R/10V
capacitors on the application board as close as
possible to the VCC and PVCC pins (Figure 18).
d) Step load (infinite slew rate)
Assumptions (a), (b) and (c) are liberal, whereas (d)
is conservative. Therefore, in a real application,
additional capacitance may be required to meet
transient requirements and should be carefully
considered by the system designer.
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Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
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Data and specifications subject to change without notice.
FS1412 µPOL™
Figure 14 Peak-peak voltage deviation (PVIN = 12V, VOUT = 0.6V, COUT = 4 x 47 μF)
Figure 15 Peak-peak voltage deviation (PVIN = 12V, VOUT = 1.0V, COUT = 4 x 47 μF)
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Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
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Data and specifications subject to change without notice.
FS1412 µPOL™
Figure 16 Peak-peak voltage deviation (PVIN = 12V, VOUT = 1.8V, COUT = 4 x 47 μF)
Figure 17 Minimum output capacitance
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Data and specifications subject to change without notice.
FS1412 µPOL™
Note:
SALERT and PG require pull-up resistors when used.
Figure 18 Application circuit for a single supply (PVIN = 12V, VOUT = 1.0V, IOUT = 12A)
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Data and specifications subject to change without notice.
FS1412 µPOL™
Typical operating waveforms
Figure 19 Startup with no load (Ch2:PVIN, Ch5:VCC, Ch6: VOUT, Ch7: PGood, Ch8: Enable)
Figure 20 Startup with 12 A load (Ch2:PVIN, Ch5:VCC, Ch6: VOUT, Ch7: PGood, Ch8: Enable)
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Data and specifications subject to change without notice.
FS1412 µPOL™
Figure 21 Shutdown with Enable de-assertion at 12A load
(Ch2:PVIN, Ch5:VCC, Ch6: VOUT, Ch7: PGood, Ch8: Enable)
Figure 22 Soft turn off at no load (Ch2:PVIN, Ch5:VCC, Ch6: VOUT, Ch7: PGood, Ch8: Enable)
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Data and specifications subject to change without notice.
FS1412 µPOL™
Figure 23 Switch node waveforms at no load
Figure 24 Switch node waveforms at 12A
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Data and specifications subject to change without notice.
FS1412 µPOL™
Figure 25 VO ripple at 12A (Ch1:IO, Ch8: VOUT), peak-peak VO ripple = 4.6mV
Figure 26 Transient response 0A to 6A (Ch6: VOUT, Ch8:IO), peak-peak deviation = 53 mV, load slew rate ≈ 40A/µs
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Data and specifications subject to change without notice.
FS1412 µPOL™
Figure 27 Thermal image at PVIN = 12V, VOUT = 1.0V, IO = 12A,
room temperature, no airflow, FS1412 maximum temperature rise = 55.5°C
Page 33
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Copyright © 2021–22 TDK Corporation. All rights reserved.
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Data and specifications subject to change without notice.
FS1412 µPOL™
Layout recommendations
Thermal considerations
FS1412 is a highly integrated device with very few
external components, which simplifies PCB layout.
However, to achieve the best performance, these
general PCB design guidelines should be followed:
The FS1412 has been thermally tested and
modelled in accordance with JEDEC specifications
JESD 51-2A and JESD 51-8. It has been tested using
a 4-layer application PCB, with thermal vias under
the device to assist cooling (for details of the PCB,
refer to the application notes).
•
Bypass capacitors, including input/output
capacitors and the VCC bypass capacitor (if
used), should be placed as close as possible to
the FS1412 pins.
The FS1412 has two significant sources of heat:
•
•
The power MOSFET section of the IC
The inductor
•
•
Output voltage should be sensed with a
separated trace directly from the output
capacitor.
To aid thermal dissipation, the PGnd pad
should be connected to the power ground
plane using vias. Copper-filled vias are
preferred but plated-through-hole vias are
acceptable, provided that they are not covered
with solder mask. VIPPO techniques are
acceptable.
The IC is well coupled to the PCB, which provides
its primary cooling path. Although the inductor is
also connected to the PCB, its primary cooling path
is through convection. The cooling process for both
heat sources is ultimately through convection. The
PCB can be seen as a heat-spreader or, to some
degree, a heat-sink.
•
Adequate numbers of vias should be used to
make connections between layers, especially
for the power traces.
•
•
AGnd pins should be connected by vias to
PGnd copper layer
To minimize power losses and thermal
dissipation, wide copper polygons should be
used for input and output power connections.
SCL and SDA traces must be at least 10mil
wide, with 20–30mil spacing between them.
•
Figure 28 Heat sources in the FS1412
Page 34
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Figure 29 shows the thermal resistances in the
FS1412, where:
The values of the thermal resistances are:
•
•
ϴJA = 20.5°C/W
ϴJCbottom = 5.5°C/W
•
•
•
ϴJA is the measure of natural convection from
the assembled test sample within a confined
enclosure of approximately 30x30x30cm. The
air is passive within this environment and the
only air movement is due to convection from
the device on test.
ϴJCbottom is the heat flow from the IC to the
bottom of the package, to which it is well
coupled. The testing method adopts the
method outlined in JESD 51-8, where the test
PCB is clamped between cold plates at defined
distances from the device.
Although these values indicate how the FS1412
compares with similar point-of-load products
tested using the same conditions and
specifications, they cannot be used to predict
overall thermal performance. For accurate
modeling of the µPOL™’s interaction with its
environment, computational fluid dynamics (CFD)
simulation software is needed to calculate
combined routes of conduction and convection
simultaneously.
Note:
In all tests, airflow has been considered as
passive or static; applications using forced air
may achieve a greater cooling effect.
ϴJCtop is theoretically the heat flow from the IC
to the top of the package. This is not
representative for the FS1412 for two reasons:
firstly, it is not the primary conduction path of
the IC and, more importantly, the inductor is
positioned directly over the IC. As the inductor
is a heat source, generating a similar amount
of heat to the IC, a meaningful value for
junction-to-case (top) cannot be derived.
Figure 29 Thermal resistances of the FS1412
Page 35
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
I2C protocol
S
P
A
=
=
=
=
Start bit
Stop bit
Ack
W
R
Sr
=
=
=
Write bit (‘1’)
Read (‘0’)
Repeated start
White bits
Grey bits
=
=
Issued by master
Sent by slave (FS140x)
N
Nack
Write transaction
1
7
1
1
8
1
8
1
1
P
S
Slave Address
W
A
Register Address
A
Data Byte
A
Read transaction
1
7
1
1
8
1
1
7
1
1
8
1
1
P
S
Slave Address
W
A
Register Address
A
Sr
Slave Address
R
A
Data Byte
N
Page 36
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Supported PMBus™ commands
Code Command
Code Command
VIN_OV_FAULT_LIMIT
01
02
03
15
16
19
1B
20
21
24
25
26
27
29
35
36
39
40
41
42
43
44
45
46
47
4F
OPERATION
55
56
58
5E
60
61
62
63
64
65
78
79
7A
7B
7C
7D
7E
88
8B
8D
98
99
9A
9B
AD
AE
ON_OFF_CONFIG
CLEAR_FAULTS
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
SMBALERT_MASK
VOUT_MODE
VOUT_COMMAND
VOUT_MAX
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VOUT_TRANSITION_RATE
VOUT_SCALE_LOOP
VIN_ON
VIN_OV_FAULT_RESPONSE
VIN_UV_WARN_LIMIT
POWER_GOOD_ON
TON_DELAY
TON_RISE
TON_MAX_FAULT_LIMIT
TON_MAX_FAULT_RESPONSE
TOFF_DELAY
TOFF_FALL
STATUS_BYTE
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
STATUS_TEMPERATURE
STATUS_CML
READ_VIN
READ_VOUT
READ_TEMPERATURE
PMBUS_REVISION
MFR_ID
MFR_MODEL
MFR_REVISION
IC_DEVICE_ID
VIN_OFF
IOUT_CAL_OFFSET
VOUT_OV_FAULT_LIMIT
VOUT_OV_FAULT_RESPONSE
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
VOUT_UV_FAULT_RESPONSE
IOUT_OC_FAULT_LIMIT
IOUT_OC_FAULT_RESPONSE
OT_FAULT_LIMIT
IC_DEVICE_REV
Page 37
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
Package description
The FS1412 is designed for use with standard surface-
mount technology (SMT) population techniques. It
has a positive (raised) footprint, with the pads
being higher than the surrounding substrate. The
finish on the pads is ENEPIG (Electroless Nickel
As a result of these properties, the FS1412 works
extremely well in lead-free environments. The
surface wets easily and the positive footprint
accommodates processing variations.
Note:
Refer to the Design Guidelines for more
Electroless
Palladium
Immersion
Gold).
information about TDK’s µPOL™ package series.
Figure 30 Dimensioned drawings
Page 38
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1412 µPOL™
REMINDERS FOR USING THESE PRODUCTS
Before using these products, be sure to request the delivery specifications.
SAFETY REMINDERS
Please pay sufficient attention to the warnings for safe designing when using these products.
REMINDER
The products listed on this specification sheet are intended for use in general electric equipment (AV equipment, telecommunication
equipment, home appliances, amusement equipment, computer equipment, personal equipment, office equipment, measurement
equipment, industrial robots) under a normal condition and use condition.
The products are not designed or warranted to meet the requirements of the applications listed below, whose performance and/or
quality require a more stringent level of safety or reliability, or whose failure, malfunction or trouble could cause serious damage to
sociality, person or property. Please understand that we are not responsible for any damage or liability caused by use of the products
in any of the applications below or for any other use exceeding the range or conditions set forth in this specification sheet.
1.
Aerospace/Aviation equipment
2.
Transportation equipment (cars, electric trains, ships, etc.)
Medical equipment
3.
4.
Power-generation control equipment
Atomic energy related equipment
Seabed equipment
5.
6.
7.
Transportation control equipment
Public Information-processing equipment
Military equipment
8.
9.
10.
11.
12.
13.
Electric heating apparatus, burning equipment
Disaster prevention/crime prevention equipment
Safety equipment
Other applications that are not considered general-purpose applications
When using this product in general-purpose application, you are kindly requested to take into consideration securing protection
circuit/ equipment or providing backup circuits, etc., to ensure higher safety. To allow flexibility in the applications of the FS1412
device family, some parameters are accessible to the users through an I2C/PMBus™ interface. These parameters can only be changed
within limits that are acceptable to the device. However, it is the responsibility of the user to ensure that any parameter change,
whether it be deliberate or inadvertent, does not violate the specifications of the end user system.
This product is subject to a license from Power One, Inc. related to digital power technology patents
owned by Power One, Inc. Power One, Inc. technology is protected by patents including:
AU 3287379M 3287437AA 3290643AA 3291357AA
CN 10371856C 10452610C 10458656C 10459360C 10465848C 1069332A 11124619A 11346682A
1685299A 1685459A 1685582A 1685583A 1698023A 1802619A
EP 1561156A1 1561268A2 1576710A1 1576711A1 1604254A4 1604264A4 1714369A2 1745536A4
1769382A4 1899789A2 1984801A2
US 20040246754 2004090219A1 2004093533A1 2004123164A1 2004123167A1 2004178780A1
2004179382A1 20050200344 20050223252 2005209373A1 20060061214 2006015619A1
20060174145 20070226526 20070234095 20070240000 20080052551 20080072080 20080186006
6741099 6788036 6936999 6949916 7000125 7049798 7069021 7080265 7249267 7266709 7315156
7372682 7373527 7394445 7456617 7459892 7493504 7526660
WO 04044718A1 04045042A3 04045042C1 04062061A1 04062062A1 04070780A3 04084390A3
04084391A3 05079227A3 05081771A3 06019569A3 2007001584A3 2007094935A3
Page 39
Rev 2.5 July 27, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2; US 11,063,516 B1
Copyright © 2021–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
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