FS1703-3300-AL [TDK]
µPOL™嵌入式DC-DC转换器;
| 型号： | FS1703-3300-AL |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | µPOL™嵌入式DC-DC转换器 DC-DC转换器 |
| 文件： | 总27页 (文件大小：1511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FS1703 µPOL™
3A Rated µPOL™ Buck Regulator with Integrated Inductor
Description
µPOL™ package with output inductor included
DATASHEET
Features
The FS1703 is an easy-to-use, fully integrated and
highly efficient micro-point-of-load (µPOL™) voltage
regulator. The on-chip pulse-width modulation
(PWM) controller and integrated MOSFETs, plus
incorporated inductor and capacitors, result in an
extremely compact and accurate regulator. The
low-profile package is suitable for automated
assembly using standard surface-mount equipment.
Small size: 3.3mm x 3.3mm x 1.5mm
Continuous 3A load capability
Plug and play: no external compensation required
Input voltage range: 4.5V–5.5V
Factory trimmed 3.3V ±0.5% initial accuracy
Supports 3.3V output applications with 5V input
Enabled input, programmable under-voltage
lock-out (UVLO) circuit
Developed by a cross-functional engineering team, the
design exemplifies best practice and uses class-leading
technologies. From early in the integrated circuit
design phase, designers worked with application and
packaging engineers to select compatible
technologies and implement them in ways that
reduce compromise. Developing and optimizing all
of these elements together has yielded the
smallest, most efficient and fully featured
3A µPOL™ currently available.
Open-drain power-good indicator
Built-in protection features
Operating temperature from -40°C to +125°C
Lead-free and halogen-free
Compliant with EU REACH and RoHS
Applications
Storage applications
Telecom, wireless and 5G applications
Networking and datacenter applications
Industrial applications
The built-in protection features include pre-biased
start-up, soft-start protection, over-voltage protection,
thermally compensated over-current protection with
hiccup mode, thermal shut-down with auto-recovery.
Distributed point-of-load power architectures
Computing peripheral voltage regulation
General DC-DC conversion
3.5
3
VOUT
2.5
2
VOUT
VOS
PVIN
PVIN
VIN
VCC
1.5
1
LFM = 0
PGnd
AGnd
0.5
0
PVIN = 5V, VOUT = 3.3V
PG
En
0
20
40
60
80
100
120
Ambient Temperature (°C)
Page 1
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright © 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Pin configuration
1
2
3
4
5
6
13
12
11
10
9
15
14
17
13
12
11
10
9
14
17
15
16
1
2
3
4
5
6
16
7
7
8
8
Figure 1 Pin layout (top view)
Figure 2 Pin layout (bottom view)
Pin functions
Pin
Name Description
Number
1
2
NC
PG
Connect to AGnd.
Power Good status. Open drain of an internal MOSFET.
Pull up to VCC – pin 10 or an external bias voltage – with a 49.9kΩ resistor.
3
4
En
Enable. Switches the FS1703 on and off. Can be used with two external resistors to set an external UVLO
NC
Connect to AGnd.
VOUT sense pin. Connect to VOUT on the application board using an external resistor divider to set
desired output voltage (subject to minimum off time and maximum duty limitations)
5
VOS
6
7
NC
Connect to AGnd.
VOUT Regulator output voltage. Place output capacitors between this pin and PGnd (pin 8).
Power ground. Serves as a separate ground for the MOSFETs. Connect to the power ground plane in the
application.
8, 16
PGnd
9
AGnd Signal ground. Serves as the ground for the internal reference and control circuitry.
10
11
VCC
VIN
Supply voltage. May be an input bias for an external VCC voltage. Tie to the VIN pin externally.
Input voltage. Tie to PVIN through a 2.7Ω resistor.
12,13,14,
17
PVIN Power input voltage. Input for the MOSFETs.
15
VSW
Test point for internal VSW. Connect to an isolated pad on the PCB.
Page 2
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Block diagram
VIN
VCC
AGnd
Low Drop-Out
(LDO)
Regulator
fault
VOUT
En
PVIN
Internal Reference
(Digital-to-Analog
Converter (DAC))
VCC
Pulse Generator
for Pulse Width
Modulaꢀon (PWM)
PVIN
PWM
signal
Soꢁ
HDrv
Start
SS
signal
Gate Drive
Logic and
Deadꢀme
Control
L
OTP fault
VOUT
VCC HDrv
thermal
VCC
LDrv
shut-down
fault
VOS
En
Control
PGnd
and Fault
Logic
PG
power-on reset
Figure 3 FS1703 µPOL™
Typical applications
3.3V
VOUT
VOS
4.5V to 5.5V
PVIN
VIN
VCC
PGnd
AGnd
PG
En
Figure 4 Single supply applications circuit
Page 3
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Absolute maximum ratings
Warning: Stresses beyond those shown may cause permanent damage to the FS1703.
Note:
Functional operation of the FS1703 is not implied under these or any other conditions beyond those stated in
the FS1703 specification.
Reference
Range
PVIN, VIN, En to PGnd
VCC to PGnd
-0.3V to 18V (Note 1, page 6)
-0.3V to 6V (Note 2, page 6)
-0.3V to VCC (Note 2, page 6)
-0.3V to VCC (Note 2, page 6)
-0.3V to +0.3V
VOS to AGnd
PG to AGnd
PGnd to AGnd
ESD Classification
Moisture Sensitivity Level
2kV (HBM JESD22-A114)
MSL 3 (JEDEC J-STD-020D)
Thermal Information
Range
Junction-to-Ambient Thermal Resistance ƟJA
Junction to PCB Thermal Resistance ƟJ-PCB
Storage Temperature Range
22.6°C/W
2.36°C/W
-55°C to 150°C
-40°C to 150°C
Junction Temperature Range
Note:
ƟJA : FS1703 evaluation board and JEDEC specifications JESD 51-2A
J-c (bottom) : JEDEC specification JESD 51-8
Ɵ
Order information
Package details
The FS1703 uses a µPOL™ 3.3 mm x 3.3 mm package delivered in tape-and-reel format, with either 250 or
4000 devices on a reel.
Standard part numbers
Part numbers
VOUT
250 devices on a reel
4000 devices on a reel
3.3
FS1703-3300-AS
FS1703-3300-AL
Page 4
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Recommended operating conditions for various output voltages
Output voltage= 3.3V
Definition
Symbol
Min
Max
Units
Input Voltage Range with external VCC (Note 3, Note 5)
PVIN
4.5
5.5
V
Supply Voltage Range (Note 2)
Continuous Output Current Range
Operating Junction Temperature
VCC, VIN
4.5
0
5.5
3
IO
TJ
A
-40
125
°C
Electrical characteristics
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply over: 4.5V < PVIN < 5.5V, 4.5V < VIN < 5.5V, 0°C < T < 125°C
Typical values are specified at TA = 25°C
Parameter
Symbol
Conditions
Min Typ Max Unit
Supply Current
VIN Supply Current (Standby)
VIN Supply Current (Static)
IIN (STANDBY)
IIN (STATIC)
Enable low
1
No switching, En = 2V
En high, VIN = 5V, VOUT = 3.3V,
FSW = 570kHz
2
mA
VIN Supply Current (Dynamic)
IIN (DYN)
6.3
9
Soft-Start
Soft-Start Rate
Output Voltage
SSRATE (default)
(Note 6)
1
V/ms
%
TJ = 25°C, PVIN = 5V, VOUT = 3.3V (Note 5)
-40°C < TJ < 125°C, PVIN = 5V,
(Note 5), VOUT = 3.3V
±0.5
Accuracy
-1.4
+1.4
On-Time Timer Control
On Time
TON
PVIN = 5V, VOUT = 3.3V, FSW = 570kHz
(Note 6)
1190
50
ns
°C
Minimum On-Time
Thermal Shut-Down
Thermal Shut-Down
Hysteresis
TON(MIN)
TSD (default)
145
25
Under-Voltage Lock-Out
VCC Start Threshold
VCC Stop Threshold
VCC_UVLO(START)
VCC_UVLO(STOP)
En(HIGH)
VCC Rising Trip Level
VCC Falling Trip Level
Ramping Up
3.7 4.0 4.2
3.6 3.8 3.95
1.1 1.2 1.3
V
Enable Threshold
En(LOW)
Ramping Down
0.9
1
1.06
Input Impedance
Current Limit
REN
500 1000 1500 kΩ
Current Limit Threshold
IOC (default)
TJ = 25°C
3.6
4
4.3
A
Page 5
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply over: 4.5V < PVIN < 5.5V, 4.5V < VIN < 5.5V, 0°C < T < 125°C
Typical values are specified at TA = 25°C
Parameter
Symbol
Conditions
Min Typ Max Unit
20 ms
Hiccup Blanking Time
Over-Voltage Protection
TBLK(HICCUP)
Output Over-Voltage Protection
Threshold
VOVP (default)
OVP Detect (Note 6), VOUT = 3.3V
115 120 125 VOS%
Output Over-voltage Protection Delay TOVPDEL
5
µs
Power Good (PG)
Power Good Upper Threshold
Power Good Hysteresis
VPG(UPPER) (default) VOUT Rising to 3.3V
85 90 95
VOS%
mA
VPG(LOWER)
IPG
VOUT Falling from 3.3V
PG = 0.5V, En = 2V
5
9
Power Good Sink Current
Notes
1
2
3
PGnd pin and AGnd pin are connected together
Must not exceed 6V
VIN is connected to VCC to bypass the internal Low Drop-Out (LDO) regulator
and also to PVIN
4
5
Maximum switch node voltage should not exceed 22V
Hot and cold temperature performance is assured by correlation using
statistical quality control, but not tested in production; performance at 25°C is
tested and guaranteed in production environment
6
Guaranteed by design but not tested in production
Page 6
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Temperature characteristics
Output Voltage
VIN Supply Current (Dynamic)
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
Enable Start Threshold
Enable Stop Threshold
VCC Start Threshold
VCC Stop Threshold
Page 7
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
On Time
1.30
Soft-Start Rate
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Current Limit Threshold
Page 8
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Efficiency characteristics
Typical efficiency and power loss
PVIN =4.5V–5.5V, IO = 0A–3A, room temperature, no air flow, all losses included
100
95
90
85
80
75
70
65
60
PVIN = VIN = VCC = 5V
PVIN = VIN = VCC = 4.5V
PVIN = VIN = VCC = 5.5V
0
500
1000
1500
2000
2500
3000
Load Current (mA)
1200
1000
800
600
400
200
0
PVIN = VIN = VCC = 4.5V
PVIN = VIN = VCC = 5V
PVIN = VIN = VCC = 5.5V
0
500
1000
1500
IOUT (mA)
2000
2500
3000
Page 9
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Typical load regulation
PVIN = 4.5V–5.5V, IO = 0A–3A, room temperature, no air flow
Load Current (mA)
0
500
1000
1500
2000
2500
3000
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
PVIN = VIN = VCC = 5V
PVIN = VIN = VCC = 5.5V
PVIN = VIN = VCC = 4.5V
Page 10
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Applications information
Soft-start and target output voltage
The FS1703 has an internal digital soft-start circuit
to control output voltage rise-time and limit current
surge at start-up. When VCC exceeds its start
threshold (VCC_UVLO(START)), the FS1703 exits reset
mode and initialization begins.
Overview
The FS1703 is an easy-to-use, fully integrated and
highly efficient DC/DC regulator. It uses
a
proprietary modulator to deliver fast transient
responses. The modulator has internal stability
compensation so that it can be used in a wide
range of applications, with various types of output
capacitors, without loop stability issues.
Once initialization is complete and the Enable (En)
pin has been asserted (Figure 6), the internal
reference soft-starts to the target output voltage
at 1mV/µs.
During initial start-up, the FS1703 operates with a
minimum of high-drive (HDrv) pulses until the
output voltage increases (see Switching frequency
and minimum values for on-time on page 12). On-
time is increased until VOUT reaches the target value.
Bias voltage
For single-rail operation, the VIN pin of the FS1703
should be connected to the PVIN pin and VCC pin
(Figure 5).
Note:
Until initialization is complete, a small
leakage current (≈3.4µA) will flow from the
device into the output. This may significantly
pre-bias the output voltage in applications
with long VIN/VCC rise times. To prevent this,
a small load capable of sinking 3.4µA should
be connected in such applications.
PVIN
PVIN
VCC VIN
Figure 6 Theoretical operational waveforms
during soft-start
REN1
En
FS1703
REN2
Figure 5 Single supply configuration: internal LDO
regulator, adjustable PVIN_UVLO
Page 11
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Pre-biased start-up
Enable (En) pin
The FS1703 can start up into a pre-charged output
smoothly, without causing oscillations and
disturbances of the output voltage. When it starts up
in this way, the Control and Synchronous MOSFETs
are forced off until the internal Soft-Start (SS)
signal exceeds the sensed output voltage at the VOS
pin. Only then is the first gate signal of the Control
MOSFET generated, followed by complementary
turn on of the Synchronous MOSFET. The Power
Good (PG) function is not active until this point.
The Enable (En) pin has several functions:
It is used to switch the FS1703 on and off. It
has a precise threshold, which is internally
monitored by the UVLO circuit. If it is left
floating, an internal 1MΩ resistor pulls it down
to prevent the FS1703 being switched on
unintentionally.
It can be used to implement a precise input
voltage UVLO. The input of the En pin is
derived from the PVIN voltage by a set of
resistive dividers, REN1 and REN2 (Figure 5).
Users can program the UVLO threshold voltage
by selecting different ratios. This is a useful
feature that stops the FS1703 regulating when
PVIN is lower than the desired voltage.
It can be directly connected to PVIN without
external resistive dividers for some space-
constrained designs. This is a useful feature for
standalone start-up, when no logic signal is
available to enable the FS1703.
Shut-down mechanism
The FS1703 shuts down by de-asserting the En pin.
Both drivers switch off and the digital-to-analog
converter (DAC) and soft-start are pulled down
instantaneously.
Switching frequency and minimum
values for on-time
The switching frequency of the FS1703 is set at the
factory to 570kHz.
As a result, system designers need not concern
themselves with selecting the switching frequency
and have one fewer design task to manage.
When input voltage is high relative to target
output voltage, the Control MOSFET is switched on
for shorter periods. The shortest period for which
it can reliably be switched on is defined by
minimum on-time (TON(MIN)). During start-up, when
the output voltage is very small, the FS1703
operates with minimum on-time.
Figure 7 Start-up:
PVIN, VIN, VCC and En pins tied together,
PG pin pulled up to an external supply
Page 12
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
When the current exceeds the OCP threshold, the
PG and SS signals are pulled low. The Synchronous
MOSFET remains on until the current falls to 0,
then the FS1703 enters hiccup mode (Figure 9).
Both the Control MOSFET and the Synchronous
MOSFET remain off for the hiccup-blanking time.
After this time, the FS1703 tries to restart. If an
over-current fault is still detected, the preceding
actions are repeated. The FS1703 remains in
hiccup mode until the over-current fault is
remedied.
Figure 8 Start-up: En pin asserted after PVIN and VIN,
PG pin pulled up to an external supply
For VOUT to start up as defined by the soft-start rate
requires correct sequencing:
PVIN must start up before VCC and/or Enable.
PVIN must ramp down only after VCC has
ramped down below its UVLO threshold
and/or Enable has been de-asserted.
Figure 9 Illustration of OCP in hiccup mode
Over-current protection (OCP)
Over-voltage protection (OVP)
Over-current protection (OCP) is provided by
sensing the current through the RDS(on) of the
Synchronous MOSFET. When this current exceeds
the OCP threshold, a fault condition is generated.
This method provides several benefits:
Over-voltage protection (OVP) is provided by
sensing the voltage at the VOS pin. When VOS
exceeds the output OVP threshold for longer than
the output OVP delay (typically 5μs), a fault
condition is generated.
Provides accurate overcurrent protection
without reducing converter efficiency
(the current sensing is lossless)
Reduces cost by eliminating a current-sense
resistor
The OVP threshold is set internally to 120% of VOUT
When an OVP condition is detected, the Control
MOSFET is switched off immediately and the PG
pin is pulled low. The Synchronous MOSFET is
switched on to discharge the output capacitor.
Reduces any layout-related noise issues.
The Control MOSFET remains latched off until reset
by cycling either VCC or En. The voltage at the VOS
pin falling below the output OVP threshold (with
5% hysteresis) does not switch on the Control
The OCP threshold is set to 4A.
The threshold is internally compensated so that it
remains almost constant at different ambient
temperatures.
Page 13
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
MOSFET but it does switch off the Synchronous
MOSFET to prevent build-up of negative current.
Power Good (PG)
Figure 11 shows PG behavior.
The PG signal is asserted when:
Figure 10 shows a timing diagram for over-voltage
protection.
En and VCC are both above their thresholds
No fault has occurred
(including over-current, over-voltage and
over-temperature)
VOUT is within the target range
(determined by continuously monitoring
whether VOS is above the PG threshold)
Figure 10 Illustration of latched OVP
Over-temperature protection (OTP)
Temperature sensing is provided inside the
FS1703. The OTP threshold is internally set to
145°C.
Figure 11 PG signal behavior
As can be seen, when VOS rises above the power
good rising threshold (90% of setpoint), the PG
signal is pulled high. When VOS drops below the
power good falling threshold (85% of setpoint), the
PG signal is pulled low.
When the threshold is exceeded, thermal shut-
down switches off both MOSFETs and resets the
internal soft-start, but the internal LDO regulator is
still in operation.
For pre-biased start-up, the PG signal is not active
until the first gate signal of the Control MOSFET is
generated.
Automatic restart is initiated when the sensed
temperature drops within the operating range.
There is a 20°C hysteresis in the OTP threshold.
FS1703 also integrates an additional PMOS in
parallel to the NMOS internally connected to the
PG pin (Figure 3). This PMOS allows the PG signal
to stay at logic low, even if VCC is low and the PG
pin is pulled up to an external voltage not VCC
(Figure 7 and Figure 8).
Page 14
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
noise on PVIN. The VIN pin should be shorted to the
VCC pin, bypassing the internal LDO.
Design example
Let us now consider a simple design example, using
the FS1703 for the following design parameters:
Output voltage and output capacitor
PVIN = VIN = 5V
The FS1703 is supplied pre-programmed and
factory-trimmed in a closed loop to the target
voltage specified for the part number. As a result,
no external resistor divider is required and resistor
tolerances are eliminated from the error budget.
VOUT = 3.3V
FSW = 570kHz
COUT = 3 x 22μF
CIN = 2 x 22μF
Ripple Voltage = ± 1% * VOUT
ΔVOUT(MAX) = ±3% * VOUT
(for 100% load transient)
The design requires minimal output capacitance to
meet the target output voltage ripple and target
maximum output voltage deviation under load
transient conditions.
Input capacitor
For the FS1703, the minimum number of output
capacitors required to achieve target peak-to-peak
The input capacitor selected for this design must:
Handle the peak and root mean square (RMS)
input currents required by the FS1703
Have low equivalent series resistance and
inductance (ESR and ESL) to reduce input
voltage ripple
V
OUT ripple is:
ꢈꢙ ꢉ ꢚꢊ
ꢗꢛꢜꢝꢞ
ꢠꢝꢢ ꢘ ꢜꢝꢞ ꢘ ꢈꢙ ꢉ ꢚꢊꢣ
ꢚ
∆ꢤꢥꢦꢧꢨꢩꢪꢪꢫꢬꢈꢪꢭꢪꢊ
ꢈ
ꢊ
ꢟ ꢠꢝꢡ ꢙ ꢉ ꢚ ꢟ
ꢒꢓꢔꢒ ꢄ ꢕ. ꢖꢗ ꢘ
where:
MLCCs (multi-layer ceramic capacitors) are ideal.
Typically, in 0805 case size, they can handle 2A
RMS current with less than 5°C temperature rise.
NMIN = minimum number of output capacitors
D = duty cycle
C = equivalent capacitance of each output
capacitor
For a buck converter operating at duty cycle D and
output current IO, the RMS value of the input
current is:
FSW = switching frequency
ESR = equivalent series resistance of each
output capacitor
ꢀꢁꢂꢃ ꢄ ꢀꢅ ꢇꢈ1 ꢉ ꢇꢊ
ꢆ
ESL = equivalent series inductance of each
output capacitor
ꢋ
ꢌꢍꢎ
In this application, IO = 3A and ꢇ ꢄ
ꢄ 0.667
∆ꢤꢥꢦꢧꢨꢩꢪꢪꢫꢬꢈꢪꢭꢪꢊ
ꢏꢋ
ꢐꢑ
= target peak-to-peak VOUT ripple
Therefore, IRMS = 1.4A and we can select two 22μF
16V ceramic capacitors for the input capacitors
(C3216X5R1C226M160AB from TDK).
This design uses C2012X5R0J226K125AB from TDK;
this is a 22μF MLCC, 0805 case size, rated at 6.3V.
At 3.3V, accounting for DC bias and AC ripple
derating, it has an equivalent capacitance of 7μF
(C). Equivalent series resistance is 3mΩ (ESR) and
equivalent series inductance is 0.44nH (ESL).
If the FS1703 is not located close to the 12V power
supply, a bulk capacitor (68–330μF) may be used in
addition to the ceramic capacitors.
For VIN, it is recommended to use a 1μF capacitor
very close to the pin. The VIN pin should be
Putting these parameters into the equation gives:
connected to PVIN through
a
2.7Ω resistor.
NMIN = 1.02
Together, the 2.7Ω resistor and 1μF capacitor filter
Page 15
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
To meet the maximum voltage deviation ΔVomax
under a ∆ꢀꢮ load transient, the minimum required
number of output capacitors is:
Assumptions (a), (b) and (c) are liberal, whereas (d)
is conservative. Therefore, in a real application,
additional capacitance may be required to meet
transient requirements and should be carefully
considered by the system designer.
ꢕꢯꢯ ꢘ ꢙꢯꢭꢰ ꢘ ∆ꢔꢱꢣ
∆ꢤꢥꢦꢧꢲꢳꢴ ꢘ ꢤꢥꢦꢧ ꢘ ꢵ
The typical application waveforms in Figure 19 and
Figure 20 show the steady state VOUT ripple as well
as the voltage deviation in response to a 50% load
transient.
where:
∆ꢀꢮ = load step
∆ꢤꢥꢦꢧꢲꢳꢴ = target maximum voltage deviation
ꢤꢥꢦꢧ = output voltage
C = equivalent capacitance of each output
capacitor
It should be noted that even in the absence of a
target VOUT ripple or target maximum voltage
deviation under load transient, at least one 22μF
capacitor is still required in order to ensure stable
operation without excessive jitter.
Again, using C = 7μF, it can be seen that the
minimum number of output capacitors required is
1.96.
Up to six 22μF capacitors may be used in the
design. If more capacitance is required, it is
recommended to use a capacitor with relatively
high ESR (>3mΩ) such as POSCAP or specialty
polymer capacitors.
In our design intended for space-constrained
applications,
C2012X5R0J226K125AB capacitors.
therefore,
we
use
three
It should be noted here that the calculation for the
minimum number of output capacitors under a
load transient makes some assumptions:
VCC capacitor selection
FS1703 uses an on-package VCC capacitor to ensure
effective high-frequency bypassing. The 1μF
capacitor on the VIN pin provides additional
bypassing when the LDO is bypassed by shorting
the VIN pin to the VCC pin.
a) No ESR or ESL
b) Converter can saturate its duty cycle instantly
c) No latency
d) Step load (infinite slew rate)
Page 16
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
CIN
VOUT
PVIN (5V)
PVIN
VIN
V
OUT (3.3V)
VOS
2.7Ω
VCC
COUT
CVcc
49.9k
Ω
PGnd
PG
En
AGnd
CIN
1 X 68uF/25V (opꢀonal)
+ 2 X 22uF/0805/X5R/16V
CVcc
1µF/0603/X5R/10V
COUT
3 X 22µF/0805/X5R/6.3V
Figure 12 Application circuit for a single supply, PVIN=5V, VOUT=3.3V, 3A
Page 17
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Typical operating waveforms
PVIN=5V, VOUT=3.3V, IO=0–3A, room temperature, no airflow
Figure 13 Startup with no load (Ch1:PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8:IOUT
)
Figure 14 Startup with 3A load (Ch1:PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8: IOUT
)
Page 18
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Figure 15 Shutdown with VCC UVLO at 3A load (Ch1: PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8: IOUT
)
Figure 16 Soft turn off at 3A load (Ch1:PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8: IOUT
)
Page 19
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Figure 17 Startup into pre-bias (Ch1: PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8: IOUT
)
Figure 18 Over-current protection and auto-recover to 3A
(Ch1: PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8: IOUT
)
Page 20
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Figure 19 Sw and VOUT ripple at 0A (Ch2: VOUT Ripple, Ch4: Sw)
Figure 20 Sw and VOUT ripple at 3A (Ch2: VOUT Ripple, Ch4: Sw)
Page 21
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Figure 21 Transient response 0A to 1.5A (Ch2: VOUT rIpple, Ch3: IOUT ), peak-peak deviation = 89mV
Figure 22 Thermal image (PVIN=5V, IOUT =3A) – maximum temperature rise = 30°C
Page 22
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Layout recommendations
Thermal considerations
FS1703 is a highly integrated device with very few
external components, which simplifies PCB layout.
However, to achieve the best performance, these
general PCB design guidelines should be followed:
The FS1703 has been thermally tested and
modelled in accordance with JEDEC specifications
JESD 51-2A and JESD 51-8. It has been tested using
a 4-layer application PCB, with thermal vias under
the device to assist cooling (for details of the PCB,
refer to the application notes).
Bypass capacitors, including input/output
capacitors and the VCC bypass capacitor (if
used), should be placed as close as possible to
the FS1703 pins.
The FS1703 has two significant sources of heat:
The power MOSFET section of the IC
The inductor
Output voltage should be sensed with a
separated trace directly from the output
capacitor.
The IC is well coupled to the PCB, which provides
its primary cooling path. Although the inductor is
also connected to the PCB, its primary cooling path
is through convection. The cooling process for both
heat sources is ultimately through convection. The
PCB can be seen as a heat-spreader or, to some
degree, a heat-sink.
Analog ground and power ground are
connected through a single-point connection.
To aid thermal dissipation, the PGnd pad
should be connected to the power ground
plane using vias. Copper-filled vias are
preferred but plated-through-hole vias are
acceptable, provided that they are not filled
with resin or covered with solder mask.
Adequate numbers of vias should be used to
make connections between layers, especially
for the power traces.
Inductor Thermal Output
Inductor
To minimize power losses and thermal
dissipation, wide copper polygons should be
used for input and output power connections.
IC
IC Thermal Output
Figure 23 Heat sources in the FS1703
Page 23
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
Figure 24 shows the thermal resistances in the
FS1703, where:
The values of the thermal resistances are:
ϴJA = 22.6°C/W
ϴJA is the measure of natural convection from
the assembled test sample within a confined
enclosure of approximately 30x30x30cm. The
air is passive within this environment and the
only air movement is due to convection from
the device on test.
ϴJCbottom = 2.36°C/W
Although these values indicate how the FS1703
compares with similar point-of-load products
tested using the same conditions and
specifications, they cannot be used to predict
overall thermal performance. For accurate
modeling of the µPOL™’s interaction with its
environment, computational fluid dynamics (CFD)
simulation software is needed to calculate
combined routes of conduction and convection
simultaneously.
ϴ
JCbottom is the heat flow from the IC to the
bottom of the package, to which it is well
coupled. The testing method adopts the
method outlined in JESD 51-8, where the test
PCB is clamped between cold plates at defined
distances from the device.
Note:
In all tests, airflow has been considered as
passive or static; applications using forced air
may achieve a greater cooling effect.
ϴ
JCtop is theoretically the heat flow from the IC
to the top of the package. This is not
representative for the FS1703 for two reasons:
firstly, it is not the primary conduction path of
the IC and, more importantly, the inductor is
positioned directly over the IC. As the inductor
is a heat source, generating a similar amount
of heat to the IC, a meaningful value for
junction-to-case (top) cannot be derived.
Juncꢀon
Ambient
Juncꢀon-to-case (top)
Top-to-ambient
ϴ
ϴ
topA
JCtop
[low contribuꢀon]
[low contribuꢀon]
Juncꢀon-
to-case
Boꢁom-
to-PCB
PCB-
to-ambient
(PCB)
(boꢁom)
(solder)
ϴ
JCboꢀom
FS1703 µPOL™
External
Figure 24 Thermal resistances of the FS1703
Page 24
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
As a result of these properties, the FS1703 works
extremely well in lead-free environments. The
surface wets easily and the positive footprint
accommodates processing variations.
Package description
The FS1703 is designed for use with standard
surface-mount technology (SMT) population
techniques. It has a positive (raised) footprint, with
the pads being higher than the surrounding
substrate. The finish on the pads is ENiG
(Electroless Nickel Immersion Gold).
Note:
Refer to the Design Guidelines for more
information about TDK’s µPOL™ package series,
including importance guidance on checking the
compatibility of manufacturing processes such
as cleanable flux systems.
3.300
1.140
0.360
> 0.175
> 0.175
1.350
1.350
1 x (1.70 x 0.40)
0.850 0.850
All dimensions subject to +/- 0.100mm tolerance
1 x (0.30 x 0.70)
1 x (1.10 x 0.30)
1.100
0.300
12 x (0.40 x 0.30)
1 x (0.30 x 0.30)
0.700
Figure 25 Dimensioned drawings
Page 25
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
4.00 0.10
8.00 0.10
2.00 0.05
Ø1.50-1.60
3.60
Ø1.50min
Pin 1
0.30 0.05
3.60
1.80
A
Reel capacity
Reel diameter
(number of devices) (dimension A)
4000
250
330 2.0
178 1.0
2.0 0.2
8.5 0.03
102 1.0
Figure 26 Tape and reel pack
Page 26
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1703 µPOL™
REMINDERS FOR USING THESE PRODUCTS
Before using these products, be sure to request the delivery specifications.
SAFETY REMINDERS
Please pay sufficient attention to the warnings for safe designing when using these products.
REMINDER
The products listed on this specification sheet are intended for use in general electric equipment (AV equipment, telecommunication
equipment, home appliances, amusement equipment, computer equipment, personal equipment, office equipment, measurement
equipment, industrial robots) under a normal condition and use condition.
The products are not designed or warranted to meet the requirements of the applications listed below, whose performance and/or
quality require a more stringent level of safety or reliability, or whose failure, malfunction or trouble could cause serious damage to
sociality, person or property. Please understand that we are not responsible for any damage or liability caused by use of the products
in any of the applications below or for any other use exceeding the range or conditions set forth in this specification sheet.
1.
Aerospace/Aviation equipment
2.
Transportation equipment (cars, electric trains, ships, etc.)
Medical equipment
3.
4.
Power-generation control equipment
Atomic energy related equipment
Seabed equipment
5.
6.
7.
Transportation control equipment
Public Information-processing equipment
Military equipment
8.
9.
10.
11.
12.
13.
Electric heating apparatus, burning equipment
Disaster prevention/crime prevention equipment
Safety equipment
Other applications that are not considered general-purpose applications
When using this product in general-purpose application, you are kindly requested to take into consideration securing protection
circuit/ equipment or providing backup circuits, etc., to ensure higher safety.
Page 27
Rev 1.2, July 11, 2022
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–22 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
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