HVC4420F [TDK]
嵌入式控制器;型号: | HVC4420F |
厂家: | TDK ELECTRONICS |
描述: | 嵌入式控制器 控制器 |
文件: | 总59页 (文件大小:474K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Hardware
Documentation
Data Sheet
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HVC 4x Family
Motor Drivers for Control of BLDC,
BDC, or Stepper Motors
Edition July 9, 2021
O??c?t. 1223, 20230
DSH000216_001EN
AT62SI050010-02?03?0?7_-_?00P001D1EENN
DATA SHEET
HVC 4x Family
Copyright, Warranty, and Limitation of Liability
The information and data contained in this document are believed to be accurate and reli-
able. The software and proprietary information contained therein may be protected by
copyright, patent, trademark and/or other intellectual property rights of TDK-Micronas. All
rights not expressly granted remain reserved by TDK-Micronas.
TDK-Micronas assumes no liability for errors and gives no warranty representation or
guarantee regarding the suitability of its products for any particular purpose due to
these specifications.
By this publication, TDK-Micronas does not assume responsibility for patent infringements
or other rights of third parties which may result from its use. Commercial conditions, prod-
uct availability and delivery are exclusively subject to the respective order confirmation.
Any information and data which may be provided in the document can and do vary in
different applications, and actual performance may vary over time.
All operating parameters must be validated for each customer application by customers’
technical experts. Any mention of target applications for our products is made without a
claim for fit for purpose as this has to be checked at system level.
Any new issue of this document invalidates previous issues. TDK-Micronas reserves
the right to review this document and to make changes to the document’s content at any
time without obligation to notify any person or entity of such revision or changes. For
further advice please contact us directly.
Do not use our products in life-supporting systems, military, aviation, or aerospace
applications! Unless explicitly agreed to otherwise in writing between the parties,
TDK-Micronas’ products are not designed, intended or authorized for use as compo-
nents in systems intended for surgical implants into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the
product could create a situation where personal injury or death could occur.
No part of this publication may be reproduced, photocopied, stored on a retrieval sys-
tem or transmitted without the express written consent of TDK-Micronas.
TDK-Micronas Trademarks
– SmartHVC
– easyLIN
Third-Party Trademarks
All brand and product names or company names may be trademarks of their respective
companies.
License Note
If LIN auto-addressing features are used, third-party rights such as EP 1490 772 B
should be considered.
TDK-Micronas GmbH
July 9, 2021; DSH000216_001EN
2
DATA SHEET
HVC 4x Family
Contents
Page
Section
Title
5
1.
Introduction
6
1.1.
1.2.
Features
13
Top Level / Block Diagrams
14
14
15
17
17
18
19
20
21
22
23
24
2.
2.1.
2.2.
Package and Pins
Pin Assignment
Pin List
2.3.
Multifunctional Pins
LGPIO Ports
LIN I/O
2.3.1.
2.3.2.
2.3.3.
2.3.4.
2.4.
MOUT
Alternative Function Description
External Components Circuit Diagrams
2.4.1.
2.5.
2.6.
External Components Circuit Diagrams for BLDC Motor Control
External Components Circuit Diagram for Stepper Motor Control
Package Outline Dimensions
25
25
27
28
29
32
42
3.
Electrical Data
Absolute Maximum Ratings
ESD and Latch-Up
Transient Supply Voltage
Recommended Operating Conditions
Characteristics
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
MOUT Fly-Back Current Derating
44
44
44
44
45
45
46
46
46
46
47
48
48
48
48
49
49
49
49
50
50
4.
4.1.
4.1.1.
4.2.
4.3.
Functional Description
Power Supply
Start-Stop Applications
Voltage Regulators
Operating Modes
Temperature Monitoring
Core
Core Extensions
Debug Interface
Read-Out Protection
Memory Protection Unit
Clock System
4.4.
4.5.
4.5.1.
4.5.2.
4.5.3.
4.5.4.
4.6.
4.6.1.
4.6.2.
4.7.
Clock Supervision
EMI Reduction Module (ERM)
Bus System
4.8.
Memory
Memory Map
Startup ROM
4.8.1.
4.8.2.
4.8.3.
4.8.4.
4.8.5.
Flash Memory
SRAM
NVRAM
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DATA SHEET
HVC 4x Family
Contents, continued
Page
Section
Title
51
52
52
52
53
53
53
53
53
54
54
54
55
55
56
56
57
57
58
58
4.9.
4.9.1.
Power-Bridges / MOUT Ports
BLDC Motor Control
4.9.2.
4.9.3.
4.10.
Stepper Motor Control
BEMF Comparators
Ports
4.10.1.
4.10.2.
4.10.3.
4.10.4.
4.11.
4.11.1.
4.11.2.
4.11.3.
4.11.4.
4.11.5.
4.11.6.
4.11.7.
4.11.8.
4.11.9.
4.11.10.
Low-Voltage General-Purpose I/O (LGPIO)
LIN Port
High-Side BVDD Switch (HSBVDD)
MON Pin
Peripherals
ADC
Clock and Reset System Control
TIMER
LIN-UART
PWMIO
Enhanced PWM (EPWM)
Capture Compare Unit (CAPCOM)
SPI
Digital Watchdog (DWDG)
Window Watchdog (WWDG) and Wake-Up Timer
59
5.
Document History
TDK-Micronas GmbH
July 9, 2021; DSH000216_001EN
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DATA SHEET
HVC 4x Family
Motor Drivers for Control of BLDC, BDC, or Stepper Motors
Release Note: Revision bars indicate significant changes compared to the
HVC 4222F-D2 Data Sheet.
1. Introduction
The HVC 4x family contains a group of highly integrated, intelligent embedded BLDC
motor and stepper motor drivers for direct 12V-battery operation with six integrated half-
bridges. All modules to directly drive PMSM, BLDC, or stepper motors are on chip. The
CPU is a 32-bit Arm® Cortex®-M3 with 1.25 DMIPS/MHz including a Nested Vectored
Interrupt Controller (NVIC). The Integrated Circuit (IC) features a debug interface, timers/
counters, capture compare units, a multichannel A/D converter with integrated program-
mable gain amplifier, an advanced LIN-UART with a LIN 2.x compliant physical layer, lin-
ear temperature sensors, Back Electromotive Force Comparators (BEMFC), and PWM-
controlled motor output (MOUT) ports with diagnostic functions for Permanent Magnet
Synchronous Motors (PMSM), Brushless Direct Current (BLDC) motors, brush-type DC
(BDC) motors or bipolar- and 3-phase stepper motor control. The computation capacity
supports complex motor control algorithms such as Space Vector Modulation (SVM) for
PMSMs. The hardware supports voltage controlled or current regulated bipolar stepper
motor control for full-stepping, half-stepping and micro-stepping mode.
The integrated digital and analog features reduce the number of necessary external
components to a minimum. Different operating modes make it possible to minimize the
current consumption according to the system needs.
The HVC 4x family features a flash program memory with a size of 32 KB or 64 KB, pro-
viding high flexibility in code development, production ramp-up, and in-system re-pro-
grammability. The 64 KB version contains an MPU for memory protection. Grade 1 and
grade 1+ versions exist. Grade 1+ indicates an extended operating temperature range for
high-temperature applications up to 160 °C junction.
Table 1–1: Ordering Information
Part Number
Flash
SRAM Junction Temperature Special Features
HVC 4223F-D2 32 K
HVC 4222F-D2 32 K
HVC 4420F-B1 64 K
HVC 4422F-B1 64 K
2 K
2 K
4 K
4 K
Grade 1
Grade 1
Grade 1
Grade 1
+
+
Memory Protection Unit
Memory Protection Unit
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DATA SHEET
HVC 4x Family
1.1. Features
The following list gives an overview of the features of the HVC 4x family (see Table 1–2
on page 11 for a detailed feature list).
Core and Interrupt System
– CPU: Arm® Cortex®-M3 core with on-chip serial-wire debug interface
(Memory Protection Unit MPU for the 64 KB version)
– Nested Vectored Interrupt Controller (NVIC):
over 20 interrupt lines, each programmable with 8 (3-bit) priority levels.
– 24-bit SysTick timer
– CPU operating modes: ACTIVE, OVERVOLTAGE
– Power-saving modes (CPU inactive): IDLE, SLEEP
– Retention mode for start-stop applications: RETENTION
– Programmable CPU clock of up to 20 MHz
Internal Oscillators:
– Main oscillator: 40 MHz with clock divider and EMI reduction
– Auxiliary oscillator: 35 kHz
Memory
– RAM: 2/4 KB
– Flash: 32/64 KB
– NVRAM: 512 byte (448 byte for customer use)
Functional Safety1)
– For the HVC 4x family there is additional information available how to use the diag-
nostic and safety features of the IC on top of the standard AEC-Q100 requirements.
This functional safety readiness results in additional documentation like FMEDA sum-
mary report and a dedicated Functional Safety Manual.
– The Functional Safety Manual describes, how to implement the Application Software
and Application itself in order to correctly and beneficially utilize the regarding device
features. The Functional Safety Manual provides information to support customers to
realize an ISO 26262 compliant system using the HVC 4x family as a QM hardware
part inside functional safety applications.
– The FMEDA summary report describes the assumed Safety Goal, the corresponding
Failure Modes as well as the base failure rates according to IEC TR 62380.
1) The HVC family members are developed as QM part with respect to ISO 26262.
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DATA SHEET
HVC 4x Family
Advanced Motor Control
– One enhanced PWM (EPWM) module with 12-bit resolution and six outputs to control
either a BLDC motor with six half-bridges (B6 configuration) or a bipolar stepper
motor with four half-bridges. The module supports center- and edge-aligned mode
with automatic dead-time insertion.
– Three high-voltage Back Electromotive Force Comparators (BEMFC) are supporting
zero crossing detection for sensorless BLDC motor control with integrated virtual star
point reference. Furthermore, the three comparators can be used for closed-loop cur-
rent control with bipolar stepper motors or alternatively for BEMF voltage measure-
ments with stepper motor for commutation and / or stall detection.
– Integrated phase current measurement for bipolar stepper motor control with closed-
loop current control.
– Two 8-bit DACs used as reference for current limitation (CLDAC) for bipolar stepper
motors in closed-loop current control.
– One 12-bit ADC with HW trigger option:
Five external inputs (four single ended and one differential) + VBVDD + VMON
+
linear temperature sensor + input for motor current sensing + inputs for stepper
motor stall detection + inputs for LIN Auto-Addressing (BSM).
– ADC reference: internal band-gap reference
– One integrated Programmable Gain Amplifier (PGA) as part of the ADC signal path.
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DATA SHEET
HVC 4x Family
High-Current Drivers and Phase Sensing
– MOUT ports:
Six half-bridges with integrated charge pump for motor control, connected each to one
MOUT port. Bridge configuration for either BLDC motor, BDC motor(s), or bipolar
stepper motor by connecting the MOUT ports accordingly.
– MVSS0 and MVSS1 pins to connect an external shunt resistor to ground for current
measurement e.g. in BLDC motor control applications.
– Integrated bridge current measurement for bipolar stepper motor closed-loop current
control and overcurrent detection.
– Phase voltage sensing via the integrated BEMF comparators (BEMFC).
MOUT (Motor Output) Ports – Protection and Diagnosis
– Power-bridge open load detection with BEMFCs.
– Power-bridge overcurrent protection: The concerned half-bridge or all six half-bridges
are automatically switched off in an overcurrent condition.
Other Analog Peripherals
– HSBVDD port:
High-side switch to battery supply (BVDD) with overcurrent protection for power supply
of external devices (e.g. Hall sensors).
– Thermal shutdown at overtemperature.
– Supply supervision: undervoltage reset, VBAT and BVDD under/overvoltage supervision
with alarm interrupt.
– Voltage supervision possible by software up to load dump voltage (application SW has
to limit the power consumption with respect to the limits of the thermal budget).
– Start-stop applications supported by RETENTION mode.
– Two overtemperature detection units (placed close to power-bridge).
– One linear temperature sensor readable by the ADC.
– One overtemperature detection unit for return from overtemperature shutdown.
Input and Output
– Low-voltage General-Purpose I/O (LGPIO) ports:
General purpose I/O ports with 3.2 V digital I/O (digital input: floating, weak pull-up or
pull-down, digital output: push-pull or open drain) and analog input function.
– LIN 2.x physical layer interfaces (pins LIN, LIN_O). Including hardware provisions to
support LIN Auto-Addressing.
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DATA SHEET
HVC 4x Family
Communication
– LIN telegram supporting UART with automatic baud rate adjustment and receive/
transmit FIFOs, usable for LIN slave operation.
– Synchronous Serial Peripheral Interface (SPI), master mode only.
– Special PWM module (PWMIO), e.g. for customer specific bus communication. The
module can be accessed either via LGPIO alternative functions or the LIN pin. If LGPIO
ports shall be used the ESD-protection and open-drain architecture must be applied by
external components.
Timers and Counters
– One Capture Compare (CAPCOM) unit with three channels and one 16-bit free-run-
ning counter.
– Two 16-bit timer modules: usable as timer, counter, input capture, or PWM output.
Miscellaneous
– Digital watchdog clocked with the system clock fSYS
.
– Window watchdog and wake-up timer clocked with the auxiliary oscillator clock fAUX
– Power supply voltage (VBVDD):
.
• Nominal: 8 V to 18 V
• With degraded analog parameters from 5.4 V to 8 V. From 18 V to 40 V with limited
BVDD current according to thermal power budget boundaries.
• Support of jump-start and load-dump requirements.
– 5 V LDO pre-regulator with support of start-stop applications.
– RAM data retention to support crank-pulse / start-stop applications.
– Automotive AEC-Q100 Grade 1 qualified
– Extended junction temperature range: 40 °C to 160 °C
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DATA SHEET
HVC 4x Family
LIN Auto-Addressing Support
– In applications where LIN Auto-Addressing is required, either by a need for plug&play
or “off-the-shelf” requirements, the HVC can support by a dedicated IP set. With mini-
mized additional software effort, a LIN slaves’ node address is automatically deter-
mined. This helps reducing additional cost for mechanical- or application-related
implementations.
– To utilize device with LIN Auto-Addressing enabled, a dedicated license fee has to be
agreed with TDK-Micronas
– An agreement results in a dedicated hardware version where LIN Auto-Addressing is
enabled.
– Please contact your local sales support for additional information.
TDK-Micronas GmbH
July 9, 2021; DSH000216_001EN
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DATA SHEET
HVC 4x Family
Table 1–2: HVC 4x family feature list
Item
HVC 4x family with integrated motor bridges
Core and Interrupt System
CPU
ArmCortex-M3
Memory Protection Unit for 64 KB flash version
ACTIVE, OVERVOLTAGE
IDLE, SLEEP
CPU active operation mode
CPU power saving modes
Retention mode to support start-stop applications
RETENTION
CPU clock (fCPU
)
Up to 20 MHz
Interrupt Controller
HVC 422xF
NVIC with 22 interrupt lines, 8 priority
levels
HVC 442xF
NVIC with 23 interrupt lines, 8 priority
levels
EMI reduction module
Integrated Oscillators
Selectable in CPU ACTIVE operating modes
40 MHz main oscillator with clock divider
35 kHz auxiliary oscillator
Memory
RAM
HVC 422xF
HVC 442xF
HVC 422xF
HVC 442xF
2 KB
4 KB
Flash / ROM
32 KB flash
64 KB flash
Startup ROM
1 KB (includes utility routines for flash erase and program)
512 byte (448 byte for customer use)
NVRAM1)
Advanced Motor Control
Enhanced PWM module with up to six outputs and
up to 12-bit resolution to control either a B6 bridge
configuration for BLDC motor or a four half-bridge
configuration for bipolar stepper motor control. The
module supports center- and edge-aligned mode
with automatic dead-time insertion
1
High-voltage Back Electromotive Force Comparator
(BEMFC) for diagnostics, BEMF zero crossing
detection and closed-loop current control
3
BEMF comparator reference
Integrated virtual star point resistor network or Current Limit DAC (CLDAC).
Motion feedback for sensored rotor position detection E.g. via Hall sensor switches connected to LGPIO ports.
One 12-bit ADC with Programmable Gain Amplifier
(PGA) and HW trigger option
Inputs for VBAT + VBVDD + linear temperature sensor + input for motor current
shunt voltage sensing + differential inputs for stepper motor stall detection +
LIN current sense + four LGPIO ports single-ended input + 2 LGPIO ports for
differential input3) + LIN auto-addressing (according to bus-shunt method)
ADC reference
Internal (band gap)
1
Resistor network serving as virtual star-point refer-
ence to the BEMF comparator
Protection and Diagnosis
MOUT overcurrent protection
Overtemperature protection
VBVDD overvoltage detection
Yes
Yes
Yes
Differential port for motor current shunt measurement Yes
Phase current sensing
BLDC motor control: with external shunt connected to MVSS0 and MVSS1
Stepper motor control: integrated current measurement
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DATA SHEET
HVC 4x Family
Table 1–2: HVC 4x family feature list, continued
Item
HVC 4x family with integrated motor bridges
Integrated High-Current Drivers
Integrated charge pump with charge pump capacitor Yes
pin VCP
MOUT ports
Six fully integrated half-bridges. Configurable by external connection of MOUTx
pins for BLDC, BDC or bipolar stepper motor control.
Other Analog Peripherals
HSBVDD port: High-side switch to battery supply
(BVDD) with overcurrent protection for power supply
of external devices (e.g. hall sensors)
Yes
Overtemperature supervision for Thermal Shutdown Yes
(TSD) with two overtemperature detection (OTD)
units
Overtemperature detection unit for return from TSD Yes
Linear temperature sensor readable by ADC
1
Supply supervision: undervoltage reset, VBAT over-/
undervoltage alarm interrupts. Voltage supervision
possible by software beyond 18V with limited BVDD
supply current according to thermal budget limitations.
Yes
Communication
LIN-UART with automatic baud rate adjustment and
receive/transmit FIFOs
1
SPI module
1
1
PWMIO module
Input and Output
LGPIO ports (general purpose I/O) with 3.2 V digital 11 ports
I/O (push-pull or open drain mode).
One LGPIO port pair usable as 3.2 V differential analog input.2)
Four ports usable as 3.2 V single-ended analog input.
LIN 2.x physical layer interfaces (LIN, LIN_O).
Including support of LIN Auto-Addressing.
1
Alternatively usable as PWM communication interface with PWMIO module.
Timers and Counters
24-bit SysTick timer
1
1
CAPCOM unit with three channels and 16-bit free
running counter
16-bit timers usable as timer, counter, capture input,
output compare or PWM output
2
Miscellaneous
Digital watchdog clocked with the system clock fSYS Yes
Window watchdog and wake-up timer clocked with
Yes
the auxiliary oscillator clock (fAUX
)
5V LDO pre-regulator
Yes, can be used to drive external 5V loads at SMPSI pin
Support of start-stop function (RETENTION mode)
Yes
Package
PQFN6x6, 40 pins
TJ temperature range
HVC 4223F and HVC 4420F
HVC 4x22F
40 °C TJ 150 °C
40 °C TJ 160 °C
1) NVRAM is a non-volatile memory which is used to store non-volatile application data and to configure basic functions of the system,
like operating status of digital and window watchdogs after reset, etc.
2) The differential input LGPIO8/9 is not calibrated and has only limited accuracy.
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DATA SHEET
HVC 4x Family
1.2. Top Level / Block Diagrams
AVDD AVSS
DVDD
DVSS
VCP
SMPSI
SMPSO
BVSS1
BVDD
12-bit EPWM0
12-bit EPWM1
12-bit EPWM2
REG_DIG
VDVDD
REG_ANA
VAVDD
5 V
LDO
Charge Pump
MVDD0
MVDD1
VSMPSI
REG_STBY
VSVDD
BVSS0
SVDD
half-bridges
MOUT0
BVDD
Monitoring
Temperature
MOUT1
MON
VBAT
Monitoring
Monitoring
MOUT2
MOUT3
Arm® Cortex®-M3
CPU
Flash Memory
32/64 KB
fCPU
BEMFC 0
BEMFC 1
BEMFC 2
current sensing
MOUT4
MOUT5
NVIC
zero-cross ref.
SDA
SCK
Data SRAM
2/4 KB
Debug
Interface
BEMFC Reference
8-Bit DAC 0
MVSS1
diagnosis /
protection
MVSS0
TRACE_SWO
NVRAM
8-Bit DAC 1
512 byte
TEST
TEST
Controller
(128 x 32-bit)
BVSS2
BVSS3
Diagnosis
Temp. Sens. Bridge
&
Startup ROM
Protection
AHB2APB
Bridge
35 kHz
fAUX
Aux. Oscillator
MVSS0
MVSS1
STDA+/-
Digital
Watchdog
40 MHz
Main Oscillator
fSYS
:2
STDB+/-
ADC0 to ADC3
12-Bit ADC
Window Watchdog
Wake Timer
PGA
ERM
ADC4 +/-
VMON
VBVDD
System Control
Clock
Setup
fSYS
fCPU
fCP
Temp.Sensor
LIN current sense +/-
APB Bus
SPI
LGPIOx
11
CAPCOM
LIN
LIN-UART
16-bit Counter
Channel 0
Channel 1
Channel 2
LIN_DI/ LIN_DO
16-bit Timer 0
16-bit Timer 1
HSBVDD
LIN_O
LIN
Output
PWMIO
Fig. 1–1: Block diagram of the HVC 4x family
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DATA SHEET
HVC 4x Family
2. Package and Pins
2.1. Pin Assignment
Pin Name
Pin
No.
Pin
No.
Pin Name
LGPIO4 21
20 SDA
LGPIO5 22
LGPIO6 23
LGPIO7 24
LGPIO8 25
LGPIO9 26
LGPIO10 27
MOUT5 28
MOUT3 29
MVSS1 30
MOUT2 31
MVDD1 32
BVSS3 33
VCP 34
19 SCK
18 LGPIO3
17 LGPIO2
16 LGPIO1
15 LGPIO0
14 AVDD
13 AVSS
12 DVSS
11 DVDD
10 TEST
21
30
20
11
31
40
9
8
7
6
5
4
3
2
1
SMPSI
SMPSO
BVSS1
BVDD
1
10
LIN 35
BVSS0 36
LIN_O 37
MON
HSBVDD
MOUT4
MOUT1
MVSS0
BVSS2 38
MVDD0 39
MOUT0 40
Fig. 2–1: Pin assignment of the HVC 4x family in PQFN40 package.
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DATA SHEET
HVC 4x Family
2.2. Pin List
Table 2–1 shows the primary functions of the pins of the HVC 4x family.
Refer to Table 2–2 for the alternative functions assigned to the I/O pins.
Table 2–1: Pin description
Name
Type1) Module / Function2)
Power Supply Pins
BVDD
P
Positive power supply (14 V nominal)
BVSS0
BVSS1
BVSS2
BVSS3
AVDD
P
P
P
P
P
P
P
P
Battery ground
Internally connected to EPAD. Must be connected to BVSS0
Must be connected to BVSS0
Must be connected to BVSS0
Output of the internal AVDD regulator (must be buffered by an external capacitor to AVSS)
Analog ground
AVSS
SMPSI
SMPSO
Internally connected to SMPSO (must be buffered by an external capacitor to BVSS1)
Output of 5 V LDO. Pin is internally connected to pin SMPSI and therefore can be left
open. For compatibility reasons with HVC 4223F Bx, this pin may also be externally
shorted to SMPSI.
DVDD
DVSS
P
P
Output of the internal DVDD regulator (must be buffered by an external capacitor to DVSS)
Digital ground
Power Supply Pins for Integrated Half-Bridges
MVDD0
MVDD1
MVSS0
MVSS1
VCP
P
P
P
P
P
Positive power supply of half-bridges. Pins must be shorted with low impedance on the PCB.
Common ground of half-bridges;
BLDC motor control: Both connected to system ground with one shunt.
Stepper motor control: Both connected to system ground. No external shunt necessary.
Output of the internal charge pump (must be buffered by an external capacitor to BVDD)
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DATA SHEET
HVC 4x Family
Table 2–1: Pin description, continued
Name
Type1) Module / Function2)
Application Pins
SDA
I/O
Debug interface data (in application mode the pin can be left open due to the internal
weak pull-up resistor)
SCK
I
Debug interface clock (in application mode the pin can be left open due to the internal
weak pull-down resistor)
MON
I
Supply voltage supervision input. If not used for VBAT supervision, the MON pin shall be
connected to BVDD.
LGPIO0 to
LGPIO10
I/O
3.2 V digital I/O
Input: floating, weak pull-up or weak pull-down
Output: push-pull, open-drain
The LGPIO ports 0 to 3 can be used as single ended 3.2 V analog input. The ports
LGPIO8 and LGPIO9 together as 3.2 V differential analog input 3)
.
If not used in the application the pins can be left open. To avoid cross-currents it is recom-
mended to activate the internal weak pull-down resistors for unused LGPIO pins. Alterna-
tively, connect unused pins to GND.
MOUT0 to
MOUT5
O
O
I/O
P
Outputs of the six half-bridges, whereas one MOUTx connects to one half-bridge each
(refer to block diagram Fig. 1–1 on page 13)
LIN_O
LIN output for LIN Auto-Addressing purpose (together with the LIN pin). If not used, the
LIN_O pin can be connected to LIN or left open.
LIN
LIN transceiver I/O. Alternatively VBAT open drain digital I/O for PWM communication
function.
HSBVDD
TEST
High-side switch to BVDD supply.
If not used in the application this pin should be connected to BVDD.
I
Test pin
In application mode it is recommended to connect the pin to GND.
Exposed Pad (chip back-side area for thermal coupling of the device to the PCB)
-/-
-/-
The exposed pad is directly connected to the substrate at the chip backside. It is recom-
mended to connect the exposed pad to GND.
1) Types are defined as: I = Input, O = Output, P = Power
2) Refer also to Fig. 2–2 on page 22 and Fig. 2–3 on page 23 for the recommended circuitry
3) The differential input LGPIO8/9 is not calibrated and has only limited accuracy.
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DATA SHEET
HVC 4x Family
2.3. Multifunctional Pins
2.3.1. LGPIO Ports
The LGPIO ports (LGPIO0 to LGPIO10) are implemented as low-voltage general-purpose
I/Os. Each LGPIO port can be separately configured to operate in one of several input or
output modes.
All LGPIO ports are configurable in three different digital input modes (floating, weak pull-
up or pull-down) whereas the analog input mode is only available for LGPIO0 to LGPIO3
(single ended analog input) and LGPIO8/9 (differential analog input). In digital input mode
the input level of the LGPIO ports is signaled in the data input register of the LGPIO mod-
ule (LGPIOx.DI) and is in parallel available as input signal for internal digital peripherals
(refer to Table 2–2). In analog input mode the input voltage of the according port is routed
to the ADC input multiplexer and the corresponding bit in LGPIOx.DI is set to '0'.
All LGPIO ports are configurable in two digital output modes (push-pull or open drain)
and additionally the ports can be separately configured to operate in normal output
mode or alternative output mode. In normal output mode the level of the LGPIO ports is
defined by the data output register of the LGPIO module (LGPIOx.DO). In alternative
output mode the level of the LGPIO ports is driven by output signals generated from
internal digital peripherals. For each LGPIO port there are two alternative output signals
available. Table 2–2 shows the functions which can be assigned to the LGPIO pins.
Table 2–2: LGPIO pin function assignments
Pin Function LGPIO
Pin
Name
Analog
Input
Normal
Input
Normal Out-
put
Alternative
Output#0
Alternative
Output#1
Alternative
Inputs
3.2 V digital input (floating, pull-up or pull-down), 3.2 V digital output (push-pull or open drain), 3.2 V analog input
1)
LGPIO0
LGPIO1
LGPIO2
LGPIO3
LGPIO4
LGPIO5
LGPIO6
LGPIO7
LGPIO8
LGPIO9
LGPIO0.DI
LGPIO1.DI
LGPIO2.DI
LGPIO3.DI
LGPIO4.DI
LGPIO5.DI
LGPIO6.DI
LGPIO7.DI
LGPIO8.DI
LGPIO9.DI
LGPIO0.DO
LGPIO1.DO
LGPIO2.DO
LGPIO3.DO
LGPIO4.DO
LGPIO5.DO
LGPIO6.DO
LGPIO7.DO
LGPIO8.DO
LGPIO9.DO
CAPCOM0_OUT TIMER0_OUT
CAPCOM1_OUT TIMER1_OUT
CAPCOM2_OUT TRACE_SWO
CAPCOM0_IN , TIMER0_IN ADC0
1)
CAPCOM1_IN , TIMER1_IN ADC1
1)
CAPCOM2_IN
ADC2
1)
TIMER0_OUT
TIMER1_OUT
TRACE_SWO
PWMIO_OUT
SPI_CSN
TRACE_SWO
LINUART_TX
TIMER0_IN , LINUART_RX
ADC3
1)
1)
TIMER1_IN , SPI_MISO
-
1)
CAPCOM0_OUT
CAPCOM1_OUT
CAPCOM2_OUT
TRACE_SWO
TRACE_SWO
PWMIO_OUT
PWMIO_IN , CAPCOM0_IN
-
CAPCOM1_IN
-
CAPCOM2_IN
-
-
SPI_SCK
ADC4+
ADC4-
-
1)
SPI_MOSI
PWMIO_IN, LINUART_RX
LGPIO10 LGPIO10.DI LGPIO10.DO LINUART_TX
SPI_MISO
1)
Selectable by MUX setting for Alternative Input Select (LGPIO_AIS).
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DATA SHEET
HVC 4x Family
2.3.2. LIN I/O
The LIN port is mainly used to drive the output via the physical LIN 2.x interface for the
communication via the LIN bus. In addition to the LIN I/O function of the port, alternative
output or input functions can be assigned according to Table 2–3 on page 18.
An incoming LIN message can be used as wake signal for the system in the power-saving
modes (IDLE and SLEEP).
Table 2–3: LIN I/O function assignment
Pin Function LIN I/O
Pin
Normal
Input
Normal Out- Alternative
put Output#0
Alternative
Output#1
Alternative
Output#2
Alternative
Input
Name
LIN Transceiver I/O
LIN 1) 2)
LIN_O
LINUART_RX LINUART_TX PWMIO_OUT TIMER0_OUT LIN_DO
PWMIO_IN, LIN_DI
For slave node position detection together with LIN pin. Connected internally via series resistor to LIN port.
1) The LIN pin can be alternatively used for PWM communication with the PWMIO module (selectable by MUX setting).
2) The LIN can be used as wake-port in the power saving modes (IDLE and SLEEP).
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DATA SHEET
HVC 4x Family
2.3.3. MOUT
The MOUT ports (MOUT0 to MOUT5) are implemented as high-current outputs for direct
motor operation. The ports are driven by the integrated power bridges and can be con-
figured either in paired mode (for BLDC motors) or separated mode (for stepper motors).
Table 2–4 shows the functions which can be assigned to the MOUT ports.
Table 2–4: Motor half-bridge outputs
Pin
Name
Controlled
Transistor
Pin Output Function
Analog I/O
BLDC
Stepper
EPWM Module
Comparator and Reference
EPWM Module
Phase
Phase
Assignment
BLDC
Stepper
Assignment
MOUT0 high-side
low-side
EPWM_HS(0)
EPWM_LS(0)
EPWM_HS(1)
EPWM_LS(1)
EPWM_HS(2)
EPWM_LS(2)
EPWM_HS(3)
EPWM_LS(3)
EPWM_HS(4)
EPWM_LS(4)
EPWM_HS(5)
EPWM_LS(5)
U
EPWM_HS(0)
A1
BEMFC0,
integrated
star point
resistor net-
work.
Integrated
phase current
measure-
ment. Refer-
ence with
EPWM_LS(0)
EPWM_HS(1)
EPWM_LS(1)
EPWM_HS(2)
EPWM_LS(2)
EPWM_HS(3)
EPWM_LS(3)
EPWM_HS(4)
EPWM_LS(4)
EPWM_HS(5)
EPWM_LS(5)
MOUT1 high-side
low-side
A2
CLDAC0.
MOUT2 high-side
low-side
V
B1
BEMFC1,
integrated
star point
resistor net-
work.
Integrated
phase current
measure-
ment. Refer-
ence with
MOUT3 high-side
low-side
B2
CLDAC1.
MOUT4 high-side
low-side
W
Not used
BEMFC2,
integrated
star point
resistor net-
work.
Integrated
phase current
measure-
ment. Refer-
ence input
configurable
for CLDAC0 or
CLDAC1.
MOUT5 high-side
low-side
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DATA SHEET
HVC 4x Family
2.3.4. Alternative Function Description
The table below describes all special function designators used in the tables above.
Table 2–5: Alternative function descriptions
Name
Function
ADCx
Analog input connected to ADC input multiplexer [x: 0 to 4]
Input of BEMF comparator x [x: 0 to 2]
BEMFCx
CAPCOMx_IN
CAPCOMx_OUT
Capture input of the CAPCOM channel x [x: 0 to 2]
Compare output of the CAPCOM channel x [x: 0 to 2]
Enhanced PWM module output according to MOUTx [x: 0 to 5]
EPWM_HS(x),
EPWM_LS(x)
LGPIOx.DI
LGPIOx.DO
LINUART_RX
LINUART_TX
LIN_DI
LGPIO port data input register [x: 0 to 10]
LGPIO port data output register [x: 0 to 10]
Receive input line of the LIN-UART
Transmit output line of the LIN-UART (connected to LIN port output multiplexer)
LIN port input register (to LIN transceiver receive input)
LIN port data output (connected to LIN port output multiplexer)
Output of the PWMIO module
LIN_DO
PWMIO_OUT
PWMIO_IN
TIMERx_IN
TIMERx_OUT
TRACE_SWO
SPI_SCK
Input of the PWMIO module
TIMER module x input [x: 0 to 1]
TIMER module x output [x: 0 to 1]
Trace Data Single Wire Output
SPI clock
SPI_MOSI
SPI_MISO
SPI_CSN
SPI Master Out Slave In
SPI Master In Slave Out
SPI Chip Select
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DATA SHEET
HVC 4x Family
2.4. External Components Circuit Diagrams
If using the device in the extended temperature range, the application developer is
responsible for verifying the external circuit parameters over production, voltage and
temperature variation to fulfill the following requirements:
– The VSMPSI voltage must not exceed 7.5 V in order to avoid triggering the ESD pro-
tection of the SMPSI pin.
– In order to bypass the internal linear regulator, the VSMPSI voltage should be greater
than VSMPSI(max). If the externally supplied voltage on SMPSI is lower than the inter-
nal pre-regulator voltage, the bypass is not effective.
– The total output current of the SMPSI pin must be within the specification limits
(parameter Iout total).
– The internal 5V regulator at the pin SMPSI must only be bypassed in ACTIVE and
OVERVOLTAGE mode and therefore it must be possible to disable the bypass circuit
e.g. by the HSBVDD pin. Turning on the HSBVDD port will switch on the external NPN
transistor which then overdrives the SMPSI node to reduce the internal current flow-
ing from BVDD to SMPSI. The bypass circuit with NPN transistor (10) in Fig. 2–2 and
Fig. 2–3 is one suggestion to bypass the internal regulator. The customer might apply
a specific circuit fulfilling the afore mentioned properties. TDK-Micronas shall review
the customer schematic to confirm its principle function. The customer must provide
simulation and measurement results to confirm its function within the range of the
device specification.
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DATA SHEET
HVC 4x Family
2.4.1. External Components Circuit Diagrams for BLDC Motor Control
V
BAT
8)
C
(50 V type)
VCP
VCP
Pump Capacitor
7)
7)
C
mon_ext
Charge
Pump
MVDD0
MVDD1
MON
R
mon_ext
10)
V
SUP B
BVDD
SVDD
100nF
2)
3.0 V
1 µF
integrated
half-bridges
BVSS0
BVSS1
SMPSO
MOUT0
GND
MOUT1
MOUT2
10)
BLDC
Motor
5 V
SMPSI
MOUT3
MOUT4
LDO
C
SMPS
(10 V type
MOUT5
SR =50 m)
AVDD
AVSS
5 V
1.8 V
C
AVDD
BVSS2
BVSS3
DVDD
(6.3 V type)
9)
Ferrite bead
1 k @100 MHz
5 V
3.2 V
GND
DVSS
AVDD
1)
shunt resistor
MVSS1
MVSS0
C
DVDD
(6.3 V type)
DVDD
SDA
GND
6)
Ferrite bead
4)
LIN
LIN bus
5)
6)
serial-wire debug interface
V
C
8)
SCK
BUS
LIN
GND
GND
HSBVDD
GND
LIN_O
3)
4)
LIN bus (output)
exposed pad
(chip backside)
TEST
GND
GND
Notes: All capacitors are ceramic types. Refer to the “Recommended Operating Conditions” for the resistor, inductor and capacitor values.
Blocking capacitors have to be placed as close as possible to the pins.
1)
Choose the shunt resistor value according to the application needs and the limits specified in “Electrical Data” section, respectively.
2)
Choose the BVDD capacitor value according to the application needs, e.g. if the NVRAM shall be programmed after V
undervoltage interrupt threshold.
has dropped below the
BVDD
3)
4)
5)
6)
To control SMPSI pass transistor
In applications with LIN auto-addressing the LIN pin is the input of the LIN bus and LIN_O the output to the LIN bus.
It is recommended to provide access to the debug interface in the customer application HW for the purpose of analysis.
Components to be applied for specific EMC tests and/or to be compliant to different OEM requirements. Refer also to corresponding standards and
test specifications.
7)
The resistor is required to limit the input current for negative input voltages relative to V
. The capacitor filters the noise coming from V
.
BVSS0
BAT
If the MON is not used in the application, it should be connected to BVDD (pin is protected against reverse polarity and input current is minimized).
A TVS diode or sufficiently dimensioned capacitor is recommended with respect to ISO7637-2:2004 Pulse 2a.
8)
9)
A ferrite bead is recommended to be conform with the EME requirements of some OEMs. An impedance of 1 k @ 100 MHz is recommended.
10)
Optional circuitry to reduce internal power dissipation. Contact TDK-Micronas for the recommended dimensioning and type of the external
components.
Fig. 2–2: Recommended circuitry for BLDC motor control
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DATA SHEET
HVC 4x Family
2.5. External Components Circuit Diagram for Stepper Motor Control
V
BAT
7)
C
(50 V type)
VCP
VCP
Pump Capacitor
6)
C
mon_ext
Charge
Pump
MVDD0
MVDD1
MON
6)
mon_ext
10)
R
V
BVDD
SUP B
SVDD
100nF
3.0 V
2)
1µF
integrated
half-bridges
BVSS0
MOUT0
MOUT1
MOUT2
MOUT3
MOUT4
MOUT5
GND
BVSS1
Stepper
Motor
10)
SMPSO
5 V
LDO
SMPSI
C
SMPS
(10 V type,
ESR 50 m
AVDD
AVSS
5 V
1.8 V
C
AVDD
BVSS2
BVSS3
DVDD
(6.3 V type)
8)
Ferrite bead
1 k @100 MHz
5 V
3.2 V
GND
AVDD
DVSS
DVDD
MVSS1
MVSS0
C
DVDD
(6.3 V type)
1)
GND
SDA
9)
4)
LIN
Ferrite bead
LIN bus
5)
9)
serial-wire debug interface
SCK
V
C
7)
BUS
LIN
3)
GND
LIN_O
HSBVDD
GND
GND
4)
LIN bus (output)
exposed pad
(chip backside)
TEST
GND
GND
Notes: All capacitors are ceramic types. Refer to the “Recommended Operating Conditions” for the resistor, inductor and capacitor values.
Blocking capacitors have to be placed as close as possible to the pins.
1)
Stepper motor phase currents measured chip internally. No external shunt resistor needed.
2)
Choose the BVDD capacitor according to the application needs, e.g. if the NVRAM shall be programmed after VBVDD has dropped below the
undervoltage interrupt threshold.
3)
To control SMPSI pass transistor.
4)
In applications with LIN auto-addressing the LIN pin is the input of the LIN bus and LIN_O the output to the LIN bus.
5)
It is recommended to provide access to the debug interface in the customer application HW for the purpose of analysis.
6)
The resistor is required to limit the input current for negative input voltages relative to V
. The capacitor filters the noise coming from V
.
BVSS0
BAT
If the MON is not used in the application, it should be connected to BVDD (pin is protected against reverse polarity and input current is minimized).
7)
A TVS diode or sufficiently dimensioned capacitor is recommended with respect to ISO7637-2:2004 Pulse 2a.
8)A ferrite bead is recommended to be conform with the EME requirements of some OEMs. An impedance of 1 k @ 100 MHz is recommended.
9)
Components to be applied for specific EMC tests and/or to be compliant to different OEM requirements. Refer also to corresponding standards and
test specifications.
10)
Optional circuit to reduce internal power dissipation. Please contact TDK-Micronas for the recommended dimensioning and type of the external
components
Fig. 2–3: Recommended circuitry for stepper motor control
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DATA SHEET
HVC 4x Family
2.6. Package Outline Dimensions
ꢀ0.1
6
2x
B
A
ꢁ
0,15
C
1
.
0
ꢀ
6
A ( 20 : 1 )
PIN 1 INDEX
2
2
2x
.
0
ꢁ
0.15
C
C
.
x
a
m
0,1
A
ꢄ
.
x
LEADFRAME TIE BAR
a
m
1
.
5
0
0
.
ꢀ
0
9
.
0
not Sn-plated
(40x)
SEATING PLANE
C
ꢁ
0,08
C
ꢀ0.05
0.25
tin plated
ꢀ0.1
0.4
40x
0.1 ꢃ
C
A
B
ꢂ
1
.
0.5
0
ꢀ
4
.
PIN 1 INDEX
0
0.35x45°
die pad tin plated
1
.
0
ꢀ
7
.
4
5
.
0
ꢀ0.1
4.7
0
2.5
5 mm
scale
Dimensions are in mm.
Physical dimensions do not include moldflash.
Sn-thickness might be reduced by mechanical handling.
BACK VIEW
FRONT VIEW
JEDEC STANDARD
SPECIFICATION
ISSUE DATE
REVISION DATE
PACKAGE
QFN40-4
ANSI
REV.NO.
4
DRAWING-NO.
(YY-MM-DD)
(YY-MM-DD)
ITEM NO. ISSUE
MO-220
TYPE
NO.
18-05-29
C
18-05-29
CQFN40029016.1
ZG
001104_Ver.04
© Copyright 2018 TDK-Micronas GmbH, all rights reserved
Fig. 2–4: PQFN40-4: Plastic Quad Flat Non-leaded package,
40 pins, 6.06.00.9 mm3, 0.5 mm pitch.
Ordering code: DL. Weight approximately 0.105 g
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DATA SHEET
HVC 4x Family
3. Electrical Data
3.1. Absolute Maximum Ratings
Stress conditions beyond those listed in the “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only. Functional operation of
the device at these conditions is not implied. Exposure to absolute maximum ratings
conditions for extended periods will affect device reliability.
This device contains circuitry to protect the inputs and outputs against damage due to high
electro-static voltages or electric fields; however, it is advised that normal precautions must
be taken to avoid application of any voltage higher than absolute maximum-rated voltages.
Note
All voltages listed in Table 3–1 are referenced to VBVSS0 = VBVSS1 = VBVSS2
= VBVSS3 = VAVSS = VDVSS = 0 V and VBVDD = VMVDD0 = VMVDD1 except
where otherwise noted. All ground pins must be connected to a low-resistive
ground plane close to the IC. Negative currents indicate currents flowing out
of the chip.
Table 3–1: Absolute maximum ratings
Symbol
Parameter
Pin Name
Min.
Max.
Unit
Condition
TJ
Junction temperature
under bias
40
175
°C
A thermal shutdown (TSD) is
generated above
recommended operation
temperature to force device
into a reset state (see
Section 3.4.)
Tstorage
Transportation/short-term
storage temperature
55
150
40
°C
V
Device only without packing
material.
VSUP B
Main supply voltage
BVDD,
0.3
MVDD0,
MVDD1
DV/Dt VSUP B Main supply voltage slope
BVDD,
MVDD0,
MVDD1
10
V/µs
VBVDD 19 V
For 40 V VBVDD > 19 V refer
to maximum main supply
voltage slope value according
to ISO 7637-2:2004 pulse 5b.
E07 pulse requirement with
0.5 V/min is fulfilled.
For elevated temperature
range together with recom-
mend external components
as shown in Fig. 2–2 and
Fig. 2–3 the CSMPS shall be
CSMPS 4.7 F
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DATA SHEET
HVC 4x Family
Table 3–1: Absolute maximum ratings, continued
Symbol
Parameter
Pin Name
Min.
Max.
Unit
Condition
ISUP
Supply current
BVDD,
100
100
mA
Supply current limitation with
respect to product reliability
over lifetime (e.g. due to
electro migration). The cur-
rent can be interpreted as an
RMS value.
BVSS0,
BVSS1,
BVSS2,
BVSS3
Motor supply current
MVDD0,
MVDD1,
MVSS0,
MVSS1,
MOUTx
1000 1000
mA
V
With MOUTx port limits for
I
out RMS and Iout peak
according to the recom-
mended operating condi-
tions.
VMVSS
Motor bridge ground
MVSS0,
MVSS1
0.3
27
0.3
Vin
Input voltage on LIN pin
LIN
40
V
V
Input voltage for 3.2 V GPIO
ports
SDA, SCK, 0.3
LGPIOx,
TEST
3.65
Min. value calculated
according to VAVSS 0.3 V
Max. value calculated
according to VAVDD +0.3 V
Input voltage
on MOUT pins
MOUTx
0.3
40
V
5 400 ms, with 30 sec.
period. cumulative 1 h max.
The application SW has to
take measures to reduce the
motor-current or to turn off the
motor due to the deactivated
charge-pump in overvoltage
mode. It is recommended to
stop the motor and to turn-on
all power-bridge low-side
MOSFETs.
Dynamically lower voltages
during free-wheeling are
covered by the maximum
specified phase currents.
Input voltage
on HSBVDD pin
HSBVDD
MON
0.3
27
40
40
V
V
5 400 ms, with 30 sec.
period. cumulative 1 h max.
Min. value calculated accord-
ing to VBVSS 0.3 V
Input voltage on MON pin
applied via resistor Rmon_ext
(see Fig. 2–2 and Fig. 2–3)
5 400 ms, with 30 sec.
period. cumulative 1 h max.
Iout
Output current LGPIOx pins
and SDA pin
SDA,
LGPIOx
20
30
20
20
0
mA
mA
mA
Output current
for HSBVDD port
HSBVDD
Iout total
Sum of output currents
derived from AVDD regulator
SDA,
LGPIOx,
for 3.2 V GPIO ports and from AVDD
AVDD pin
Sum of output currents derived SMPSI,
from SMPSI pin, AVDD regula- SDA,
40
mA
tor for 3.2 V GPIO ports and
from AVDD pin
LGPIOx,
AVDD
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DATA SHEET
HVC 4x Family
3.2. ESD and Latch-Up
Table 3–2: ESD and latch-up
Symbol
Parameter
Min.
Max.
Unit
Comment
Ilatch
Maximum latch-up free current (measurement
according to AEC Q100-004 Grade 1 at TA=+125 °C)
300
300
mA
MOUT pins,
TJ > 130 °C
1000
1000
mA
MOUT pins,
TA = 25 °C
100
8
100
8
mA
kV
kV
kV
V
All other pins.
LIN 1)
VHBM
Human body model, equivalent to discharge 100 pF
with 1.5 k (measurement according to
AEC-Q100-002)
2
2
All other pins.
LIN to GND1)
VSystem ESD
VCDM
According to IEC 61000-4-2 (330 , 150 pF)
6
6
Charged device model (measurement according to
AEC-Q100-011) 1)
750
750
Machine model is
only optional
according to
AEC-Q100.
VMM
Machine model (measurement according to JESD22- 200
A115 / AEC-Q100-003)
200
V
Machine model is
only optional
according
AEC-Q100.
1) According to OEM requirement specification “Hardware Requirements for LIN, CAN, and FlexRay Interfaces in
Automotive Applications v1.3” from May 4, 2012. Further components like varistor, TVS diode, or passives might be
necessary to fulfill requirements of other OEM specifications.
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DATA SHEET
HVC 4x Family
3.3. Transient Supply Voltage
Table 3–3: Transient supply voltage
Parameter
Pin Name
Min.
Max.
Unit
ISO 7637-2:2004 pulse 11)
ISO 7637-2:2004 pulse 2a 2)
ISO 7637-2:2004 pulse 2b
ISO 7637-2:2004 pulse 3a 1) 4)
ISO 7637-2:2004 pulse 3b 4) 5)
ISO16750-2:2012
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
100
V
75 3)7)
10
V
V
V
V
V
150
1007)
6)
6)
ISO 16750-2:2012
40
V
400
ms
ISO 16750-2
BVDD
28
2
V
min.
1)
2)
With reverse polarity diode.
Reverse polarity diode and 1 F blocking capacitor with low ESR.
3) According to OEM requirement specification “Hardware Requirements for LIN, CAN and FlexRay
Interfaces in Automotive Applications v1.3” from May 4, 2012.
4)
5)
6)
7)
4.7 k minimum series resistance for I/O ports.
The sum of the whole clamping currents must not exceed 100 mA.
Values according to OEM specifications.
With TVS diode.
The ISO 7637 standard is the base for the OEM supplier specifications.
Automotive test pulses are applied on module level. The IC pins used to connect the
module to the wiring harness shall be used with appropriate protection circuitry. Refer
also to Fig. 2–2 on page 22 and Fig. 2–3 on page 23.
TDK-Micronas GmbH
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DATA SHEET
HVC 4x Family
3.4. Recommended Operating Conditions
Warning Do not insert the device into a live socket. Instead, after proper inser-
tion into the socket apply power by switching on the external power
supply.
Failure to comply with the above recommendations will result in unpredictable behavior of
the device and may result in device destruction. Functional operation of the device at con-
ditions beyond those indicated in the “Recommended Operating Conditions” is not implied
and may result in unpredictable behavior, reduce reliability and lifetime of the device.
All externally applied discrete components must be selected according to the required
temperature range in the application.
Note
All voltages listed in Table 3–4 are referenced to VBVSS0 = VBVSS1 = VBVSS2
= VBVSS3= VDVSS = VAVSS = 0 V and VSUP B = VBVDD = VMVDD = VMVDD1
except where otherwise noted. All ground pins (BVSS0, BVSS1, BVSS2,
BVSS3, AVSS, DVSS) must be connected to a low-resistive ground plane
close to the IC. The pins MVSS0 and MVSS1 might be connected to ground
via shunt resistor for motor current measurements.
Table 3–4: Recommended operating conditions
Symbol
Parameter
Pin Name Min.
Typ.
Max.
Unit
Condition
40
160
TJ
Junction temperature
under bias
°C
According to Mission
Profile for extended
HVC 4x22F only
temperature range up to
160 °C. Please contact
TDK-Micronas for more
detailed information.
-40
150
18
all others
°C
V
2)3)
VSUP B
Main supply voltage
BVDD,
8
14
MVDD0,
MVDD1
1)2)3)
5.4
40
V
5 x 400 ms, with 30 sec.
period. cumulative 1 h
max.
Refer to Table 3–3 on
page 28 for transient
supply voltages.
VSUP B
RETENTION
Main supply voltage
during RETENTION
mode
BVDD,
MVDD0,
MVDD1
2.5
V
RAM content is pre-
served. No CPU func-
tion. Return from
RETENTION mode with
Power-on Reset (POR).
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DATA SHEET
HVC 4x Family
Table 3–4: Recommended operating conditions, continued
Symbol
Parameter
Pin Name Min.
Typ.
Max.
Unit
Condition
VMVSS
Motor bridge ground
MVSSx
0.065
0.3
V
Min value limited due to
linearity of ADC.
If negative voltage ADC
measurement is not
needed this voltage can
be extended to 0.3 V.
3.2 V Port input voltage
Vil
Input low voltage
LGPIOx,
TEST,
SCK, SDA
0
0.28
1
VAVDD
Vih
Input high voltage
LGPIOx,
TEST,
0.72
VAVDD
SCK, SDA
Port output currents
Iout
Continuous output
current LGPIO port
LGPIOx
HSBVDD
SMPSI
4
4
mA
mA
mA
Continuous output
current HSBVDD port
15
40
Continuous output
current SMPSI
According to Iout total in
Table 3–1 on page 25.
The sum of currents
derived from SMPSI,
AVDD, and LGPIO ports
must not exceed the
here specified limits!
Iout RMS
MOUT port RMS out- MOUTx
put current
300
500
300
500
mA
mA
According to the fly-back
current derating speci-
fied under Section 3.6.
on page 42.
Iout peak
MOUT port peak out- MOUTx
put current tON < 1 s
(single MOUT)
Contact TDK-Micronas
for dedicated applica-
tion support.
LIN Transceiver3)
VBUS LIN bus voltage
twhi
LIN
LIN
2.7
20.7
V
High time after Wake
Pulse
1
1 / fAUX
AVDD Regulator, 3.2 V supply voltage
4)
4)
CAVDD
External buffer
capacitor
AVDD
DVDD
100
1
470
2.2
nF
µF
DVDD Regulator, 1.8 V supply voltage
CDVDD
External buffer
capacitor
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DATA SHEET
HVC 4x Family
Table 3–4: Recommended operating conditions, continued
Symbol
Parameter
Pin Name Min.
Typ.
Max.
Unit
Condition
Charge pump (integrated bridge)
4)
CVCP
Charge pump
capacitor
VCP
22
1
1000
nF
µF
5 V LDO
4)
CSMPS
SMPS capacitor
SMPSI
2.2
22
ESR 50 m
For elevated tempera-
ture range together with
recommend external
components as shown
in Fig. 2–2 and Fig. 2–3
the CSMPS shall be
CSMPS 4.7F
VBAT Monitor
4)
4)
Rmon_ext
External resistor on
MON Pin for current
limitation
MON
4.7
47
27
k
Cmon_ext
External capacitor on MON
MON Pin
nF
1) Some analog parameters may degrade and full motor operation is not guaranteed.
2) If VBVDD > VBVDDO the application SW is responsible to limit the power dissipation to keep TJ inside Recommended
Operating Conditions.
3) Compliant with “LIN Physical Layer Specification Revision 2.1”.
4) All externally applied discrete components must be selected according to the required temperature range in the appli-
cation.
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DATA SHEET
HVC 4x Family
3.5. Characteristics
Note
Unless otherwise written all parameters listed in Table 3–5 are valid for the
conditions VBVSS0 = VBVSS1 = VBVSS2= VBVSS3= VDVSS = VAVSS = 0 V,
8 V VBVDD 18 V, VSUP B = VBVDD = VMVDD0 = VMVDD1, TJ = 40 °C to
150 °C. HVC 4x22F devices are also tested at 160 °C. External components
and connections according to Fig. 2–2 on page 22 or Fig. 2–3 on page 23.
Table 3–5: Characteristics
Symbol
Parameter
Pin
Name
Min.
Typ.1) Max.
Unit
Conditions
Package
RthJC
Thermal resistance from
junction to case
10
25
K/W
K/W
Parameter is simulated
with model of 1s1p
board according
JEDEC.
RthJA
Thermal resistance from
junction to ambient
Values are only valid if
the exposed pad is sol-
dered onto the PCB.
Supply Currents (CMOS levels on all inputs, no loads on outputs)
IDDP
ACTIVE mode supply current BVDD
HVC 422xF
22
25
30
38
mA
mA
fSYS = fCPU = 20 MHz,
V
BVDD = 12 V, all
peripherals on.
ACTIVE mode supply current
HVC 442xF
IDDP can be reduced
by activating peri-
pherals only during the
time they are used.
IDDI
IDLE mode supply current
HVC 422xF
BVDD
2.6
3.5
4
Main osc. off
CP off
ERM off,
IDLE mode supply current
HVC 442xF
All peripherals off,
VBVDD = 12 V,
Maximum value valid
for TJ 100 °C.
2)
IDDSL
SLEEP mode supply current
BVDD,
35
50
µA
MVDD0,
MVDD1
RAM off, main osc. off,
auxiliary osc. on
VAVDD = VDVDD
SMPSI = 0 V
=
V
Maximum value valid at
TA = TJ 100 °C.
TJ ~ TA due to the very
low self-heating in
SLEEP Mode.
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DATA SHEET
HVC 4x Family
Table 3–5: Characteristics, continued
Symbol
Parameter
Pin
Name
Min.
Typ.1) Max.
Unit
Conditions
Low-Voltage General-Purpose I/O Ports (LGPIO Ports), SDA, SCK, and TEST Pin
Vihl
Input high-to-low threshold
voltage
LGPIOx, 0.28
SDA,
SCK,
VAVDD
VAVDD
Vilh
Input low-to-high threshold
voltage
0.72
110
TEST
2)
Vhyst
Schmitt trigger hysteresis
Input with weak pull-down
0.5
5
V
Iihigh_pd
30
µA
Vin=VAVDD. LGPIO port
internal weak pull-
down configuration
applied.
Iilow
Input low current
10
10
µA
µA
Vin = 0 V
Iilow_pu
Input with weak pull-up
LGPIOx, 110
30
5
Vin = 0 V. LGPIO port
internal weak pull-up
configuration applied.
SDA
Iihigh
Input high current
10
10
µA
Vin = VAVDD
No internal weak pull-
down/up configuration
applied.
Vol
Port low output voltage
Port high output voltage
LGPIOx,
SDA
0.4
V
Iol = 4 mA
Voh
LGPIOx, 0.8
SDA
VAVDD
Ioh = 4 mA
HSBVDD Pin
Voh
Port high output voltage
HSB-
VDD
1
VBVDD
1 V
IO = 15 mA
Iocson
Overcurrent shutdown in on-
state
HSB-
VDD
20
mA
HSBVDD.DO = 1
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DATA SHEET
HVC 4x Family
Table 3–5: Characteristics, continued
Symbol
Parameter
Pin
Name
Min.
Typ.1) Max.
Unit
Conditions
MOUT Ports
RDS(ON)hs
Static drain-source on-resis-
tance of high-side N-channel
MOSFET
MOUTx
MOUTx
2
2
2.8
2.8
IMOUT = 500 mA,
VMVSS0 = VMVSS1
BVSS0 = VBVSS1
VBVSS2 = VBVSS3
=
=
V
RDS(ON)ls
Static drain-source on-resis-
tance of low-side
N-channel MOSFET
IMOUT = 500 mA,
VMVSS0 = VMVSS1
=
=
V
BVSS0 = VBVSS1
VBVSS2 = VBVSS3
Iocshi
Overcurrent shutdown in high MOUTx
state
0.9
A
Iocslo
Overcurrent shutdown in low
state
MOUTx
0.9
A
RMOUT
MOUT pull-down resistor net- MOUTx
work (for BEMFC reference
generation)
96
k
VMOUT0 = VMOUT1=
V
MOUT2 = VMOUT3 =
VMOUT4 = VMOUT5
2)
LIN Pin (7 V VBVDD 18 V)
VBUSL
Output low voltage
LIN
LIN
0.8
30
1.2
60
V
Refer to LIN-Specifi-
cation v1.3,
VBusdom_DRV_LoSUP
RSLAVE
Internal pull-up resistance at
output
20
k
VBUS_OH
IBUS_LIM
Transmitter recessive voltage LIN
0.8
40
1
VBVDD
mA
Open load
Current shutdown threshold
for driver dominant state
LIN
200
VBUS = 18 V
Driver on
IBUS_PAS_dom Input leakage current at the
receiver inclusive pull-up
LIN
1
1
mA
µA
VBUS = 0 V
VBAT = 12 V
resistor as specified
Driver off
IBUS_PAS_rec Leakage current at the
receiver inclusive pull-up
LIN
20
8 V < VBUS < 18 V
8 V < VBAT < 18 V
VBUS VBAT
resistor as specified
Driver off
IBUS_NO_GND Leakage current at ground
loss
LIN
LIN
1
mA
µA
VGND = VBVDD
0 V < VBUS < 18 V
VBAT =12 V
IBUS_NO_BAT Leakage current at BVDD
loss
30
0.4
VBVDD = VGND
0 V < VBUS < 18 V
VBAT =disconnected
VBUSdom
VBUSrec
Receiver dominant state
Receiver recessive state
Center of receiver threshold
LIN
LIN
LIN
VBVDD
VBVDD
VBVDD
Without external diode.
0.6
VBUS_CNT
0.475
0.5
0.525
0.175
VBUS_CNT
=
(Vth_dom + Vth_rec) / 2
VHYS
Hysteresis of receiver thresh- LIN
old
VBVDD
VHYS
=
Vth_rec Vth_dom
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DATA SHEET
HVC 4x Family
Table 3–5: Characteristics, continued
Symbol
Parameter
Pin
Name
Min.
Typ.1) Max.
Unit
Conditions
LIN Driver, 20.0 kbps (tBit = 50 µs), LIN_CR.SR = 2, bus load conditions (CBUS; RBUS): 1 nF; 1 k / 6.8 nF; 660 / 10 nF;
500 ; 7 V VBVDD 18 V.
D1
Duty cycle 1
LIN
0.396
THRec(max) = 0.744 x
VBVDD
THDom(max) = 0.581 x
;
VBVDD
;
VBVDD = 7.0 V to 18 V;
D1 = tBus_rec(min) / (2 x
tBit)
D2
Duty cycle 2
LIN
0.581
THRec(min) = 0.422 x
VBVDD
THDom(min) = 0.284 x
;
VBVDD
;
VBVDD = 7.6 V to 18 V;
D2 = tBus_rec(max) / (2 x
tBit)
LIN Driver, 10.4 kbps (tBit = 96 µs), LIN_CR.SR = 3, Bus/LIN load conditions (CBus; RBus): 1 nF; 1 k / 6.8 nF; 660 /
10 nF; 500 ; 7 V VBVDD 18 V.
D3
Duty cycle 3
LIN
0.417
THRec(max) = 0.778 x
VBVDD
THDom(max) = 0.616 x
VBVDD
BVDD = 7.0 V to 18 V;
D3 = tBus_rec(min) / (2 x
tBit
;
;
V
)
D4
Duty cycle 4
LIN
0.590
THRec(min) = 0.389 x
VBVDD
THDom(min) = 0.251 x
VBVDD
BVDD = 7.6 V to 18 V;
D4 = tBus_rec(max) / (2 x
tBit
;
;
V
)
The following parameters are defined in the LIN specification Rev. 2.x: Vth_dom, Vth_rec, THRec(max), THRec(min)
,
THDom(max), THDom(min), tBus_rec(max), tBus_rec(min), tBit
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DATA SHEET
HVC 4x Family
Table 3–5: Characteristics, continued
Symbol
Parameter
Pin
Name
Min.
Typ.1) Max.
Unit
Conditions
LIN Transceiver (7 V VBVDD 18 V).
trx_pd
Receiver propagation delay
LIN
LIN
6
2
s
s
trx_sym
Receiver propagation delay
symmetry
2
CSLAVE
Slave capacitance
LIN
30
48
60
pF
Guaranteed by design
with respect to LIN 2.1
physical layer confor-
mance test specifica-
tion.
dV/dtfall
Falling edge slew rate
LIN
1.5
10
V/s
SR = 1, 2, or 32)
SR = 02)
With bus-load
CBUS =1 nF
and RBUS =1 k.
Fast slew-rate e.g.
needed for operation
with PWMIO at LIN
port.
dV/dtrise_max Maximum rising edge slew
rate
LIN
1.5
10
V/s
SR = 1, 2, or 32)
SR = 02)
With bus-load
CBUS =1 nF
and RBUS =1 k.
Fast slew-rate e.g.
needed for operation
with PWMIO at LIN
port.
twup
Low pulse time for wake-up
LIN
28
150
s
VBUS < VBVDD / 2
360 mV.
Minimum value accord-
ing to “Hardware
Requirements for LIN,
CAN and FlexRay
Interfaces in Automo-
tive Applications v1.3”
from May 4, 2012.
Maximum value
according to “LIN
Specification Package
Revision 2.1” from
November 24, 2006.
LIN Auto-Addressing related parameter (9 V VBVDD 15 V, 0 °C TA 50 °C).
According to “Lastenheft Klima-Standardaktuator mit LIN-Bus Schnittstelle 2.x” from January 28, 2013.
ICS
Current source
LIN
1.85
2.05
1
2.25
1.25
mA
RBSM
Bus shunt resistor
LIN,
LIN_O
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DATA SHEET
HVC 4x Family
Table 3–5: Characteristics, continued
Symbol
Parameter
Pin
Name
Min.
Typ.1) Max.
Unit
Conditions
BEMF Comparators (BEMFC)
BEMFCdelay BEMF Comparator delay time MOUTx
2)
2)
500
550
70
ns
BEMFChyst
BEMF Comparator input hys- MOUTx
teresis
30
mV
8-Bit Current Limit DAC (CLDAC)
2)
LSBCLDAC
LSB value CLDAC
1.6
2.0
2
2.8
2.1
mA
mA
Without SW trimming
for gain and offset
correction
IMOUT > 10 mA
2) 3)
LSBCLDAC
LSB value CLDAC
1.9
With SW trimming for
gain and offset correc-
tion
IMOUT > 10 mA
2)
ZECLDAC
CLDAC zero error
CLDAC zero error
20
5
10
5
LSB
LSB
Without SW trimming
for gain and offset
correction
2) 3)
ZECLDAC
With SW trimming for
gain and offset
correction
2)
DNLCLDAC
INLCLDAC
CLDAC differential non-
linearity
0.5
5.0
0.5
5.0
LSB
LSB
2)
CLDAC integral nonlinearity
12-Bit ADC (including signal path)
LSBADC&SP
INLADC&SP
DNLADC&SP
LSB value of the ADC includ-
ing the signal path
0.976
mV
Guaranteed by design
(VREF-ADC trimmed).
2)
ADC integral non-linearity
including the signal path
16
8
16
8
LSB
LSB
2)
ADC differential non-linearity
including the signal path
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DATA SHEET
HVC 4x Family
Table 3–5: Characteristics, continued
Symbol
Parameter
Pin
Name
Min.
Typ.1) Max.
Unit
Conditions
2)
Vin ADC
ADC linear input voltage
range LGPIO ports versus
AVSS
LGPIO0,
LGPIO1,
LGPIO2,
LGPIO3
0
3.3
V
GPGA = 4
2)
ADC linear input voltage
range MON and BVDD ver-
sus AVSS
MON,
BVDD
8
18
18
V
V
GPGA = 4
2)
ADC linear input voltage
range STDA and STDB inputs MOUT1,
(from motor phase)
MOUT0, 18
GPGA = 4
MOUT2,
MOUT3
2)
ADC linear input voltage
range motor current shunt
MVSSx versus BVSS0
MVSS0, 65
300
175
2.7
mV
mV
V
MVSS1
GPGA = 4
2)
65
GPGA = 10
2)
ADC linear input voltage
range differential input
LGPIO8 versus LGPIO9
LGPIO8, 2.7
LGPIO9
GPGA = 4
2)
SPE
Signal path error of ADC
measurement at LGPIO ports LGPIO1,
versus AVSS
LGPIO0, 3
3
5
%
%
GPGA = 4
LGPIO2,
LGPIO3
2)
5
GPGA = 10
SPE for gain 20 and 40
on customer request.
2)
Signal path error of ADC
measurement at MON and
BVDD versus AVSS
MON,
BVDD
2
2
%
GPGA = 4
2)
Signal path error of ADC
measurement at STDA and
STDB inputs (from motor
phase)
MOUT0, 5
MOUT1,
MOUT2,
5
7
4
%
%
%
GPGA = 4
2)
MOUT3
7
GPGA = 10
2)
Signal path error of ADC
measurement at motor cur-
rent shunt MVSSx versus
BVSS0
MVSS0, 4
MVSS1
GPGA = 4
65 mVVMVSS
0.3 V
2)
7
7
%
GPGA = 10
65 mVVMVSS
175 mV
2)
Signal path error of ADC
measurement at differential
input LGPIO8 versus LGPIO9
LGPIO8, 5
5
8
%
%
LGPIO9
GPGA = 4
2)
Signal path error of ADC
measurement at differential
input LGPIO8 versus LGPIO9
LGPIO8, 8
LGPIO9
GPGA = 10
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DATA SHEET
HVC 4x Family
Table 3–5: Characteristics, continued
Symbol
Parameter
Pin
Name
Min.
Typ.1) Max.
Unit
Conditions
2)
ZEADC&SP
ADC zero error including the
LGPIO signal path
LGPIO0, 20
LGPIO1,
LGPIO2,
20
LSB
GPGA = 4
2)
LGPIO3
50
50
LSB
GPGA = 10. ZE for gain
20 and 40 on customer
request.
2)
ADC zero error including the
STDA or STDB signal path
MOUT0, 20
MOUT1,
MOUT2,
20
20
50
50
LSB
LSB
LSB
LSB
GPGA = 4
BEMFC off
MOUT3
2)
40
50
GPGA = 4
BEMFC on
2)
GPGA = 10
BEMFC off
2)
100
GPGA = 10
BEMFC on
2)
ADC zero error including the
LGPIO8/9 signal path
LGPIO8, 20
20
60
20
20
LSB
LSB
LSB
LSB
LGPIO9
GPGA = 4
2)
60
GPGA = 10
2)
ADC zero error including the
MON or BVDD signal path
MON,
BVDD
20
GPGA = 4
2)
ADC zero error including the
MVSSx signal path
MVSS0, 20
MVSS1
GPGA = 4
65 mV VMVSS
0.3 V
2)
50
1
50
LSB
GPGA = 10
65 mV VMVSS
175 mV
CR
tc
Conversion range
Conversion time
1
VREF-
ADC
Guaranteed by design
(VREF-ADC trimmed).
1
µs
Conversion time varia-
tion according to fMAIN
tolerance must be
added.
2)
tW
ADC signal path warm-up time
ADC reference voltage
10
µs
V
VREF-ADC
2
Guaranteed by design.
VREF-ADC trimmed.
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DATA SHEET
HVC 4x Family
Table 3–5: Characteristics, continued
Symbol
Parameter
Pin
Min.
10
167
Typ.1) Max.
Unit
°C
Conditions
Name
High-Resolution Temperature Sensors
2)
T
Temperature error of sensor
readable by ADC
10
Temperature supervision / Thermal shutdown
2)
TTSD
Thermal shutdown
temperature HVC 4x22F
172
177
°C
2)
2)
others
155
125
165
135
175
145
°C
°C
TTSDR
Thermal shutdown return
temperature
40 MHz Main Oscillator
fMAIN Main oscillator output
37.1
21
40
35
41.1
49
MHz
kHz
With ERM off.
frequency
35 kHz Auxiliary Oscillator
fAUX Auxiliary oscillator output
frequency
5V LDO Pre-regulator (Supply Voltage to AVDD and DVDD Regulators)
VSMPSI
SMPS output voltage
SMPSI
AVDD
4.5
3.1
5
5.5
V
V
AVDD Regulator (Analog Supply Voltage)
VAVDD
Internal analog supply
voltage
3.25
3.35
DVDD Regulator (Digital Supply Voltage)
VDVDD
Internal digital supply voltage DVDD
1.6
6
1.85
1.98
V
V
VBAT Monitor
VBATin
2)
MON pin input voltage where MON
the ADC can be used for VBAT
measurement and the VBAT
OV/UV comparators work
according specification
VBATUp
VBATUn
VBATOp
VBATOn
Battery undervoltage low-to-
high threshold
MON
7.9
8.25
21.4
V
V
V
V
Battery undervoltage high-to- MON
low threshold
7.32
18.8
7.67
20.6
19.4
Battery overvoltage low-to-
high threshold
MON
Battery overvoltage high-to-
low threshold
MON
BVDD Monitor
VBVDDUp
BVDD undervoltage low-to-
high threshold
BVDD
BVDD
BVDD
BVDD
6.45
6.26
19
6.75
V
V
V
V
VBVDDUn
VBVDDOp
VBVDDOn
BVDD undervoltage high-to-
low threshold
5.97
18.2
17.2
BVDD overvoltage low-to-
high threshold
19.7
18.4
BVDD overvoltage high-to-
low threshold
17.9
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DATA SHEET
HVC 4x Family
Table 3–5: Characteristics, continued
Symbol
Parameter
Pin
Name
Min.
Typ.1) Max.
Unit
Conditions
Power-On Reset (POR) Voltage
2)
2)
2)
2)
VPOR
POR release threshold voltage BVDD
if going from power-up to
ACTIVE mode
5.4
V
V
V
V
VPOR_sleep
Supply voltage limit where a
POR is asserted if chip is in
SLEEP mode
BVDD
BVDD
BVDD
0.5
VPOR_retention Supply voltage limit where a
POR is asserted if chip is in
RETENTION mode
2.5
3
VPOR_tsd
Supply voltage limit where a
POR is asserted if chip is in
TSD mode
RETENTION Mode
2)
VRET
Threshold voltage when
BVDD
5.35
V
going from ACTIVE mode to
RETENTION mode. Refer
also to the respective state
chart in the User Guide of
HVC 4223F.
NVRAM
tSTORE
Time to store all data within
one NVRAM page
15
ms
Storage time for
NVRAM page data.
NNs
Number of store cycles for
each NVRAM page
10 k
cycles
TJ = 150 °C
For store cycles at
150°C < TJ 160 °C
please contact
TDK-Micronas
100 k
16
cycles
years
TJ = 25 °C
tNret
NVRAM data retention
Qualified according to
AEC-Q100 for temper-
ature grade 1.
Flash
NFwe
Flash memory endurance
write/erase cycles
1000
cycles
years
Qualified according to
AEC-Q100 for temper-
ature grade 3.
Customer specific mis-
sion profiles might
allow other cycle num-
bers.
tFret
Flash memory data retention
16
Qualified according to
AEC-Q100 for temper-
ature grade 1.
1)
Typical values describe typical behavior at room temperature (25 °C, unless otherwise noted), with typical Recom-
mended Operating Conditions applied, and are not 100% tested.
Parameter is derived from design characterization on a small sample size.
For detailed information on the CLDAC trimming algorithm, please refer to the Application Note “HVC 4223F CLDAC
Trimming Algorithm”.
2)
3)
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3.6. MOUT Fly-Back Current Derating
To allow operation at elevated temperatures according to the customer mission profile,
it is recommended to apply additional circuitry.
1. Freewheeling Schottky diodes connected from the three motor phase outputs
MOUT0/1, MOUT2/3 and MOUT4/5 to MVDD.
2. Supply SMPSI node externally by over-driving this node (applying a higher voltage)
• An NPN transistor to reduce power dissipation of internal 5V regulator. See Fig. 2–2
and Fig. 2–3.
• If the node SMPSI is externally supplied, the internal linear regulator will limit the
internal current from BVDD to a minimum.
If the freewheeling Schottky diodes are not used, Fig. 3–1 and Fig. 3–2 illustrate the
derating curves for the sum of the MOUT port fly-back currents with respect to the fly-
back discharge type (passive or active). Refer also to the recommended operating con-
ditions.
1000
900
800
700
600
500
Passive flyback current discharge, C
= 2.2 µF, Lphase-phase 1mH
SMPS
400
300
Active flyback current discharge, C
= 2.2 µF
SMPS
200
100
0
140
130
50
100
T [°C]
110
150
60
80
90
120
70
160
j
Fig. 3–1: Brushless motor derating curve for sum of MOUT currents with active or passive fly-back
current discharge.
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HVC 4x Family
1000
900
800
700
600
500
400
300
Passive flyback current discharge, CSMPS = 1 µF, L
50 mH
phase-phase
200
100
0
140
130
50
100
T [°C]
110
150
160
60
80
90
120
70
J
Fig. 3–2: Stepper motor derating curve for sum of MOUT currents with passive fly-back current
discharge.
Note
Single reset events (e.g. by watch-dog reset or other chip reset sources)
during motor operation will cause passive freewheeling. Such conditions
are acceptable with motor currents within the active flyback SOA curves.
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HVC 4x Family
4. Functional Description
4.1. Power Supply
The HVC 4x family can be directly connected to the 12 V automobile on-board power
supply and withstands all disturbances appearing on the car’s supply, specified in
ISO 7637-2:2004. The polarity protection for the HVC 4x family should be provided by
an external device (e.g. diode or MOSFET). An external voltage regulator for the sys-
tem supply is not required.
4.1.1. Start-Stop Applications
The HVC 4x family preserves the SRAM during voltage drops e.g. at car engine start-up
(cranking- and start-stop conditions). In this case the BVDD voltage drops from its typi-
cal value to the range of VPOR_retentionVBVDD < VRET. Only the digital regulator is
functional. In this mode, the peripherals and the Arm® core are kept in the reset state
and no program is executed. Memory contents are retained while analog and digital
functions are stopped (RETENTION mode).
If the supply voltage VBVDD did not drop below VPOR_retention during RETENTION
mode, the CPU starts from the reset vector and the RETENTION mode is signaled in
the reset source status register. If VBVDD drops below VPOR_retention, then the POR sig-
nal is generated. In such a case the chip starts up in normal power-up mode without
retaining the content of the volatile memories (SRAM and RAM layer of NVRAM).
4.2. Voltage Regulators
The HVC 4x family features a 5V pre-regulator which generates an intermediate voltage
that is used by internal linear regulators to supply the different voltage domains.
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HVC 4x Family
4.3. Operating Modes
In order to offer a flexible solution in terms of high system performance and low current
consumption, the HVC 4x family provides several operating modes:
– ACTIVE mode, in which all features are available and the CPU is clocked at selectable
speed.
– RETENTION mode, in which the CPU and the peripherals are reset and the RAM
content is preserved.
– Power-saving modes (IDLE and SLEEP), in which only few parts of the system are active
to achieve low current consumption. An activity on the LIN bus can wake-up the system
from IDLE or SLEEP. In addition the wake-up timer or an over/undervoltage condition on
the BVDD or MON pin can be used as wake-up source from IDLE.
– THERMAL SHUTDOWN mode, in which only a few modules of the device are active
to achieve a minimum of current consumption and to avoid malfunction during over-
temperature condition.
– OVERVOLTAGE mode, in which all features are available but the charge pump is
switched off automatically. It is in the responsibility of the application SW to reduce the
current consumption of the chip in order to meet the thermal budget of the device, and it
is recommended to switch off the MOUT ports within the BVDD_OV interrupt service
routine.
4.4. Temperature Monitoring
The HVC 4x family features two overtemperature detection units to monitor the junction
temperature inside the chip for overtemperature protection and one temperature sensor for
the purpose of a controlled return from a Thermal Shutdown (TSD). The sensors are
placed close to the power-bridges, where most of the power in the device is dissipated.
An additional linear temperature sensor is connected to the ADC to provide junction tem-
perature information to the application SW. By polling the corresponding channel of the
ADC, the application SW can continuously monitor the junction temperature and react on
rising temperatures, e.g. by switching-off modules or reducing the CPU clock. If the tem-
perature exceeds a certain threshold the TSD logic will invoke a TSD reset to protect the
device from being thermally destroyed.
Note
The TSD is a device protection mechanism for exceptional failure conditions
only. The application SW has to take care that TJ does not exceed the shut-
down temperature TTSD(min).
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HVC 4x Family
4.5. Core
The HVC 4x family features an Arm® Cortex®-M3 core (revision r2p1) which is an indus-
try-leading 32-bit RISC processor, widespread in the automotive industry. The Arm
Cortex-M3 is based on a Harvard architecture with a 3-stage pipeline and supports an
address space of 4 Gbyte. It executes the Thumb®-2 instruction set for optimal per-
formance and code size, including division and single-cycle multiply, and reaches a high
performance of 1.25 DMIPS/MHz at zero wait-states (Dhrystone 2.1).
4.5.1. Core Extensions
As the Arm Cortex-M3 is targeting a wide range of applications, the processor is based on
a modular concept which includes fixed (basic) components (e.g. Arm core, NVIC) as well
as optional core extensions listed below. The configuration for HVC 4x family is as fol-
lows:
– NVIC: up to 23 IRQs, 8 priority levels
– DAP: AHB-AP & SW-DP
– Serial wire viewer
– Three data watchpoints
– Flash patch: 8 breakpoint comparators
4.5.2. Debug Interface
The Arm Cortex-M3 includes a Debug Access Port (DAP), which is used to connect a
Debug Port (DP) to the Arm core to allow external access by a debugger.
For the HVC 4x family the Serial Wire Debug Port (SW-DP) interface is implemented.
For the debug interface two dedicated pins, SCK (clock input), and SDA (bidirectional
data IO) are reserved, which are not multiplexed with any alternative functions.
4.5.3. Read-Out Protection
The HVC 4x family can be protected against unauthorized access by disabling the debug
interface via a configuration bit in the customer area of the NVRAM. The debug interface
can be re-enabled only by TDK-Micronas (e.g. for failure analysis) or by code inside the
customer application SW.
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4.5.4. Memory Protection Unit
The HVC 442xF double memory (64 KB Flash) versions feature an MPU (Memory Protec-
tion Unit) which divides the memory map into separate regions. Each of them is controlled
by the MPU via location, size, memory attributes, and access permissions. By providing
access permission bits, the Region Access Control Registers control the access to the cor-
responding memory regions. Access to an area without required permission does result in
raising a MemManage fault. Without programming and enabling the MPU, the system
behavior is exactly the same compared to HVC 422xF.
More details are included in the User Guide of HVC 4x Family. Original information can be
found in the “Arm®v7-M Architecture Reference Manual”, which is the information base
around the MPU implemented in the HVC 4x Family.
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4.6. Clock System
There are two independent on-chip RC oscillators and a clock input for the Arm® debug
interface. The main oscillator is combined with an EMI reduction module and provides
the operating clock (fMAIN) to the system. In parallel the clock of the auxiliary oscillator
(fAUX) can be used to clock the window watchdog for supervising both RC oscillators or
to generate a time triggered wake-up event from IDLE mode. Clock dividers inside the
peripherals are used to derive the internal clocks for the analog and digital modules from
fMAIN
.
4.6.1. Clock Supervision
A supervision of both RC oscillator clocks (fMAIN and fAUX) can be achieved using the
window watchdog (WWDG). The WWDG is clocked with fAUX and requires continuous
triggering by the CPU (running at fCPU which is derived from fMAIN) within a dedicated
time window. If the triggering is not done within the valid trigger window the device will
be reset.
4.6.2. EMI Reduction Module (ERM)
The ERM reduces electromagnetic radiation that might cause interference to other elec-
tronic equipment. The reduction of the radiation is done by applying a predefined modu-
lation on the frequency of the main oscillator.
Without modulation, the noise emission of the chip is concentrated at discrete frequen-
cies. The controlled modulation of the oscillator introduced by the ERM distributes the
power of the emission over a defined frequency range, thus reducing the power spectral
density at the oscillator frequency and its harmonics.
4.7. Bus System
The on-chip bus system of the HVC 4x family is based on the Advanced Microcontroller
Bus Architecture (AMBA®) which is an open standard defined by Arm. Within the bus
system, the Arm Cortex-M3 is the only master and therefore initiates every read/write
transfer.
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4.8. Memory
The HVC 4x family features several on-chip memory blocks to provide high flexibility.
For storing instruction code a startup ROM and a flash memory are used whereas vola-
tile and non-volatile application data are stored in the SRAM or in the NVRAM respec-
tively.
4.8.1. Memory Map
The Arm Cortex-M3 provides a fixed linear memory map with 4 Gbyte of addressable
memory space. The internally predefined memory map specifies which bus interface is to
be used when a memory location is accessed. In order to make it easier to port software
the registers of all internal peripherals like Nested Vectored Interrupt Controller (NVIC) or
Instruction Trace Module (ITM) have a fixed position in the memory map.
For the HVC 4x family the memory mapping is aligned to the Arm recommendations for
integrating a Cortex-M3 core in a SoC design.
4.8.2. Startup ROM
The HVC 4x family contains a startup ROM with the size of 1024 byte, organized as a
256-word by 32-bit array. It is used to store the start-up sequence which is executed
after a reset, the default interrupt table and flash utility functions that can be used by the
application SW. The memory content is fixed by design and cannot be reprogrammed in
application.
4.8.3. Flash Memory
The HVC 422xF devices contain one block of flash memory which has the size of 32 KB
and is organized as an 8192-word by 32-bit array. The HVC 442xF flash memory is
organized in two blocks with the size of 32 KB each and is organized as a two-times
8192-word by 32-bit array. It is used to store the application SW and can be re-
programmed in system. For programming, each flash memory block is organized in
256 pages of 128 byte and for erasing in 16 sectors of 2 KB. Each block can only be
programmed page by page while erasing is performed either sector by sector or the
entire flash memory at once.
The flash memory is able to detect and to correct a single bit error within a 32-bit word.
A double bit-error is detected during read of a 32-bit word. The error conditions are sig-
nalled in the flash status registers and can be configured as interrupt source.
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4.8.4. SRAM
The on-chip SRAM has the size of 2 KB in the HVC 422xF - organized as a 512-word by
32-bit array, and 4 KB in the HVC 442xF - organized as a 1024-word by 32-bit array. It is
used to store volatile application data, but can also be used to store and execute instruc-
tion code.
The content of the SRAM is preserved in ACTIVE, IDLE, RETENTION, and OVER-
VOLTAGE mode but will be lost after power-down, thermal shutdown, and in SLEEP
mode.
4.8.5. NVRAM
The on-chip NVRAM has the size of 512 byte (448 byte available for customer use) and is
organized as a 128-word by 32-bit array. It is used to store non-volatile application data like
trimming values or error counters. The NVRAM consists of a 512 byte RAM module and an
EEPROM of the same size.
Before entering power-down mode the non-volatile data can be preserved in the EEPROM
by a STORE sequence which has to be triggered intentionally by the application SW. After
power-on reset the memory content of the EEPROM is automatically transferred to the
RAM (RECALL sequence).
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4.9. Power-Bridges / MOUT Ports
For the control of BLDC, BDC or stepper motors the HVC 4x family provides the following
features:
– Six integrated N/N-channel half-bridges, each connected to one MOUT port for direct
motor operation, respectively switching of inductive loads. Each half-bridge consists
of two N-channel power FETs for switching high-current loads to motor ground
(MVSS0/1) or positive motor supply (MVDD0/1)
– Internal cross-current protection by gate-voltage monitoring
– High-side N-channel FETs are driven by gate-drivers with internal charge-pump
– Overcurrent detection for each low-side and high-side FET and automatic overcurrent
shut-down (high impedance) of either all half-bridges or the affected half-bridge only
– Interrupt source for overcurrent shutdown
– Integrated resistor network for internal reference voltage generation and signal con-
ditioning of MOUT voltages (e.g. BEMF detection for sensor-less BLDC control or
commutated bipolar stepper motor driving)
– Integrated current sensors on all low-side FETs to support phase current limitation
(e.g. closed-loop current control for bipolar stepper motor application)
– Switched off automatically during SLEEP, RETENTION and TSD mode
The MOUT ports are driven by N/N-channel half-bridges and are implemented for direct
motor operation (e.g. brush-type and brushless DC motors or bipolar stepper motors).
They can switch high-currents on inductive loads without external components.1) Each
of the half-bridges consists of two N-channel power FETs which are used as a low-side
switch2) to the motor ground (MVSS0/1) and as a high-side switch to motor supply
(MVDD0/1), respectively. The power FETs are driven by internal gate-drivers which are
controlled by the EPWM module.
A diagnosis block monitors the gate voltages of the power FETs and provides a signal
which is used in the EPWM module to implement the cross-current protection. Additionally,
the currents flowing through the power FETs are monitored to detect an overcurrent condi-
tion which is evaluated in the EPWM module to either switch-off all six half-bridges or the
affected half-bridge only as well as to generate an overcurrent interrupt.
1)For VBVDD > 18 V it is recommended to turn off the power-bridge due to deactivated charge-pump.
2)It is recommended to use passive free-wheeling only on the low-side of the power-bridge. This is due
to the power dissipation by a parasitic bipolar transistor which conducts free-wheeling currents to the
substrate causing device heating. If high-side passive free-wheeling shall be used it is recommended
to apply external free-wheeling diodes to the respective MOUT port.
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4.9.1. BLDC Motor Control
The three phases of a BLDC motor are connected to the six MOUT ports as illustrated
in Fig. 2–2 on page 22. The voltage levels at the MOUT ports are scaled down and
connected to the BEMF comparators. A resistive network connected to the MOUT ports
can be configured by multiplexers to generate a virtual starpoint voltage as a reference
for the BEMF comparators (refer to Fig. 1–1 on page 13). For the control of sensorless
BLDC motors, the BEMF comparators can be used to detect the BEMF zero-crossing of
the floating motor phase.
4.9.2. Stepper Motor Control
The two coils of a bipolar stepper motor are connected to four of the six MOUT ports as
illustrated in Fig. 2–3 on page 23. The ports MOUT0 to MOUT3 are internally connected
to resistive voltage dividers providing the scaled down MOUTx voltages to the corre-
sponding BEMF comparators.
The internal current through the low-side switches of the ports MOUT0 to MOUT3 can
be measured for the purpose of current controlled stepper motor driving. The currents
are compared to individual 8-bit DAC current reference values. The EPWM module
switches off the corresponding bridge if the current exceeds the given reference value.
The bridge ground pins of the MOUT ports (MVSS0 and MVSS1) have to be grounded
externally. Optionally, an external shunt resistor can be connected between MVSS0/1
and system ground to measure the total motor current by the ADC.
4.9.3. BEMF Comparators
The BEMF comparators can be used to acquire the voltage induced by the back electro-
motive force on a floating BLDC or stepper motor phase to build up a sensorless motor
control application without external components.
The following features are provided:
– Configurable to detect the zero-crossing of the BEMF voltage in an open motor phase
of either a BLDC or a stepper motor.
– Configurable to compare a phase current with an 8-bit programmable reference current
to implement current limit feature.
– Interrupt generation on every change on the comparator output.
– Fast reaction time for BEMF evaluation in BLDC and stepper motor applications.
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4.10. Ports
4.10.1. Low-Voltage General-Purpose I/O (LGPIO)
– Digital output: push-pull or open drain
– Digital input: floating, weak pull-down or weak pull-up
– Analog input: Four ports with single-ended analog input functionality and two ports
configurable as differential analog input. The differential input is not calibrated and
has only limited accuracy.
– Alternative output and input functions selectable
– Port interrupt on rising and/or falling edges
4.10.2. LIN Port
– Physical LIN interface according LIN 2.x
– Support of LIN Auto-Addressing
– Overcurrent protection
– Multiple I/O sources selectable (PWMIO, LIN-UART, Timer 0, LIN_DO)
– Wake-port function (in SLEEP and IDLE mode)
– Selectable slew-rate
– Support of LIN tx dominant time-out function to switch off the transmitter if the LIN bus
is stuck at dominant level (according OEM requirement specification “Hardware
Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications v1.3”
from May 4, 2012)
The LIN port is mainly used to drive the output via the physical LIN interface for the
communication via the LIN bus. Alternatively, it can be used for PWM communication
together with the PWMIO module.
4.10.3. High-Side BVDD Switch (HSBVDD)
The HVC 4x family features a HSBVDD port which is composed of a high-side switch to
VBVDD equipped with an overcurrent protection circuitry. It is designed to supply exter-
nal devices, such as hall sensors. If the output current exceeds the specified overcur-
rent limit, the HSBVDD port is switched off automatically. The occurrence of an over-
current condition may trigger an interrupt.
4.10.4. MON Pin
The MON pin is a high voltage analog input pin to monitor the battery supply voltage. For
connection to the battery supply refer to Fig. 2–2 on page 22 and Fig. 2–3 on page 23.
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4.11. Peripherals
The HVC 4x family features several peripherals to offer an optimized solution for typical
BLDC, BDC, and stepper motor applications.
4.11.1. ADC
– 12-bit resolution
– Fast conversion time of 1 µs
– Input multiplexer with 13 analog channels: LGPIO0 to LGPIO3 single-ended, LGPIO8/
9 differential, VBAT at MON pin, VBVDD , internal temperature sensor VTEMP, motor
current sensing via shunt resistor at MVSS0 and MVSS1, differential inputs STDA+/
and STDB+/ for stepper motor stall detection, differential input LIN Auto- Addressing
– Selectable trigger source for software-driven, event-driven or time-dependent start of
the acquisition queue
– Operating clock derived from main oscillator
– Internal band-gap voltage reference VREF-ADC
– Acquisition queue for automatic sequential acquisition of up to eight entries
– Programmable gain amplifier with four possible gain settings
– Eight 16-bit sign-extended data registers
– End of conversion and trigger collision interrupt
The analog-to-digital converter allows the conversion of an analog voltage in the range
from VREF-ADC to +VREF-ADC. The reference voltage is derived from the internal band-
gap.
The acquisition queue holds up to eight entries and is executed after a defined start con-
dition. The entries contain the input source, the PGA gain setting and an entry enable
flag. The converted values are stored in dedicated result registers. If all valid entries of
the acquisition queue have been executed an interrupt indicates the end of the conver-
sion.
4.11.2. Clock and Reset System Control
The HVC 4x family includes system control registers for the clock system configuration,
ERM control, peripheral clock setup in debug mode, power-saving mode setup and
interrupt generation (MON and BVDD over/undervoltage).
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4.11.3. TIMER
– Two timer modules: TIM0 and TIM1
– Selectable input clocks: internal or external
– 16-bit input clock prescaler
– 16-bit timer counter
– Selectable operating modes: timer, compare or capture
– Optional buffering of prescaler, reload- and capture values
– Selectable output signal: static value, PWM signal or timer input signal
The HVC 4x family features two instances of the timer module (TIM0, TIM1) with identi-
cal implementation which operate independently from each other. The timer modules
are based on a 16-bit input clock prescaler and a 16-bit timer counter.
The timers can be used e.g. to generate periodic interrupts, to generate PWM output
signals or to measure the pulse length of input signals.
4.11.4. LIN-UART
– LIN 2.x compliant data link layer
– Full duplex in non-LIN mode
– 8-bit frames
– Parity: none, odd or even
– One or two stop bits
– Programmable inverters at transmit output and receive input
– Baud rate pre-scaler: adjustment accuracy <0.5% (for entire LIN bit-rate range)
– Interrupts: transmitted, form error, parity error, transmit error, break or synch detected,
RX FIFO not empty, RX/TX FIFO fill level reached, RX/TX FIFO overrun, TX FIFO
empty, RX/TX FIFO full
– Two independent 9-byte FIFOs for data reception and transmission
– Break/sync detection with automatic bit-rate adjustment in LIN mode
– Automatic LIN-header reception
The LIN-UART is a general purpose UART with enhanced features to unburden the CPU
from LIN communication. It is a full duplex UART which can handle 8-bit telegrams with or
without odd or even parity and one or two stop bits. The bit timing logic allows to adjust the
necessary bit rate in small steps in order to synchronize to the LIN bit rate with a minimum
residual error. Two 9-byte FIFOs are available for data reception and transmission. A bit-
rate adjustment logic can be used for automatic adjustment of the UART bit rate to the bit
rate of the LIN master. The enhanced features are optimized for the LIN slave mode.
The LIN-UART is compliant to the OEM requirement specification “Hardware Require-
ments for LIN, CAN and FlexRay Interfaces in Automotive Applications v1.3” from May 4,
2012.
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4.11.5. PWMIO
– Periodic input signal measurement (1 Hz to 10 kHz)
– Interrupt source (falling or rising edge, counter overflow, and end of period)
– Measurement of high- and low-time of the input signal
– Input deglitch filter with 3 µs selectable
– PWM signal output (single pulse, periodic, static low or high) at LIN pin or LGPIO
alternative output (refer to Table 2–2)
– Two independent 14-bit counters for input capture and output compare
The PWMIO module supports a bidirectional communication via a PWM protocol with
minimum CPU interaction. It can generate PWM output signals and measure the high-
and low-time of an applied PWM input signal. The input and output signals of the PWMIO
module are routed to the LIN port and to the LGPIO ports (as alternative functions).
4.11.6. Enhanced PWM (EPWM)
– Support of BLDC, BDC or stepper motor control
– Three EPWM control modules with programmable PWM period, PWM duty cycle and
ADC trigger signal
– Center- or edge-aligned PWM signal generation
– Multiplexers for each half-bridge to select control signals for high-side and low-side
switches
– Overcurrent and cross-current protection for each MOUT half-bridge
– Current limit mode with PWM duty cycle capture
– Three interrupt lines, each with five interrupt sources: end-of-period, compare value
matched, trigger value matched, capture event, overcurrent
– Programmable minimum on-time of PWM signal
– Buffered control registers
– Programmable slew rate for the half-bridges
The HVC 4x family features an enhanced PWM (EPWM) module with 12-bit resolution
to generate the digital control signals for the half-bridges that drive the MOUT ports. It is
optimized for BLDC, brush-type DC and bipolar stepper motor control supporting open
loop control modes (fixed voltage / fixed current) as well as closed loop current control
with minimum amount of SW interaction.
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4.11.7. Capture Compare Unit (CAPCOM)
– Processing of up to three channels in parallel
– 16-bit clock prescaler
– 16-bit free running CAPCOM counter
– 16-bit capture and compare registers for each channel
– Input capture event on rising, falling, or both edges
– Advanced capture mode with input pattern compare
– Optional buffering for configuration registers
– Three separately configurable output signals (static at logical '0', toggle on compare
and/or overflow events)
– One interrupt line for each CAPCOM channel triggered by: overflow, compare, capture,
capture overflow events; additional right / wrong pattern detection event for channel 0
The HVC 4x family features a capture-compare unit (CAPCOM) which is optimized to
capture and process up to three channels in parallel, e.g. three hall sensor signals for sen-
sor-based six-step BLDC motor control. In parallel the compare feature can be used to
generate up to three output signals which are routed as alternative function to LGPIO
ports.
4.11.8. SPI
– 4-line interface (CSN, SCK, MISO, MOSI), full-duplex
– Master operation only
– Programmable bit rate from 78.125 kHz up to 2.5 MHz
– Programmable clock phase and polarity
– 8-, 16-, 24-, and 32-bit data frames supported by HW chip select (CSN)
– Chip Select (CSN) generation by HW or SW
– Programmable order of data bits (MSB or LSB first)
– Receive and transmit FIFOs with 8 x 8 bit each, organized according to the data frame
width
– Interrupt generation at RX/TX events and FIFO flags
The SPI module provides a serial input and output link to external hardware, e.g. an
EEPROM.
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DATA SHEET
HVC 4x Family
4.11.9. Digital Watchdog (DWDG)
– 16-bit down counter
– Counter clock selectable
– Programmable trigger time
– Enabled by NVRAM setting or application SW
The digital watchdog module is used to supervise the program flow. A failure of the pro-
gram flow that prevents retriggering the watchdog within a configurable time will gener-
ate a reset. The occurrence of the reset is stored in the reset status register and so the
application SW can distinguish between a DWDG reset and any other reset source and
thus react accordingly.
4.11.10. Window Watchdog (WWDG) and Wake-Up Timer
– Auxiliary oscillator as clock source
– Trigger window adjustable from 100% to 0% of the counter period
– Counter clock selectable
– Can be used as wake-up timer in IDLE mode
– Wake-up time adjustable from 256/fAUX to 32768/fAUX (typ. 7.3 ms to 936 ms)
– Enabled by NVRAM setting or application SW
The window watchdog module is used to supervise the program flow and the clocks
generated by the main oscillator and the auxiliary oscillator. A failure of the program
flow or an oscillator malfunction that prevents continuous triggering of the watchdog
within a configurable time window will generate a reset. The occurrence of the reset is
stored in the reset status register. By evaluating the reset status register the application
SW can distinguish between a WWDG reset and any other reset source to react
accordingly.
In IDLE mode the WWDG module is configured as wake-up timer and can be used to
generate periodic wake-up events. The WWDG counter works then as wake-up counter
for periodic wake-up.
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July 9, 2021; DSH000216_001EN
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DATA SHEET
HVC 4x Family
5. Document History
1. Data Sheet: “HVC 4222F-D2 Flex Servo-Drive for Direct Control of BLDC/BDC/Stepper Motors in
High-Temperature Applications”, Edition March 23, 202, DSH000213_001EN. First release of the
HVC 4222F-D2 data sheet.
2. Data Sheet: “HVC 4x Family Motor Drivers for Control of BLDC, BDC, or Stepper Motors”, July 9,
2021, DSH 000216_001EN. First release of the HVC 4x family data sheet.
Major changes compared to the HVC 4222F-D2 data sheet:
– Combined single and double memory versions - temperature grade 1 and grade 1+.
– Increased ADC linear input voltage range via single-ended LGPIO ports from 2.7 V to 3.3 V.
TDK-Micronas GmbH
Hans-Bunte-Strasse 19 D-79108 Freiburg P.O. Box 840 D-79008 Freiburg, Germany
Tel. +49-761-517-0 Fax +49-761-517-2174 www.micronas.tdk.com
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July 9, 2021; DSH000216_001EN
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