IAM-20680HT [TDK]
IMU (惯性测量设备);
| 型号： | IAM-20680HT |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | IMU (惯性测量设备) |
| 文件： | 总55页 (文件大小：1956K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IAM-20680HT
High Performance Automotive 6-Axis MotionTracking Device
GENERAL DESCRIPTION
APPLICATIONS
The IAM-20680HT is a 6-axis MotionTracking device for
Automotive non-safety applications that combines a 3-
axis gyroscope and a 3-axis accelerometer in a thin
3x3x0.75mm3 (16-pin LGA) package. It also features a
4096-byte FIFO that can lower the traffic on the serial
bus interface and reduce power consumption by allowing
the system processor to burst read sensor data and then
go into a low-power mode. IAM-20680HT, with its 6-axis
integration, enables manufacturers to eliminate the
costly and complex selection, qualification, and system
level integration of discrete devices, guaranteeing
optimal motion performance.
IAM-20680HT address a wide range of Automotive
applications, including but not limited to:
•
•
•
Navigation Systems Aids for Dead Reckoning
Lift Gate Motion Detection
Accurate Location for Vehicle to Vehicle and
Infrastructure
•
•
•
•
•
View Camera Stabilization and Vision Systems
Head-up display (HUD) and augmented reality HUD
Car Alarm
Telematics
Insurance Vehicle Tracking
ORDERING INFORMATION
The gyroscope has a programmable full-scale range of
±250 dps, ±500 dps, ±1000 dps and ±2000 dps. The
accelerometer has a user-programmable accelerometer
full-scale range of ±2g, ±4g, ±8g, and ±16g. Factory-
calibrated initial sensitivity of both sensors reduces
production-line calibration requirements.
PART
AXES
TEMP RANGE
PACKAGE
MSL*
IAM-20680HT†
X, Y, Z -40°C to +105°C 16-Pin LGA
3
†Denotes RoHS and Green-compliant package
* Moisture sensitivity level of the package
FEATURES
Other industry-leading features include on-chip 16-bit
ADCs, programmable digital filters, an embedded
temperature sensor, and two programmable interrupts.
The device features I2C and SPI serial interfaces, a VDD
operating range of 1.71V to 3.6V, and a separate digital
IO supply, VDDIO from 1.71V to 3.6V.
•
Digital-output X-, Y-, and Z-axis angular rate sensors
(gyroscopes) with a user-programmable full-scale
range of ±250dps, ±500dps, ±1000dps, and
±2000dps, integrated 16-bit ADCs.
•
•
Digital-output X-, Y-, and Z-axis accelerometer with
a user-programmable full-scale range of ±2g, ±4g,
±8g, and ±16g and integrated 16-bit ADCs
User-programmable digital filters for gyroscope,
accelerometer, and temperature sensor
Embedded Self-test
Two interrupt lines
Wake-on-Motion interrupt for low-power operation
of applications processor
BLOCK DIAGRAM
•
•
•
•
Reliability testing performed according to
AEC–Q100: PPAP and qualification report available
upon request
•
Final test at -40°C, 25°C, and +105°C
TYPICAL OPERATING CIRCUIT
LONGEVITY COMMITMENT
To provide the best service for customers developing products
with a long-life cycle we have designed and engineered
products with longevity in mind. These products are designed
for harsher environments and are tested and manufactured to
higher accuracy and stability.
https://invensense.tdk.com/longevity/
InvenSense, Inc. reserves the right to change
specifications and information herein without notice
unless the product is in mass production and the
datasheet has been designated by InvenSense in
writing as subject to a specified Product / Process
Change Notification Method regulation.
InvenSense, a TDK Group Company
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 988–7339
Document Number: DS-000481
Revision: 1.1
Rev. Date: 02/15/2022
invensense.tdk.com
IAM-20680HT
TABLE OF CONTENTS
General Description............................................................................................................................................ 1
Block Diagram..................................................................................................................................................... 1
Applications........................................................................................................................................................ 1
Ordering Information ......................................................................................................................................... 1
Features.............................................................................................................................................................. 1
Typical Operating Circuit .................................................................................................................................... 1
TABLE OF CONTENTS ..................................................................................................................................................... 2
LIST OF FIGURES ............................................................................................................................................................ 5
LIST OF TABLES .............................................................................................................................................................. 6
1
2
3
Introduction........................................................................................................................................................ 7
Purpose and Scope .................................................................................................................................. 7
Product Overview .................................................................................................................................... 7
Applications ............................................................................................................................................. 7
Features.............................................................................................................................................................. 8
Gyroscope Features................................................................................................................................. 8
Accelerometer Features .......................................................................................................................... 8
Additional Features.................................................................................................................................. 8
Electrical Characteristics..................................................................................................................................... 9
Gyroscope Specifications......................................................................................................................... 9
Accelerometer Specifications ................................................................................................................10
Electrical Specifications ......................................................................................................................... 11
I2C Timing Characterization ...................................................................................................................14
SPI Timing Characterization...................................................................................................................15
Absolute Maximum Ratings...................................................................................................................16
Thermal Information.............................................................................................................................. 16
Applications Information.................................................................................................................................. 17
Pin Out Diagram and Signal Description................................................................................................17
Typical Operating Circuit........................................................................................................................ 18
Bill of Materials for External Components.............................................................................................18
Block Diagram........................................................................................................................................ 19
Overview................................................................................................................................................ 19
Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning..............................................20
Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning .......................................20
I2C and SPI Serial Communications Interfaces.......................................................................................20
Self-Test ................................................................................................................................................. 21
Clocking.................................................................................................................................................. 21
4
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IAM-20680HT
Sensor Data Registers ............................................................................................................................ 22
FIFO........................................................................................................................................................ 22
Interrupts............................................................................................................................................... 22
Digital-Output Temperature Sensor ......................................................................................................22
Bias and LDOs ........................................................................................................................................ 22
Charge Pump ......................................................................................................................................... 22
Standard Power Modes ......................................................................................................................... 22
Sensor Initialization and Basic Configuration ........................................................................................23
Programmable Interrupts................................................................................................................................. 25
Wake-on-Motion Interrupt....................................................................................................................25
Digital Interface ................................................................................................................................................ 26
I2C and SPI Serial Interfaces ...................................................................................................................26
I2C Interface ........................................................................................................................................... 26
IC Communications Protocol .................................................................................................................26
I2C Terms................................................................................................................................................ 28
SPI Interface........................................................................................................................................... 29
Serial Interface Considerations......................................................................................................................... 30
IAM-20680HT Supported Interfaces......................................................................................................30
Register Map .................................................................................................................................................... 31
Register Descriptions........................................................................................................................................ 33
Registers 0 to 2 – Gyroscope Self-Test Registers...................................................................................33
Registers 13 to 15 – Accelerometer Self-Test Registers ........................................................................33
Register 19 – Gyro Offset Adjustment Register.....................................................................................34
Register 20 – Gyro Offset Adjustment Register.....................................................................................34
Register 21 – Gyro Offset Adjustment Register.....................................................................................34
Register 22 – Gyro Offset Adjustment Register.....................................................................................34
Register 23 – Gyro Offset Adjustment Register.....................................................................................35
Register 24 – Gyro Offset Adjustment Register.....................................................................................35
Register 25 – Sample Rate Divider.........................................................................................................35
Register 26 – Configuration ...................................................................................................................35
Register 27 – Gyroscope Configuration .................................................................................................36
Register 28 – Accelerometer Configuration ..........................................................................................36
Register 29 – Accelerometer Configuration 2........................................................................................37
Register 30 – Low Power Mode Configuration......................................................................................38
Register 31 – Wake-on Motion Threshold (Accelerometer)..................................................................39
Register 35 – FIFO Enable ...................................................................................................................... 39
Register 54 – FSYNC Interrupt Status.....................................................................................................40
5
6
7
8
9
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IAM-20680HT
Register 55 – INT/INT2 Pin / Bypass Enable Configuration....................................................................40
Register 56 – Interrupt Enable...............................................................................................................41
Register 58 – Interrupt Status................................................................................................................41
Registers 59 to 64 – Accelerometer Measurements .............................................................................41
Registers 65 and 66 – Temperature Measurement...............................................................................42
Registers 67 to 72 – Gyroscope Measurements ....................................................................................42
Register 104 – Signal Path Reset............................................................................................................44
Register 105 – Accelerometer Intelligence Control...............................................................................44
Register 106 – User Control...................................................................................................................44
Register 107 – Power Management 1 ...................................................................................................45
Register 108 – Power Management 2 ...................................................................................................45
Registers 114 and 115 – FIFO Count Registers ......................................................................................46
Register 116 – FIFO Read Write.............................................................................................................47
Register 117 – Who Am I ....................................................................................................................... 47
Registers 119, 120, 122, 123, 125, 126 Accelerometer Offset Registers...............................................48
Assembly .......................................................................................................................................................... 49
Orientation of Axes................................................................................................................................ 49
Package Dimensions .............................................................................................................................. 50
Part Number Package Marking......................................................................................................................... 52
Reference ......................................................................................................................................................... 53
Revision History................................................................................................................................................ 54
10
11
12
13
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Revision: 1.1
Page 4 of 55
IAM-20680HT
LIST OF FIGURES
Figure 1. I2C Bus Timing Diagram.................................................................................................................................14
Figure 2. SPI Bus Timing Diagram ................................................................................................................................15
Figure 3. Pin out Diagram for IAM-20680HT 3.0x3.0x0.75mm3 LGA...........................................................................17
Figure 4. IAM-20680HT LGA Application Schematic....................................................................................................18
Figure 5. IAM-20680HT Block Diagram........................................................................................................................19
Figure 6. IAM-20680HT Solution Using I2C Interface...................................................................................................20
Figure 7. IAM-20680HT Solution Using SPI Interface ..................................................................................................21
Figure 8. START and STOP Conditions..........................................................................................................................26
Figure 9. Acknowledge on the I2C Bus .........................................................................................................................27
Figure 10. Complete I2C Data Transfer ........................................................................................................................27
Figure 11. Typical SPI Master/Slave Configuration......................................................................................................29
Figure 12. I/O Levels and Connections ........................................................................................................................30
Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation........................................................................49
Figure 14. Package Dimensions ...................................................................................................................................50
Figure 15. Part Number Package Marking...................................................................................................................52
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Revision: 1.1
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IAM-20680HT
LIST OF TABLES
Table 1. Gyroscope Specifications .................................................................................................................................9
Table 2. Accelerometer Specifications ........................................................................................................................10
Table 3. D.C. Electrical Characteristics.........................................................................................................................11
Table 4. A.C. Electrical Characteristics.........................................................................................................................13
Table 5. Other Electrical Specifications .......................................................................................................................13
Table 6. I2C Timing Characteristics...............................................................................................................................14
Table 7. SPI Timing Characteristics (8 MHz Operation) ...............................................................................................15
Table 8. Absolute Maximum Ratings ...........................................................................................................................16
Table 9. Thermal Information......................................................................................................................................16
Table 10. Signal Descriptions.......................................................................................................................................17
Table 11. Bill of Materials ............................................................................................................................................18
Table 12. Standard Power Modes for IAM-20680HT...................................................................................................22
Table 13. Table of Interrupt Sources ...........................................................................................................................25
Table 14. Serial Interface.............................................................................................................................................26
Table 15. I2C Terms......................................................................................................................................................28
Table 16. Register Map................................................................................................................................................32
Table 17. Gyroscope and Temperature Sensor Data Rates and Bandwidths (Low-Noise Mode) ...............................36
Table 18. Accelerometer Data Rates and Bandwidths (Low-Noise Mode)..................................................................37
Table 19. Example Configurations for Accelerometer WoM Mode ............................................................................38
Table 20. Example Configurations for Gyroscope when GYRO_CYCLE = 1..................................................................39
Table 21. Package Dimensions ....................................................................................................................................51
Table 22. Part Number Package Marking ....................................................................................................................52
Document Number: DS-000481
Revision: 1.1
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IAM-20680HT
1 INTRODUCTION
PURPOSE AND SCOPE
This document is a product specification, providing description, specifications, and design related information on
the IAM-20680HT Automotive MotionTracking device. The device is housed in a thin 3x3x0.75 mm3 16-pin LGA
package.
PRODUCT OVERVIEW
The IAM-20680HT is a 6-axis MotionTracking device for Automotive non-safety applications, that combines a 3-axis
gyroscope and a 3-axis accelerometer in a thin 3x3x0.75 mm3 (16-pin LGA) package. It also features a 4096-byte
FIFO that can lower the traffic on the serial bus interface and reduce power consumption by allowing the system
processor to burst read sensor data and then go into a low-power mode. IAM-20680HT, with its 6-axis integration,
enables manufacturers to eliminate the costly and complex selection, qualification, and system level integration of
discrete devices, guaranteeing optimal motion performance.
The gyroscope has a programmable full-scale range of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps. The
accelerometer has a user-programmable accelerometer full-scale range of ±2g, ±4g, ±8g, and ±16g. Factory-
calibrated initial sensitivity of both sensors reduces production-line calibration requirements.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts. The device features I2C and SPI serial interfaces, a VDD
operating range of 1.71V to 3.6V, and a separate digital IO supply, VDDIO from 1.71V to 3.6V.
Communication with all registers of the device is performed using either I2C at 400 kHz or SPI at 8 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers
with companion CMOS electronics through wafer-level bonding, TDK-InvenSense has driven the package size down
to a footprint and thickness of 3x3x0.75 mm3 (16-pin LGA), to provide a very small yet high-performance. The
device provides high robustness by supporting 10,000g shock reliability.
APPLICATIONS
•
•
•
•
•
•
•
•
Navigation Systems Aids for Dead Reckoning
Lift Gate Motion Detections
Accurate Location for Vehicle to Vehicle and Infrastructure
View Camera Stabilization and Vision Systems
Head-up display (HUD) and augmented reality HUD
Car Alarm
Telematics
Insurance Vehicle Tracking
Document Number: DS-000481
Revision: 1.1
Page 7 of 55
IAM-20680HT
2 FEATURES
GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the IAM-20680HT includes a wide range of features:
•
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-scale
range of ±250 dps, ±500 dps, ±1000 dps and ±2000 dps and integrated 16-bit ADCs
Digitally-programmable low-pass filter
Factory calibrated sensitivity scale factor
Self-test
•
•
•
ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in IAM-20680HT includes a wide range of features:
•
Digital-output X-, Y-, and Z-axis accelerometer with a programmable full-scale range of ±2g, ±4g, ±8g and
±16g and integrated 16-bit ADCs
•
•
•
Two user-programmable interrupts
Wake-on-Motion (WoM) interrupt for low-power operation of applications processor
Self-test
ADDITIONAL FEATURES
The IAM-20680HT includes the following additional features:
•
•
•
•
•
•
•
•
•
•
Thinnest LGA package for automotive applications: 3x3x0.75 mm3 (16-pin LGA)
Minimal cross-axis sensitivity between the accelerometer and gyroscope axes
4096-byte FIFO buffer enables the applications processor to read the data in bursts
Digital-output temperature sensor
User-programmable digital filters for gyroscope, accelerometer, and temperature sensor
10,000g shock tolerant
400 kHz Fast Mode I2C for communicating with all registers
8 MHz SPI serial interface for communicating with all registers
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
Document Number: DS-000481
Revision: 1.1
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IAM-20680HT
3 ELECTRICAL CHARACTERISTICS
GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, Full Scale = 2000dps, Low-Noise
Mode enabled unless otherwise noted.
All Zero-rate output, sensitivity, and noise specifications include board soldering effects, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
GYROSCOPE SENSITIVITY
FS_SEL=0
FS_SEL=1
FS_SEL=2
FS_SEL=3
±250
±500
±1000
±2000
16
dps
dps
dps
dps
bits
3
3
3
3
3
3
3
3
3
1
1
Full-Scale Range
Gyroscope ADC Word Length
Sensitivity Scale Factor
FS_SEL=0
FS_SEL=1
FS_SEL=2
FS_SEL=3
Best fit straight line; 25°C
25°C
131
LSB/(dps)
LSB/(dps)
LSB/(dps)
LSB/(dps)
%
65.5
32.8
16.4
±0.1
±1
Nonlinearity
Cross-Axis Sensitivity
%
ZERO-RATE OUTPUT (ZRO)
ZRO Tolerance
ZRO Variation Over Temperature
All axes combined, 25°C
±0.8
±1.0
dps
dps
1,2
1,2
All axes combined, -40°C to +105°C
GYROSCOPE NOISE PERFORMANCE
25°C, initial, Noise BW = 306 Hz,
VDD = VDDIO = 1.8V
Rate Noise Spectral Density
0.005
27
dps/√Hz
1,4
Gyroscope Mechanical Frequencies
Low Pass Filter Response
Gyroscope Start Up Time
KHz
Hz
ms
2
3
1
Programmable Range
From Sleep mode, 25°C
Programmable, Normal (Filtered)
mode
5
4
250
50
35
Output Data Rate
8000
Hz
1
Table 1. Gyroscope Specifications
Notes:
1. Based on characterization data on a limited number of parts.
2. Tested in production at component level. Over temperature tests are performed at 25°C, 105°C, and/or -40°C.
3. Guaranteed by design.
4. Calculated from Total RMS Noise.
Document Number: DS-000481
Revision: 1.1
Page 9 of 55
IAM-20680HT
ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, Full Scale = 8g, Low-Noise Mode
enabled unless otherwise noted.
All Zero-g output, sensitivity, and noise specifications include board soldering effects, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ACCELEROMETER SENSITIVITY
AFS_SEL=0
AFS_SEL=1
AFS_SEL=2
AFS_SEL=3
Output in two’s complement format
AFS_SEL=0
AFS_SEL=1
AFS_SEL=2
AFS_SEL=3
Best Fit Straight Line for 2g, 25°C
25°C
±2
±4
±8
±16
16
16,384
8,192
4,096
2,048
±0.05
±1
g
g
g
3
3
3
3
3
3
3
3
3
1
1
Full-Scale Range
g
ADC Word Length
bits
LSB/g
LSB/g
LSB/g
LSB/g
%
Sensitivity Scale Factor
Nonlinearity
Cross-Axis Sensitivity
%
ZERO-G OUTPUT
All axes combined, 25°C
Zero-G Level Tolerance
Zero-G Level Variation Over
Temperature
±50
±50
mg
mg
1,2
1,2
All axes combined, -40°C to +105°C
NOISE PERFORMANCE
Low-noise mode, +25°C, initial,
Noise BW = 235 Hz, VDD = VDDIO = 1.8V
Programmable Range
From Sleep mode, 25°C
Low-noise (active)
Power Spectral Density
135
µg/√Hz
1,4
Low Pass Filter Response
Accelerometer Start-up Time
Output Data Rate
5
4
218
20
4000
Hz
ms
Hz
3
1
1
Table 2. Accelerometer Specifications
Notes:
1. Based on characterization data on a limited number of parts.
2. Tested in production at component level. Over temperature tests are performed at 25°C, 105°C, and/or -40°C.
3. Guaranteed by design.
4. Calculated from Total RMS Noise.
Document Number: DS-000481
Revision: 1.1
Page 10 of 55
IAM-20680HT
ELECTRICAL SPECIFICATIONS
D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, Low-Noise Mode enabled unless
otherwise noted.
PARAMETER
CONDITIONS
SUPPLY VOLTAGES
MIN
TYP
MAX
UNITS
NOTES
VDD
VDDIO
1.71
1.71
1.8
1.8
3.6
3.6
V
V
1
1
SUPPLY CURRENTS & BOOT TIME
6-axis Gyroscope + Accelerometer,
-40°C to +105°C
3
3.75
mA
1
Low-Noise Mode
3-axis Gyroscope
3-axis Accelerometer, 4 kHz ODR
2.6
390
6
mA
µA
µA
1
1
1
Full-Chip Sleep Mode
TEMPERATURE RANGE
Specified Temperature Range
Performance parameters are not applicable
beyond Specified Temperature Range
-40
+105
°C
1,2
Table 3. D.C. Electrical Characteristics
Notes:
1. Based on characterization data on a limited number of parts.
2. Based on qualification.
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Revision: 1.1
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IAM-20680HT
A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLIES
Supply Ramp Time (TRAMP
)
Monotonic ramp. Ramp
rate is 10% to 90% of the
final value
0.01
100
ms
1
TEMPERATURE SENSOR
Operating Range
Room Temperature Offset
Sensitivity
Ambient
25°C
Untrimmed
-40
105
°C
°C
LSB/°C
1
1
1
0
326.8
POWER-ON RESET
Supply Ramp Time (TRAMP
)
Valid power-on RESET
From power-up
From sleep
0.01
100
100
5
ms
ms
ms
1
1
1
11
Start-up time for register read/write
SA0 = 0
SA0 = 1
1101000
1101001
I2C ADDRESS
DIGITAL INPUTS (FSYNC, SA0, SPC, SDI, CS)
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
0.7*VDDIO
V
V
pF
0.3*VDDIO
1
1
< 10
DIGITAL OUTPUT (SDO, INT)
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT, INT Low-Level Output Voltage
RLOAD=1 MΩ;
RLOAD=1 MΩ;
OPEN=1, 0.3 mA sink
Current
0.9*VDDIO
V
V
V
0.1*VDDIO
0.1
Output Leakage Current
tINT, INT Pulse Width
OPEN=1
LATCH_INT_EN=0
100
50
nA
µs
I2C I/O (SCL, SDA)
VIL, LOW Level Input Voltage
VIH, HIGH-Level Input Voltage
-0.5V
0.7*VDDIO
0.3*VDDIO
VDDIO + 0.5
V
V
V
Vhys, Hysteresis
0.1*VDDIO
V
VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current
3 mA sink current
VOL=0.4V
VOL=0.6V
0
0.4
V
1
3
6
100
mA
mA
nA
Output Leakage Current
tof, Output Fall Time from VIHmax to
VILmax
Cb bus capacitance in pf
20+0.1Cb
300
ns
Document Number: DS-000481
Revision: 1.1
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IAM-20680HT
INTERNAL CLOCK SOURCE
FCHOICE_B=1,2,3
SMPLRT_DIV=0
FCHOICE_B=0;
DLPFCFG=0 or 7
SMPLRT_DIV=0
FCHOICE_B=0;
32
8
kHz
kHz
2
2
Sample Rate
DLPFCFG=1,2,3,4,5,6;
SMPLRT_DIV=0
1
kHz
2
CLK_SEL=0, 6 or gyro
inactive; 25°C
CLK_SEL=1,2,3,4,5 and gyro
active; 25°C
CLK_SEL=0,6 or gyro
inactive
CLK_SEL=1,2,3,4,5 and gyro
active
-5
-1
+5
+1
%
%
%
%
1
1
1
1
Clock Frequency Initial Tolerance
-10
-1
+10
+1
Frequency Variation over
Temperature
Table 4. A.C. Electrical Characteristics
Notes:
1. Based on characterization data on a limited number of parts.
2. Guaranteed by design.
Other Electrical Specifications
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
SERIAL INTERFACE
MIN
TYP
MAX
UNITS NOTES
100
±10%
1
Low Speed Characterization
High Speed Characterization
kHz
1
SPI Operating Frequency, All
Registers Read/Write
8
MHz
1, 2
Modes 0
and 3
SPI Modes
All registers, Fast-mode
All registers, Standard-mode
400
100
kHz
kHz
1
1
I2C Operating Frequency
Table 5. Other Electrical Specifications
Notes:
1. Based on characterization data on a limited number of parts.
2. SPI clock duty cycle between 45% and 55% should be used for 8-MHz operation.
Document Number: DS-000481
Revision: 1.1
Page 13 of 55
IAM-20680HT
I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETERS
I2C TIMING
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
I2C FAST-MODE
fSCL, SCL Clock Frequency
tHD.STA, (Repeated) START Condition Hold Time
400
kHz
µs
1
1
0.6
tLOW, SCL Low Period
tHIGH, SCL High Period
tSU.STA, Repeated START Condition Setup Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
1.3
0.6
0.6
0
100
20+0.1Cb
20+0.1Cb
0.6
µs
µs
µs
µs
ns
ns
ns
µs
1
1
1
1
1
1
1
1
Cb bus cap. from 10 to 400 pF
Cb bus cap. from 10 to 400 pF
300
300
tf, SDA and SCL Fall Time
tSU.STO, STOP Condition Setup Time
tBUF, Bus Free Time Between STOP and START
Condition
1.3
µs
1
Cb, Capacitive Load for each Bus Line
tVD.DAT, Data Valid Time
tVD.ACK, Data Valid Acknowledge Time
< 400
pF
µs
µs
1
1
1
0.9
0.9
Table 6. I2C Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
t
f
tSU.DAT
t
r
SDA
SCL
70%
30%
70%
30%
continued below at
A
t
f
t
r
t
VD.DAT
70%
30%
70%
30%
t
HD.DAT
9
th clock cycle
tHD.STA
1/fSCL
tLOW
1
st clock cycle
S
t
HIGH
t
BUF
SDA
SCL
70%
30%
A
tSU.STO
t
SU.STA
tHD.STA
t
VD.ACK
70%
30%
th clock cycle
S
P
Sr
9
Figure 1. I2C Bus Timing Diagram
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Revision: 1.1
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IAM-20680HT
SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
NOTES
PARAMETERS
SPI TIMING
CONDITIONS
MIN
TYP
MAX
UNITS
fSPC, SPC Clock Frequency
tLOW, SPC Low Period
tHIGH, SPC High Period
tSU.CS, CS Setup Time
tHD.CS, CS Hold Time
8
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
2
2
56
56
2
63
3
tSU.SDI, SDI Setup Time
tHD.SDI, SDI Hold Time
tVD.SDO, SDO Valid Time
tHD.SDO, SDO Hold Time
tDIS.SDO, SDO Output Disable Time
tFall, SCLK Fall Time
7
Cload = 20 pF
Cload = 20 pF
40
6
20
6.5
6.5
tRise, SCLK Rise Time
Table 7. SPI Timing Characteristics (8 MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
2. Based on other parameter values.
CS
70%
30%
tFall
tRise
t
HD;CS
t
SU;CS
70%
t
HIGH
1/fCLK
SCLK
30%
tSU;SDI
t
HD;SDI
tLOW
70%
30%
SDI
LSB IN
MSB IN
tDIS;SDO
tVD;SDO
t
HD;SDO
70%
30%
SDO
MSB OUT
LSB OUT
Figure 2. SPI Bus Timing Diagram
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IAM-20680HT
ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the
absolute maximum ratings conditions for extended periods may affect device reliability.
PARAMETER
RATING
-0.5V to 4V
Supply Voltage, VDD
Supply Voltage, VDDIO
REGOUT
-0.5V to 4V
-0.5V to 2V
Input Voltage Level (SA0, FSYNC, SCL, SDA)
Acceleration (Any Axis, unpowered)
Temperature Range
-0.5V to VDDIO + 0.5V
10,000g for 0.2ms
-40°C to 105°C
Storage Temperature Range
-40°C to 125°C
2 kV (HBM);
Electrostatic Discharge (ESD) Protection
750V (CDM corner pins)
500V (CDM all other pins)
JEDEC Class II (2),125°C
±100 mA
Latch-up
Ultrasonic excitation (cleaning/welding/…)
Not allowed
Table 8. Absolute Maximum Ratings
THERMAL INFORMATION
THERMAL METRIC
DESCRIPTION
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
VALUE
84.58 °C/W
7 °C/W
θJA
ψJT
Table 9. Thermal Information
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IAM-20680HT
4 APPLICATIONS INFORMATION
PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
PIN NUMBER
PIN NAME
VDDIO
SCL/SPC
SDA/SDI
SA0/SDO
CS
INT
INT2
FSYNC
RESV
PIN DESCRIPTION
Digital I/O supply voltage
1
2
3
4
5
6
7
8
9
I2C serial clock (SCL); SPI serial clock (SPC)
I2C serial data (SDA); SPI serial data input (SDI)
I2C slave address LSB (SA0); SPI serial data output (SDO)
Chip select (0 = SPI mode; 1 = I2C mode)
Interrupt digital output (push-pull or open-drain)
Second Interrupt digital output (push-pull or open-drain)
Synchronization digital input (optional). Connect to GND if unused
Reserved. Connect to GND
10
11
12
13
14
15
RESV
RESV
RESV
GND
Reserved. Connect to GND
Reserved. Connect to GND
Reserved. Connect to GND
Connect to GND
REGOUT
Regulator filter capacitor connection
RESV
Reserved. Connect to GND
16
VDD
Power Supply
Table 10. Signal Descriptions
Note: VDD, VDDIO, SCL/SPC and CS pins must be correctly managed at power-up to guarantee proper IAM-20680HT start-up. Please refer to
sections 4.18.1 and 4.18.2 for detailed power-up instructions.
Figure 3. Pin out Diagram for IAM-20680HT 3.0x3.0x0.75mm3 LGA
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IAM-20680HT
TYPICAL OPERATING CIRCUIT
Figure 4. IAM-20680HT LGA Application Schematic
Note: I2C lines are open drain and pullup resistors (e.g. 10 kΩ) are required.
BILL OF MATERIALS FOR EXTERNAL COMPONENTS
COMPONENT
REGOUT Capacitor
LABEL
C1
SPECIFICATION
QUANTITY
X7R, 0.47 µF ±10%
X7R, 0.1 µF ±10%
X7R, 2.2 µF ±10%
X7R, 10 nF ±10%
1
1
1
1
C2
VDD Bypass Capacitors
VDDIO Bypass Capacitor
C4
C3
Table 11. Bill of Materials
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IAM-20680HT
BLOCK DIAGRAM
Figure 5. IAM-20680HT Block Diagram
OVERVIEW
The IAM-20680HT is comprised of the following key blocks and functions:
•
•
•
•
•
•
•
•
•
•
•
•
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
Primary I2C and SPI serial communications interfaces
Self-Test
Clocking
Sensor Data Registers
FIFO
Two independent Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes
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IAM-20680HT
THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The IAM-20680HT consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the
X-, Y-, and Z- Axes. When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration
that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a
voltage that is proportional to the angular rate. This voltage is digitized using individual on-chip 16-bit Analog-to-
Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors may be digitally
programmed to ±250, ±500, ±1000, or ±2000 degrees per second (dps). The ADC sample rate is programmable
from 8,000 samples per second, down to 3.9 samples per second, and user-selectable low-pass filters enable a
wide range of cut-off frequencies.
THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The IAM-20680HT’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular
axis induces displacement on the corresponding proof mass, and capacitive sensors detect the displacement
differentially. The IAM-20680HT’s architecture reduces the accelerometers’ susceptibility to fabrication variations
as well as to thermal drift. When the device is placed on a flat surface, it will measure 0g on the X- and Y-axes and
+1g on the Z-axis. The accelerometers’ scale factor is calibrated at the factory and is nominally independent of
supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs. The full-scale range of
the digital output can be adjusted to ±2g, ±4g, ±8g, or ±16g.
I2C AND SPI SERIAL COMMUNICATIONS INTERFACES
The IAM-20680HT communicates to a system processor using either a SPI or an I2C serial interface. The IAM-
20680HT always acts as a slave when communicating to the system processor. The LSB of the I2C slave address is
set by pin 4 (SA0).
IAM-20680HT Solution Using I2C Interface
In Figure 6, the system processor is an I2C master to the IAM-20680HT.
Figure 6. IAM-20680HT Solution Using I2C Interface
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IAM-20680HT
IAM-20680HT Solution Using SPI Interface
In Figure 7, the system processor is an SPI master to the IAM-20680HT. Pins 2, 3, 4, and 5 are used to support the
SPC, SDI, SDO, and CS signals for SPI communications.
Figure 7. IAM-20680HT Solution Using SPI Interface
SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each
measurement axis can be activated by means of the gyroscope and accelerometer self-test registers (registers 27
and 28).
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The
output signal is used to observe the self-test response.
The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED
When the value of the self-test response is within the specified min/max limits of the product specification, the
part has passed self-test. When the self-test response exceeds the min/max values, the part is deemed to have
failed self-test.
CLOCKING
The IAM-20680HT has a flexible clocking scheme, allowing a variety of internal clock sources to be used for the
internal synchronous circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various
control circuits and registers. An on-chip PLL provides flexibility in the allowable inputs for generating this clock.
Allowable internal sources for generating the internal clock are:
a) An internal relaxation oscillator
b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best
available source
The only setting supporting specified performance in all modes is option b). It is recommended that option b) be
used.
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IAM-20680HT
SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They
are read-only registers and are accessed via the serial interface. Data from these registers may be read anytime.
FIFO
The IAM-20680HT contains a 4096-byte FIFO register that is accessible via the Serial Interface. The FIFO
configuration register determines which data are written into the FIFO. Possible choices include gyro data,
accelerometer data, temperature readings, and FSYNC input. A FIFO counter keeps track of how many bytes of
valid data are contained in the FIFO. The FIFO register supports burst reads. The interrupt function may be used to
determine when new data are available.
INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the
INT pin configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can
trigger an interrupt are new data are available to be read (from the FIFO and Data registers), FIFO overflow wake
on motion. The interrupt status can be read from the Interrupt Status register.
DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the IAM-20680HT die temperature. The readings
from the ADC can be read from the FIFO or the Sensor Data registers.
BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the
IAM-20680HT. Its two inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output
is bypassed by a capacitor at REGOUT. For further details on the capacitor, please refer to the Bill of Materials for
External Components.
CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
STANDARD POWER MODES
Table 12 lists the user-accessible power modes for IAM-20680HT.
MODE
NAME
GYRO
Off
Drive On
Off
ACCEL
Off
Off
Duty-Cycled
On
1
2
3
4
5
6
Sleep Mode
Standby Mode
Accelerometer Wake-on-Motion (WoM) Mode
Accelerometer Low-Noise Mode
Gyroscope Low-Noise Mode
Off
On
On
Off
On
6-Axis Low-Noise Mode
Table 12. Standard Power Modes for IAM-20680HT
Notes:
1. Power consumption for individual modes can be found in section 3.3.1.
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IAM-20680HT
SENSOR INITIALIZATION AND BASIC CONFIGURATION
The basic configuration of the IAM-20680HT includes the following steps:
•
•
•
•
•
•
•
Power-up sequence
Sensor initialization and clock source selection
Digital interface access test
Output data rate (i.e. sampling frequency) selection
Full scale range selection
Filter frequency selection
Power mode selection
Power-up sequence
When applying VDD, the power voltage ramp is detected and a power-on-reset sequence is triggered inside the
component. During this phase the device starts operating and internal logic levels are defined. For proper
component initialization the power-up should be performed with both CS and SCL/SPC low, ensuring that CS and
SCL pins are not in an undetermined state during the VDD ramp. If starting in I2C mode (CS at logic high), power-up
should be performed with SCL/SPC low. Power-up with SCL/SPC high is not a supported case and must be avoided.
It is worth noting that if the I/O pins (e.g. CS, SCL/SPC) are between VIL and VIH when the power-on-reset sequence
is triggered, their value is undetermined and the internal logic levels may not be properly defined. It should also be
noted that VIL and VIH are related to VDDIO and their value changes at power-up according to the applied VDDIO
voltage ramp.
Power-up sequences that do not respect the conditions above may not lead to proper digital interface initialization.
In this case a preliminary soft reset operation (PWR_MGMT_1 register set 0x81) must be performed to reset the
digital interface, as soon as both VDD and VDDIO are stable at their final voltage. Since the digital interface may not
be properly initialized, the device may not provide the acknowledge signal if the I2C protocol is used.
Sensor Initialization and Clock Source Selection
When power-up sequence is completed (as per section 4.18.1), a soft reset is required to initialize the sensor and
let the IAM-20680HT select the best clock source. The soft reset must be performed by setting the register
PWR_MGMT_1 (address 0x6B) to 0x81 (see section 9.27), prior to registers initialization.
Soft reset must be performed as first operation after the power-up sequence to ensure the proper component
registers setting.
Correct WHO_AM_I value is ensured only after the soft reset has been completed.
Digital interface access test
When soft reset is completed, make sure the component registers access can be done as expected. WHO_AM_I
(address 0x75) register can be used for this purpose to verify the identity of the device.
Output Data Rate Selection
To set the output data rate (ODR) to the desired frequency, select the sample rate divider by setting the register
SMPLRT_DIV (address 0x19) to the desired value (see section 9.9). For instance, to set the output data rate to 100
Hz, write 0x09 into SMPLRT_DIV.
Full-Scale Range Selection
To set the full-scale range (FSR) of the accelerometer, set the register ACCEL_CONFIG (address 0x1C) to the desired
value (see section 9.12). For instance, to set the FSR of the accelerometer to 2g, write 0x00 into ACCEL_CONFIG.
To set the FSR of the gyroscope, set the register GYRO_CONFIG (address 0x1B) to the desired value (see section
9.11). For instance, to set the FSR of the gyroscope to 250 dps, write 0x00 into GYRO_CONFIG.
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IAM-20680HT
Filter Selection
To set the corner frequency of the digital low-pass filter (DLPF) of the accelerometer, set the register
ACCEL_CONFIG2 (address 0x1D) to the desired value (see section 9.13). For instance, to set the corner frequency
of the DLPF of the accelerometer to 10.2 Hz, write 0x05 into ACCEL_CONFIG2.
To set the corner frequency of the DLPF of the gyroscope, set the register CONFIG (address 0x1A) to the desired
value (see section 9.10). For instance, to set the corner frequency of the DLPF of the gyroscope to 10 Hz, write
0x05 into CONFIG.
Power mode selection
To set desired power modes for IAM-20680HT (see section 4.17).
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IAM-20680HT
5 PROGRAMMABLE INTERRUPTS
The IAM-20680HT has a programmable interrupt system which can generate an interrupt signal on the INT pin.
Status flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually.
INTERRUPT NAME
Motion Detection
MODULE
Motion
FIFO Overflow
Data Ready
FIFO
Sensor Registers
Table 13. Table of Interrupt Sources
WAKE-ON-MOTION INTERRUPT
The IAM-20680HT provides motion detection capability. A qualifying motion sample is one where the high passed
sample from any axis has an absolute value exceeding a user-programmable threshold. The following steps explain
how to configure the Wake-on-Motion Interrupt.
Step 1: Ensure that Accelerometer is running
•
In PWR_MGMT_1 register (0x6B) set ACCEL_CYCLE = 0, SLEEP = 0, and GYRO_STANDBY = 0
Step 2: Accelerometer Configuration
In ACCEL_CONFIG2 register (0x1D) set ACCEL_FCHOICE_B = 0 and A_DLPF_CFG[2:0] = b111
Step 3: Enable Motion Interrupt
•
•
In INT_ENABLE register (0x38) set WOM_INT_EN[2:0] = b111 to enable motion interrupt
Once triggered, WOM interrupt is generated on INT pin (if INT2_EN bit is set to 0) or on INT2 pin (if INT2_EN is set
to 1).
Step 4: Set Motion Threshold
•
Set the motion threshold in ACCEL_WOM_THR register (0x1F)
Step 5: Enable Accelerometer Hardware Intelligence
•
•
•
In ACCEL_INTEL_CTRL register (0x69) set ACCEL_INTEL_EN = 1 to enable the Wake-on-Motion detection
logic
In ACCEL_INTEL_CTRL register (0x69) set ACCEL_INTEL_MODE = 1 to make the detection insensitive to the
acceleration DC-component
In ACCEL_INTEL_CTRL register (0x69) ensure that bit 0 is set to 0.
Step 6: Set Accelerometer WoM ODR Selection
In LP_MODE_CFG register (0x1E) set ACCEL_WOM_ODR_CTRL[3:0] according to Table 19
Step 7: Enable Cycle Mode (Accelerometer WoM Mode)
•
•
In PWR_MGMT_2 register (0x6C) set STBY_XA = STBY_YA = STBY_ZA = 0, and STBY_XG = STBY_YG =
STBY_ZG = 1
•
In PWR_MGMT_1 register (0x6B) set ACCEL_CYCLE = 1
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IAM-20680HT
6 DIGITAL INTERFACE
I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the IAM-20680HT can be accessed using either I2C at 400 kHz or SPI at 8
MHz. SPI operates in four-wire mode.
PIN NUMBER
PIN NAME
VDDIO
PIN DESCRIPTION
Digital I/O supply voltage.
1
4
2
3
SA0 / SDO
SCL / SPC
SDA / SDI
I2C Slave Address LSB (SA0); SPI serial data output (SDO)
I2C serial clock (SCL); SPI serial clock (SPC)
I2C serial data (SDA); SPI serial data input (SDI)
Table 14. Serial Interface
Note: To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration bit.
Setting this bit should be performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write” in section
3.3.2.
For further information regarding the I2C_IF_DIS bit, please refer to sections 8 and 9 of this document.
I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are
open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or a
slave. The master device puts the slave address on the bus, and the slave device with the matching address
acknowledges the master.
The IAM-20680HT always operates as a slave device when communicating to the system processor, which acts as
the master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the IAM-20680HT is b110100X which is 7 bits long. The LSB bit of the 7-bit address is
determined by the logic level on pin SA0. This allows two IAM-20680HTs to be connected to the same I2C bus.
When used in this configuration, the address of one of the devices should be b1101000 (pin SA0 is logic low) and
the address of the other should be b1101001 (pin SA0 is logic high).
IC COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as
a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered busy until
the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line
while SCL is HIGH (see Figure 8).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
P
START condition
STOP condition
Figure 8. START and STOP Conditions
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IAM-20680HT
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data
transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge
signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA
and holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it
can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is
ready, and releases the clock line (refer to Figure 9).
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM
MASTER
1
2
8
9
clock pulse for
acknowledgement
START
condition
Figure 9. Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by
an 8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to
the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave
device. Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the
SDA line LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the
master with a STOP condition (P), thus freeing the communications line. However, the master can generate a
repeated START condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to
HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place
when SCL is low, with the exception of start and stop conditions.
SDA
SCL
1 – 7
8
9
1 – 7
8
9
1 – 7
8
9
S
P
START
STOP
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
condition
condition
Figure 10. Complete I2C Data Transfer
To write the internal IAM-20680HT registers, the master transmits the start condition (S), followed by the I2C
address and the write bit (0). At the 9th clock cycle (when the clock is high), the IAM-20680HT acknowledges the
transfer. Then the master puts the register address (RA) on the bus. After the IAM-20680HT acknowledges the
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IAM-20680HT
reception of the register address, the master puts the register data onto the bus. This is followed by the ACK signal,
and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the
master can continue outputting data rather than transmitting a stop signal. In this case, the IAM-20680HT
automatically increments the register address and loads the data to the appropriate register. The following figures
show single and two-byte write sequences.
Single-Byte Write Sequence
Master
Slave
S
AD+W
RA
DATA
P
ACK
ACK
ACK
Burst Write Sequence
Master
Slave
S
AD+W
RA
DATA
DATA
P
ACK
ACK
ACK
ACK
To read the internal IAM-20680HT registers, the master sends a start condition, followed by the I2C address and a
write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the IAM-
20680HT, the master transmits a start signal followed by the slave address and read bit. As a result, the IAM-
20680HT sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a
stop bit from master. The NACK condition is defined such that the SDA line remains high at the 9th clock cycle. The
following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
RA
RA
S
AD+R
AD+R
NACK
P
ACK
ACK
ACK
ACK
ACK
DATA
Burst Read Sequence
Master
Slave
S
AD+W
S
ACK
NACK
P
ACK
DATA
DATA
I2C TERMS
SIGNAL
DESCRIPTION
S
AD
W
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
Write bit (0)
R
Read bit (1)
ACK
NACK
RA
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
IAM-20680HT internal register address
DATA
P
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 15. I2C Terms
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IAM-20680HT
SPI INTERFACE
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The IAM-20680HT always
operates as a Slave device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SPC), the Serial Data Output (SDO) and the Serial Data Input
(SDI) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the
master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active
at a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices
are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interfere
with any active devices.
SPI Operational Features
1. Data are delivered MSB first and LSB last
2. Data are latched on the rising edge of SPC
3. Data should be transitioned on the falling edge of SPC
4. The maximum frequency of SPC is 8 MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first
byte contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first
byte contains the Read/Write bit and indicates the Read (1) or Write (0) operation. The following 7 bits
contain the Register Address. In cases of multiple-byte Read/Writes, data are two or more bytes:
SPI Address format
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
SPI Data format
MSB
D7
LSB
D6 D5 D4 D3 D2 D1 D0
6. Supports Single or Burst Read/Writes.
SPC
SDI
SPI Master
SPI Slave 1
SDO
CS
CS1
CS2
SPC
SDI
SDO
CS
SPI Slave 2
Figure 11. Typical SPI Master/Slave Configuration
Document Number: DS-000481
Revision: 1.1
Page 29 of 55
IAM-20680HT
7 SERIAL INTERFACE CONSIDERATIONS
IAM-20680HT SUPPORTED INTERFACES
The IAM-20680HT supports I2C communications on its serial interface.
The IAM-20680HT’s I/O logic levels are set to be VDDIO.
Figure 12 depicts a sample circuit of IAM-20680HT. It shows the relevant logic levels and voltage connections.
Figure 12. I/O Levels and Connections
Document Number: DS-000481
Revision: 1.1
Page 30 of 55
IAM-20680HT
8 REGISTER MAP
The following table lists the register map for the IAM-20680HT.
Accessible
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
(writable)
in Sleep
Mode
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00
01
02
0D
0E
0F
13
14
15
16
17
18
19
1A
1B
1C
00
01
02
13
14
15
19
20
21
22
23
24
25
26
27
28
SELF_TEST_X_GYRO
SELF_TEST_Y_GYRO
SELF_TEST_Z_GYRO
SELF_TEST_X_ACCEL
SELF_TEST_Y_ACCEL
SELF_TEST_Z_ACCEL
XG_OFFS_USRH
XG_OFFS_USRL
YG_OFFS_USRH
YG_OFFS_USRL
ZG_OFFS_USRH
ZG_OFFS_USRL
SMPLRT_DIV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
XG_ST_DATA[7:0]
YG_ST_DATA[7:0]
ZG_ST_DATA[7:0]
XA_ST_DATA[7:0]
YA_ST_DATA[7:0]
ZA_ST_DATA[7:0]
X_OFFS_USR [15:8]
X_OFFS_USR [7:0]
Y_OFFS_USR [15:8]
Y_OFFS_USR [7:0]
Z_OFFS_USR [15:8]
Z_OFFS_USR [7:0]
SMPLRT_DIV[7:0]
CONFIG
-
FIFO_MODE
YG_ST
EXT_SYNC_SET[2:0]
DLPF_CFG[2:0]
GYRO_CONFIG
XG_ST
XA_ST
ZG_ST
ZA_ST
FS_SEL [1:0]
-
FCHOICE_B[1:0]
ACCEL_CONFIG
YA_ST
ACCEL_FS_SEL[1:0]
-
ACCEL_FCHOI
CE_B
1D
1E
1F
29
30
31
ACCEL_CONFIG 2
LP_MODE_CFG
R/W
R/W
R/W
N
FIFO_SIZE[1:0]
DEC2_CFG[1:0]
A_DLPF_CFG[2:0]
GYRO_CYCL
E
N
N
G_AVGCFG[2:0]
ACCEL_WOM_ODR_CTRL [3:0]
ACCEL_WOM_THR
WOM_THR[7:0]
TEMP_FIFO
_EN
ACCEL_FIFO_
EN
23
36
35
54
FIFO_EN
R/W
R/C
N
N
XG_FIFO_EN
-
YG_FIFO_EN
-
ZG_FIFO_EN
-
-
-
-
-
-
-
FSYNC_INT
FSYNC_INT
-
FSYNC
_INT_MODE_
EN
LATCH
_INT_EN
INT_RD
_CLEAR
FSYNC_INT_L
EVEL
37
38
3A
55
56
58
INT_PIN_CFG
INT_ENABLE
INT_STATUS
R/W
R/W
R/C
Y
Y
INT_LEVEL
INT_OPEN
-
-
-
INT2_EN
FIFO
_OFLOW
_EN
GDRIVE_INT_
EN
DATA_RDY_I
NT_EN
WOM_INT_EN[2:0]
WOM_INT[2:0]
-
-
FIFO
_OFLOW
_INT
DATA
_RDY_INT
N
GDRIVE_INT
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
59
60
61
62
63
64
65
66
67
68
69
70
71
72
ACCEL_XOUT_H
ACCEL_XOUT_L
ACCEL_YOUT_H
ACCEL_YOUT_L
ACCEL_ZOUT_H
ACCEL_ZOUT_L
TEMP_OUT_H
TEMP_OUT_L
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
ACCEL_XOUT_H[15:8]
ACCEL_XOUT_L[7:0]
ACCEL_YOUT_H[15:8]
ACCEL_YOUT_L[7:0]
ACCEL_ZOUT_H[15:8]
ACCEL_ZOUT_L[7:0]
TEMP_OUT[15:8]
TEMP_OUT[7:0]
GYRO_XOUT_H
GYRO_XOUT_L
GYRO_YOUT_H
GYRO_YOUT_L
GYRO_ZOUT_H
GYRO_ZOUT_L
GYRO_XOUT[15:8]
GYRO_XOUT[7:0]
GYRO_YOUT[15:8]
GYRO_YOUT[7:0]
GYRO_ZOUT[15:8]
GYRO_ZOUT[7:0]
ACCEL
_RST
TEMP
_RST
68
104
SIGNAL_PATH_RESET
R/W
N
-
-
-
-
-
-
Document Number: DS-000481
Revision: 1.1
Page 31 of 55
IAM-20680HT
Accessible
(writable)
in Sleep
Mode
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ACCEL_INTE
L_EN
ACCEL_INTEL
_MODE
69
6A
6B
105
106
107
ACCEL_INTEL_CTRL
USER_CTRL
R/W
R/W
R/W
N
N
Y
-
I2C_IF
_DIS
FIFO
_RST
SIG_COND
_RST
-
FIFO_EN
SLEEP
-
-
-
DEVICE_RES
ET
GYRO_
STANDBY
PWR_MGMT_1
ACCEL_CYCLE
STBY_XA
TEMP_DIS
STBY_ZA
CLKSEL[2:0]
STBY_YG
6C
72
73
74
75
77
78
7A
7B
7D
7E
108
114
115
116
117
119
120
122
123
125
126
PWR_MGMT_2
FIFO_COUNTH
FIFO_COUNTL
FIFO_R_W
R/W
R
Y
FIFO_LP_EN
-
-
STBY_YA
STBY_XG
STBY_ZG
N
N
N
N
N
N
N
N
N
N
FIFO_COUNT[12:8]
R
FIFO_COUNT[7:0]
R/W
R
FIFO_DATA[7:0]
WHOAMI[7:0]
XA_OFFS [14:7]
WHO_AM_I
XA_OFFSET_H
XA_OFFSET_L
YA_OFFSET_H
YA_OFFSET_L
ZA_OFFSET_H
ZA_OFFSET_L
R/W
R/W
R/W
R/W
R/W
R/W
XA_OFFS [6:0]
YA_OFFS [14:7]
YA_OFFS [6:0]
ZA_OFFS [14:7]
ZA_OFFS [6:0]
-
-
-
Table 16. Register Map
Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register value.
In the detailed register tables that follow, register names are in capital letters, while register values are in capital
letters and italicized. For example, the ACCEL_XOUT_H register (Register 59) contains the 8 most significant bits,
ACCEL_XOUT[15:8], of the 16-bit X-Axis accelerometer measurement, ACCEL_XOUT.
The reset value is 0x00 for all registers other than the registers below:
•
•
•
•
Self-test registers 0, 1, 2, 13, 14, 15 contain pre-programmed values
Register 107, PWR_MGMT_1 = 0x01
Register 117, WHO_AM_I: (default value is reported in section 9.31)
Registers 119, 120, 122, 123, 125, 126 contain pre-programmed offset cancellation values
Document Number: DS-000481
Revision: 1.1
Page 32 of 55
IAM-20680HT
9 REGISTER DESCRIPTIONS
This section describes the function and contents of each register within the IAM-20680HT.
Note: The device will come up in 6-Axis Low-Noise Mode upon power-up.
REGISTERS 0 TO 2 – GYROSCOPE SELF-TEST REGISTERS
Register Name: SELF_TEST_X_GYRO, SELF_TEST_Y_GYRO, SELF_TEST_Z_GYRO
Type: READ/WRITE
Register Address: 00, 01, 02 (Decimal); 00, 01, 02 (Hex)
REGISTER
BIT
NAME
FUNCTION
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be used
to check against subsequent self-test outputs performed by
the end user.
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be used
to check against subsequent self-test outputs performed by
the end user.
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be used
to check against subsequent self-test outputs performed by
the end user.
SELF_TEST_X_GYRO
[7:0] XG_ST_DATA[7:0]
[7:0] YG_ST_DATA[7:0]
[7:0] ZG_ST_DATA[7:0]
SELF_TEST_Y_GYRO
SELF_TEST_Z_GYRO
The equation to convert self-test codes in OTP to factory self-test measurement is:
ST _OTP = (2620/ 2FS )*1.01(ST _code−1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on
the Self-Test value (ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following
equation:
log(ST _ FAC /(2620/ 2FS ))
ST _ code = round(
) +1
log(1.01)
REGISTERS 13 TO 15 – ACCELEROMETER SELF-TEST REGISTERS
Register Name: SELF_TEST_X_ACCEL, SELF_TEST_Y_ACCEL, SELF_TEST_Z_ACCEL
Type: READ/WRITE
Register Address: 13, 14, 15 (Decimal); 0D, 0E, 0F (Hex)
REGISTER
BITS
NAME
FUNCTION
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be
used to check against subsequent self-test outputs
performed by the end user.
SELF_TEST_X_ACCEL
[7:0]
XA_ST_DATA[7:0]
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be
used to check against subsequent self-test outputs
performed by the end user.
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be
used to check against subsequent self-test outputs
performed by the end user.
SELF_TEST_Y_ACCEL
SELF_TEST_Z_ACCEL
[7:0]
[7:0]
YA_ST_DATA[7:0]
ZA_ST_DATA[7:0]
The equation to convert self-test codes in OTP to factory self-test measurement is:
Document Number: DS-000481
Revision: 1.1
Page 33 of 55
IAM-20680HT
ST _OTP = (2620/ 2FS )*1.01(ST _code−1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on
the Self-Test value (ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following
equation:
log(ST _ FAC /(2620/ 2FS ))
ST _ code = round(
) +1
log(1.01)
REGISTER 19 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 19 (Decimal); 13 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of X gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
[7:0]
X_OFFS_USR[15:8]
REGISTER 20 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 20 (Decimal); 14 (Hex)
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of X gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
[7:0]
X_OFFS_USR[7:0]
REGISTER 21 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 21 (Decimal); 15 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of Y gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
[7:0]
Y_OFFS_USR[15:8]
REGISTER 22 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 22 (Decimal); 16 (Hex)
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of Y gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
[7:0]
Y_OFFS_USR[7:0]
Document Number: DS-000481
Revision: 1.1
Page 34 of 55
IAM-20680HT
REGISTER 23 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 23 (Decimal); 17 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of Z gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
[7:0]
Z_OFFS_USR[15:8]
REGISTER 24 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 24 (Decimal); 18 (Hex)
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of Z gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
[7:0]
Z_OFFS_USR[7:0]
REGISTER 25 – SAMPLE RATE DIVIDER
Register Name: SMPLRT_DIV
Register Type: READ/WRITE
Register Address: 25 (Decimal); 19 (Hex)
BIT
NAME
FUNCTION
[7:0] SMPLRT_DIV[7:0]
Divides the internal sample rate (see register CONFIG) to generate the sample rate that
controls sensor data output rate, FIFO sample rate.
Note: This register is only effective when FCHOICE_B register bits are 2’b00, and (0 < DLPF_CFG < 7).
This is the update rate of the sensor register:
SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV)
Where INTERNAL_SAMPLE_RATE = 1 kHz
REGISTER 26 – CONFIGURATION
Register Name: CONFIG
Register Type: READ/WRITE
Register Address: 26 (Decimal); 1A (Hex)
BIT
[7]
NAME
FUNCTION
-
Always set to 0
[6]
FIFO_MODE
When set to ‘1’, when the FIFO is full, additional writes will not be written to FIFO.
When set to ‘0’, when the FIFO is full, additional writes will be written to the FIFO, replacing
the oldest data.
[5:3]
EXT_SYNC_SET[2:0]
Enables the FSYNC pin data to be sampled.
EXT_SYNC_SET
FSYNC bit location
function disabled
0
1
2
3
4
5
6
7
TEMP_OUT_L[0]
GYRO_XOUT_L[0]
GYRO_YOUT_L[0]
GYRO_ZOUT_L[0]
ACCEL_XOUT_L[0]
ACCEL_YOUT_L[0]
ACCEL_ZOUT_L[0]
FSYNC will be latched to capture short strobes. This will be done such that if FSYNC toggles,
the latched value toggles, but won’t toggle again until the new latched value is captured by
the sample rate strobe.
Document Number: DS-000481
Revision: 1.1
Page 35 of 55
IAM-20680HT
[2:0]
DLPF_CFG[2:0]
For the DLPF to be used, FCHOICE_B[1:0] is 2’b00.
See Table 17.
The DLPF is configured by DLPF_CFG, when FCHOICE_B [1:0] = 2b’00. The gyroscope and temperature sensor are
filtered according to the value of DLPF_CFG and FCHOICE_B as shown in Table 17.
Temperature
FCHOICE_B
Gyroscope
Sensor
DLPF_CFG
3-dB BW
(Hz)
Noise BW
(Hz)
Rate
(kHz)
<1>
<0>
3-dB BW (Hz)
X
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
X
X
0
1
2
3
4
5
6
7
8173
3281
250
176
92
8595.1
32
4000
4000
4000
188
98
3451.0
306.6
177.0
108.6
59.0
32
8
1
1
1
41
20
42
20
30.5
1
10
15.6
10
1
5
8.0
5
1
8
3281
3451.0
4000
Table 17. Gyroscope and Temperature Sensor Data Rates and Bandwidths (Low-Noise Mode)
REGISTER 27 – GYROSCOPE CONFIGURATION
Register Name: GYRO_CONFIG
Register Type: READ/WRITE
Register Address: 27 (Decimal); 1B (Hex)
BIT
[7]
[6]
[5]
NAME
FUNCTION
XG_ST
YG_ST
ZG_ST
X Gyro self-test
Y Gyro self-test
Z Gyro self-test
Gyro Full Scale Select:
00 = ±250 dps
01= ±500 dps
[4:3]
FS_SEL[1:0]
10 = ±1000 dps
11 = ±2000 dps
Reserved
[2]
-
[1:0]
FCHOICE_B[1:0]
Used to bypass DLPF as shown in Table 17 above.
REGISTER 28 – ACCELEROMETER CONFIGURATION
Register Name: ACCEL_CONFIG
Register Type: READ/WRITE
Register Address: 28 (Decimal); 1C (Hex)
BIT
[7]
[6]
[5]
NAME
FUNCTION
XA_ST
YA_ST
ZA_ST
X Accel self-test
Y Accel self-test
Z Accel self-test
Accel Full Scale Select:
±2g (00), ±4g (01), ±8g (10), ±16g (11)
Reserved
[4:3]
[2:0]
ACCEL_FS_SEL[1:0]
-
Document Number: DS-000481
Revision: 1.1
Page 36 of 55
IAM-20680HT
REGISTER 29 – ACCELEROMETER CONFIGURATION 2
Register Name: ACCEL_CONFIG2
Register Type: READ/WRITE
Register Address: 29 (Decimal); 1D (Hex)
BIT
NAME
FUNCTION
Specifies FIFO size according to the following:
0 = 512 Byte
1 = 1 kByte
2 = 2 kByte
3 = 4 kByte
[7:6]
FIFO_SIZE[1:0]
Averaging filter settings for WoM Accelerometer Mode:
0 = Average 4 samples
1 = Average 8 samples
[5:4]
DEC2_CFG[1:0]
2 = Average 16 samples
3 = Average 32 samples
[3]
[2:0]
ACCEL_FCHOICE_B
A_DLPF_CFG
Used to bypass DLPF as shown in the table below.
Accelerometer low pass filter setting as shown in the table below.
Accelerometer
ACCEL_FCHOICE_B
A_DLPF_CFG
3-dB BW
(Hz)
Noise BW
(Hz)
Rate
(kHz)
1
0
0
0
0
0
0
0
0
X
0
1
2
3
4
5
6
7
1046.0
218.1
218.1
99.0
1100.0
235.0
235.0
121.3
61.5
4
1
1
1
1
1
1
1
1
44.8
21.2
31.0
10.2
15.5
5.1
7.8
420.0
441.6
Table 18. Accelerometer Data Rates and Bandwidths (Low-Noise Mode)
The data output rate of the DLPF filter block can be further reduced by a factor of 1/(1+SMPLRT_DIV), where
SMPLRT_DIV is an 8-bit integer. Following is a small subset of ODRs that are configurable for the accelerometer in
the Low-Noise mode in this manner (Hz): 3.91, 7.81, 15.63, 31.25, 62.50, 125, 250, 500, 1K.
The Table 19 lists the accelerometer filter bandwidths and noise available in the WoM mode of operation. In the
WoM mode of operation, the accelerometer is duty-cycled.
To operate in accelerometer WoM mode, gyroscope must be off and ACCEL_CYCLE must be set to ‘1’ in
PWR_MGMT_1 (address 0x6B).
Document Number: DS-000481
Revision: 1.1
Page 37 of 55
IAM-20680HT
ACCEL_FCHOICE_B
A_DLPF_CFG
DEC2_CFG
1
x
0
7
0
7
0
7
0
7
x
0
1
2
3
Averages
1x
1.084
1100.0
4x
1.84
441.6
8x
2.84
235.4
16x
4.84
121.3
32x
8.84
61.5
Ton (ms)
Noise BW (Hz)
Noise (mg rms) TYP 1
Based on 250 µg/√Hz
8.3
5.3
3.8
2.8
2.0
ACCEL_WOM_ODR_CTRL
ODR (Hz)
3.9
Current Consumption (µA) TYP 1
4
5
8.4
9.8
9.4
11.9
17.0
27.1
47.2
87.5
168.1
329.3
10.8
14.7
13.6
20.3
19.2
31.4
7.8
6
15.6
12.8
18.7
30.4
57.4
100.9
194.9
22.5
33.7
55.9
7
31.3
38.2
60.4
104.9
202.8
N/A
8
62.5
69.4
113.9
220.9
9
10
11
125.0
250.0
500.0
132.0
257.0
N/A
N/A
Table 19. Example Configurations for Accelerometer WoM Mode
Notes:
1. Not tested in production, not guaranteed
REGISTER 30 – LOW POWER MODE CONFIGURATION
Register Name: LP_MODE_CFG
Register Type: READ/WRITE
Register Address: 30 (Decimal); 1E (Hex)
BIT
NAME
GYRO_CYCLE 1
FUNCTION
When set to ‘1’ gyroscope or 6-axis are duty-cycled. Default setting is
‘0’
[7]
Gyroscope averaging filter settings when GYRO_CYCLE is set to ‘1’.
Default setting is ‘000’
[6:4]
G_AVGCFG[2:0]
Accelerometer WoM Mode ODR configuration.
ACCEL_WOM_ODR_CTRL is effective only when GYRO is off
and ACCEL_CYCLE is set to ‘1’:
0 to 3 = RESERVED
4 = 3.9 Hz
5 = 7.8 Hz
6 = 15.6 Hz
[3:0]
ACCEL_WOM_ODR_CTRL[3:0]
7 = 31.3 Hz
8 = 62.5 Hz
9 = 125 Hz
10 = 250 Hz
11 = 500 Hz
12 to 15 = RESERVED
Notes:
1. Not tested in production, not guaranteed
To reduce gyroscope or 6-axis power consumption, GYRO_CYCLE should be set to ‘1'. When GYRO_CYCLE is set to
'1' gyroscope is duty-cycled and performance are reduced compared to Low-Noise mode. When GYRO_CYCLE is set
to '1' gyroscope filter configuration is determined by G_AVGCFG[2:0] that sets the averaging filter configuration,
gyroscope filter is not dependent on DLPF_CFG[2:0]. Table 20 shows some example configurations when
GYRO_CYCLE is set to '1'.
Document Number: DS-000481
Revision: 1.1
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FCHOICE_B
G_AVGCFG
Averages
Ton (ms)
0
0
0
1
0
2
0
3
0
0
5
0
6
0
7
4
1x
2x
4x
8x
16x
9.23
60.2
32x
17.23
30.6
64x
33.23
15.6
128x
65.23
8.0
1.73
650.8
2.23
407.1
3.23
224.2
5.23
117.4
Noise BW (Hz)
Noise (dps rms) TYP 1
Based on 0.008 dps/√Hz
0.20
0.16
0.12
0.09
0.06
0.04
0.03
0.02
SMPLRT_DIV
ODR (Hz)
Current Consumption (mA) TYP 1
255
99
64
32
19
9
3.9
10.0
1.3
1.3
1.4
1.4
1.5
1.6
1.7
1.9
2.1
2.3
2.9
1.3
1.3
1.4
1.4
1.5
1.7
1.8
2.1
2.3
2.6
1.3
1.4
1.4
1.5
1.6
1.9
2.0
2.5
2.7
1.3
1.4
1.5
1.6
1.8
2.2
2.5
1.4
1.5
1.6
1.8
2.1
3.0
1.4
1.6
1.8
2.2
2.8
1.5
1.9
2.2
1.8
2.5
15.4
N/A
30.3
N/A
50.0
100.0
125.0
200.0
250.0
333.3
500.0
N/A
7
4
N/A
N/A
3
2
N/A
1
N/A
Table 20. Example Configurations for Gyroscope when GYRO_CYCLE = 1
Notes:
1. Not tested in production, not guaranteed
REGISTER 31 – WAKE-ON MOTION THRESHOLD (ACCELEROMETER)
Register Name: ACCEL_WOM_THR
Register Type: READ/WRITE
Register Address: 31 (Decimal); 1F (Hex)
BIT
NAME
FUNCTION
This register holds the threshold value for the Wake on Motion Interrupt for accelerometer.
Wake on motion threshold resolution is 4 mg/LSB regardless the selected full scale.
[7:0]
WOM_THR[7:0]
REGISTER 35 – FIFO ENABLE
Register Name: FIFO_EN
Register Type: READ/WRITE
Register Address: 35 (Decimal); 23 (Hex)
BIT
NAME
FUNCTION
1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
0 – Function is disabled.
[7]
TEMP_FIFO_EN
1 – Write GYRO_XOUT_H and GYRO_XOUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
0 – Function is disabled.
1 – Write GYRO_YOUT_H and GYRO_YOUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
[6]
[5]
XG_FIFO_EN
YG_FIFO_EN
0 – Function is disabled.
Note: Enabling any one of the bits corresponding to the Gyros or Temp data paths, data are buffered into
the FIFO even though that data path is not enabled.
Document Number: DS-000481
Revision: 1.1
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IAM-20680HT
BIT
NAME
FUNCTION
1 – Write GYRO_ZOUT_H and GYRO_ZOUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
0 – Function is disabled
[4]
ZG_FIFO_EN
1 – Write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H,
and ACCEL_ZOUT_L to the FIFO at the sample rate;
0 – Function is disabled.
[3]
ACCEL_FIFO_EN
-
[2:0]
Reserved.
REGISTER 54 – FSYNC INTERRUPT STATUS
Register Name: FSYNC_INT
Register Type: READ to CLEAR
Register Address: 54 (Decimal); 36 (Hex)
BIT
NAME
FUNCTION
This bit automatically sets to 1 when a FSYNC interrupt has been generated. The bit
clears to 0 after the register has been read.
[7]
FSYNC_INT
REGISTER 55 – INT/INT2 PIN / BYPASS ENABLE CONFIGURATION
Register Name: INT_PIN_CFG
Register Type: READ/WRITE
Register Address: 55 (Decimal); 37 (Hex)
BIT
NAME
FUNCTION
1 – The logic level for INT/INT2 pin is active low.
0 – The logic level for INT/INT2 pin is active high.
1 – INT/INT2 pin is configured as open drain.
0 – INT/INT2 pin is configured as push-pull.
1 – INT/INT2 pin level held until interrupt status is cleared.
0 – INT/INT2 pin indicates interrupt pulse’s width is 50 µs.
1 – Interrupt status is cleared if any read operation is performed.
0 – Interrupt status is cleared only by reading INT_STATUS register
1 – The logic level for the FSYNC pin as an interrupt is active low.
0 – The logic level for the FSYNC pin as an interrupt is active high.
When this bit is equal to 1, the FSYNC pin will trigger an interrupt when it transitions to
the level specified by FSYNC_INT_LEVEL. When this bit is equal to 0, the FSYNC pin is
disabled from causing an interrupt.
[7]
INT_LEVEL
INT_OPEN
[6]
[5]
[4]
[3]
LATCH_INT_EN
INT_RD_CLEAR
FSYNC_INT_LEVEL
[2]
[1]
[0]
FSYNC_INT_MODE_EN
-
Reserved.
When INT2_EN = 0, all of the interrupts appear on the INT pin, and INT2 interrupt pin is
unused. When INT2_EN = 1, all interrupts except for data ready appear on the INT2 pin,
and data ready interrupt appears on the INT interrupt pin.
-INT2_EN
Document Number: DS-000481
Revision: 1.1
Page 40 of 55
IAM-20680HT
REGISTER 56 – INTERRUPT ENABLE
Register Name: INT_ENABLE
Register Type: READ/WRITE
Register Address: 56 (Decimal); 38 (Hex)
BIT
NAME
FUNCTION
111 – Enable WoM interrupt on accelerometer.
000 – Disable WoM interrupt on accelerometer.
[7:5]
WOM_INT_EN[2:0]
1 – Enables a FIFO buffer overflow to generate an interrupt.
0 – Function is disabled.
[4]
FIFO_OFLOW_EN
[3]
[2]
[1]
[0]
-
Reserved.
GDRIVE_INT_EN
-
DATA_RDY_INT_EN
Gyroscope Drive System Ready interrupt enable.
Reserved.
Data ready interrupt enable.
Data ready interrupt is always generated on INT pin. All the other interrupts signals are generated on INT pin if
INT2_EN bit is set to 0 or on INT2 pin if INT2_EN bit is set to 1.
REGISTER 58 – INTERRUPT STATUS
Register Name: INT_STATUS
Register Type: READ to CLEAR
Register Address: 58 (Decimal); 3A (Hex)
BIT
NAME
FUNCTION
Accelerometer WoM interrupt status. Cleared on Read.
111 – WoM interrupt on accelerometer
[7:5]
WOM_INT[2:0]
This bit automatically sets to 1 when a FIFO buffer overflow has been generated. The bit
clears to 0 after the register has been read.
[4]
FIFO_OFLOW_INT
[3]
[2]
[1]
-
Reserved.
GDRIVE_INT
-
Gyroscope Drive System Ready interrupt
Reserved.
This bit automatically sets to 1 when a Data Ready interrupt is generated. The bit clears
to 0 after the register has been read.
[0]
DATA_RDY_INT
REGISTERS 59 TO 64 – ACCELEROMETER MEASUREMENTS
Register Name: ACCEL_XOUT_H
Register Type: READ only
Register Address: 59 (Decimal); 3B (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_XOUT_H[15:8]
High byte of accelerometer x-axis data.
Register Name: ACCEL_XOUT_L
Register Type: READ only
Register Address: 60 (Decimal); 3C (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_XOUT_L[7:0]
Low byte of accelerometer x-axis data.
Register Name: ACCEL_YOUT_H
Register Type: READ only
Register Address: 61 (Decimal); 3D (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_YOUT_H[15:8]
High byte of accelerometer y-axis data.
Document Number: DS-000481
Revision: 1.1
Page 41 of 55
IAM-20680HT
Register Name: ACCEL_YOUT_L
Register Type: READ only
Register Address: 62 (Decimal); 3E (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_YOUT_L[7:0]
Low byte of accelerometer y-axis data.
Register Name: ACCEL_ZOUT_H
Register Type: READ only
Register Address: 63 (Decimal); 3F (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_ZOUT_H[15:8]
High byte of accelerometer z-axis data.
Register Name: ACCEL_ZOUT_L
Register Type: READ only
Register Address: 64 (Decimal); 40 (Hex)
BIT
[7:0]
NAME
ACCEL_ZOUT_L[7:0]
FUNCTION
Low byte of accelerometer z-axis data.
REGISTERS 65 AND 66 – TEMPERATURE MEASUREMENT
Register Name: TEMP_OUT_H
Register Type: READ only
Register Address: 65 (Decimal); 41 (Hex)
BIT
NAME
FUNCTION
[7:0]
TEMP_OUT[15:8]
High byte of the temperature sensor output.
Register Name: TEMP_OUT_L
Register Type: READ only
Register Address: 66 (Decimal); 42 (Hex)
BIT
NAME
FUNCTION
Low byte of the temperature sensor output
[7:0]
TEMP_OUT[7:0]
TEMP_degC
= ((TEMP_OUT –
RoomTemp_Offset)/Temp_Sensitivity) + 25degC
REGISTERS 67 TO 72 – GYROSCOPE MEASUREMENTS
Register Name: GYRO_XOUT_H
Register Type: READ only
Register Address: 67 (Decimal); 43 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_XOUT[15:8]
High byte of the X-Axis gyroscope output.
Register Name: GYRO_XOUT_L
Register Type: READ only
Register Address: 68 (Decimal); 44 (Hex)
BIT
NAME
FUNCTION
Low byte of the X-Axis gyroscope output.
GYRO_XOUT = Gyro_Sensitivity * X_angular_rate
[7:0]
GYRO_XOUT[7:0]
Nominal
FS_SEL = 0
Conditions
Gyro_Sensitivity = 131 LSB/(dps)
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Revision: 1.1
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IAM-20680HT
Register Name: GYRO_YOUT_H
Register Type: READ only
Register Address: 69 (Decimal); 45 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_YOUT[15:8]
High byte of the Y-Axis gyroscope output.
Register Name: GYRO_YOUT_L
Register Type: READ only
Register Address: 70 (Decimal); 46 (Hex)
BIT
NAME
FUNCTION
Low byte of the Y-Axis gyroscope output.
GYRO_YOUT = Gyro_Sensitivity * Y_angular_rate
[7:0]
GYRO_YOUT[7:0]
Nominal
FS_SEL = 0
Conditions
Gyro_Sensitivity = 131 LSB/(dps)
Register Name: GYRO_ZOUT_H
Register Type: READ only
Register Address: 71 (Decimal); 47 (Hex)
BIT
[7:0]
NAME
GYRO_ZOUT[15:8]
FUNCTION
High byte of the Z-Axis gyroscope output.
Register Name: GYRO_ZOUT_L
Register Type: READ only
Register Address: 72 (Decimal); 48 (Hex)
BIT
NAME
FUNCTION
Low byte of the Z-Axis gyroscope output.
GYRO_ZOUT =
Gyro_Sensitivity * Z_angular_rate
FS_SEL = 0
Gyro_Sensitivity = 131 LSB/(dps)
[7:0]
GYRO_ZOUT[7:0]
Nominal
Conditions
Document Number: DS-000481
Revision: 1.1
Page 43 of 55
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REGISTER 104 – SIGNAL PATH RESET
Register Name: SIGNAL_PATH_RESET
Register Type: READ/WRITE
Register Address: 104 (Decimal); 68 (Hex)
BIT
NAME
FUNCTION
[7:2]
Reserved.
-
Reset accel digital signal path.
[1]
[0]
ACCEL_RST
Note: Sensor registers are not cleared. Use SIG_COND_RST to clear sensor registers.
Reset temp digital signal path.
TEMP_RST
Note: Sensor registers are not cleared. Use SIG_COND_RST to clear sensor registers.
REGISTER 105 – ACCELEROMETER INTELLIGENCE CONTROL
Register Name: ACCEL_INTEL_CTRL
Register Type: READ/WRITE
Register Address: 105 (Decimal); 69 (Hex)
BIT
[7]
NAME
ACCEL_INTEL_EN
FUNCTION
This bit enables the Wake-on-Motion detection logic.
0 – Compares the current sample to the first sample taken when entering in
WoM mode.
[6]
ACCEL_INTEL_MODE
1 – Compare the current sample with the previous sample.
[5:1]
[0]
Reserved.
-
-
Reserved, must be set to 0 when WoM is activated. Please refer to section 5.1
REGISTER 106 – USER CONTROL
Register Name: USER_CTRL
Register Type: READ/WRITE
Register Address: 106 (Decimal); 6A (Hex)
BIT
[7]
NAME
FUNCTION
Reserved.
1 – Enable FIFO operation mode.
-
[6]
FIFO_EN
0 – Disable FIFO access from serial interface. To disable FIFO writes by DMA, use FIFO_EN
register.
[5]
[4]
-
Reserved.
I2C_IF_DIS
1 – Disable I2C Slave module and put the serial interface in SPI mode only.
[3]
Reserved.
-
1 – Reset FIFO module. Reset is asynchronous. This bit auto clears after one clock cycle of the
internal 20 MHz clock.
Reserved.
1 – Reset all gyro digital signal path, accel digital signal path, and temp digital signal path.
This bit also clears all the sensor registers.
[2]
[1]
[0]
FIFO_RST
-
SIG_COND_RST
Document Number: DS-000481
Revision: 1.1
Page 44 of 55
IAM-20680HT
REGISTER 107 – POWER MANAGEMENT 1
Register Name: PWR_MGMT_1
Register Type: READ/WRITE
Register Address: 107 (Decimal); 6B (Hex)
BIT
NAME
FUNCTION
1 – Reset the internal registers and restores the default settings. The bit automatically clears
to 0 once the reset is done.
[7]
DEVICE_RESET
[6]
[5]
SLEEP
When set to 1, the chip is set to sleep mode. Default setting is 0.
When set to 1, and SLEEP and STANDBY are not set to 1, the chip will cycle between sleep
and taking a single accelerometer sample.
Note: When all accelerometer axes are disabled via PWR_MGMT_2 register bits and cycle is enabled, the
chip will wake up at the rate determined by the respective registers above, but will not take any
samples.
ACCEL_CYCLE
When set, the gyro drive and PLL circuitry are enabled, but the sense paths are disabled. This
is a power mode that allows quick enabling of the gyros.
When set to 1, this bit disables the temperature sensor.
Code Clock Source
[4]
[3]
GYRO_STANDBY
TEMP_DIS
0
1
2
3
4
5
6
7
Internal 20 MHz oscillator.
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
Internal 20 MHz oscillator.
[2:0]
CLKSEL[2:0]
Stops the clock and keeps timing generator in reset.
Note: The default value of CLKSEL[2:0] is 001.
REGISTER 108 – POWER MANAGEMENT 2
Register Name: PWR_MGMT_2
Register Type: READ/WRITE
Register Address: 108 (Decimal); 6C (Hex)
BIT
[7]
[6]
NAME
FIFO_LP_EN
FUNCTION
1 – Enable FIFO in Accelerometer WoM mode. Default setting is 0.
Reserved.
-
1 – X accelerometer is disabled.
0 – X accelerometer is on.
1 – Y accelerometer is disabled.
0 – Y accelerometer is on.
1 – Z accelerometer is disabled.
0 – Z accelerometer is on.
1 – X gyro is disabled.
0 – X gyro is on.
1 – Y gyro is disabled.
0 – Y gyro is on.
1 – Z gyro is disabled.
0 – Z gyro is on.
[5]
STBY_XA
[4]
[3]
[2]
[1]
[0]
STBY_YA
STBY_ZA
STBY_XG
STBY_YG
STBY_ZG
Document Number: DS-000481
Revision: 1.1
Page 45 of 55
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REGISTERS 114 AND 115 – FIFO COUNT REGISTERS
Register Name: FIFO_COUNTH
Register Type: READ Only
Register Address: 114 (Decimal); 72 (Hex)
BIT
NAME
FUNCTION
[7:5]
Reserved.
-
High Bits; count indicates the number of written bytes in the FIFO.
Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL.
[4:0]
FIFO_COUNT[12:8]
Register Name: FIFO_COUNTL
Register Type: READ Only
Register Address: 115 (Decimal); 73 (Hex)
BIT
NAME
FUNCTION
Low Bits; count indicates the number of written bytes in the FIFO.
Note: Must read FIFO_COUNTH to latch new data for both FIFO_COUNTH and FIFO_COUNTL.
[7:0]
FIFO_COUNT[7:0]
Document Number: DS-000481
Revision: 1.1
Page 46 of 55
IAM-20680HT
REGISTER 116 – FIFO READ WRITE
Register Name: FIFO_R_W
Register Type: READ/WRITE
Register Address: 116 (Decimal); 74 (Hex)
BIT
[7:0]
NAME
FIFO_DATA[7:0]
FUNCTION
Read/Write command provides Read or Write operation for the FIFO.
Description:
This register is used to read and write data from the FIFO buffer.
Data are written to the FIFO in order of register number (from lowest to highest). If all the FIFO enable flags (see
below) are enabled, the contents of registers 59 through 72 will be written in order at the Sample Rate.
The contents of the sensor data registers (Registers 59 to 72) are written into the FIFO buffer when their
corresponding FIFO enable flags are set to 1 in FIFO_EN (Register 35).
If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is automatically set to 1. This bit is located in
INT_STATUS (Register 58). When the FIFO buffer has overflowed, the oldest data will be lost and new data will be
written to the FIFO unless register 26 CONFIG, bit[6] FIFO_MODE = 1.
If the FIFO buffer is empty, reading register FIFO_DATA will return a unique value of 0xFF until new data are
available. Normal data are precluded from ever indicating 0xFF, so 0xFF gives a trustworthy indication of FIFO
empty.
REGISTER 117 – WHO AM I
Register Name: WHO_AM_I
Register Type: READ only
Register Address: 117 (Decimal); 75 (Hex)
BIT
NAME
FUNCTION
[7:0]
WHOAMI
Register to indicate to user which device is being accessed.
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default
value of the register is 0xFA. This is different from the I2C address of the device as seen on the slave I2C controller
by the applications processor. The I2C address of the IAM-20680HT is 0x68 or 0x69 depending upon the value
driven on AD0 pin.
Document Number: DS-000481
Revision: 1.1
Page 47 of 55
IAM-20680HT
REGISTERS 119, 120, 122, 123, 125, 126 ACCELEROMETER OFFSET REGISTERS
Register Name: XA_OFFSET_H
Register Type: READ/WRITE
Register Address: 119 (Decimal); 77 (Hex)
BIT
NAME
FUNCTION
Bits 14 to 7 of the 15-bit of the X accelerometer offset cancellation (2’s complement).
±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps.
[7:0]
XA_OFFS[14:7]
Register Name: XA_OFFSET_L
Register Type: READ/WRITE
Register Address: 120 (Decimal); 78 (Hex)
BIT
NAME
FUNCTION
Bits 6 to 0 of the 15-bit of the X accelerometer offset cancellation (2’s complement).
±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps.
[7:1]
XA_OFFS[6:0]
[0]
Reserved. This bit is set during factory calibration and the value must be kept unchanged.
-
Register Name: YA_OFFSET_H
Register Type: READ/WRITE
Register Address: 122 (Decimal); 7A (Hex)
BIT
NAME
FUNCTION
Bits 14 to 7 of the 15-bit of the Y accelerometer offset cancellation (2’s complement).
±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps.
[7:0]
YA_OFFS[14:7]
Register Name: YA_OFFSET_L
Register Type: READ/WRITE
Register Address: 123 (Decimal); 7B (Hex)
BIT
NAME
FUNCTION
Bits 6 to 0 of the 15-bit of the Y accelerometer offset cancellation (2’s complement).
±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps.
[7:1]
YA_OFFS[6:0]
[0]
Reserved. This bit is set during factory calibration and the value must be kept unchanged.
-
Register Name: ZA_OFFSET_H
Register Type: READ/WRITE
Register Address: 125 (Decimal); 7D (Hex)
BIT
NAME
FUNCTION
Bits 14 to 7 of the 15-bit of the Z accelerometer offset cancellation (2’s complement).
±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps.
[7:0]
ZA_OFFS[14:7]
Register Name: ZA_OFFSET_L
Register Type: READ/WRITE
Register Address: 126 (Decimal); 7E (Hex)
BIT
NAME
FUNCTION
Bits 6 to 0 of the 15-bit of the Z accelerometer offset cancellation (2’s complement).
±16g Offset cancellation in all Full-Scale modes, 15 bit 0.98-mg steps.
[7:1]
ZA_OFFS[6:0]
[0]
Reserved. This bit is set during factory calibration and the value must be kept unchanged.
-
Document Number: DS-000481
Revision: 1.1
Page 48 of 55
IAM-20680HT
10 ASSEMBLY
This section provides general guidelines for assembling TDK-InvenSense Micro Electro-Mechanical Systems (MEMS)
gyros packaged in LGA package.
ORIENTATION OF AXES
Figure 13 below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1
identifier (•) in the figure.
Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation
Document Number: DS-000481
Revision: 1.1
Page 49 of 55
IAM-20680HT
PACKAGE DIMENSIONS
16 Lead LGA 3x3x0.75 mm3 NiAu pad finish.
Figure 14. Package Dimensions
Document Number: DS-000481
Revision: 1.1
Page 50 of 55
IAM-20680HT
DIMENSIONS IN MILLIMETERS
MIN NOM MAX
0.8
REF
REF
3.1
SYMBOLS
Total Thickness
Substrate Thickness
Mold Thickness
A
A1
A2
0.7
0.75
0.105
0.63
D
E
2.9
2.9
0.2
0.3
3
3
Body Size
3.1
0.3
0.4
Lead Width
Lead Length
W
0.25
L
e
n
0.35
0.5
16
Lead Pitch
Lead Count
BSC
D1
E1
SD
2
1
BSC
BSC
BSC
BSC
Edge Ball Center to Center
Body Center to Contact Ball
---
SE
b
---
---
---
---
---
Ball Width
Ball Diameter
Ball Opening
Ball Pitch
Ball Count
---
---
---
e1
n1
---
---
Pre-Solder
---
Package Edge Tolerance
Mold Flatness
aaa
bbb
ddd
eee
fff
0.1
0.2
0.08
---
---
0.1
Coplanarity
Ball Offset (Package)
Ball Offset (Ball)
Lead Edge to Package Edge
M
0.05
0.15
Table 21. Package Dimensions
Document Number: DS-000481
Revision: 1.1
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IAM-20680HT
11 PART NUMBER PACKAGE MARKING
The part number package marking for IAM-20680HT devices is summarized below:
PART NUMBER
IAM-20680HT
PART NUMBER PACKAGE MARKING
IA268HT
Table 22. Part Number Package Marking
Figure 15. Part Number Package Marking
Samples with Part Number Package Marking “IA268HT E” are engineering samples and may have deviations in
respect to the specifications and functions reported in the datasheet. Engineering samples are not production-
intent parts.
Document Number: DS-000481
Revision: 1.1
Page 52 of 55
IAM-20680HT
12 REFERENCE
Please refer to “InvenSense MEMS Motion Handling and Assembly Guide (AN-IVS-0002A-00)” for the following
information:
•
Manufacturing Recommendations
o
o
o
o
o
o
o
o
o
o
o
Assembly Guidelines and Recommendations
PCB Design Guidelines and Recommendations
MEMS Handling Instructions
ESD Considerations
Reflow Specification
Storage Specifications
Package Marking Specification
Tape & Reel Specification
Reel & Pizza Box Label
Packaging
Representative Shipping Carton Label
•
Compliance
o
o
o
Environmental Compliance
DRC Compliance
Compliance Declaration Disclaimer
Document Number: DS-000481
Revision: 1.1
Page 53 of 55
IAM-20680HT
13 REVISION HISTORY
REVISION DATE
REVISION
DESCRIPTION
10/21/2021
02/15/2022
1.0
1.1
Initial revision
Updated formatting
Added longevity info
Document Number: DS-000481
Revision: 1.1
Page 54 of 55
IAM-20680HT
https://invensense.tdk.com/longevity/
This information furnished by InvenSense or its affiliates (“TDK InvenSense”) is believed to be accurate and reliable. However, no responsibility is
assumed by TDK InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use.
Specifications are subject to change without notice. TDK InvenSense reserves the right to make changes to this product, including its circuits and
software, in order to improve its design and/or performance, without prior notice. TDK InvenSense makes no warranties, neither expressed nor
implied, regarding the information and specifications contained in this document. TDK InvenSense assumes no responsibility for any claims or
damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not
limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or
otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied.
Trademarks that are registered trademarks are the property of their respective companies. TDK InvenSense sensors should not be used or sold
in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life
threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear
instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2021—2022 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps,
DMP, AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and
product names may be trademarks of the respective companies with which they are associated.
©2021—2022 InvenSense. All rights reserved.
Document Number: DS-000481
Revision: 1.1
Page 55 of 55
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