ICG-20330 [TDK]
陀螺仪;
| 型号： | ICG-20330 |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | 陀螺仪 |
| 文件： | 总56页 (文件大小：1028K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICG-20330
High Performance 3-Axis OIS/EIS Optimized MEMS Gyro
GENERAL DESCRIPTION
APPLICATIONS
The ICG-20330 is a 3-axis MotionTracking® device
that includes a 3-axis gyroscope in a small
3x3x 0.75 mm (16-pin LGA) package.
•
OIS (Optical Image Stabilization) in phone
camera modules, DSLR, and DSC
EIS (Electronic Image Stabilization) in
DSC, and phone camera modules
•
•
High performance specs
o
Gyroscope sensitivity error: ±1%
FEATURES
o
Gyroscope noise: 5 mdps/Hz
•
1% Gyro initial sensitivity eliminates OIS
dynamic calibration
•
Includes 512-byte FIFO to reduce traffic on the
serial bus interface, and reduce power
consumption by allowing the system processor
to burst read sensor data and then go into a
low-power mode
•
Optimized OIS/EIS programmable gyro
FSR of ±31.25dps, ±62.5dps, ±125ps and
±250dps
•
•
•
•
High Resolution at up to 1048 LSB/(º/s)
Low 5mdps/√Hz Noise
•
EIS FSYNC support
User-programmable interrupts
Wake-on-motion interrupt for low power
operation of applications processor
512-byte FIFO buffer enables the
applications processor to read the data in
bursts
ICG-20330 includes on-chip 16-bit ADCs,
programmable digital filters, an embedded
temperature sensor, and programmable interrupts.
The device features an operating voltage range
down to 1.71V. Communication ports include I2C
and high-speed SPI at 7 MHz.
•
•
•
On-Chip 16-bit ADCs and Programmable
Filters
Host interface: 7 MHz SPI or 400 kHz Fast
ORDERING INFORMATION
Mode I2C
•
•
•
Digital-output temperature sensor
VDD operating range of 1.71 V to 3.45 V
MEMS structure hermetically sealed and
bonded at wafer level
PART
AXES
TEMP RANGE
PACKAGE
ICG-20330† X,Y,Z -40°C to +85°C
16-Pin LGA
•
RoHS and Green compliant
†Denotes RoHS and Green-Compliant Package
TYPICAL OPERATING CIRCUIT
BLOCK DIAGRAM
1.8 – 3.3VDC
VDD
C2, 0.1 mF
C4, 2.2 mF
REGOUT
16 15 14
ICG-20330
INT
C1, 0.47 mF
Self
test
X Gyro
Y Gyro
Z Gyro
ADC
ADC
ADC
Interrupt
Status
Register
GND
VDDIO
1.8 – 3.3 VDC
C3, 10 nF
13
12
11
10
9
1
2
3
4
5
SCL/SPC
SDA/SDI
NC
NC
CS
SCL
SDA
AD0
Self
test
Slave I2C and
SPI Serial
Interface
SA0 / SDO
SCL / SPC
SDA / SDI
ICG-20330
FIFO
SA0/SDO
CS
NC
NC
VDDIO
Self
test
User & Config
Registers
FSYNC
6
7
8
Temp Sensor
ADC
Sensor
Registers
Charge
Pump
Bias & LDOs
VDD
GND
REGOUT
InvenSense reserves the right to change the
detail specifications as may be required to
permit improvements in the design of its
products.
InvenSense, a TDK Group Company
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 988–7339
Document Number: DS-000127
Revision: 1.1
Release Date: 03/18/2021
invensense.tdk.com
ICG-20330
TABLE OF CONTENTS
General Description ........................................................................................................................................................ 1
Ordering Information...................................................................................................................................................... 1
Block Diagram ................................................................................................................................................................ 1
Applications .................................................................................................................................................................... 1
Features.......................................................................................................................................................................... 1
Typical Operating Circuit ................................................................................................................................................ 1
1
INTRODUCTION....................................................................................................................................................7
1.1
1.2
1.3
Purpose and Scope.............................................................................................................................................. 7
Product Overview................................................................................................................................................ 7
Applications ........................................................................................................................................................ 7
2
3
Features...............................................................................................................................................................8
2.1
2.2
Gyroscope Features ............................................................................................................................................ 8
Additional Features............................................................................................................................................. 8
Electrical Characteristics ......................................................................................................................................9
3.1
3.2
3.2.2
Gyroscope Specifications .................................................................................................................................... 9
Electrical Specifications .................................................................................................................................... 10
D.C. Electrical Characteristics ................................................................................................................... 10
A.C. Electrical Characteristics ................................................................................................................... 11
Other Electrical Specifications .................................................................................................................. 12
3.2.2
3.2.3
3.3
I2C Timing Characterization .............................................................................................................................. 13
SPI Timing Characterization.............................................................................................................................. 14
Absolute Maximum Ratings.............................................................................................................................. 15
3.4
3.5
4
Applications Information ...................................................................................................................................16
4.1
Pin Out Diagram and Signal Description........................................................................................................... 16
Typical Operating Circuit .................................................................................................................................. 17
Bill of Materials for External Components........................................................................................................ 17
Block Diagram................................................................................................................................................... 18
Overview........................................................................................................................................................... 18
Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ......................................................... 18
4.2
4.3
4.4
4.5
4.6
4.7
I2C and SPI Serial Communications Interfaces .................................................................................................. 19
ICG-20330 Solution Using I2C Interface .................................................................................................... 19
ICG-20330 Solution Using SPI Interface.................................................................................................... 20
4.7.1
4.7.2
4.8
Self-Test ............................................................................................................................................................ 20
Document Number: DS-000127
Revision: 1.1
Page 2 of 56
Rev Date: 03/18/2021
ICG-20330
4.9
Clocking ............................................................................................................................................................ 21
4.10 Sensor Data Registers....................................................................................................................................... 21
4.11 FIFO................................................................................................................................................................... 21
4.12 Interrupts .......................................................................................................................................................... 21
4.13 Digital-Output Temperature Sensor ................................................................................................................. 21
4.14 Bias and LDOs ................................................................................................................................................... 21
4.15 Charge Pump .................................................................................................................................................... 21
4.16 Standard Power Modes .................................................................................................................................... 22
4.17 Power-Up Sequence.......................................................................................................................................... 22
4.18 Sensor Initialization and Clock Source Selection............................................................................................... 22
5
6
Programmable Interrupts ..................................................................................................................................23
Digital Interface .................................................................................................................................................24
6.1
6.2
6.3
6.4
6.5
I2C and SPI Serial Interfaces .............................................................................................................................. 24
I2C Interface ...................................................................................................................................................... 24
I2C Communications Protocol ........................................................................................................................... 24
I2C Terms........................................................................................................................................................... 27
SPI Interface...................................................................................................................................................... 28
7
8
Serial Interface Considerations ..........................................................................................................................29
7.1
ICG-20330 Supported Interfaces....................................................................................................................... 29
Assembly ...........................................................................................................................................................30
8.1
8.2
Orientation of Axes........................................................................................................................................... 30
Package Dimensions......................................................................................................................................... 31
9
Part Number Package Marking ..........................................................................................................................33
Reference.......................................................................................................................................................34
Register Map..................................................................................................................................................35
10
11
12
Register Descriptions .....................................................................................................................................37
12.1 Registers 0 to 2 – Gyroscope Self-Test Registers .............................................................................................. 37
12.2 Register 4 – Gyroscope Offset Temperature Compensation (TC) Register........................................................ 38
12.3 Register 5 – Gyroscope Offset Temperature Compensation (TC) Register........................................................ 38
12.4 Register 07 – Gyroscope Offset Temperature Compensation (TC) Register...................................................... 39
12.5 Register 08 – Gyroscope Offset Temperature Compensation (TC) Register...................................................... 39
Document Number: DS-000127
Revision: 1.1
Page 3 of 56
Rev Date: 03/18/2021
ICG-20330
12.6 Register 10 – Gyroscope Offset Temperature Compensation (TC) Register...................................................... 39
12.7 Register 11 – Gyroscope Offset Temperature Compensation (TC) Register...................................................... 40
12.8 Registers 19 – Gyro Offset Adjustment Register............................................................................................... 40
12.9 Registers 20 – Gyro Offset Adjustment Register............................................................................................... 40
12.10
12.11
12.12
12.13
12.14
12.15
12.16
12.17
12.18
12.19
12.20
12.21
12.22
12.23
12.24
12.24
12.25
12 26
12.27
12.28
12.29
Registers 21 – Gyro Offset Adjustment Register........................................................................................... 41
Registers 22 – Gyro Offset Adjustment Register........................................................................................... 41
Registers 23 – Gyro Offset Adjustment Register........................................................................................... 41
Register 24 – Gyro Offset Adjustment Register ............................................................................................ 42
Register 25 – Sample Rate Divider................................................................................................................ 42
Register 26 – Configuration .......................................................................................................................... 43
Register 27 – Gyroscope Configuration ........................................................................................................ 44
Register 35 – FIFO Enable ............................................................................................................................. 45
Register 54 – FSYNC Interrupt Status............................................................................................................ 46
Register 55 – INT Pin / Bypass Enable Configuration.................................................................................... 46
Register 56 – Interrupt Enable...................................................................................................................... 47
Register 58 – Interrupt Status....................................................................................................................... 47
Registers 65 and 66 – Temperature Measurement ...................................................................................... 48
Registers 67 to 72 – Gyroscope Measurements............................................................................................ 49
Register 104 – Signal Path Reset .................................................................................................................. 50
Register 106 – User Control .......................................................................................................................... 51
Register 107 – Power Management 1 .......................................................................................................... 52
Register 108 – Power Management 2 .......................................................................................................... 53
Register 114 and 115 – FIFO Count Registers............................................................................................... 53
Register 116 – FIFO Read Write.................................................................................................................... 54
Register 117 – Who Am I .............................................................................................................................. 54
13
Revision History .............................................................................................................................................55
Document Number: DS-000127
Revision: 1.1
Page 4 of 56
Rev Date: 03/18/2021
ICG-20330
LIST OF FIGURES
Figure 1. I2C Bus Timing Diagram....................................................................................................................13
Figure 2. SPI Bus Timing Diagram...................................................................................................................14
Figure 3. Pin-out Diagram for ICG-20330 3.0x3.0x0.75 mm LGA....................................................................16
Figure 4. ICG-20330 LGA Application Schematic ............................................................................................17
Figure 5. ICG-20330 Block Diagram ................................................................................................................18
Figure 6. ICG-20330 Solution Using I2C Interface............................................................................................19
Figure 7. ICG-20330 Solution Using SPI Interface...........................................................................................20
Figure 8. START and STOP Conditions...........................................................................................................25
Figure 9. Acknowledge on the I2C Bus.............................................................................................................25
Figure 10. Complete I2C Data Transfer ............................................................................................................26
Figure 11. Typical SPI Master / Slave Configuration........................................................................................28
Figure 12. I/O Levels and Connections ............................................................................................................29
Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation..............................................................30
Document Number: DS-000127
Revision: 1.1
Page 5 of 56
Rev Date: 03/18/2021
ICG-20330
LIST OF TABLES
Table 1. Gyroscope Specifications .....................................................................................................................9
Table 2. D.C. Electrical Characteristics ............................................................................................................10
Table 3. A.C. Electrical Characteristics ............................................................................................................12
Table 4. Other Electrical Specifications............................................................................................................12
Table 5. I2C Timing Characteristics ..................................................................................................................13
Table 6. SPI Timing Characteristics (7 MHz Operation) ..................................................................................14
Table 7. Absolute Maximum Ratings................................................................................................................15
Table 8. Signal Descriptions.............................................................................................................................16
Table 9. Bill of Materials ...................................................................................................................................17
Table 10. Standard Power Modes for ICG-20330 ............................................................................................22
Table 11. Table of Interrupt Sources ................................................................................................................23
Table 12. Serial Interface..................................................................................................................................24
Table 13. I2C Terms..........................................................................................................................................27
Table 14. ICG-20330 Register Map..................................................................................................................36
Document Number: DS-000127
Revision: 1.1
Page 6 of 56
Rev Date: 03/18/2021
ICG-20330
1 INTRODUCTION
1.1 PURPOSE AND SCOPE
This document is a preliminary product specification, providing a description, specifications, and design related
information on the ICG-20330 MotionTracking device for imaging applications, such as Optical Image
Stabilization, OIS, or Electronic Image Stabilization, EIS. The device is housed in a small 3x3x0.75 mm 16-pin
LGA package.
1.2 PRODUCT OVERVIEW
The ICG-20330 is a 3-axis MotionTracking device that has a 3-axis gyroscope in a small 3x3x0.75 mm (16-pin
LGA) package. It also features a 512-byte FIFO for EIS applications to lower the traffic on the serial bus
interface, and reduce power consumption by allowing the system processor to burst read sensor data for a
given video frame. The unique support for FSYNC (frame sync), facilitates synchronization of Video Frame
Sync from Image sensors and Motion data from gyro collected during a given frame via an interrupt to the host.
The gyroscope has a programmable full-scale range of ±31.25, ±62.5, ±125 and ±250 degrees/sec, optimized
for Image Stabilization applications.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts. The device features I2C and SPI serial interfaces, a VDD
operating range of 1.71 V to 3.6 V, and a separate digital IO supply, VDDIO from 1.71 V to 3.6 V.
Communication with all registers of the device is performed using either I2C at 400 kHz or SPI at 7 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS
wafers with companion CMOS electronics through wafer-level bonding, InvenSense has driven the package
size down to a footprint and thickness of 3x3x0.75 mm (16-pin LGA), to provide a very small yet
high-performance, low-cost package. The device provides high robustness by supporting 10,000g shock
reliability.
1.3 APPLICATIONS
•
•
OIS, Optical Image Stabilization in phone camera modules, DSLR, and DSC
EIS, Electronic Image Stabilization in DSC, and phone camera modules
Document Number: DS-000127
Revision: 1.1
Page 7 of 56
Rev Date: 03/18/2021
ICG-20330
2 FEATURES
2.1 GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICG-20330 includes a wide range of features:
•
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-
scale range of ±31.25, ±62.5, ±125 and ±250 °/sec and integrated 16-bit ADCs
Digitally-programmable low-pass filter
Factory calibrated sensitivity scale factor
Self-test
•
•
•
2.2 ADDITIONAL FEATURES
The ICG-20330 includes the following additional features:
•
•
•
•
•
•
•
•
512-byte FIFO buffer enable the applications processor to read the data in bursts
Digital-output temperature sensor
User-programmable digital filters for gyroscope and temp sensor
10,000 g shock tolerant
400-kHz Fast Mode I2C for communicating with all registers
7-MHz SPI serial interface for communicating with all registers
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
Document Number: DS-000127
Revision: 1.1
Page 8 of 56
Rev Date: 03/18/2021
ICG-20330
3 ELECTRICAL CHARACTERISTICS
3.1 GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
GYROSCOPE SENSITIVITY
MIN
TYP
MAX
UNITS
NOTES
Full-Scale Range
FS_SEL= 0
FS_SEL= 1
FS_SEL= 2
FS_SEL= 3
±31.25
±62.5
±125
±250
16
º/s
º/s
3
3
3
3
3
3
3
3
3
1
1
º/s
º/s
ADC Word Length
bits
Sensitivity Scale Factor
FS_SEL= 0
FS_SEL=1
FS_SEL= 2
FS_SEL= 3
25°C
1048
524
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
%
262
131
Sensitivity Scale Factor Tolerance
±1
Sensitivity Scale Factor Variation Over
Temperature
-20°C to +75°C
±3
%
Nonlinearity
Best fit straight line; 25°C
±0.1
±2
%
%
1
1
Cross-Axis Sensitivity
ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance
25°C
±5
±5
º/s
º/s
2
1
ZRO Variation Over Temperature
-20°C to +75°C
GYROSCOPE NOISE PERFORMANCE (FS_SEL=0)
Total RMS Noise
DLPFCFG = 2 (92 Hz)
DLPFCFG = 2 (92 Hz)
At 10 Hz
0.06
0.30
º/s-rms
º/s-p-p
º/s/√Hz
2
2
2
Total Peak-to-Peak Noise
Rate Noise Spectral Density
0.005
GYROSCOPE MECHANICAL
Mechanical Frequency
Sensor Mechanical Bandwidth
LOW PASS FILTER RESPONSE
25
1.6
27
80
29
KHz
KHz
2
1
3
Programmable Range
92
250
Hz
ms
1
1
GYROSCOPE START-UP TIME
OUTPUT DATA RATE
Programmable, Normal (Filtered)
mode
1000
8000
Hz
Table 1. Gyroscope Specifications
Notes:
1. Derived from validation or characterization of parts on PCB, not guaranteed in production.
2. Tested in production.
3. Guaranteed by design.
4. Calculated from Total RMS Noise.
Document Number: DS-000127
Revision: 1.1
Page 9 of 56
Rev Date: 03/18/2021
ICG-20330
3.2 ELECTRICAL SPECIFICATIONS
3.2.2
D.C. Electrical Characteristics
Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLY VOLTAGES
VDD
1.71
1.71
1.8
1.8
3.45
3.45
V
V
1
1
VDDIO
SUPPLY CURRENTS & BOOT TIME
3-Axis Gyroscope
Active Current
2.9
mA
1
Full-Chip Sleep Mode
Boot Time
10
50
µA
ms
1
1
VDD on to first register write
TEMPERATURE RANGE
Operating Temperature Range
-40
+85
°C
1
Table 2. D.C. Electrical Characteristics
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Based on simulation.
Document Number: DS-000127
Revision: 1.1
Page 10 of 56
Rev Date: 03/18/2021
ICG-20330
3.2.2
A.C. Electrical Characteristics
Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
Parameter
Conditions
MIN
TYP
MAX
UNITS
NOTES
SUPPLIES
Monotonic ramp. Ramp rate
is 10% to 90% of the final
value
Supply Ramp Time
0.01
100
ms
1
TEMPERATURE SENSOR
Operating Range
Room Temperature Offset
Sensitivity
Ambient
25°C
1
1
1
-40
85
°C
°C
0
Untrimmed
326.8
LSB/°C
Power-On RESET
Supply Ramp Time (TRAMP
)
Valid power-on RESET
0.01
100
100
ms
ms
1
1
Start-up time for register read/write
From power-up
11
SA0 = 0
SA0 = 1
1101000
1101001
I2C ADDRESS
DIGITAL INPUTS (FSYNC, SA0, SPC, SDI, CS)
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
0.7*VDDIO
V
V
0.3*VDDIO
1
1
< 10
pF
DIGITAL OUTPUT (SDO, INT)
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT, INT Low-Level Output Voltage
RLOAD = 1MΩ;
RLOAD = 1MΩ;
0.9*VDDIO
V
V
V
0.1*VDDIO
0.1
OPEN = 1, 0.3 mA sink
Current
Output Leakage Current
tINT, INT Pulse Width
OPEN = 1
100
50
nA
µs
LATCH_INT_EN = 0
I2C I/O (SCL, SDA)
VIL, LOW Level Input Voltage
VIH, HIGH-Level Input Voltage
-0.5V
0.3*VDDIO
V
V
0.7*VDDIO
VDDIO +
0.5V
Vhys, Hysteresis
0.1*VDDIO
V
V
VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current
3 mA sink current
0
0.4
1
VOL = 0.4V
VOL = 0.6 V
3
6
mA
mA
Output Leakage Current
100
nA
ns
tof, Output Fall Time from VIHmax to VILmax Cb bus capacitance in pf
20+0.1Cb
300
INTERNAL CLOCK SOURCE
FCHOICE_B = 1,2,3
32
8
kHz
kHz
2
2
SMPLRT_DIV = 0
FCHOICE_B = 0;
DLPFCFG = 0 or 7
SMPLRT_DIV = 0
FCHOICE_B = 0;
DLPFCFG = 1,2,3,4,5,6;
SMPLRT_DIV = 0
Sample Rate
1
kHz
2
Document Number: DS-000127
Revision: 1.1
Page 11 of 56
Rev Date: 03/18/2021
ICG-20330
Parameter
Conditions
MIN
TYP
MAX
UNITS
NOTES
CLK_SEL = 0, 6 or gyro
inactive; 25°C
CLK_SEL = 1,2,3,4,5 and
gyro active; 25°C
CLK_SEL = 0,6 or gyro
inactive
-5
+5
%
1
Clock Frequency Initial Tolerance
-1
+1
%
%
%
1
1
1
-10
+10
Frequency Variation over Temperature
CLK_SEL = 1,2,3,4,5 and
gyro active
±1
Table 3. A.C. Electrical Characteristics
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Guaranteed by design.
3.2.3
Other Electrical Specifications
Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SERIAL INTERFACE
100
±10%
Low Speed Characterization
High Speed Characterization
kHz
1
SPI Operating Frequency, All
Registers Read/Write
1
7
MHz
1, 2
Modes 0
and 3
SPI Modes
All registers, Fast-mode
400
100
kHz
kHz
1
1
I2C Operating Frequency
All registers, Standard-mode
Table 4. Other Electrical Specifications
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. SPI clock duty cycle between 45% and 55% should be used for 7-MHz operation.
Document Number: DS-000127
Revision: 1.1
Page 12 of 56
Rev Date: 03/18/2021
ICG-20330
3.3 I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
Parameters
I2C TIMING
Conditions
I2C FAST-MODE
MIN
TYP
MAX
UNITS
NOTES
fSCL, SCL Clock Frequency
tHD.STA, (Repeated) START Condition Hold Time
400
kHz
µs
1
1
0.6
tLOW, SCL Low Period
1.3
0.6
µs
µs
µs
µs
ns
ns
ns
µs
1
1
1
1
1
1
1
1
tHIGH, SCL High Period
tSU.STA, Repeated START Condition Setup Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
tf, SDA and SCL Fall Time
0.6
0
100
Cb bus cap. from 10 to 400 pF
Cb bus cap. from 10 to 400 pF
20+0.1Cb
20+0.1Cb
0.6
300
300
tSU.STO, STOP Condition Setup Time
tBUF, Bus Free Time Between STOP and START
Condition
1.3
µs
1
Cb, Capacitive Load for each Bus Line
tVD.DAT, Data Valid Time
< 400
pF
µs
µs
1
1
1
0.9
0.9
tVD.ACK, Data Valid Acknowledge Time
Table 5. I2C Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
tf
tSU.DAT
tr
SDA
SCL
70%
30%
70%
30%
continued below at
9th clock cycle
A
tf
tr
tVD.DAT
70%
30%
70%
30%
tHD.DAT
tHD.STA
1/fSCL
tLOW
1st clock cycle
S
tHIGH
tBUF
SDA
SCL
70%
30%
A
tSU.STO
tSU.STA
tHD.STA
tVD.ACK
70%
30%
9th clock cycle
S
P
Sr
Figure 1. I2C Bus Timing Diagram
Document Number: DS-000127
Revision: 1.1
Page 13 of 56
Rev Date: 03/18/2021
ICG-20330
3.4 SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
MIN
TYP
MAX
UNITS
NOTES
Parameters
Conditions
SPI TIMING
fSCLK, SCLK Clock Frequency
7
MHz
ns
tLOW, SCLK Low Period
tHIGH, SCLK High Period
tSU.CS, CS Setup Time
tHD.CS, CS Hold Time
tSU.SDI, SDI Setup Time
tHD.SDI, SDI Hold Time
64
64
8
ns
ns
500
5
ns
ns
7
ns
tVD.SDO, SDO Valid Time
Cload = 20pF
Cload = 20pF
59
50
ns
ns
ns
tHD.SDO, SDO Hold Time
6
tDIS.SDO, SDO Output Disable Time
Table 6. SPI Timing Characteristics (7 MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
CS
70%
30%
tHD;CS
tSU;CS
70%
tHIGH
1/fCLK
SCLK
30%
tSU;SDI
tHD;SDI
tLOW
70%
30%
SDI
LSB IN
MSB IN
tDIS;SDO
tVD;SDO
70%
30%
SDO
MSB OUT
LSB OUT
Figure 2. SPI Bus Timing Diagram
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ICG-20330
3.5 ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to
the absolute maximum ratings conditions for extended periods may affect device reliability.
Parameter
Rating
Supply Voltage, VDD
-0.5 V to +4 V
Supply Voltage, VDDIO
REGOUT
-0.5 V to +4 V
-0.5 V to 2 V
Input Voltage Level (SA0, FSYNC, SCL, SDA)
Acceleration (Any Axis, unpowered)
Storage Temperature Range
-0.5 V to VDD + 0.5 V
10,000g for 0.2 ms
-40°C to +125°C
2 kV (HBM);
250 V (MM)
Electrostatic Discharge (ESD) Protection
Latch-up
JEDEC Class II (2),125°C
±100 mA
Table 7. Absolute Maximum Ratings
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Revision: 1.1
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ICG-20330
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
Pin Number
Pin Name
VDDIO
SCL/SPC
SDA/SDI
SA0/SDO
CS
Pin Description
1
2
Digital I/O supply voltage
I2C serial clock (SCL); SPI serial clock (SPC)
3
I2C serial data (SDA); SPI serial data input (SDI)
I2C slave address LSB (SA0); SPI serial data output (SDO)
Chip select (0 = SPI mode; 1 = I2C mode)
Interrupt digital output (totem pole or open-drain)
Reserved. Do not connect.
4
5
6
INT
7
RESV
FSYNC
NC
8
Synchronization digital input (optional). Connect to GND if unused.
Connect to GND or do not connect
9
10
11
12
13
14
15
NC
Connect to GND or do not connect
NC
Connect to GND or do not connect
NC
Connect to GND or do not connect
GND
Connect to GND
REGOUT
RESV
Regulator filter capacitor connection
Reserved. Connect to GND
16
VDD
Power Supply
Table 8. Signal Descriptions
Note: VDD, VDDIO, SCL/SPC and CS pins must be correctly managed at power-up to guarantee proper device start-up. Please refer to sections 4.17
and 4.18 for detailed power-up instructions.
16 15 14
13
12
11
10
9
VDDIO
SCL/SPC
SDA/SDI
SA0/SDO
CS
1
2
3
4
5
GND
NC
+Z
ICG-20330
NC
I
C
G
-
2
0
3
3
NC
0
NC
+Y
+X
6
7
8
LGA Package (Top View)
16-pin, 3 mm x 3 mm x 0.75 mm
Typical Footprint and thickness
Orientation of Axes of Sensitivity and Polarity of Rotation
Figure 3. Pin-out Diagram for ICG-20330 3.0x3.0x0.75 mm LGA
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Revision: 1.1
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ICG-20330
4.2 TYPICAL OPERATING CIRCUIT
1.8 – 3.3VDC
C2, 0.1 mF
VDD
C4, 2.2 mF
REGOUT
16 15 14
C1, 0.47 mF
GND
VDDIO
1.8 – 3.3 VDC
13
12
11
10
9
1
2
3
4
5
C3, 10 nF
SCL/SPC
SDA/SDI
NC
NC
SCL
SDA
AD0
ICG-20330
SA0/SDO
CS
NC
NC
VDDIO
6
7
8
Figure 4. ICG-20330 LGA Application Schematic
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS
Component
Label
Specification
Quantity
REGOUT Capacitor
C1
Ceramic, X7R, 0.47 µF ±10%, 2 V
Ceramic, X7R, 0.1 µF ±10%, 4 V
Ceramic, X7R, 2.2 µF ±10%, 4 V
Ceramic, X7R, 10 nF ±10%, 4 V
1
1
1
1
C2
VDD Bypass Capacitors
VDDIO Bypass Capacitor
C4
C3
Table 9. Bill of Materials
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Revision: 1.1
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ICG-20330
4.4 BLOCK DIAGRAM
ICG-20330
INT
Self
X Gyro
test
ADC
ADC
ADC
Interrupt
Status
Register
CS
Self
Y Gyro
test
Slave I2C and
SPI Serial
Interface
SA0 / SDO
SCL / SPC
SDA / SDI
FIFO
Self
test
Z Gyro
User & Config
Registers
FSYNC
Temp Sensor
ADC
Sensor
Registers
Charge
Pump
Bias & LDOs
VDD
GND
REGOUT
Figure 5. ICG-20330 Block Diagram
4.5 OVERVIEW
The ICG-20330 is comprised of the following key blocks and functions:
•
•
•
•
•
•
•
•
•
•
•
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Primary I2C and SPI serial communications interfaces
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes
4.6 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICG-20330 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about
the X-, Y-, and Z- Axes. When the gyros are rotated about any of the sense axes, the Coriolis Effect causes
a vibration that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered
to produce a voltage that is proportional to the angular rate. This voltage is digitized using individual on-chip
16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors may
be digitally programmed to ±31.25, ±62.5, ±125 and ±250 degrees per second (dps). The ADC sample rate is
programmable up to 8,000 samples per second with user-selectable low-pass filters that enable a wide range
of cut-off frequencies.
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ICG-20330
4.7 I2C AND SPI SERIAL COMMUNICATIONS INTERFACES
The ICG-20330 communicates to a system processor using either a SPI or an I2C serial interface. The ICG-
20330 always acts as a slave when communicating to the system processor. The LSB of the I2C slave address
is set by pin 4 (SA0).
4.7.1
ICG-20330 Solution Using I2C Interface
In the figure below, the system processor is an I2C master to the ICG-20330.
Interrupt
Status
Register
I2C Processor Bus: for reading all
sensor data
INT
ICG-20330
SA0
SCL
VDDIO or GND
Slave I2C
or SPI
SCL
SDA
System
Processor
Serial
Interface
SDA
FIFO
User & Config
Registers
Sensor
Register
Factory
Calibration
Bias & LDOs
VDD
GND
REGOUT
Figure 6. ICG-20330 Solution Using I2C Interface
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Revision: 1.1
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ICG-20330
4.7.2
ICG-20330 Solution Using SPI Interface
In the figure below, the system processor is an SPI master to the ICG-20330. Pins 2, 3, 4, and 5 are used to
support the SPC, SDI, SDO, and CS signals for SPI communications.
Processor SPI Bus: for reading all
data
Interrupt
Status
Register
INT
nCS
CS
ICG-20330
SDO
SDI
Slave I2C
or SPI
Serial
Interface
System
Processor
SPC
SDI
SPC
SDO
FIFO
Config
Register
Sensor
Register
Factory
Calibration
Bias & LDOs
VDD
GND
REGOUT
Figure 7. ICG-20330 Solution Using SPI Interface
4.8 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each
measurement axis can be activated by means of the gyroscope self-test registers (registers 27 and 28).
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal.
The output signal is used to observe the self-test response.
The self-test response is defined as follows:
Self-test response = Sensor output with self-test enabled – Sensor output with self-test disabled
The self-test response for each gyroscope axis is defined in the gyroscope specification table.
When the value of the self-test response is within the specified min/max limits of the product specification, the
part has passed self-test. When the self-test response exceeds the min/max values, the part is deemed to
have failed self-test. It is recommended to use InvenSense MotionApps software for executing self-test.
For further information on Self-Test, please refer to the register map of ICG-20330.
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ICG-20330
4.9 CLOCKING
The ICG-20330 has a flexible clocking scheme, allowing a variety of internal clock sources to be used for the
internal synchronous circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and
various control circuits and registers. An on-chip PLL provides flexibility in the allowable inputs for generating
this clock.
Allowable internal sources for generating the internal clock are:
a) An internal relaxation oscillator
b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best
available source
The only setting supporting specified performance in all modes is option b). It is recommended that option b)
be used.
4.10 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope and temperature measurement data. They are read-
only registers, and are accessed via the serial interface. Data from these registers may be read anytime.
4.11 FIFO
The ICG-20330 contains a 512-byte FIFO register that is accessible via the Serial Interface. The FIFO
configuration register determines which data is written into the FIFO. Possible choices include gyro data and
temperature readings, and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are
contained in the FIFO. The FIFO register supports burst reads. The interrupt function may be used to
determine when new data is available.
For further information regarding the FIFO, please refer to the register map of ICG-20330.
4.12 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include
the INT pin configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that
can trigger an interrupt are (1) Clock generator locked to new reference oscillator (used when switching clock
sources); (2) new data is available to be read (from the FIFO and Data registers); (3) FIFO overflow. The
interrupt status can be read from the Interrupt Status register.
4.13 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICG-20330 die temperature. The readings
from the ADC can be read from the FIFO or the Sensor Data registers.
4.14 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by
the ICG-20330. Its two inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO
output is bypassed by a capacitor at REGOUT. For further details on the capacitor, please refer to the Bill of
Materials for External Components.
4.15 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
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ICG-20330
4.16 STANDARD POWER MODES
The following table lists the user-accessible power modes for ICG-20330.
Mode Name
Gyro
Off
1
2
Sleep Mode
Standby Mode
Drive On
Table 10. Standard Power Modes for ICG-20330
Notes:
1. Power consumption for individual modes can be found in section 0.
4.17 POWER-UP SEQUENCE
When applying VDD, the power voltage ramp is detected and a power-on-reset sequence is triggered inside
the component. During this phase the device starts operating and internal logic levels are defined. For proper
component initialization the power-up should be performed with both CS and SCL/SPC low, ensuring that CS
and SCL pins are not in an undetermined state during the VDD ramp. If starting in I2C mode (CS at logic
high), power-up should be performed with SCL/SPC low. Power-up with SCL/SPC high is not a supported
case and must be avoided.
It is worth noting that if the I/O pins (e.g. CS, SCL/SPC) are between VIL and VIH when the power-on-reset
sequence is triggered, their value is undetermined and the internal logic levels may not be properly defined.
It should also be noted that VIL and VIH are related to VDDIO and their value changes at power-up according
to the applied VDDIO voltage ramp.
Power-up sequences that do not respect the conditions above may not lead to proper digital interface
initialization. In this case a preliminary soft reset operation (PWR_MGMT_1 register set 0x81) must be
performed to reset the digital interface, as soon as both VDD and VDDIO are stable at their final voltage. Since
the digital interface may not be properly initialized, the device may not provide the acknowledge signal if the
I2C protocol is used.
4.18 SENSOR INITIALIZATION AND CLOCK SOURCE SELECTION
When power-up sequence is completed (as per section 4.17), a soft reset is required to initialize the sensor
and let the device select the best clock source. The soft reset must be performed by setting the register
PWR_MGMT_1 (address 0x6B) to 0x81, prior to registers initialization.
Soft reset must be performed as first operation after the power-up sequence to ensure the proper component
registers setting. Correct WHOAMI value is ensured only after the soft reset has been completed.
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ICG-20330
5 PROGRAMMABLE INTERRUPTS
The ICG-20330 has a programmable interrupt system which can generate an interrupt signal on the INT pin.
Status flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually.
Interrupt Name
FIFO Overflow
Data Ready
Module
FIFO
Sensor Registers
Table 11. Table of Interrupt Sources
For information regarding the interrupt enable/disable registers and flag registers, please refer to the register
map of ICG-20330 in this document.
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ICG-20330
6 DIGITAL INTERFACE
6.1 I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICG-20330 can be accessed using either I2C at 400 kHz or SPI at
7 MHz. SPI operates in four-wire mode.
Pin Number
Pin Name
VDDIO
Pin Description
1
4
2
3
Digital I/O supply voltage.
SA0 / SDO
SCL / SPC
SDA / SDI
I2C Slave Address LSB (SA0); SPI serial data output (SDO)
I2C serial clock (SCL); SPI serial clock (SPC)
I2C serial data (SDA); SPI serial data input (SDI)
Table 12. Serial Interface
Note:
To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the
I2C_IF_DIS configuration bit. Setting this bit should be performed immediately after waiting for the time
specified by the “Start-Up Time for Register Read/Write” in Section 6.3.
For further information regarding the I2C_IF_DIS bit, please refer to the register map of ICG-20330.
6.2 I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the
lines are open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be
a master or a slave. The master device puts the slave address on the bus, and the slave device with the
matching address acknowledges the master.
The ICG-20330 always operates as a slave device when communicating to the system processor, which thus
acts as the master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is
400 kHz.
The slave address of the ICG-20330 is b110100X which is 7 bits long. The LSB bit of the 7-bit address is
determined by the logic level on pin SA0. This allows two ICG-20330s to be connected to the same I2C bus.
When used in this configuration, the address of one of the devices should be b1101000 (pin SA0 is logic low)
and the address of the other should be b1101001 (pin SA0 is logic high).
6.3 I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is
defined as a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is
considered to be busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to
HIGH transition on the SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
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ICG-20330
SDA
SCL
S
P
START condition
STOP condition
Figure 8. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8 bits long. There is no restriction to the number of bytes transmitted per data
transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the
acknowledge signal is generated by the master, while the receiver generates the actual acknowledge signal
by pulling down SDA and holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed,
it can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave
is ready, and releases the clock line (refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM
MASTER
1
2
8
9
clock pulse for
acknowledgement
START
condition
Figure 9. Acknowledge on the I2C Bus
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ICG-20330
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed
by an 8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is
writing to the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK)
from the slave device. Each byte transferred must be followed by an acknowledge bit. To acknowledge, the
slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line. Data transmission
is always terminated by the master with a STOP condition (P), thus freeing the communications line. However,
the master can generate a repeated START condition (Sr), and address another slave without first generating
a STOP condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition.
All SDA changes should take place when SCL is low, with the exception of start and stop conditions.
SDA
SCL
1 – 7
8
9
1 – 7
8
9
1 – 7
8
9
S
P
START
STOP
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
condition
condition
Figure 10. Complete I2C Data Transfer
To write the internal ICG-20330 registers, the master transmits the start condition (S), followed by the I2C
address and the write bit (0). At the 9th clock cycle (when the clock is high), the ICG-20330 acknowledges the
transfer. Then the master puts the register address (RA) on the bus. After the ICG-20330 acknowledges the
reception of the register address, the master puts the register data onto the bus. This is followed by the ACK
signal, and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK
signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ICG-
20330 automatically increments the register address and loads the data to the appropriate register. The
following figures show single and two-byte write sequences.
Single-Byte Write Sequence
Master
Slave
S
AD+W
RA
RA
DATA
DATA
P
ACK
ACK
ACK
ACK
ACK
ACK
Burst Write Sequence
Master
Slave
S
AD+W
DATA
P
ACK
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ICG-20330
To read the internal ICG-20330 registers, the master sends a start condition, followed by the I2C address and
a write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the ICG-
20330, the master transmits a start signal followed by the slave address and read bit. As a result, the ICG-
20330 sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal
and a stop bit from master. The NACK condition is defined such that the SDA line remains high at the 9th clock
cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
RA
RA
S
S
AD+R
AD+R
NACK
ACK
P
ACK
ACK
ACK
ACK
ACK DATA
ACK DATA
Burst Read Sequence
Master
Slave
S
AD+W
NACK
P
DATA
6.4 I2C TERMS
Signal Description
S
AD
W
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
Write bit (0)
R
Read bit (1)
ACK
Acknowledge: SDA line is low while the SCL line is high at the 9th
clock cycle
NACK Not-Acknowledge: SDA line stays high at the 9th clock cycle
RA
DATA
P
ICG-20330 internal register address
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 13. I2C Terms
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Revision: 1.1
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ICG-20330
6.5 SPI INTERFACE
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The ICG-20330
always operates as a Slave device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SPC), the Serial Data Output (SDO) and the Serial Data
Input (SDI) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line
from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is
active at a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected
slave devices are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they
do not interfere with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SPC
3. Data should be transitioned on the falling edge of SPC
4. The maximum frequency of SPC is 7 MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The
first byte contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first bit
of the first byte contains the Read/Write bit and indicates the Read (1) or Write (0) operation. The
following 7 bits contain the Register Address. In cases of multiple-byte Read/Writes, data is two
or more bytes:
SPI Address format
MSB
LSB
R/W A6 A5 A4 A3 A2 A1
A0
SPI Data format
MSB
LSB
D7
D6 D5 D4 D3 D2 D1
D0
6. Supports Single or Burst Read/Writes.
SPC
SDI
SPI Master
CS1
SPI Slave 1
SDO
CS
CS2
SPC
SDI
SDO
CS
SPI Slave 2
Figure 11. Typical SPI Master / Slave Configuration
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Revision: 1.1
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ICG-20330
7 SERIAL INTERFACE CONSIDERATIONS
7.1 ICG-20330 SUPPORTED INTERFACES
The ICG-20330 supports I2C communications on its serial interface.
The ICG-20330’s I/O logic levels are set to be VDDIO.
The figure below depicts a sample circuit of ICG-20330. It shows the relevant logic levels and voltage
connections.
VDDIO
VDD_IO
(0V - VDDIO)
SYSTEM BUS
System
Processor IO
VDD
VDDIO
VDD
(0V - VDDIO)
INT
SDA
SCL
(0V - VDDIO)
(0V - VDDIO)
(0V - VDDIO)
SYNC
VDDIO
ICG-20330
VDDIO
(0V, VDDIO)
SA0
Figure 12. I/O Levels and Connections
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Revision: 1.1
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ICG-20330
8 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems
(MEMS) gyros packaged in LGA package.
8.1 ORIENTATION OF AXES
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1
identifier (•) in the figure.
+Z
I
C
+Y
G
-
2
0
3
3
0
+X
Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation
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ICG-20330
8.2 PACKAGE DIMENSIONS
16 Lead LGA (3x3x0.75) mm NiAu pad finish
Document Number: DS-000127
Revision: 1.1
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ICG-20330
DIMENSIONS IN MILLIMETERS
SYMBOLS
MIN
NOM
MAX
Total Thickness
Substrate Thickness
Mold Thickness
A
A1
A2
0.7
0.75
0.105
0.63
0.8
REF
REF
D
E
2.9
2.9
0.2
0.3
3
3
3.1
3.1
0.3
Body Size
Lead Width
Lead Length
W
0.25
L
e
n
0.35
0.5
16
2
0.4
BSC
Lead Pitch
Lead Count
D1
E1
SD
BSC
BSC
BSC
Edge Ball Center to Center
Body Center to Contact Ball
1
---
SE
b
---
---
---
---
---
---
---
BSC
---
Ball Width
Ball Diameter
Ball Opening
Ball Pitch
Ball Count
Pre-Solder
---
---
e1
n1
---
Package Edge Tolerance
aaa
bbb
ddd
eee
fff
0.1
0.2
0.08
---
Mold Flatness
Coplanarity
Ball Offset (Package)
Ball Offset (Ball)
---
Lead Edge to Package Edge
M
0.01
0.06
0.11
Document Number: DS-000127
Revision: 1.1
Page 32 of 56
Rev Date: 03/18/2021
ICG-20330
9 PART NUMBER PACKAGE MARKING
The part number package marking for ICG-20330 devices is summarized below:
Part Number
Part Number Package Marking
IC2330
ICG-20330
Document Number: DS-000127
Revision: 1.1
Page 33 of 56
Rev Date: 03/18/2021
ICG-20330
10 REFERENCE
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following
information:
• Manufacturing Recommendations
o
o
o
o
o
o
o
o
o
o
o
Assembly Guidelines and Recommendations
PCB Design Guidelines and Recommendations
MEMS Handling Instructions
ESD Considerations
Reflow Specification
Storage Specifications
Package Marking Specification
Tape & Reel Specification
Reel & Pizza Box Label
Packaging
Representative Shipping Carton Label
• Compliance
o
o
o
Environmental Compliance
DRC Compliance
Compliance Declaration Disclaimer
Document Number: DS-000127
Revision: 1.1
Page 34 of 56
Rev Date: 03/18/2021
ICG-20330
11 REGISTER MAP
The following table lists the register map for the ICG-20330.
The device will come up in sleep mode upon power-up. In order to take the device out of the sleep mode set
the PWR_MGMT_1[6] = 0 in register 107 (sleep mode bit in power management register).
Accessible in
Sleep and
LPA Modes?
Addr
(Hex)
Addr
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(Dec.)
00
READ/
WRITE
00
01
02
04
SELF_TEST_X_GYRO
SELF_TEST_Y_GYRO
SELF_TEST_Z_GYRO
XG_OFFS_TC_H
N
N
N
N
XG_ST_DATA[7:0]
YG_ST_DATA[7:0]
ZG_ST_DATA[7:0]
READ/
WRITE
01
READ/
WRITE
02
READ/
WRITE
XG_OFFS_
TC_H [9]
XG_OFFS_
TC_H [8]
04
-
-
-
-
-
-
-
-
-
-
-
-
-
-
READ/
WRITE
05
07
08
0A
0B
05
07
08
10
11
XG_OFFS_TC_L
YG_OFFS_TC_H
YG_OFFS_TC_L
ZG_OFFS_TC_H
ZG_OFFS_TC_L
N
N
N
N
N
XG_OFFS_TC_L [7:0]
READ/
WRITE
YG_OFFS_
TC_H [9]
YG_OFFS_
TC_H [8]
-
-
READ/
WRITE
YG_OFFS_TC_L [7:0]
READ/
WRITE
ZG_OFFS_
TC_H [9]
ZG_OFFS_
TC_H [8]
-
-
READ/
WRITE
ZG_OFFS_TC_L [7:0]
READ/
WRITE
13
14
15
16
17
18
19
1A
1B
23
19
20
21
22
23
24
25
26
27
35
XG_OFFS_USRH
XG_OFFS_USRL
YG_OFFS_USRH
YG_OFFS_USRL
ZG_OFFS_USRH
ZG_OFFS_USRL
SMPLRT_DIV
N
N
N
N
N
N
Y
N
N
N
X_OFFS_USR [15:8]
X_OFFS_USR [7:0]
Y_OFFS_USR [15:8]
Y_OFFS_USR [7:0]
Z_OFFS_USR [15:8]
Z_OFFS_USR [7:0]
SMPLRT_DIV[7:0]
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
FIFO_
MODE
CONFIG
-
EXT_SYNC_SET[2:0]
FS_SEL [1:0]
ZG_FIFO_E
DLPF_CFG[2:0]
READ/
WRITE
GYRO_CONFIG
FIFO_EN
XG_ST
YG_ST
ZG_ST
-
-
FCHOICE_B[1:0]
READ/
WRITE
TEMP
_FIFO_EN
XG_FIFO_E
N
YG_FIFO_E
N
-
-
-
-
-
-
N
READ
to
CLEA
R
FSYNC_IN
T
36
54
FSYNC_INT
N
-
-
-
-
FSYNC
_INT_MOD
E_EN
READ/
WRITE
LATCH
_INT_EN
INT_RD
_CLEAR
FSYNC_INT
_LEVEL
37
38
55
56
INT_PIN_CFG
INT_ENABLE
Y
Y
-
-
INT_OPEN
-
-
-
FIFO
_OFLOW
_EN
READ/
WRITE
GDRIVE_IN
T_EN
DATA_RDY
_INT_EN
-
-
WOM_EN
-
READ
to
CLEA
R
FIFO
_OFLOW
_INT
GDRIVE_IN
T
DATA
_RDY_INT
3A
41
58
65
INT_STATUS
TEMP_OUT_H
N
N
-
-
READ
TEMP_OUT[15:8]
Document Number: DS-000127
Revision: 1.1
Page 35 of 56
Rev Date: 03/18/2021
ICG-20330
Accessible in
Sleep and
LPA Modes?
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
42
43
44
45
46
47
48
66
67
68
69
70
71
72
TEMP_OUT_L
GYRO_XOUT_H
GYRO_XOUT_L
GYRO_YOUT_H
GYRO_YOUT_L
GYRO_ZOUT_H
GYRO_ZOUT_L
READ
READ
READ
READ
READ
READ
READ
N
N
N
N
N
N
N
TEMP_OUT[7:0]
GYRO_XOUT[15:8]
GYRO_XOUT[7:0]
GYRO_YOUT[15:8]
GYRO_YOUT[7:0]
GYRO_ZOUT[15:8]
GYRO_ZOUT[7:0]
READ/
WRITE
TEMP
_RST
68
6A
6B
6C
104
106
107
108
SIGNAL_PATH_RESET
USER_CTRL
N
N
Y
Y
-
-
-
-
-
-
-
-
-
-
-
READ/
WRITE
I2C_IF
_DIS
FIFO
_RST
SIG_COND
_RST
FIFO_EN
SLEEP
-
-
READ/
WRITE
DEVICE_
RESET
GYRO_
STANDBY
PWR_MGMT_1
PWR_MGMT_2
TEMP_DIS
-
CLKSEL[2:0]
STBY_YG
READ/
WRITE
-
-
-
-
STBY_XG
STBY_ZG
72
73
114
115
FIFO_COUNTH
FIFO_COUNTL
READ
READ
Y
Y
FIFO_COUNT[12:8]
FIFO_COUNT[7:0]
READ/
WRITE
74
75
116
117
FIFO_R_W
WHO_AM_I
Y
N
FIFO_DATA[7:0]
WHOAMI[7:0]
READ
Table 14. ICG-20330 Register Map
Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register
value.
In the detailed register tables that follow, register names are in capital letters, while register values are in capital
letters and italicized. For example, the GYRO_XOUT_H register (Register 59) contains the 8 most significant
bits, GYRO_XOUT[15:8], of the 16-bit X-Axis Gyroscope measurement, GYRO_XOUT.
The reset value is 0x00 for all registers other than the registers below, also the self-test registers contain pre-
programmed values and will not be 0x00 after reset.
•
•
Register 107 (0x01) Power Management 1
Register 117 (0x92) WHO_AM_I
Document Number: DS-000127
Revision: 1.1
Page 36 of 56
Rev Date: 03/18/2021
ICG-20330
12 REGISTER DESCRIPTIONS
This section describes the function and contents of each register within the ICG-20330.
Note: The device will come up in active mode upon power-up.
12.1 REGISTERS 0 TO 2 – GYROSCOPE SELF-TEST REGISTERS
Register Name: SELF_TEST_X_GYRO, SELF_TEST_Y_GYRO, SELF_TEST_Z_GYRO
Type: READ/WRITE
Register Address: 00, 01, 02 (Decimal); 00, 01, 02 (Hex)
REGISTER
BIT NAME
FUNCTION
The value in this register indicates the self-test
output generated during manufacturing tests. This
value is to be used to check against subsequent
self-test outputs performed by the end user.
SELF_TEST_X_GYRO [7:0] XG_ST_DATA[7:0]
SELF_TEST_Y_GYRO [7:0] YG_ST_DATA[7:0]
SELF_TEST_Z_GYRO [7:0] ZG_ST_DATA[7:0]
The value in this register indicates the self-test
output generated during manufacturing tests. This
value is to be used to check against subsequent
self-test outputs performed by the end user.
The value in this register indicates the self-test
output generated during manufacturing tests. This
value is to be used to check against subsequent
self-test outputs performed by the end user.
The equation to convert self-test codes in OTP to factory self-test measurement is:
ST _OTP = (2620/2FS )*1.01(ST _code−1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is
based on the Self-Test value (ST_ FAC) determined in InvenSense’s factory final test and calculated based
on the following equation:
log(ST _ FAC /(2620 / 2FS ))
ST _ code = round(
) +1
log(1.01)
Document Number: DS-000127
Revision: 1.1
Page 37 of 56
Rev Date: 03/18/2021
ICG-20330
12.2 REGISTER 4 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: XG_OFFS_TC_H
Register Type: READ/WRITE
Register Address: 04 (Decimal); 04 (Hex)
BIT
NAME
FUNCTION
[7:2]
[1:0]
-
Reserved
XG_OFFS_TC_H[9:8] Bits 9 and 8 of the 10-bit offset of X gyroscope (2’s complement)
12.3 REGISTER 5 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: XG_OFFS_TC_L
Type: READ/WRITE
Register Address: 05 (Decimal); 05 (Hex)
BIT
NAME
FUNCTION
[7:0]
XG_OFFS_TC_L[7:0]] Bits 7 to 0 of the 10-bit offset of X gyroscope (2’s complement)
Description:
The temperature compensation (TC) registers are used to reduce gyro offset variation due to
temperature change. The TC feature is always enabled. However, the compensation only
happens when a TC coefficient is programed during factory trim which gets loaded into these
registers at power up or after a DEVICE_RESET. If these registers contain a value of zero,
temperature compensation has no effect on the offset of the chip. The TC registers have a 10-
bit magnitude and sign adjustment in all full scale modes with a resolution of 2.52 mdps/C steps.
If these registers contain a non-zero value after power up, the user may write zeros to them to
see the offset values without TC with temperature variation. Note that doing so may result in
offset values that exceed data sheet “Initial ZRO Tolerance” in other than normal ambient
temperature (~25 °C). The TC coefficients maybe restored by the user with a power up or a
DEVICE_RESET.
The above description also applies to registers 7-8 and 10-11.
Document Number: DS-000127
Revision: 1.1
Page 38 of 56
Rev Date: 03/18/2021
ICG-20330
12.4 REGISTER 07 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: YG_OFFS_TC_H
Register Type: READ/WRITE
Register Address: 07 (Decimal); 07 (Hex)
BIT
NAME
FUNCTION
[7:2]
[1:0]
-
Reserved
YG_OFFS_TC_H[9:8] Bits 9 and 8 of the 10-bit offset of Y gyroscope (2’s complement)
12.5 REGISTER 08 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: YG_OFFS_TC_L
Register Type: READ/WRITE
Register Address: 08 (Decimal); 08 (Hex)
BIT
NAME
FUNCTION
[7:0]
YG_OFFS_TC_L[7:0]] Bits 7 to 0 of the 10-bit offset of Y gyroscope (2’s complement)
12.6 REGISTER 10 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: ZG_OFFS_TC_H
Register Type: READ/WRITE
Register Address: 10 (Decimal); 0A (Hex)
BIT
NAME
FUNCTION
[7:2]
[1:0]
-
Reserved
ZG_OFFS_TC_H[9:8] Bits 9 and 8 of the 10-bit offset of Z gyroscope (2’s complement)
Document Number: DS-000127
Revision: 1.1
Page 39 of 56
Rev Date: 03/18/2021
ICG-20330
12.7 REGISTER 11 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: ZG_OFFS_TC_L
Register Type: READ/WRITE
Register Address: 11 (Decimal); 0B (Hex)
BIT
NAME
FUNCTION
ZG_OFFS_TC_L[7:0]]
[7:0]
Bits 7 to 0 of the 10-bit offset of Z gyroscope (2’s complement)
12.8 REGISTERS 19 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 19 (Decimal); 13 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of X gyroscope (2’s complement).
This register is used to remove DC bias from the sensor output.
The value in this register is added to the gyroscope sensor value
before going into the sensor register.
[7:0]
X_OFFS_USR[15:8]
12.9 REGISTERS 20 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 20 (Decimal); 14 (Hex)
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of X gyroscope (2’s complement).
This register is used to remove DC bias from the sensor output.
The value in this register is added to the gyroscope sensor value
before going into the sensor register.
[7:0]
X_OFFS_USR[7:0]
Document Number: DS-000127
Revision: 1.1
Page 40 of 56
Rev Date: 03/18/2021
ICG-20330
12.10 REGISTERS 21 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 21 (Decimal); 15 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of Y gyroscope (2’s complement).
This register is used to remove DC bias from the sensor output.
The value in this register is added to the gyroscope sensor value
before going into the sensor register.
[7:0]
Y_OFFS_USR[15:8]
12.11 REGISTERS 22 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 22 (Decimal); 16 (Hex)
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of Y gyroscope (2’s complement).
This register is used to remove DC bias from the sensor output.
The value in this register is added to the gyroscope sensor value
before going into the sensor register.
[7:0]
Y_OFFS_USR[7:0]
12.12 REGISTERS 23 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 23 (Decimal); 17 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of Z gyroscope (2’s complement).
This register is used to remove DC bias from the sensor output.
The value in this register is added to the gyroscope sensor value
before going into the sensor register.
[7:0]
Z_OFFS_USR[15:8]
Document Number: DS-000127
Revision: 1.1
Page 41 of 56
Rev Date: 03/18/2021
ICG-20330
12.13 REGISTER 24 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 24 (Decimal); 18 (Hex)
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of Z gyroscope (2’s complement).
This register is used to remove DC bias from the sensor output.
The value in this register is added to the gyroscope sensor value
before going into the sensor register.
[7:0]
Z_OFFS_USR[7:0]
12.14 REGISTER 25 – SAMPLE RATE DIVIDER
Register Name: SMPLRT_DIV
Register Type: READ/WRITE
Register Address: 25 (Decimal); 19 (Hex)
BIT
NAME
FUNCTION
[7:0]
SMPLRT_DIV[7:0]
Divides the internal sample rate (see register CONFIG) to generate the
sample rate that controls sensor data output rate, FIFO sample rate. NOTE:
This register is only effective when FCHOICE_B register bits are 2’b00, and
(0 < DLPF_CFG < 7).
This is the update rate of the sensor register:
SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV)
Where INTERNAL_SAMPLE_RATE = 1kHz
Document Number: DS-000127
Revision: 1.1
Page 42 of 56
Rev Date: 03/18/2021
ICG-20330
12.15 REGISTER 26 – CONFIGURATION
Register Name: CONFIG
Register Type: READ/WRITE
Register Address: 26 (Decimal); 1A (Hex)
BIT
[7]
NAME
FUNCTION
-
Reserved.
[6]
FIFO_MODE
When set to ‘1’, when the FIFO is full, additional writes will not be written to
FIFO.
When set to ‘0’, when the FIFO is full, additional writes will be written to the
FIFO, replacing the oldest data.
[5:3] EXT_SYNC_SET[2:0]
Enables the FSYNC pin data to be sampled.
EXT_SYNC_SET
FSYNC bit location
function disabled
0
1
2
3
4
TEMP_OUT_L[0]
GYRO_XOUT_L[0]
GYRO_YOUT_L[0]
GYRO_ZOUT_L[0]
FSYNC will be latched to capture short strobes. This will be done such that if
FSYNC toggles, the latched value toggles, but won’t toggle again until the new
latched value is captured by the sample rate strobe.
[2:0] DLPF_CFG[2:0]
For the DLPF to be used, FCHOICE_B[1:0] is 2’b00.
See the table below.
The DLPF is configured by DLPF_CFG, when FCHOICE_B [1:0] = 2b’00. The gyroscope and
temperature sensor are filtered according to the value of DLPF_CFG and FCHOICE_B as shown in
the table below.
Temperature
FCHOICE_B
<1> <0>
Gyroscope
Sensor
DLPF_CFG
3-dB
BW
(Hz)
Noise
Rate Delay
3-dB BW
(Hz)
BW (Hz) (kHz) (ms)
X
1
X
X
0
1
2
7
8173
8595.1
3451.0
306.6
177.0
108.6
32
32
8
1
1
0.064
0.11
0.97
2.9
3.9
0.17
4000
4000
4000
188
98
4000
1
0
0
0
0
0
0
0
0
0
3281
250
176
92
3281
3451.0
8
Document Number: DS-000127
Revision: 1.1
Page 43 of 56
Rev Date: 03/18/2021
ICG-20330
12.16 REGISTER 27 – GYROSCOPE CONFIGURATION
Register Name: GYRO_CONFIG
Register Type: READ/WRITE
Register Address: 27 (Decimal); 1B (Hex)
BIT
[7]
[6]
[5]
NAME
XG_ST
YG_ST
ZG_ST
FUNCTION
X Gyro self-test.
Y Gyro self-test.
Z Gyro self-test.
Gyro Full Scale Select:
00 = ±31.25 dps
01= ±62.5 dps
10 = ±125 dps
11= ±250 dps
[4:3]
FS_SEL[1:0]
[2]
-
Reserved.
[1:0]
FCHOICE_B[1:0]
Used to bypass DLPF as shown in table 1 above.
Document Number: DS-000127
Revision: 1.1
Page 44 of 56
Rev Date: 03/18/2021
ICG-20330
12.17 REGISTER 35 – FIFO ENABLE
Register Name: FIFO_EN
Register Type: READ/WRITE
Register Address: 35 (Decimal); 23 (Hex)
BIT
[7]
NAME
FUNCTION
1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate;
If enabled, buffering of data occurs even if data path is in standby.
TEMP_FIFO_EN
0 – Function is disabled.
1 – Write GYRO_XOUT_H and GYRO_XOUT_L to the FIFO at the sample
rate; If enabled, buffering of data occurs even if data path is in standby.
[6]
[5]
[4]
XG_FIFO_EN
YG_FIFO_EN
ZG_FIFO_EN
0 – Function is disabled.
1 – Write GYRO_YOUT_H and GYRO_YOUT_L to the FIFO at the sample
rate; If enabled, buffering of data occurs even if data path is in standby.
0 – Function is disabled.
Note: Enabling any one of the bits corresponding to the Gyros or Temp data
paths, data is buffered into the FIFO even though that data path is not
enabled.
1 – Write GYRO_ZOUT_H and GYRO_ZOUT_L to the FIFO at the sample
rate; If enabled, buffering of data occurs even if data path is in standby.
0 – Function is disabled.
Reserved.
[3]
-
-
[2:0]
Reserved.
Document Number: DS-000127
Revision: 1.1
Page 45 of 56
Rev Date: 03/18/2021
ICG-20330
12.18 REGISTER 54 – FSYNC INTERRUPT STATUS
Register Name: FSYNC_INT
Register Type: READ to CLEAR
Register Address: 54 (Decimal); 36 (Hex)
BIT
[7]
NAME
FUNCTION
This bit automatically sets to 1 when a FSYNC interrupt has been
generated. The bit clears to 0 after the register has been read.
FSYNC_INT
12.19 REGISTER 55 – INT PIN / BYPASS ENABLE CONFIGURATION
Register Name: INT_PIN_CFG
Register Type: READ/WRITE
Register Address: 55 (Decimal); 37 (Hex)
BIT
[7]
NAME
FUNCTION
1 – The logic level for INT pin is active low.
INT_LEVEL
0 – The logic level for INT pin is active high.
1 – INT pin is configured as open drain.
[6]
[5]
[4]
[3]
[2]
INT_OPEN
0 – INT pin is configured as push-pull.
1 – INT pin level held until interrupt status is cleared.
0 – INT pin indicates interrupt pulse’s width is 50 ms.
1 – Interrupt status is cleared if any read operation is performed.
0 – Interrupt status is cleared only by reading INT_STATUS register.
1 – The logic level for the FSYNC pin as an interrupt is active low.
0 – The logic level for the FSYNC pin as an interrupt is active high.
LATCH_INT_EN
INT_RD_CLEAR
FSYNC_INT_LEVEL
FSYNC_INT_MODE_EN
When this bit is equal to 1, the FSYNC pin will trigger an interrupt when
it transitions to the level specified by FSYNC_INT_LEVEL. When this
bit is equal to 0, the FSYNC pin is disabled from causing an interrupt.
Reserved.
[1]
[0]
-
-
Reserved.
Document Number: DS-000127
Revision: 1.1
Page 46 of 56
Rev Date: 03/18/2021
ICG-20330
12.20 REGISTER 56 – INTERRUPT ENABLE
Register Name: INT_ENABLE
Register Type: READ/WRITE
Register Address: 56 (Decimal); 38 (Hex)
BIT
NAME
FUNCTION
‘111’ – Enable WoM interrupt.
[7:5] WOM_EN
‘000’ – Disable WoM interrupt. This is the default setting.
1 – Enables a FIFO buffer overflow to generate an interrupt.
0 – Function is disabled.
[4]
FIFO_OFLOW_EN
[3]
[2]
[1]
[0]
-
Reserved.
GDRIVE_INT_EN
Gyroscope Drive System Ready interrupt enable.
Reserved.
-
DATA_RDY_INT_EN
Data ready interrupt enable.
12.21 REGISTER 58 – INTERRUPT STATUS
Register Name: INT_STATUS
Register Type: READ to CLEAR
Register Address: 58 (Decimal); 3A (Hex)
BIT
[7]
[6]
[5]
NAME
FUNCTION
Reserved.
Reserved.
Reserved.
-
-
-
This bit automatically sets to 1 when a FIFO buffer overflow has been
generated. The bit clears to 0 after the register has been read.
[4]
FIFO_OFLOW_INT
[3]
[2]
[1]
-
Reserved.
GDRIVE_INT
-
Gyroscope Drive System Ready interrupt.
Reserved.
This bit automatically sets to 1 when a Data Ready interrupt is
generated. The bit clears to 0 after the register has been read.
[0]
DATA_RDY_INT
Document Number: DS-000127
Revision: 1.1
Page 47 of 56
Rev Date: 03/18/2021
ICG-20330
12.22 REGISTERS 65 AND 66 – TEMPERATURE MEASUREMENT
Register Name: TEMP_OUT_H
Register Type: READ only
Register Address: 65 (Decimal); 41 (Hex)
BIT
NAME
FUNCTION
High byte of the temperature sensor output.
[7:0] TEMP_OUT[15:8]
Register Name: TEMP_OUT_L
Register Type: READ only
Register Address: 66 (Decimal); 42 (Hex)
BIT
NAME
FUNCTION
Low byte of the temperature sensor output.
TEMP_degC
= ((TEMP_OUT –
[7:0] TEMP_OUT[7:0]
RoomTemp_Offset)/Temp_Sensitivity)
+ 25degC
Document Number: DS-000127
Revision: 1.1
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Rev Date: 03/18/2021
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12.23 REGISTERS 67 TO 72 – GYROSCOPE MEASUREMENTS
Register Name: GYRO_XOUT_H
Register Type: READ only
Register Address: 67 (Decimal); 43 (Hex)
BIT
NAME
FUNCTION
High byte of the X-Axis gyroscope output.
[7:0] GYRO_XOUT[15:8]
Register Name: GYRO_XOUT_L
Register Type: READ only
Register Address: 68 (Decimal); 44 (Hex)
BIT
NAME
FUNCTION
Low byte of the X-Axis gyroscope output.
GYRO_XOUT = Gyro_Sensitivity * X_angular_rate
[7:0] GYRO_XOUT[7:0]
Nominal
FS_SEL = 0
Conditions
Gyro_Sensitivity = 131 LSB/(º/s)
Register Name: GYRO_YOUT_H
Register Type: READ only
Register Address: 69 (Decimal); 45 (Hex)
BIT
NAME
FUNCTION
High byte of the Y-Axis gyroscope output.
[7:0] GYRO_YOUT[15:8]
Register Name: GYRO_YOUT_L
Register Type: READ only
Register Address: 70 (Decimal); 46 (Hex)
BIT
NAME
FUNCTION
Low byte of the Y-Axis gyroscope output.
GYRO_YOUT = Gyro_Sensitivity * Y_angular_rate
[7:0] GYRO_YOUT[7:0]
Nominal
FS_SEL = 0
Conditions
Gyro_Sensitivity = 131 LSB/(º/s)
Document Number: DS-000127
Revision: 1.1
Page 49 of 56
Rev Date: 03/18/2021
ICG-20330
Register Name: GYRO_ZOUT_H
Register Type: READ only
Register Address: 71 (Decimal); 47 (Hex)
BIT
NAME
FUNCTION
High byte of the Z-Axis gyroscope output.
[7:0] GYRO_ZOUT[15:8]
Register Name: GYRO_ZOUT_L
Register Type: READ only
Register Address: 72 (Decimal); 48 (Hex)
BIT
NAME
FUNCTION
Low byte of the Z-Axis gyroscope output.
GYRO_ZOUT = Gyro_Sensitivity * Z_angular_rate
[7:0] GYRO_ZOUT[7:0]
Nominal
FS_SEL = 0
Conditions
Gyro_Sensitivity = 131 LSB/(º/s)
12.24 REGISTER 104 – SIGNAL PATH RESET
Register Name: SIGNAL_PATH_RESET
Register Type: READ/WRITE
Register Address: 104 (Decimal); 68 (Hex)
BIT
NAME
FUNCTION
[7:1]
Reserved.
-
Reset temp digital signal path.
[0]
TEMP_RST
Note: Sensor registers are not cleared. Use SIG_COND_RST to clear
sensor registers.
Document Number: DS-000127
Revision: 1.1
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Rev Date: 03/18/2021
ICG-20330
12.24 REGISTER 106 – USER CONTROL
Register Name: USER_CTRL
Register Type: READ/WRITE
Register Address: 106 (Decimal); 6A (Hex)
BIT
[7]
NAME FUNCTION
-
Reserved.
1 – Enable FIFO operation mode.
[6]
FIFO_EN
0 – Disable FIFO access from serial interface. To disable FIFO writes by
DMA, use FIFO_EN register.
[5]
[4]
[3]
[2]
[1]
[0]
-
Reserved.
1 – Reset I2C Slave module and put the serial interface in SPI mode only.
This bit auto clears after one clock cycle of the internal 20 MHz clock.
I2C_IF_DIS
-
Reserved.
1 – Reset FIFO module. Reset is asynchronous. This bit auto clears after
one clock cycle of the internal 20 MHz clock.
FIFO_RST
-
Reserved
1 – Reset all gyro digital signal path and temp digital signal path. This bit also
clears all the sensor registers.
SIG_COND_RST
Document Number: DS-000127
Revision: 1.1
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Rev Date: 03/18/2021
ICG-20330
12.25 REGISTER 107 – POWER MANAGEMENT 1
Register Name: PWR_MGMT_1
Register Type: READ/WRITE
Register Address: 107 (Decimal); 6B (Hex)
BIT
[7]
NAME
FUNCTION
1 – Reset the internal registers and restores the default settings. The bit
automatically clears to 0 once the reset is done.
DEVICE_RESET
[6]
[5]
SLEEP
-
When set to 1, the chip is set to sleep mode.
Reserved.
When set, the gyro drive and pll circuitry are enabled, but the sense paths
are disabled. This is a low power mode that allows quick enabling of the
gyros.
[4]
[3]
GYRO_STANDBY
TEMP_DIS
When set to 1, this bit disables the temperature sensor.
Code Clock Source
0
1
Internal 20 MHz oscillator
Auto selects the best available clock source – PLL if ready, else
use the Internal oscillator.
2
3
4
5
Auto selects the best available clock source – PLL if ready, else
use the Internal oscillator.
Auto selects the best available clock source – PLL if ready, else
use the Internal oscillator.
[2:0] CLKSEL[2:0]
Auto selects the best available clock source – PLL if ready, else
use the Internal oscillator.
Auto selects the best available clock source – PLL if ready, else
use the Internal oscillator.
6
7
Internal 20 MHz oscillator.
Stops the clock and keeps timing generator in reset.
Note: The default value of CLKSEL[2:0] is 000. It is required that CLKSEL[2:0] be set to 001 to achieve full
gyroscope performance.
Document Number: DS-000127
Revision: 1.1
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Rev Date: 03/18/2021
ICG-20330
12 26REGISTER 108 – POWER MANAGEMENT 2
Register Name: PWR_MGMT_2
Register Type: READ/WRITE
Register Address: 108 (Decimal); 6C (Hex)
BIT
[7]
[6]
[5]
[4]
[3]
NAME
FUNCTION
-
-
-
-
-
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
1 – X gyro is disabled.
0 – X gyro is on.
1 – Y gyro is disabled.
0 – Y gyro is on.
1 – Z gyro is disabled.
0 – Z gyro is on.
[2]
[1]
[0]
STBY_XG
STBY_YG
STBY_ZG
12.27 REGISTER 114 AND 115 – FIFO COUNT REGISTERS
Register Name: FIFO_COUNTH
Register Type: READ Only
Register Address: 114 (Decimal); 72 (Hex)
BIT
NAME
FUNCTION
[7:5]
Reserved.
-
High bits. Count indicates the number of written bytes in the FIFO.
[4:0] FIFO_COUNT[12:8]
Reading this byte latches the data for both FIFO_COUNTH, and
FIFO_COUNTL.
Register Name: FIFO_COUNTL
Register Type: READ Only
Register Address: 115 (Decimal); 73 (Hex)
BIT
NAME
FUNCTION
Low Bits. Count indicates the number of written bytes in the FIFO.
[7:0] FIFO_COUNT[7:0]
Note: Must read FIFO_COUNTH to latch new data for both
FIFO_COUNTH and FIFO_COUNTL.
Document Number: DS-000127
Revision: 1.1
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12.28 REGISTER 116 – FIFO READ WRITE
Register Name: FIFO_R_W
Register Type: READ/WRITE
Register Address: 116 (Decimal); 74 (Hex)
BIT
NAME
FUNCTION
Read/Write command provides Read or Write operation for
the FIFO.
[7:0] FIFO_DATA[7:0]
Description:
This register is used to read and write data from the FIFO buffer.
Data is written to the FIFO in order of register number (from lowest to highest). If all the FIFO enable
flags (see below) are enabled, the contents of registers 59 through 72 will be written in order at the
Sample Rate.
The contents of the sensor data registers (Registers 59 to 72) are written into the FIFO buffer when
their corresponding FIFO enable flags are set to 1 in FIFO_EN (Register 35).
If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is automatically set to 1. This bit
is located in INT_STATUS (Register 58). When the FIFO buffer has overflowed, the oldest data will
be lost and new data will be written to the FIFO unless register 26 CONFIG, bit[6] FIFO_MODE = 1.
If the FIFO buffer is empty, reading register FIFO_DATA will return a unique value of 0xFF until new
data is available. Normal data is precluded from ever indicating 0xFF, so 0xFF gives a trustworthy
indication of FIFO empty.
12.29 REGISTER 117 – WHO AM I
Register Name: WHO_AM_I
Register Type: READ only
Register Address: 117 (Decimal); 75 (Hex)
BIT
NAME
FUNCTION
[7:0] WHOAMI
Register to indicate to user which device is being accessed.
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID.
The default value of the register is 0x92. This is different from the I2C address of the device as seen
on the slave I2C controller by the applications processor. The I2C address of the ICG-20330 is 0x68 or
0x69 depending upon the value driven on AD0 pin.
Document Number: DS-000127
Revision: 1.1
Page 54 of 56
Rev Date: 03/18/2021
ICG-20330
13REVISION HISTORY
REVISION
REVISION DESCRIPTION
DATE
06/15/2016
1.0
1.1
Initial Release
Added Note on page 16; Added Sections 4.17 and 4.18
03/18/2021
Document Number: DS-000127
Revision: 1.1
Page 55 of 56
Rev Date: 03/18/2021
ICG-20330
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InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to
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Document Number: DS-000127
Revision: 1.1
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Rev Date: 03/18/2021
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