ICM-20609 [TDK]
IMU (惯性测量设备);
| 型号： | ICM-20609 |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | IMU (惯性测量设备) |
| 文件： | 总57页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICM-20609
ICM-20609 Datasheet
Revision 1.5
TDK Corporation
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 988–7339
InvenSense reserves the right to change the detail
specifications as may be required to permit
improvements in the design of its products.
Document Number: DS-000106
Revision: 1.5
Rev Date: 03/15/2018
www.invensense.com
ICM-20609
TABLE OF CONTENTS
1.1 Purpose and Scope....................................................................................................................................6
1.2 Product Overview......................................................................................................................................6
1.3 Applications...............................................................................................................................................6
Features ............................................................................................................................................................... 7
2.1 Gyroscope Features ..................................................................................................................................7
2.2 Accelerometer Features............................................................................................................................7
2.3 Additional Features...................................................................................................................................7
2.4 Motion Processing ....................................................................................................................................7
Electrical Characteristics...................................................................................................................................... 8
3.1 Gyroscope Specifications ..........................................................................................................................8
3.2 Accelerometer Specifications....................................................................................................................9
3.3 Electrical Specifications...........................................................................................................................10
3.4 I2C Timing Characterization.....................................................................................................................14
3.5 SPI Timing Characterization ....................................................................................................................15
3.6 Absolute Maximum Ratings ....................................................................................................................16
Applications Information ................................................................................................................................... 17
4.1 Pin Out Diagram and Signal Description .................................................................................................17
4.2 Typical Operating Circuit.........................................................................................................................18
4.3 Bill of Materials for External Components..............................................................................................18
4.4 Block Diagram .........................................................................................................................................19
4.5 Overview .................................................................................................................................................19
4.6 Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ...............................................20
4.7 Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning.........................................20
4.8 Digital Motion Processor.........................................................................................................................20
4.9 I2C and SPI Serial Communications Interfaces ........................................................................................20
2
3
4
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
Self-Test ..............................................................................................................................................22
Clocking...............................................................................................................................................22
Sensor Data Registers .........................................................................................................................23
FIFO.....................................................................................................................................................23
Interrupts............................................................................................................................................23
Digital-Output Temperature Sensor ...................................................................................................23
Bias and LDOs .....................................................................................................................................23
Charge Pump ......................................................................................................................................23
Standard Power Modes ......................................................................................................................23
5
6
Programmable Interrupts .................................................................................................................................. 24
5.1 Wake-on-Motion Interrupt .....................................................................................................................25
Digital Interface ................................................................................................................................................. 26
6.1 I2C and SPI Serial Interfaces ....................................................................................................................26
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ICM-20609
6.2 I2C Interface.............................................................................................................................................26
6.3 I2C Communications Protocol.................................................................................................................26
6.4 I2C Terms .................................................................................................................................................29
6.5 SPI Interface ............................................................................................................................................30
Serial Interface Considerations.......................................................................................................................... 31
7.1 ICM-20609 Supported Interfaces............................................................................................................31
Assembly............................................................................................................................................................ 32
8.1 Orientation of Axes .................................................................................................................................32
8.2 Package Dimensions................................................................................................................................33
Part Number Package Marking.......................................................................................................................... 35
Register Map...................................................................................................................................................... 36
Register Descriptions ......................................................................................................................................... 38
7
8
9
10
11
11.1
Registers 0 to 2 – Gyroscope Self-Test Registers................................................................................38
Registers 13 to 15 – Accelerometer Self-Test Registers .....................................................................38
Registers 19 – Gyro Offset Adjustment Register ................................................................................39
Registers 20 – Gyro Offset Adjustment Register ................................................................................39
Registers 21 – Gyro Offset Adjustment Register ................................................................................39
Registers 22 – Gyro Offset Adjustment Register ................................................................................39
Registers 23 – Gyro Offset Adjustment Register ................................................................................40
Register 24 – Gyro Offset Adjustment Register..................................................................................40
Register 25 – Sample Rate Divider......................................................................................................40
Register 26 – Configuration ................................................................................................................41
Register 27 – Gyroscope Configuration..............................................................................................41
Register 28 – Accelerometer Configuration .......................................................................................42
Register 29 – Accelerometer Configuration 2.....................................................................................42
Register 30 – Low Power Mode Configuration ...................................................................................43
Register 32 – X-Axis Wake-on Motion Threshold (Accelerometer) ....................................................45
Register 33 – Y-Axis Wake-on Motion Threshold (Accelerometer) ....................................................45
Register 34 – Z-Axis Wake-on Motion Threshold (Accelerometer) ....................................................45
Register 35 – FIFO Enable ...................................................................................................................46
Register 54 – FSYNC Interrupt Status..................................................................................................46
Register 55 – INT/DRDY Pin / Bypass Enable Configuration ...............................................................46
Register 56 – Interrupt Enable............................................................................................................47
Register 57 – DMP Interrupt Status....................................................................................................47
Register 58 – Interrupt Status.............................................................................................................47
Registers 59 to 64 – Accelerometer Measurements ..........................................................................48
Registers 65 and 66 – Temperature Measurement............................................................................48
Registers 67 to 72 – Gyroscope Measurements.................................................................................49
Register 104 – Signal Path Reset.........................................................................................................50
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
11.15
11.16
11.17
11.18
11.19
11.20
11.21
11.22
11.23
11.24
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ICM-20609
11.25
11.26
11.27
11.28
11.29
11.30
11.31
11.32
Register 105 – Accelerometer Intelligence Control............................................................................50
Register 106 – User Control................................................................................................................51
Register 107 – Power Management 1 ................................................................................................51
Register 108 – Power Management 2 ................................................................................................52
Register 114 and 115 – FIFO Count Registers.....................................................................................52
Register 116 – FIFO Read Write..........................................................................................................53
Register 117 – Who Am I ....................................................................................................................53
Registers 119, 120, 122, 123, 125, 126 Accelerometer Offset Registers............................................53
12
13
Reference........................................................................................................................................................... 55
Document Information ...................................................................................................................................... 56
13.1
Revision History ..................................................................................................................................56
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Rev Date: 03/15/2018
Document Number: DS-000106
Revision: 1.5
ICM-20609
TABLE OF FIGURES
Figure 1. I2C Bus Timing Diagram.............................................................................................................................................................14
Figure 2. SPI Bus Timing Diagram.............................................................................................................................................................15
Figure 3. Pin out Diagram for ICM-20609 3.0x3.0x0.75mm LGA .............................................................................................................17
Figure 4. ICM-20609 LGA Application Schematic.....................................................................................................................................18
Figure 5. ICM-20609 Block Diagram.........................................................................................................................................................19
Figure 6. ICM-20609 Solution Using I2C Interface....................................................................................................................................21
Figure 7. ICM-20609 Solution Using SPI Interface ...................................................................................................................................22
Figure 8. START and STOP Conditions......................................................................................................................................................26
Figure 9. Acknowledge on the I2C Bus .....................................................................................................................................................27
Figure 10. Complete I2C Data Transfer.....................................................................................................................................................28
Figure 11. Typical SPI Master/Slave Configuration ..................................................................................................................................30
Figure 12. I/O Levels and Connections.....................................................................................................................................................31
Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation ....................................................................................................32
TABLE OF TABLES
Table 1. Gyroscope Specifications .............................................................................................................................................................8
Table 2. Accelerometer Specifications.......................................................................................................................................................9
Table 3. D.C. Electrical Characteristics.....................................................................................................................................................10
Table 4. A.C. Electrical Characteristics .....................................................................................................................................................12
Table 5. Other Electrical Specifications....................................................................................................................................................13
Table 6. I2C Timing Characteristics...........................................................................................................................................................14
Table 7. SPI Timing Characteristics (8MHz Operation) ............................................................................................................................15
Table 8. Absolute Maximum Ratings .......................................................................................................................................................16
Table 9. Signal Descriptions .....................................................................................................................................................................17
Table 10. Bill of Materials ........................................................................................................................................................................18
Table 11. Standard Power Modes for ICM-20609....................................................................................................................................23
Table 12. Table of Interrupt Sources........................................................................................................................................................24
Table 13. Serial Interface .........................................................................................................................................................................26
Table 14. I2C Terms ..................................................................................................................................................................................29
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Rev Date: 03/15/2018
Document Number: DS-000106
Revision: 1.5
ICM-20609
1.1 PURPOSE AND SCOPE
This document is a product specification, providing a description, specifications, and design related information on the ICM-20609™
MotionTracking device. The device is housed in a small 3x3x0.75mm 16-pin LGA package.
1.2 PRODUCT OVERVIEW
The ICM-20609 is a 6-axis MotionTracking device that combines a 3-axis gyroscope, a 3-axis accelerometer, and a Digital Motion
Processor™ (DMP) in a small 3x3x0.75mm (16-pin LGA) package. It also features a 4Kbyte FIFO that can lower the traffic on the serial
bus interface, and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-
power mode. ICM-20609, with its 6-axis integration, on-chip DMP, and run-time calibration firmware, enables manufacturers to
eliminate the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal
motion performance.
The gyroscope has a programmable full-scale range of ±250, ±500, ±1000, and ±2000 degrees/sec. The accelerometer has a user-
programmable accelerometer full-scale range of ±2g, ±4g, ±8g, and ±16g. Factory-calibrated initial sensitivity of both sensors
reduces production-line calibration requirements.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and
programmable interrupts. The device features I2C and SPI serial interfaces, a VDD operating range of 1.71 to 3.45V, and a separate
digital IO supply, VDDIO from 1.71V to 3.45V. Communication with all registers of the device is performed using either I2C at 400kHz
or SPI at 8MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion
CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of
3x3x0.75mm (16-pin LGA), to provide a very small yet high-performance low-cost package. The device provides high robustness by
supporting 10,000g shock reliability.
1.3 APPLICATIONS
•
•
•
•
•
•
Mobile phones and tablets
Drones
Handset and portable gaming
Motion-based game controllers
3D remote controls for Internet connected DTVs and set top boxes, 3D mice
Wearable sensors for health, fitness and sports
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Rev Date: 03/15/2018
Document Number: DS-000106
Revision: 1.5
ICM-20609
2 FEATURES
2.1 GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICM-20609 includes a wide range of features:
•
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-scale range of ±250, ±500,
±1000, and ±2000°/sec and integrated 16-bit ADCs
Digitally-programmable low-pass filter
Low-power gyroscope operation
Factory calibrated sensitivity scale factor
Self-test
•
•
•
•
2.2 ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in ICM-20609 includes a wide range of features:
•
Digital-output X-, Y-, and Z-axis accelerometer with a programmable full scale range of ±2g, ±4g, ±8g and ±16g and integrated
16-bit ADCs
•
•
•
User-programmable interrupts
Wake-on-motion interrupt for low power operation of applications processor
Self-test
2.3 ADDITIONAL FEATURES
The ICM-20609 includes the following additional features:
•
•
•
•
•
•
•
•
•
•
Smallest and thinnest LGA package for portable devices: 3x3x0.75mm (16-pin LGA)
Minimal cross-axis sensitivity between the accelerometer and gyroscope axes
4Kbyte FIFO buffer enables the applications processor to read the data in bursts
Digital-output temperature sensor
User-programmable digital filters for gyroscope, accelerometer, and temp sensor
10,000 g shock tolerant
400kHz Fast Mode I2C for communicating with all registers
8MHz SPI serial interface for communicating with all registers
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
2.4 MOTION PROCESSING
•
Internal Digital Motion Processing™ (DMP™) engine supports advanced MotionProcessing and low power functions such as
gesture recognition using programmable interrupts.
•
•
DMP operation is possible in low-power gyroscope and low-power accelerometer modes.
Low-power pedometer functionality allows the host processor to sleep while the DMP maintains the step count.
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ICM-20609
3 ELECTRICAL CHARACTERISTICS
3.1 GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
GYROSCOPE SENSITIVITY
FS_SEL=0
Full-Scale Range
±250
±500
±1000
±2000
16
3
3
3
3
3
3
3
3
3
2
1
1
1
°/s
°/s
FS_SEL=1
FS_SEL=2
FS_SEL=3
°/s
°/s
Gyroscope ADC Word Length
Sensitivity Scale Factor
bits
FS_SEL=0
131
LSB/(°/s)
LSB/(°/s)
LSB/(°/s)
LSB/(°/s)
%
FS_SEL=1
65.5
32.8
16.4
FS_SEL=2
FS_SEL=3
Sensitivity Scale Factor Tolerance
Sensitivity Scale Factor Variation Over Temperature
Nonlinearity
Component-level , 25°C
-40°C to +85°C
Best fit straight line; 25°C
-2
-3
+2
+3
%
±0.1
±2
%
Cross-Axis Sensitivity
%
ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance
25°C
-10
+10
2
1
°/s
ZRO Variation Over Temperature
-40°C to +85°C
-0.1
+0.1
°/s/ºC
GYROSCOPE NOISE PERFORMANCE (FS_SEL=0)
Noise Spectral Density
0.006
27
0.1
29
1
2
°/s/√Hz
Gyroscope Mechanical Frequencies
Low Pass Filter Response
Gyroscope Start-Up Time
25
kHz
Programmable Range
From Sleep mode
5
250
Hz
ms
Hz
Hz
3
1
1
1
35
Standard (duty-cycled) mode
Low-Noise (active) mode
3.91
4
500
8000
Output Data Rate
Table 1. Gyroscope Specifications
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Tested in production.
3. Guaranteed by design.
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Document Number: DS-000106
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ICM-20609
3.2 ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ACCELEROMETER SENSITIVITY
AFS_SEL=0
AFS_SEL=1
±2
±4
g
g
3
3
Full-Scale Range
AFS_SEL=2
±8
g
3
AFS_SEL=3
±16
g
3
ADC Word Length
Output in two’s complement format
AFS_SEL=0
16
bits
3
3
3
16,384
8,192
LSB/g
LSB/g
AFS_SEL=1
Sensitivity Scale Factor
AFS_SEL=2
4,096
2,048
LSB/g
LSB/g
%
3
3
2
AFS_SEL=3
Initial Tolerance
Component-level , 25°C
-2
-2
+2
+2
Sensitivity Change vs. Temperature
-40°C to +85°C AFS_SEL=0
Best Fit Straight Line
%
1
Nonlinearity
-0.25
+0.25
%
%
1
1
Cross-Axis Sensitivity
±2
ZERO-G OUTPUT
Post-Solder, all axes, 25ºC
Initial Tolerance
-100
-1.5
+100
+1.5
mg
1
1
-40°C to +85°C
Zero-G Level Change vs. Temperature
mg/ºC
NOISE PERFORMANCE
µg/√Hz
210
218
Noise Spectral Density
1
3
Low Pass Filter Response
Programmable Range
5
Hz
Intelligence Function Increment
4
20
30
mg/LSB
ms
ms
Hz
Hz
3
1
1
From Sleep mode
From Cold Start, 1ms VDD ramp
Standard (duty-cycled) mode
Low-Noise (active) mode
Accelerometer Startup Time
Output Data Rate
0.24
4
500
4000
1
Table 2. Accelerometer Specifications
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Tested in production.
3. Guaranteed by design.
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ICM-20609
3.3 ELECTRICAL SPECIFICATIONS
3.3.1 D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLY VOLTAGES
VDD
1.71
1.71
1.8
1.8
3.45
3.45
V
V
1
1
VDDIO
SUPPLY CURRENTS & BOOT TIME
Normal Mode
6-axis Gyroscope + Accelerometer
3
mA
mA
µA
1
1
1
3-axis Gyroscope
2.6
390
3-axis Accelerometer, 4kHz ODR
Accelerometer Low -Power Mode
Gyroscope Low-Power Mode
100Hz ODR, 1x averaging
100Hz ODR, 1x averaging
57
µA
2
2
1.6
mA
6-Axis Low-Power Mode (Gyroscope
Low-Power Mode; Accelerometer Low-
Noise Mode)
100Hz ODR, 1x averaging
1.9
6
mA
µA
2
1
Full-Chip Sleep Mode
TEMPERATURE RANGE
Specified Temperature Range
Performance parameters are not applicable
beyond Specified Temperature Range
-40
+85
°C
1
Table 3. D.C. Electrical Characteristics
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Based on simulation.
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ICM-20609
3.3.2 A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLIES
Supply Ramp Time (TRAMP
)
Monotonic ramp. Ramp rate is
10% to 90% of the final value
0.01
100
ms
1
TEMPERATURE SENSOR
Operating Range
Room Temperature Offset
Sensitivity
Ambient
25°C
Untrimmed
-40
85
°C
°C
LSB/°C
1
1
1
0
326.8
POWER-ON RESET
Supply Ramp Time (TRAMP
)
Valid power-on RESET
From power-up
From sleep
0.01
100
100
5
ms
ms
ms
1
1
1
11
Start-up time for register read/write
SA0 = 0
SA0 = 1
1101000
1101001
I2C ADDRESS
DIGITAL INPUTS (FSYNC, SA0, SPC, SDI, CS)
VIH, High-Level Input Voltage
VIL, Low-Level Input Voltage
CI, Input Capacitance
0.7*VDDIO
V
V
0.3*VDDIO
1
1
< 10
pF
DIGITAL OUTPUT (SDO, INT)
VOH, High- Level Output Voltage
VOL1, Low-Level Output Voltage
VOL.INT, INT Low-Level Output Voltage
RLOAD=1MΩ;
RLOAD=1MΩ;
0.9*VDDIO
V
V
V
0.1*VDDIO
0.1
OPEN=1, 0.3mA sink
Current
Output Leakage Current
tINT, INT Pulse Width
OPEN=1
100
50
nA
µs
LATCH_INT_EN=0
I2C I/O (SCL, SDA)
-0.5V
VIL, Low-Level Input Voltage
VIH, High-Level Input Voltage
0.3*VDDIO
V
V
V
V
0.7*VDDIO
VDDIO + 0.5V
Vhys, Hysteresis
0.1*VDDIO
VOL, Low-Level Output Voltage
IOL, Low-Level Output Current
3mA sink current
0
0.4
1
VOL=0.4V
VOL=0.6V
3
6
mA
mA
Output Leakage Current
100
nA
ns
tof, Output Fall Time from VIHmax to VILmax
Cb bus capacitance in pf
20+0.1Cb
300
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ICM-20609
INTERNAL CLOCK SOURCE
FCHOICE_B=1,2,3
SMPLRT_DIV=0
FCHOICE_B=0;
DLPFCFG=0 or 7
SMPLRT_DIV=0
FCHOICE_B=0;
32
8
kHz
kHz
2
2
Sample Rate
DLPFCFG=1,2,3,4,5,6;
SMPLRT_DIV=0
CLK_SEL=0, 6 or gyro inactive;
25°C
1
kHz
%
2
1
-5
+5
Clock Frequency Initial Tolerance
CLK_SEL=1,2,3,4,5 and gyro
active; 25°C
-1
-10
-1
+1
+10
+1
%
%
%
1
1
1
CLK_SEL=0,6 or gyro inactive
CLK_SEL=1,2,3,4,5 and gyro
active
Frequency Variation over Temperature
Table 4. A.C. Electrical Characteristics
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Guaranteed by design.
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ICM-20609
3.3.3 Other Electrical Specifications
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SERIAL INTERFACE
Low Speed Characterization
High Speed Characterization
100 ±10%
1
kHz
1
SPI Operating Frequency, All Registers
Read/Write
8
MHz
1, 2
Modes 0
and 3
SPI Modes
All registers, Fast-mode
400
100
kHz
kHz
1
1
I2C Operating Frequency
All registers, Standard-mode
Table 5. Other Electrical Specifications
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. SPI clock duty cycle between 45% and 55% should be used for 8-MHz operation.
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ICM-20609
3.4 I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERS
CONDITIONS
I2C FAST-MODE
MIN
TYP
MAX
UNITS
NOTES
I2C TIMING
fSCL, SCL Clock Frequency
400
kHz
µs
1
1
tHD.STA, (Repeated) START Condition Hold Time
0.6
tLOW, SCL Low Period
1.3
0.6
µs
µs
µs
µs
ns
ns
ns
µs
1
1
1
1
1
1
1
1
tHIGH, SCL High Period
tSU.STA, Repeated START Condition Setup Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
0.6
0
100
Cb bus cap. from 10 to 400pF
Cb bus cap. from 10 to 400pF
20+0.1Cb
20+0.1Cb
0.6
300
300
tf, SDA and SCL Fall Time
tSU.STO, STOP Condition Setup Time
tBUF, Bus Free Time Between STOP and START
Condition
1.3
µs
1
Cb, Capacitive Load for each Bus Line
tVD.DAT, Data Valid Time
< 400
pF
µs
µs
1
1
1
0.9
0.9
tVD.ACK, Data Valid Acknowledge Time
Table 6. I2C Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
t
f
tSU.DAT
t
r
SDA
SCL
70%
30%
70%
30%
continued below at
9th clock cycle
A
t
f
t
r
t
VD.DAT
70%
30%
70%
30%
tHD.DAT
t
HD.STA
1/fSCL
t
LOW
1st clock cycle
S
t
HIGH
tBUF
SDA
SCL
70%
30%
A
tSU.STO
tSU.STA
tHD.STA
t
VD.ACK
70%
30%
9th clock cycle
S
P
Sr
Figure 1. I2C Bus Timing Diagram
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ICM-20609
3.5 SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
NOTES
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING
fSPC, SPC Clock Frequency
tLOW, SPC Low Period
tHIGH, SPC High Period
tSU.CS, CS Setup Time
tHD.CS, CS Hold Time
8
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
2
2
56
56
2
63
3
tSU.SDI, SDI Setup Time
tHD.SDI, SDI Hold Time
tVD.SDO, SDO Valid Time
tHD.SDO, SDO Hold Time
tDIS.SDO, SDO Output Disable Time
tFall, SPC Fall Time
7
Cload = 20pF
Cload = 20pF
40
6
20
6.5
6.5
tRise, SPC Rise Time
Table 7. SPI Timing Characteristics (8MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
2. Based on other parameter values
CS
70%
30%
tFall
tRise
t
HD;CS
t
SU;CS
70%
t
HIGH
1/fCLK
SPC
30%
t
SU;SDI
t
HD;SDI
tLOW
70%
30%
SDI
LSB IN
MSB IN
t
DIS;SDO
t
VD;SDO
t
HD;SDO
70%
30%
SDO
MSB OUT
LSB OUT
Figure 2. SPI Bus Timing Diagram
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3.6 ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for
extended periods may affect device reliability.
PARAMETER
RATING
-0.5V to +4V
Supply Voltage, VDD
Supply Voltage, VDDIO
REGOUT
-0.5V to +4V
-0.5V to 2V
Input Voltage Level (SA0, FSYNC, SCL, SDA)
Acceleration (Any Axis, unpowered)
Operating Temperature Range
-0.5V to VDD + 0.5V
10,000g for 0.2ms
-40°C to +85°C
-40°C to +125°C
Storage Temperature Range
2kV (HBM);
250V (MM)
Electrostatic Discharge (ESD) Protection
Latch-up
JEDEC Class II (2),125°C
±100mA
Table 8. Absolute Maximum Ratings
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ICM-20609
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
PIN NUMBER
PIN NAME
VDDIO
SCL/SPC
SDA/SDI
SA0/SDO
CS
PIN DESCRIPTION
1
2
Digital I/O supply voltage
I2C serial clock (SCL); SPI serial clock (SPC)
I2C serial data (SDA); SPI serial data input (SDI)
I2C slave address LSB (SA0); SPI serial data output (SDO)
Chip select (0 = SPI mode; 1 = I2C mode)
Interrupt digital output (totem pole or open-drain)
Reserved. Do not connect.
3
4
5
6
INT
7
RESV
8
FSYNC
RESV
Synchronization digital input (optional). Connect to GND if unused.
Reserved. Connect to GND.
9
10
11
12
13
14
15
RESV
Reserved. Connect to GND.
RESV
Reserved. Connect to GND.
RESV
Reserved. Connect to GND.
GND
Connect to GND
REGOUT
RESV
Regulator filter capacitor connection
Reserved. Connect to GND.
16
VDD
Power Supply
Table 9. Signal Descriptions
Note: Power up with SCL/SPC and CS pins held low is not a supported use case. In case this power up approach is used, software
reset is required using the PWR_MGMT_1 register, prior to initialization.
16 15 14
13
12
11
10
9
VDDIO
SCL/SPC
SDA/SDI
SA0/SDO
CS
1
2
3
4
5
GND
+Z
RESV
RESV
RESV
RESV
ICM-20609
ICM
-
20609
+Y
+X
6
7
8
LGA Package (Top View)
16-pin, 3mm x 3mm x 0.75mm
Typical Footprint and thickness
Orientation of Axes of Sensitivity and Polarity of Rotation
Figure 3. Pin out Diagram for ICM-20609 3.0x3.0x0.75mm LGA
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ICM-20609
4.2 TYPICAL OPERATING CIRCUIT
1.8 – 3.3VDC
VDD
C4, 2.2 µF
C2, 0.1 µF
REGOUT
16 15 14
C1, 0.47 µF
GND
VDDIO
1.8 – 3.3 VDC
13
12
11
10
9
1
2
3
4
5
RESV
C3, 10 nF
SCL
SCL/SPC
SDA/SDI
RESV
RESV
ICM-20609
SDA
SA0/SDO
CS
AD0
VDDIO
RESV
6
7
8
Figure 4. ICM-20609 LGA Application Schematic
Note: I2C lines are open drain and pullup resistors (e.g. 10kΩ) are required.
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS
COMPONENT
LABEL
C1
SPECIFICATION
QUANTITY
REGOUT Capacitor
X7R, 0.47µF ±10%
X7R, 0.1µF ±10%
X7R, 2.2µF ±10%
X7R, 10nF ±10%
1
1
1
1
C2
VDD Bypass Capacitors
VDDIO Bypass Capacitor
C4
C3
Table 10. Bill of Materials
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ICM-20609
4.4 BLOCK DIAGRAM
ICM-20609
INT
Self
test
X Accel
Y Accel
ADC
ADC
Interrupt
Status
Register
CS
Self
test
Slave I2C and
SPI Serial
Interface
SA0 / SDO
SCL / SPC
SDA / SDI
FIFO
Self
test
Z Accel
X Gyro
ADC
ADC
User & Config
Registers
FSYNC
Self
test
Sensor
Registers
Self
test
Y Gyro
Z Gyro
ADC
ADC
Digital Motion
Processor
(DMP)
Self
test
Temp Sensor
ADC
Bias & LDOs
Charge
Pump
VDD
GND
REGOUT
Figure 5. ICM-20609 Block Diagram
4.5 OVERVIEW
The ICM-20609 is comprised of the following key blocks and functions:
•
•
•
•
•
•
•
•
•
•
•
•
•
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
Digital Motion Processor (DMP) engine
Primary I2C and SPI serial communications interfaces
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes
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4.6 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20609 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-, and Z- Axes.
When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff.
The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage
is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro
sensors may be digitally programmed to ±250, ±500, ±1000, or ±2000 degrees per second (dps). The ADC sample rate is
programmable from 8,000 samples per second, down to 3.9 samples per second, and user-selectable low-pass filters enable a wide
range of cut-off frequencies.
4.7 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20609’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis induces
displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially. The ICM-20609’s
architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed
on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale factor is calibrated at the
factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs.
The full scale range of the digital output can be adjusted to ±2g, ±4g, ±8g, or ±16g.
4.8 DIGITAL MOTION PROCESSOR
The embedded Digital Motion Processor (DMP) offloads computation of motion processing algorithms from the host processor. The
DMP acquires data from the accelerometer and gyroscope, and processes the data. The resulting data can be read from the FIFO.
The DMP has access to one of the external pins, which can be used for generating interrupts.
The purpose of the DMP is to offload both timing requirements and processing power from the host processor. Typically, motion
processing algorithms should be run at a high rate, often around 200Hz, in order to provide accurate results with low latency. This is
required even if the application updates at a much lower rate; for example, a low power user interface may update as slowly as 5Hz,
but the motion processing should still run at 200Hz. The DMP can be used to minimize power, simplify timing, simplify the software
architecture, and save valuable MIPS on the host processor for use in applications.
DMP operation is possible in low-power gyroscope and low-power accelerometer modes.
4.9 I2C AND SPI SERIAL COMMUNICATIONS INTERFACES
The ICM-20609 communicates to a system processor using either a SPI or an I2C serial interface. The ICM-20609 always acts as a
slave when communicating to the system processor. The LSB of the I2C slave address is set by pin 4 (SA0).
4.9.1 ICM-20609 Solution Using I2C Interface
In the figure below, the system processor is an I2C master to the ICM-20609.
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ICM-20609
Interrupt
Status
INT
Register
ICM-20609
SA0
SCL
VDDIO or GND
Slave I2C
or SPI
SCL
SDA
System
Processor
Serial
Interface
SDA
FIFO
User & Config
Registers
Digital
Motion
Processor
(DMP)
Sensor
Register
Factory
Calibration
Bias & LDOs
VDD
GND
REGOUT
Figure 6. ICM-20609 Solution Using I2C Interface
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ICM-20609
4.9.2 ICM-20609 Solution Using SPI Interface
In the figure below, the system processor is an SPI master to the ICM-20609. Pins 2, 3, 4, and 5 are used to support the SPC, SDI,
SDO, and CS signals for SPI communications.
Interrupt
INT
Status
Register
nCS
CS
ICM-20609
SDO
SDI
Slave I2C
or SPI
Serial
Interface
System
Processor
SPC
SDI
SPC
SDO
FIFO
Config
Register
Digital
Motion
Processor
(DMP)
Sensor
Register
Factory
Calibration
Bias & LDOs
VDD
GND
REGOUT
Figure 7. ICM-20609 Solution Using SPI Interface
4.10 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can
be activated by means of the gyroscope and accelerometer self-test registers (registers 27 and 28).
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is
used to observe the self-test response.
The self-test response is defined as follows:
Self-test response = Sensor output with self-test enabled – Sensor output with self-test disabled
When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed self-
test. When the self-test response exceeds the min/max values, the part is deemed to have failed self-test. It is recommended to use
InvenSense MotionApps software for executing self-test.
4.11 CLOCKING
The ICM-20609 has a flexible clocking scheme, allowing a variety of internal clock sources to be used for the internal synchronous
circuitry. This synchronous circuitry includes the signal conditioning and ADCs, the DMP, and various control circuits and registers.
An on-chip PLL provides flexibility in the allowable inputs for generating this clock.
Allowable internal sources for generating the internal clock are:
a) An internal relaxation oscillator
b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available source
The only setting supporting specified performance in all modes is option b). It is recommended that option b) be used.
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4.12 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They are read-only
registers, and are accessed via the serial interface. Data from these registers may be read anytime.
4.13 FIFO
The ICM-20609 contains a 4Kbyte FIFO register that is accessible via the Serial Interface. The FIFO configuration register determines
which data is written into the FIFO. Possible choices include gyro data, accelerometer data, temperature readings, and FSYNC input.
A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The FIFO register supports burst reads. The
interrupt function may be used to determine when new data is available.
The ICM-20609 allows FIFO read in low-power accelerometer mode.
4.14 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT pin
configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are (1)
Clock generator locked to new reference oscillator (used when switching clock sources); (2) new data is available to be read (from
the FIFO and Data registers); (3) accelerometer event interrupts; (4) DMP, (5) FIFO overflow. The interrupt status can be read from
the Interrupt Status register.
4.15 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICM-20609 die temperature. The readings from the ADC can be
read from the FIFO or the Sensor Data registers.
4.16 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the ICM-20609. Its two
inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed by a capacitor at REGOUT.
For further details on the capacitor, please refer to the Bill of Materials for External Components.
4.17 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
4.18 STANDARD POWER MODES
The following table lists the user-accessible power modes for ICM-20609.
MODE NAME
GYRO
Off
Drive On
Off
Off
Duty-Cycled
On
ACCEL
Off
Off
Duty-Cycled
DMP
Off
Off
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
1
2
3
4
5
6
7
8
Sleep Mode
Standby Mode
Accelerometer Low-Power Mode
Accelerometer Low-Noise Mode
Gyroscope Low-Power Mode
Gyroscope Low-Noise Mode
6-Axis Low-Noise Mode
On
Off
Off
On
On
On
6-Axis Low-Power Mode
Duty-Cycled
Table 11. Standard Power Modes for ICM-20609
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ICM-20609
5 PROGRAMMABLE INTERRUPTS
The ICM-20609 has a programmable interrupt system which can generate an interrupt signal on the INT pin. Status flags indicate the
source of an interrupt. Interrupt sources may be enabled and disabled individually.
INTERRUPT NAME
Motion Detection
MODULE
Motion
FIFO Overflow
Data Ready
DMP
FIFO
Sensor Registers
DMP
Table 12. Table of Interrupt Sources
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ICM-20609
5.1 WAKE-ON-MOTION INTERRUPT
The ICM-20609 provides motion detection capability. A qualifying motion sample is one where the high passed sample from any axis
has an absolute value exceeding a user-programmable threshold. The following steps explain how to configure the Wake-on-Motion
Interrupt.
Step 1: Ensure that Accelerometer is running
•
•
In PWR_MGMT_1 register (0x6B) set CYCLE = 0, SLEEP = 0, and GYRO_STANDBY = 0
In PWR_MGMT_2 register (0x6C) set STBY_XA = STBY_YA = STBY_ZA = 0, and STBY_XG = STBY_YG = STBY_ZG = 1
Step 2: Accelerometer Configuration
In ACCEL_CONFIG2 register (0x1D) set ACCEL_FCHOICE_B = 0 and A_DLPF_CFG[2:0] = 1 (b001)
•
Step 3: Enable Motion Interrupt
•
In INT_ENABLE register (0x38) set WOM_INT_EN = 111 to enable motion interrupt
Step 4: Set Motion Threshold
•
•
•
Set the motion threshold for X-axis in ACCEL_WOM_X_THR register (0x20)
Set the motion threshold for Y-axis in ACCEL_WOM_Y_THR register (0x21)
Set the motion threshold for Z-axis in ACCEL_WOM_Z_THR register (0x22)
Step 5: Enable Accelerometer Hardware Intelligence
In ACCEL_INTEL_CTRL register (0x69) set ACCEL_INTEL_EN = ACCEL_INTEL_MODE = 1; Ensure that bit 0 is set to 0.
•
Step 6: Set Frequency of Wake-Up
•
In SMPLRT_DIV register (0x19) set SMPLRT_DIV[7:0] = 3.9 Hz – 500 Hz
Step 7: Enable Cycle Mode (Accelerometer Low-Power Mode)
•
In PWR_MGMT_1 register (0x6B) set CYCLE = 1
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ICM-20609
6 DIGITAL INTERFACE
6.1 I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICM-20609 can be accessed using either I2C at 400 kHz or SPI at 8MHz. SPI operates in four-
wire mode.
PIN NUMBER
PIN NAME
VDDIO
PIN DESCRIPTION
1
4
2
3
Digital I/O supply voltage.
SA0 / SDO
SCL / SPC
SDA / SDI
I2C Slave Address LSB (SA0); SPI serial data output (SDO)
I2C serial clock (SCL); SPI serial clock (SPC)
I2C serial data (SDA); SPI serial data input (SDI)
Table 13. Serial Interface
Note:
To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration bit.
Setting this bit should be performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write”
in Section 6.3.
For further information regarding the I2C_IF_DIS bit, please refer to sections 11 and 12 of this document.
6.2 I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-
directional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the
slave address on the bus, and the slave device with the matching address acknowledges the master.
The ICM-20609 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA
and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the ICM-20609 is b110100X which is 7 bits long. The LSB bit of the 7 bit address is determined by the logic level
on pin SA0. This allows two ICM-20609s to be connected to the same I2C bus. When used in this configuration, the address of one of
the devices should be b1101000 (pin SA0 is logic low) and the address of the other should be b1101001 (pin SA0 is logic high).
6.3 I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW
transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP
condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
P
START condition
STOP condition
Figure 8. START and STOP Conditions
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ICM-20609
Data Format / Acknowledge
I2C data bytes are defined to be 8 bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte
transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master,
while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the
acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL
LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line
(refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM
MASTER
1
2
8
9
clock pulse for
acknowledgement
START
condition
Figure 9. Acknowledge on the I2C Bus
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ICM-20609
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8th bit, the
read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the
master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be
followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of
the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line.
However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP
condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take
place when SCL is low, with the exception of start and stop conditions.
SDA
SCL
1 – 7
8
9
1 – 7
8
9
1 – 7
8
9
S
P
START
STOP
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
condition
condition
Figure 10. Complete I2C Data Transfer
To write the internal ICM-20609 registers, the master transmits the start condition (S), followed by the I2C address and the write bit
(0). At the 9th clock cycle (when the clock is high), the ICM-20609 acknowledges the transfer. Then the master puts the register
address (RA) on the bus. After the ICM-20609 acknowledges the reception of the register address, the master puts the register data
onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple
bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ICM-
20609 automatically increments the register address and loads the data to the appropriate register. The following figures show
single and two-byte write sequences.
Single-Byte Write Sequence
Master
Slave
S
AD+W
RA
DATA
DATA
P
ACK
ACK
ACK
ACK
ACK
Burst Write Sequence
Master
Slave
S
AD+W
RA
DATA
P
ACK
ACK
To read the internal ICM-20609 registers, the master sends a start condition, followed by the I2C address and a write bit, and then
the register address that is going to be read. Upon receiving the ACK signal from the ICM-20609, the master transmits a start signal
followed by the slave address and read bit. As a result, the ICM-20609 sends an ACK signal and the data. The communication ends
with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high
at the 9th clock cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
RA
RA
S
AD+R
AD+R
NACK
P
ACK
ACK
ACK
ACK
ACK
DATA
Burst Read Sequence
Master
Slave
S
AD+W
S
ACK
NACK
P
ACK DATA
DATA
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6.4 I2C TERMS
SIGNAL DESCRIPTION
S
AD
W
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
Write bit (0)
R
Read bit (1)
ACK
Acknowledge: SDA line is low while the SCL line is high at the 9th clock
cycle
NACK
RA
Not-Acknowledge: SDA line stays high at the 9th clock cycle
ICM-20609 internal register address
DATA
P
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 14. I2C Terms
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ICM-20609
6.5 SPI INTERFACE
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The ICM-20609 always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SPC), the Serial Data Output (SDO) and the Serial Data Input (SDI) are shared
among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring
that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines
to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SPC
3. Data should be transitioned on the falling edge of SPC
4. The maximum frequency of SPC is 8MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the
SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit
and indicates the Read (1) or Write (0) operation. The following 7 bits contain the Register Address. In cases of multiple-
byte Read/Writes, data is two or more bytes:
SPI Address format
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
SPI Data format
MSB
LSB
D7
D6 D5 D4 D3 D2 D1 D0
6. Supports Single or Burst Read/Writes.
Figure 11. Typical SPI Master/Slave Configuration
SPC
SDI
SPI Master
SPI Slave 1
SDO
CS
CS1
CS2
SPC
SDI
SDO
CS
SPI Slave 2
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ICM-20609
7 SERIAL INTERFACE CONSIDERATIONS
7.1 ICM-20609 SUPPORTED INTERFACES
The ICM-20609 supports I2C communications on its serial interface.
The ICM-20609’s I/O logic levels are set to be VDDIO.
The figure below depicts a sample circuit of ICM-20609. It shows the relevant logic levels and voltage connections.
VDDIO
VDD_IO
(0V - VDDIO)
SYSTEM BUS
System
Processor IO
VDD
VDDIO
VDD
(0V - VDDIO)
INT
SDA
SCL
(0V - VDDIO)
(0V - VDDIO)
(0V - VDDIO)
SYNC
VDDIO
ICM-20609
VDDIO
(0V, VDDIO)
SA0
Figure 12. I/O Levels and Connections
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ICM-20609
8 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS) gyros packaged in
LGA package.
8.1 ORIENTATION OF AXES
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the
figure.
+Z
+Y
+Z
ICM
-
+Y
20609
+X
+X
Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation
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ICM-20609
8.2 PACKAGE DIMENSIONS
16 Lead LGA (3x3x0.75) mm NiAu pad finish
Page 33 of 57
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ICM-20609
DIMENSIONS IN MILLIMETERS
NOM
SYMBOLS
MIN
MAX
Total Thickness
Substrate Thickness
Mold Thickness
A
A1
A2
0.7
0.75
0.105
0.63
0.8
REF
REF
D
E
2.9
2.9
0.2
0.3
3
3
3.1
3.1
0.3
Body Size
Lead Width
Lead Length
W
0.25
L
e
n
0.35
0.5
16
2
0.4
BSC
Lead Pitch
Lead Count
D1
E1
SD
BSC
BSC
BSC
Edge Ball Center to Center
Body Center to Contact Ball
1
---
SE
b
---
---
---
---
---
---
BSC
---
Ball Width
Ball Diameter
Ball Opening
Ball Pitch
Ball Count
Pre-Solder
---
---
e1
n1
---
---
Package Edge Tolerance
aaa
bbb
ddd
eee
fff
0.1
0.2
0.08
---
Mold Flatness
Coplanarity
Ball Offset (Package)
Ball Offset (Ball)
---
Lead Edge to Package Edge
M
0.01
0.06
0.11
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ICM-20609
9 PART NUMBER PACKAGE MARKING
The part number package marking for ICM-20609 devices is summarized below:
PART NUMBER
ICM-20609
PART NUMBER PACKAGE MARKING
IC2609
TOP VIEW
IC2609
XXXXXX
YYWW
Part Number
Lot Traceability Code
YY = Year Code
WW = Work Week
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ICM-20609
10 REGISTER MAP
The following table lists the register map for the ICM-20609.
Accessible
(writable) in
Sleep Mode
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00
01
02
0D
0E
0F
13
14
15
16
17
18
19
00
01
02
13
14
15
19
20
21
22
23
24
25
SELF_TEST_X_GYRO
SELF_TEST_Y_GYRO
SELF_TEST_Z_GYRO
SELF_TEST_X_ACCEL
SELF_TEST_Y_ACCEL
SELF_TEST_Z_ACCEL
XG_OFFS_USRH
XG_OFFS_USRL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N
N
N
N
N
N
N
N
N
N
N
N
N
N
XG_ST_DATA[7:0]
YG_ST_DATA[7:0]
ZG_ST_DATA[7:0]
XA_ST_DATA[7:0]
YA_ST_DATA[7:0]
ZA_ST_DATA[7:0]
X_OFFS_USR [15:8]
X_OFFS_USR [7:0]
Y_OFFS_USR [15:8]
Y_OFFS_USR [7:0]
Z_OFFS_USR [15:8]
Z_OFFS_USR [7:0]
SMPLRT_DIV[7:0]
YG_OFFS_USRH
YG_OFFS_USRL
ZG_OFFS_USRH
ZG_OFFS_USRL
SMPLRT_DIV
FIFO_
MODE
1A
26
CONFIG
R/W
-
EXT_SYNC_SET[2:0]
DLPF_CFG[2:0]
1B
1C
27
28
GYRO_CONFIG
ACCEL_CONFIG
R/W
R/W
N
N
XG_ST
XA_ST
YG_ST
YA_ST
ZG_ST
ZA_ST
FS_SEL [1:0]
-
FCHOICE_B[1:0]
ACCEL_FS_SEL[1:0]
-
ACCEL_FCHOI
CE_B
1D
1E
29
30
ACCEL_CONFIG 2
LP_MODE_CFG
R/W
R/W
N
N
-
DEC2_CFG
A_DLPF_CFG
GYRO_CYCL
E
G_AVGCFG[2:0]
-
20
21
22
32
33
34
ACCEL_WOM_X_THR
ACCEL_WOM_Y_THR
ACCEL_WOM_Z_THR
R/W
R/W
R/W
N
N
N
WOM_X_TH[7:0]
WOM_Y_TH[7:0]
WOM_Z_TH[7:0]
TEMP
_FIFO_EN
ACCEL_FIFO_
23
36
35
54
FIFO_EN
R/W
R/C
N
N
XG_FIFO_EN
-
YG_FIFO_EN
-
ZG_FIFO_EN
-
-
-
-
-
-
-
EN
FSYNC_INT
FSYNC_INT
INT_LEVEL
-
FSYNC
_INT_MODE_
EN
LATCH
_INT_EN
INT_RD
_CLEAR
FSYNC_INT_L
EVEL
37
55
INT_PIN_CFG
R/W
Y
INT_OPEN
-
-
FIFO
_OFLOW
_EN
GDRIVE_INT_
EN
DATA_RDY_I
NT_EN
38
39
3A
56
57
58
INT_ENABLE
DMP_INT_STATUS
INT_STATUS
R/W
R/C
R/C
Y
N
N
WOM_INT_EN[7:5]
-
-
DMP_INT_EN
-
DMP_INT[5:0]
FIFO
_OFLOW
_INT
DATA
_RDY_INT
WOM_INT[7:5]
GDRIVE_INT
DMP_INT
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
59
60
61
62
63
64
65
66
67
68
69
70
71
72
ACCEL_XOUT_H
ACCEL_XOUT_L
ACCEL_YOUT_H
ACCEL_YOUT_L
ACCEL_ZOUT_H
ACCEL_ZOUT_L
TEMP_OUT_H
TEMP_OUT_L
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N
N
N
N
N
N
N
N
N
N
N
N
N
N
ACCEL_XOUT_H[15:8]
ACCEL_XOUT_L[7:0]
ACCEL_YOUT_H[15:8]
ACCEL_YOUT_L[7:0]
ACCEL_ZOUT_H[15:8]
ACCEL_ZOUT_L[7:0]
TEMP_OUT[15:8]
TEMP_OUT[7:0]
GYRO_XOUT_H
GYRO_XOUT_L
GYRO_YOUT_H
GYRO_YOUT_L
GYRO_ZOUT_H
GYRO_ZOUT_L
GYRO_XOUT[15:8]
GYRO_XOUT[7:0]
GYRO_YOUT[15:8]
GYRO_YOUT[7:0]
GYRO_ZOUT[15:8]
GYRO_ZOUT[7:0]
ACCEL
_RST
TEMP
_RST
68
104
SIGNAL_PATH_RESET
R/W
N
-
-
-
-
-
-
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ICM-20609
Accessible
(writable) in
Sleep Mode
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ACCEL_INTE
L_EN
ACCEL_INTEL
_MODE
69
6A
6B
105
106
107
ACCEL_INTEL_CTRL
USER_CTRL
R/W
R/W
R/W
N
N
Y
-
I2C_IF
_DIS
FIFO
_RST
SIG_COND
_RST
DMP_EN
FIFO_EN
SLEEP
-
DMP_RST
-
DEVICE_RES
ET
ACCEL_CYCL
E
GYRO_
STANDBY
PWR_MGMT_1
TEMP_DIS
STBY_ZA
CLKSEL[2:0]
STBY_YG
6C
72
73
74
75
77
78
7A
7B
7D
7E
108
114
115
116
117
119
120
122
123
125
126
PWR_MGMT_2
FIFO_COUNTH
FIFO_COUNTL
FIFO_R_W
R/W
R
Y
FIFO_LP_EN
DMP_LP_DIS
-
STBY_XA
STBY_YA
STBY_XG
STBY_ZG
N
N
N
N
N
N
N
N
N
N
FIFO_COUNT[12:8]
R
FIFO_COUNT[7:0]
R/W
R
FIFO_DATA[7:0]
WHOAMI[7:0]
XA_OFFS [14:7]
WHO_AM_I
XA_OFFSET_H
XA_OFFSET_L
YA_OFFSET_H
YA_OFFSET_L
ZA_OFFSET_H
ZA_OFFSET_L
R/W
R/W
R/W
R/W
R/W
R/W
XA_OFFS [6:0]
YA_OFFS [14:7]
YA_OFFS [6:0]
ZA_OFFS [14:7]
ZA_OFFS [6:0]
-
-
-
Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register value.
In the detailed register tables that follow, register names are in capital letters, while register values are in capital letters and
italicized. For example, the ACCEL_XOUT_H register (Register 59) contains the 8 most significant bits, ACCEL_XOUT[15:8], of the 16-
bit X-Axis accelerometer measurement, ACCEL_XOUT.
The reset value is 0x00 for all registers other than the registers below, also the self-test registers contain pre-programmed values
and will not be 0x00 after reset.
•
•
Register 107 (0x40) Power Management 1
Register 117 (0xA6) WHO_AM_I
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ICM-20609
11 REGISTER DESCRIPTIONS
This section describes the function and contents of each register within the ICM-20609.
Note: The device will come up in sleep mode upon power-up.
11.1 REGISTERS 0 TO 2 – GYROSCOPE SELF-TEST REGISTERS
Register Name: SELF_TEST_X_GYRO, SELF_TEST_Y_GYRO, SELF_TEST_Z_GYRO
Type: READ/WRITE
Register Address: 00, 01, 02 (Decimal); 00, 01, 02 (Hex)
REGISTER
BIT
NAME
FUNCTION
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check
against subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check
against subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check
against subsequent self-test outputs performed by the end user.
SELF_TEST_X_GYRO
[7:0] XG_ST_DATA[7:0]
[7:0] YG_ST_DATA[7:0]
[7:0] ZG_ST_DATA[7:0]
SELF_TEST_Y_GYRO
SELF_TEST_Z_GYRO
The equation to convert self-test codes in OTP to factory self-test measurement is:
ST _OTP = (2620/ 2FS )*1.01(ST _code−1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value
(ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation:
log(ST _ FAC /(2620/ 2FS ))
ST _ code = round(
) +1
log(1.01)
11.2 REGISTERS 13 TO 15 – ACCELEROMETER SELF-TEST REGISTERS
Register Name: SELF_TEST_X_ACCEL, SELF_TEST_Y_ACCEL, SELF_TEST_Z_ACCEL
Type: READ/WRITE
Register Address: 13, 14, 15 (Decimal); 0D, 0E, 0F (Hex)
REGISTER
BITS
NAME
FUNCTION
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be used
to check against subsequent self-test outputs performed by
the end user.
SELF_TEST_X_ACCEL
[7:0]
XA_ST_DATA[7:0]
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be used
to check against subsequent self-test outputs performed by
the end user.
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be used
to check against subsequent self-test outputs performed by
the end user.
SELF_TEST_Y_ACCEL
SELF_TEST_Z_ACCEL
[7:0]
[7:0]
YA_ST_DATA[7:0]
ZA_ST_DATA[7:0]
The equation to convert self-test codes in OTP to factory self-test measurement is:
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ICM-20609
ST _OTP = (2620/ 2FS )*1.01(ST _code−1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value
(ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation:
log(ST _ FAC /(2620/ 2FS ))
ST _ code = round(
) +1
log(1.01)
11.3 REGISTERS 19 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 19 (Decimal); 13 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of X gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
X_OFFS_USR[15:8]
11.4 REGISTERS 20 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 20 (Decimal); 14 (Hex)
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of X gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
X_OFFS_USR[7:0]
11.5 REGISTERS 21 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 21 (Decimal); 15 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of Y gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
Y_OFFS_USR[15:8]
11.6 REGISTERS 22 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 22 (Decimal); 16 (Hex)
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ICM-20609
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of Y gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
Y_OFFS_USR[7:0]
11.7 REGISTERS 23 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 23 (Decimal); 17 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of Z gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
Z_OFFS_USR[15:8]
11.8 REGISTER 24 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 24 (Decimal); 18 (Hex)
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of Z gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
Z_OFFS_USR[7:0]
11.9 REGISTER 25 – SAMPLE RATE DIVIDER
Register Name: SMPLRT_DIV
Register Type: READ/WRITE
Register Address: 25 (Decimal); 19 (Hex)
BIT
[7:0]
NAME
SMPLRT_DIV[7:0]
FUNCTION
Divides the internal sample rate (see register CONFIG) to generate the sample
rate that controls sensor data output rate, FIFO sample rate. NOTE: This register
is only effective when FCHOICE_B register bits are 2’b00, and (0 < DLPF_CFG < 7).
This is the update rate of the sensor register:
SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV)
Where INTERNAL_SAMPLE_RATE = 1kHz
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ICM-20609
11.10 REGISTER 26 – CONFIGURATION
Register Name: CONFIG
Register Type: READ/WRITE
Register Address: 26 (Decimal); 1A (Hex)
BIT
[7]
[6]
NAME
FIFO_MODE
FUNCTION
Always set to 0
-
When set to ‘1’, when the FIFO is full, additional writes will not be written to FIFO.
When set to ‘0’, when the FIFO is full, additional writes will be written to the FIFO,
replacing the oldest data.
[5:3] EXT_SYNC_SET[2:0]
Enables the FSYNC pin data to be sampled.
EXT_SYNC_SET
FSYNC bit location
function disabled
TEMP_OUT_L[0]
GYRO_XOUT_L[0]
GYRO_YOUT_L[0]
GYRO_ZOUT_L[0]
ACCEL_XOUT_L[0]
ACCEL_YOUT_L[0]
ACCEL_ZOUT_L[0]
0
1
2
3
4
5
6
7
FSYNC will be latched to capture short strobes. This will be done such that if FSYNC
toggles, the latched value toggles, but won’t toggle again until the new latched value
is captured by the sample rate strobe.
[2:0] DLPF_CFG[2:0]
For the DLPF to be used, FCHOICE_B[1:0] is 2’b00.
See the table below.
The DLPF is configured by DLPF_CFG, when FCHOICE_B [1:0] = 2b’00. The gyroscope and temperature sensor are filtered
according to the value of DLPF_CFG and FCHOICE_B as shown in the table below.
Temperature
FCHOICE_B
Gyroscope
Sensor
DLPF_CFG
3-dB BW Noise BW
Rate
<1>
<0>
3-dB BW (Hz)
(Hz)
8173
3281
250
176
92
41
20
10
5
(Hz)
8595.1
3451.0
306.6
177.0
108.6
59.0
30.5
15.6
8.0
3451.0
(kHz)
32
32
8
1
1
1
1
1
1
X
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
X
X
0
1
2
3
4
5
6
7
4000
4000
4000
188
98
42
20
10
5
3281
8
4000
11.11REGISTER 27 – GYROSCOPE CONFIGURATION
Register Name: GYRO_CONFIG
Register Type: READ/WRITE
Register Address: 27 (Decimal); 1B (Hex)
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ICM-20609
BIT
[7]
[6]
[5]
NAME
FUNCTION
XG_ST
YG_ST
ZG_ST
X Gyro self-test
Y Gyro self-test
Z Gyro self-test
Gyro Full Scale Select:
00 = ±250dps
01= ±500dps
[4:3]
FS_SEL[1:0]
10 = ±1000dps
11 = ±2000dps
Reserved
[2]
-
[1:0]
FCHOICE_B[1:0]
Used to bypass DLPF as shown in table 1 above.
11.12REGISTER 28 – ACCELEROMETER CONFIGURATION
Register Name: ACCEL_CONFIG
Register Type: READ/WRITE
Register Address: 28 (Decimal); 1C (Hex)
BIT
[7]
[6]
[5]
NAME
FUNCTION
XA_ST
YA_ST
ZA_ST
X Accel self-test
Y Accel self-test
Z Accel self-test
Accel Full Scale Select:
±2g (00), ±4g (01), ±8g (10), ±16g (11)
Reserved
[4:3]
[2:0]
ACCEL_FS_SEL[1:0]
-
11.13REGISTER 29 – ACCELEROMETER CONFIGURATION 2
Register Name: ACCEL_CONFIG2
Register Type: READ/WRITE
Register Address: 29 (Decimal); 1D (Hex)
BIT
NAME
FUNCTION
[7:6]
-
Reserved
Averaging filter settings for Low Power Accelerometer mode:
0 = Average 4 samples
[5:4]
DEC2_CFG[1:0]
1 = Average 8 samples
2 = Average 16 samples
3 = Average 32 samples
[3]
[2:0]
ACCEL_FCHOICE_B
A_DLPF_CFG
Used to bypass DLPF as shown in the table below.
Accelerometer low pass filter setting as shown in the table below.
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ICM-20609
Accelerometer Data Rates and Bandwidths (Low-Noise Mode)
Accelerometer
ACCEL_FCHOICE_B
A_DLPF_CFG
3-dB BW Noise BW
Rate
(Hz)
1046.0
218.1
218.1
99.0
44.8
21.2
10.2
5.1
(Hz)
1100.0
235.0
235.0
121.3
61.5
31.0
15.5
7.8
441.6
(kHz)
1
0
0
0
0
0
0
0
0
X
0
1
2
3
4
5
6
7
4
1
1
1
1
1
1
1
1
420.0
The data output rate of the DLPF filter block can be further reduced by a factor of 1/(1+SMPLRT_DIV), where SMPLRT_DIV is an 8-bit
integer. Following is a small subset of ODRs that are configurable for the accelerometer in the low-noise mode in this manner (Hz):
3.91, 7.81, 15.63, 31.25, 62.50, 125, 250, 500, 1K.
The following table lists the accelerometer filter bandwidths, noise, and current consumption available in the low-power mode of
operation. In the low-power mode of operation, the accelerometer is duty-cycled.
ACCEL_FCHOICE_B
A_DLPF_CFG
1
x
0
7
0
7
0
7
0
7
DEC2_CFG
x
0
1
2
3
Averages
Ton (ms)
Noise BW (Hz)
Noise (mg) TYP based on
250µg/√Hz
1x
1.084
1100.0
4x
1.84
441.6
8x
2.84
235.4
16x
4.84
121.3
32x
8.84
61.5
8.3
5.3
3.8
2.8
2.0
ODR
SMPLRT_DIV
(Hz)
Current Consumption (µA) TYP
255
127
63
31
15
7
3.9
7.8
8.4
9.8
9.4
11.9
17.0
27.1
47.2
87.5
168.1
329.3
10.8
14.7
22.5
38.2
69.4
13.6
20.3
33.7
60.4
113.9
220.9
19.2
31.4
55.9
104.9
202.8
N/A
15.6
31.3
62.5
125.0
250.0
500.0
12.8
18.7
30.4
57.4
100.9
194.9
132.0
257.0
3
1
N/A
N/A
11.14 REGISTER 30 – LOW POWER MODE CONFIGURATION
Register Name: LP_MODE_CFG
Register Type: READ/WRITE
Register Address: 30 (Decimal); 1E (Hex)
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BIT
[7]
NAME
GYRO_CYCLE
FUNCTION
When set to ‘1’ low-power gyroscope mode is enabled. Default
setting is ‘0’
Averaging filter configuration for low-power gyroscope mode.
Default setting is ‘000’
Reserved
[6:4]
[3:0]
G_AVGCFG[2:0]
-
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To operate in gyroscope low-power mode or 6-axis low-power mode, GYRO_CYCLE should be set to ‘1.’ Gyroscope filter
configuration is determined by G_AVGCFG[2:0] that sets the averaging filter configuration. It is not dependent on DLPF_CFG[2:0].
The following table shows some example configurations for gyroscope low power mode.
FCHOICE_B
G_AVGCFG
0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
Averages
Ton (ms)
Noise BW (Hz)
Noise (dps) TYP based on
0.008º/s/√Hz
1x
1.73
650.8
2x
2.23
407.1
4x
3.23
224.2
8x
5.23
117.4
16x
9.23
60.2
32x
17.23
30.6
64x
33.23
15.6
128x
65.23
8.0
0.20
0.16
0.12
0.09
0.06
0.04
0.03
0.02
ODR
SMPLRT_DIV
(Hz)
Current Consumption (mA) TYP
255
99
64
32
19
9
7
4
3
2
3.9
10.0
15.4
30.3
1.3
1.3
1.4
1.4
1.5
1.6
1.7
1.9
2.1
2.3
2.9
1.3
1.3
1.4
1.4
1.5
1.7
1.8
2.1
2.3
2.6
1.3
1.4
1.4
1.5
1.6
1.9
2.0
2.5
2.7
1.3
1.4
1.5
1.6
1.8
2.2
2.5
1.4
1.5
1.6
1.8
2.1
3.0
1.4
1.6
1.8
2.2
2.8
1.5
1.9
2.2
1.8
2.5
N/A
N/A
50.0
100.0
125.0
200.0
250.0
333.3
500.0
N/A
N/A
N/A
N/A
1
N/A
11.15REGISTER 32 – X-AXIS WAKE-ON MOTION THRESHOLD (ACCELEROMETER)
Register Name: ACCEL_WOM_X_THR
Register Type: READ/WRITE
Register Address: 32 (Decimal); 20 (Hex)
BIT
NAME
FUNCTION
[7:0]
WOM_X_TH[7:0]
Wake on Motion Interrupt threshold for X-axis accelerometer.
11.16REGISTER 33 – Y-AXIS WAKE-ON MOTION THRESHOLD (ACCELEROMETER)
Register Name: ACCEL_WOM_Y_THR
Register Type: READ/WRITE
Register Address: 33 (Decimal); 21 (Hex)
BIT
NAME
FUNCTION
[7:0]
WOM_Y_TH[7:0]
Wake on Motion Interrupt threshold for Y-axis accelerometer.
11.17REGISTER 34 – Z-AXIS WAKE-ON MOTION THRESHOLD (ACCELEROMETER)
Register Name: ACCEL_WOM_Z_THR
Register Type: READ/WRITE
Register Address: 34 (Decimal); 22 (Hex)
BIT
NAME
FUNCTION
[7:0]
WOM_Z_TH[7:0]
Wake on Motion Interrupt threshold for Z-axis accelerometer.
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11.15REGISTER 35 – FIFO ENABLE
Register Name: FIFO_EN
Register Type: READ/WRITE
Register Address: 35 (Decimal); 23 (Hex)
NAME
BIT
[7]
FUNCTION
1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate; If
enabled, buffering of data occurs even if data path is in standby.
0 – Function is disabled
1 – Write GYRO_XOUT_H and GYRO_XOUT_L to the FIFO at the sample rate; If
enabled, buffering of data occurs even if data path is in standby.
0 – Function is disabled
TEMP_FIFO_EN
XG_FIFO_EN
[6]
[5]
[4]
1 – Write GYRO_YOUT_H and GYRO_YOUT_L to the FIFO at the sample rate; If
enabled, buffering of data occurs even if data path is in standby.
0 – Function is disabled
NOTE: Enabling any one of the bits corresponding to the Gyros or Temp data
paths, data is buffered into the FIFO even though that data path is not
enabled.
1 – Write GYRO_ZOUT_H and GYRO_ZOUT_L to the FIFO at the sample rate; If
enabled, buffering of data occurs even if data path is in standby.
0 – function is disabled
YG_FIFO_EN
ZG_FIFO_EN
1 – Write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L,
ACCEL_ZOUT_H, and ACCEL_ZOUT_L to the FIFO at the sample rate;
0 – Function is disabled
[3]
ACCEL_FIFO_EN
-
[2:0]
Reserved
11.16REGISTER 54 – FSYNC INTERRUPT STATUS
Register Name: FSYNC_INT
Register Type: READ to CLEAR
Register Address: 54 (Decimal); 36 (Hex)
BIT
[7]
NAME
FUNCTION
This bit automatically sets to 1 when a FSYNC interrupt has been generated.
The bit clears to 0 after the register has been read.
FSYNC_INT
11.17REGISTER 55 – INT/DRDY PIN / BYPASS ENABLE CONFIGURATION
Register Name: INT_PIN_CFG
Register Type: READ/WRITE
Register Address: 55 (Decimal); 37 (Hex)
BIT
[7]
NAME
FUNCTION
1 – The logic level for INT/DRDY pin is active low.
0 – The logic level for INT/DRDY pin is active high.
1 – INT/DRDY pin is configured as open drain.
0 – INT/DRDY pin is configured as push-pull.
1 – INT/DRDY pin level held until interrupt status is cleared.
0 – INT/DRDY pin indicates interrupt pulse’s width is 50us.
1 – Interrupt status is cleared if any read operation is performed.
0 – Interrupt status is cleared only by reading INT_STATUS register
1 – The logic level for the FSYNC pin as an interrupt is active low.
0 – The logic level for the FSYNC pin as an interrupt is active high.
INT_LEVEL
INT_OPEN
[6]
[5]
[4]
[3]
LATCH_INT_EN
INT_RD_CLEAR
FSYNC_INT_LEVEL
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BIT
[2]
NAME
FUNCTION
1 – The FSYNC pin will trigger an interrupt when it transitions to the level
FSYNC_INT_MODE_EN
specified by FSYNC_INT_LEVEL.
0 – The FSYNC pin is disabled from causing an interrupt.
Reserved
[1]
[0]
-
-
Always set to 0
11.18REGISTER 56 – INTERRUPT ENABLE
Register Name: INT_ENABLE
Register Type: READ/WRITE
Register Address: 56 (Decimal); 38 (Hex)
BIT
NAME
FUNCTION
111 – Enable WoM interrupt on accelerometer.
000 – Disable WoM interrupt on accelerometer.
[7:5]
WOM_INT_EN[7:5]
1 – Enables a FIFO buffer overflow to generate an interrupt.
0 – Function is disabled.
[4]
FIFO_OFLOW_EN
[3]
[2]
[1]
[0]
-
Reserved
GDRIVE_INT_EN
DMP_INT_EN
DATA_RDY_INT_EN
Gyroscope Drive System Ready interrupt enable
DMP interrupt enable
Data ready interrupt enable
11.19REGISTER 57 – DMP INTERRUPT STATUS
Register Name: DMP_INT_STATUS
Register Type: READ to CLEAR
Register Address: 57 (Decimal); 39 (Hex)
BIT
[7:6]
[5:0]
NAME
FUNCTION
-
Reserved
DMP interrupts
DMP_INT
11.20REGISTER 58 – INTERRUPT STATUS
Register Name: INT_STATUS
Register Type: READ to CLEAR
Register Address: 58 (Decimal); 3A (Hex)
BIT
NAME
FUNCTION
Accelerometer WoM interrupt status. Cleared on Read.
111 – WoM interrupt on accelerometer
[7:5]
WOM_INT
This bit automatically sets to 1 when a FIFO buffer overflow has been
generated. The bit clears to 0 after the register has been read.
Reserved.
Gyroscope Drive System Ready interrupt
DMP interrupt
[4]
FIFO_OFLOW_INT
[3]
[2]
[1]
-
GDRIVE_INT
DMP_INT
This bit automatically sets to 1 when a Data Ready interrupt is generated. The
bit clears to 0 after the register has been read.
[0]
DATA_RDY_INT
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11.21REGISTERS 59 TO 64 – ACCELEROMETER MEASUREMENTS
Register Name: ACCEL_XOUT_H
Register Type: READ only
Register Address: 59 (Decimal); 3B (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_XOUT_H[15:8]
High byte of accelerometer x-axis data.
Register Name: ACCEL_XOUT_L
Register Type: READ only
Register Address: 60 (Decimal); 3C (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_XOUT_L[7:0]
Low byte of accelerometer x-axis data.
Register Name: ACCEL_YOUT_H
Register Type: READ only
Register Address: 61 (Decimal); 3D (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_YOUT_H[15:8]
High byte of accelerometer y-axis data.
Register Name: ACCEL_YOUT_L
Register Type: READ only
Register Address: 62 (Decimal); 3E (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_YOUT_L[7:0]
Low byte of accelerometer y-axis data.
Register Name: ACCEL_ZOUT_H
Register Type: READ only
Register Address: 63 (Decimal); 3F (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_ZOUT_H[15:8]
High byte of accelerometer z-axis data.
Register Name: ACCEL_ZOUT_L
Register Type: READ only
Register Address: 64 (Decimal); 40 (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_ZOUT_L[7:0]
Low byte of accelerometer z-axis data.
11.22REGISTERS 65 AND 66 – TEMPERATURE MEASUREMENT
Register Name: TEMP_OUT_H
Register Type: READ only
Register Address: 65 (Decimal); 41 (Hex)
BIT
NAME
FUNCTION
[7:0]
TEMP_OUT[15:8]
High byte of the temperature sensor output
Register Name: TEMP_OUT_L
Register Type: READ only
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Register Address: 66 (Decimal); 42 (Hex)
BIT
NAME
FUNCTION
Low byte of the temperature sensor output
TEMP_degC
= ((TEMP_OUT –
RoomTemp_Offset)/Temp_Sensitivity) +
[7:0]
TEMP_OUT[7:0]
25degC
11.23REGISTERS 67 TO 72 – GYROSCOPE MEASUREMENTS
Register Name: GYRO_XOUT_H
Register Type: READ only
Register Address: 67 (Decimal); 43 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_XOUT[15:8]
High byte of the X-Axis gyroscope output
Register Name: GYRO_XOUT_L
Register Type: READ only
Register Address: 68 (Decimal); 44 (Hex)
BIT NAME
FUNCTION
Low byte of the X-Axis gyroscope output
GYRO_XOUT = Gyro_Sensitivity * X_angular_rate
[7:0] GYRO_XOUT[7:0]
Nominal
FS_SEL = 0
Conditions
Gyro_Sensitivity = 131 LSB/(º/s)
Register Name: GYRO_YOUT_H
Register Type: READ only
Register Address: 69 (Decimal); 45 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_YOUT[15:8]
High byte of the Y-Axis gyroscope output
Register Name: GYRO_YOUT_L
Register Type: READ only
Register Address: 70 (Decimal); 46 (Hex)
BIT NAME
FUNCTION
Low byte of the Y-Axis gyroscope output
[7:0] GYRO_YOUT[7:0]
GYRO_YOUT = Gyro_Sensitivity * Y_angular_rate
Nominal
FS_SEL = 0
Conditions
Gyro_Sensitivity = 131 LSB/(º/s)
Register Name: GYRO_ZOUT_H
Register Type: READ only
Register Address: 71 (Decimal); 47 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_ZOUT[15:8]
High byte of the Z-Axis gyroscope output
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Register Name: GYRO_ZOUT_L
Register Type: READ only
Register Address: 72 (Decimal); 48 (Hex)
11.24
BIT
NAME
FUNCTION
Low byte of the Z-Axis gyroscope output
GYRO_ZOUT
=
Nominal
Conditions
Gyro_Sensitivity *
Z_angular_rate
FS_SEL = 0
Gyro_Sensitivity = 131
LSB/(º/s)
[7:0]
GYRO_ZOUT[7:0]
REGISTER 104 – SIGNAL PATH RESET
Register Name: SIGNAL_PATH_RESET
Register Type: READ/WRITE
Register Address: 104 (Decimal); 68 (Hex)
NAME
BIT
FUNCTION
[7:2]
Reserved
-
Reset accel digital signal path. Note: Sensor registers are not cleared. Use
SIG_COND_RST to clear sensor registers.
Reset temp digital signal path. Note: Sensor registers are not cleared. Use
SIG_COND_RST to clear sensor registers.
[1]
[0]
ACCEL_RST
TEMP_RST
11.25 REGISTER 105 – ACCELEROMETER INTELLIGENCE CONTROL
Register Name: ACCEL_INTEL_CTRL
Register Type: READ/WRITE
Register Address: 105 (Decimal); 69 (Hex)
BIT
[7]
NAME
ACCEL_INTEL_EN
FUNCTION
This bit enables the Wake-on-Motion detection logic
0 – Do not use
[6]
ACCEL_INTEL_MODE
1 – Compare the current sample with the previous sample
[5:0]
Reserved
-
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11.26 REGISTER 106 – USER CONTROL
Register Name: USER_CTRL
Register Type: READ/WRITE
Register Address: 106 (Decimal); 6A (Hex)
BIT
[7]
NAME
DMP_EN
FUNCTION
Enable DMP.
1 – Enable FIFO operation mode.
[6]
FIFO_EN
0 – Disable FIFO access from serial interface. To disable FIFO writes by DMA, use
FIFO_EN register. To disable possible FIFO writes from DMP, disable the DMP.
Reserved
1 – Disable I2C Slave module and put the serial interface in SPI mode only.
Reset DMP.
[5]
[4]
[3]
-
I2C_IF_DIS
DMP_RST
1 – Reset FIFO module. Reset is asynchronous. This bit auto clears after one clock
cycle of the internal 20MHz clock.
Reserved
1 – Reset all gyro digital signal path, accel digital signal path, and temp digital signal
path. This bit also clears all the sensor registers.
[2]
[1]
[0]
FIFO_RST
-
SIG_COND_RST
11.27 REGISTER 107 – POWER MANAGEMENT 1
Register Name: PWR_MGMT_1
Register Type: READ/WRITE
Register Address: 107 (Decimal); 6B (Hex)
BIT
[7]
NAME
FUNCTION
1 – Reset the internal registers and restores the default settings. The bit
automatically clears to 0 once the reset is done.
DEVICE_RESET
1 – The chip is set to sleep mode.
[6]
SLEEP
Note: The default value is 1; the chip comes up in Sleep mode
When set to 1, and SLEEP and STANDBY are not set to 1, the chip will cycle between
sleep and taking a single accelerometer sample at a rate determined by
SMPLRT_DIV
NOTE: When all accelerometer axes are disabled via PWR_MGMT_2 register bits
and cycle is enabled, the chip will wake up at the rate determined by the respective
registers above, but will not take any samples.
[5]
ACCEL_CYCLE
When set, the gyro drive and pll circuitry are enabled, but the sense paths are
disabled. This is a low power mode that allows quick enabling of the gyros.
When set to 1, this bit disables the temperature sensor.
[4]
[3]
GYRO_STANDBY
TEMP_DIS
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ICM-20609
BIT
NAME
FUNCTION
Code Clock Source
0
1
Internal 20MHz oscillator
Auto selects the best available clock source – PLL if ready, else use the
Internal oscillator
2
3
4
5
Auto selects the best available clock source – PLL if ready, else use the
Internal oscillator
Auto selects the best available clock source – PLL if ready, else use the
Internal oscillator
Auto selects the best available clock source – PLL if ready, else use the
Internal oscillator
Auto selects the best available clock source – PLL if ready, else use the
Internal oscillator
[2:0]
CLKSEL[2:0]
6
7
Internal 20MHz oscillator
Stops the clock and keeps timing generator in reset
Note: The default value of CLKSEL[2:0] is 000. It is required that CLKSEL[2:0] be set to 001 to achieve full gyroscope performance.
11.28 REGISTER 108 – POWER MANAGEMENT 2
Register Name: PWR_MGMT_2
Register Type: READ/WRITE
Register Address: 108 (Decimal); 6C (Hex)
BIT
[7]
[6]
NAME
FIFO_LP_EN
DMP_LP_DIS
FUNCTION
1 – Enable FIFO in low-power accelerometer mode. Default setting is 0.
1 - Disable DMP execution in low-power accelerometer mode. Default setting is 0.
1 – X accelerometer is disabled
0 – X accelerometer is on
[5]
STBY_XA
1 – Y accelerometer is disabled
0 – Y accelerometer is on
1 – Z accelerometer is disabled
0 – Z accelerometer is on
1 – X gyro is disabled
0 – X gyro is on
1 – Y gyro is disabled
0 – Y gyro is on
1 – Z gyro is disabled
0 – Z gyro is on
[4]
[3]
[2]
[1]
[0]
STBY_YA
STBY_ZA
STBY_XG
STBY_YG
STBY_ZG
11.29 REGISTER 114 AND 115 – FIFO COUNT REGISTERS
Register Name: FIFO_COUNTH
Register Type: READ Only
Register Address: 114 (Decimal); 72 (Hex)
BIT
NAME
FUNCTION
[7:5]
Reserved
-
High Bits, count indicates the number of written bytes in the FIFO.
Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL.
[4:0]
FIFO_COUNT[12:8]
Register Name: FIFO_COUNTL
Register Type: READ Only
Register Address: 115 (Decimal); 73 (Hex)
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BIT
NAME
FUNCTION
Low Bits, count indicates the number of written bytes in the
FIFO. NOTE: Must read FIFO_COUNTH to latch new data for
both FIFO_COUNTH and FIFO_COUNTL.
[7:0]
FIFO_COUNT[7:0]
11.30 REGISTER 116 – FIFO READ WRITE
Register Name: FIFO_R_W
Register Type: READ/WRITE
Register Address: 116 (Decimal); 74 (Hex)
BIT
NAME
FUNCTION
Read/Write command provides Read or Write operation for the
FIFO.
[7:0]
FIFO_DATA[7:0]
Description:
This register is used to read and write data from the FIFO buffer.
Data is written to the FIFO in order of register number (from lowest to highest). If all the FIFO enable flags (see below) are
enabled, the contents of registers 59 through 72 will be written in order at the Sample Rate.
The contents of the sensor data registers (Registers 59 to 72) are written into the FIFO buffer when their corresponding
FIFO enable flags are set to 1 in FIFO_EN (Register 35).
If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is automatically set to 1. This bit is located in INT_STATUS
(Register 58). When the FIFO buffer has overflowed, the oldest data will be lost and new data will be written to the FIFO
unless register 26 CONFIG, bit[6] FIFO_MODE = 1.
If the FIFO buffer is empty, reading register FIFO_DATA will return a unique value of 0xFF until new data is available.
Normal data is precluded from ever indicating 0xFF, so 0xFF gives a trustworthy indication of FIFO empty.
11.31 REGISTER 117 – WHO AM I
Register Name: WHO_AM_I
Register Type: READ only
Register Address: 117 (Decimal); 75 (Hex)
BIT
NAME
FUNCTION
[7:0]
WHOAMI
Register to indicate to user which device is being accessed.
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of
the register is 0xA6. This is different from the I2C address of the device as seen on the slave I2C controller by the
applications processor. The I2C address of the ICM-20609 is 0x68 or 0x69 depending upon the value driven on AD0 pin.
11.32REGISTERS 119, 120, 122, 123, 125, 126 ACCELEROMETER OFFSET REGISTERS
Register Name: XA_OFFSET_H
Register Type: READ/WRITE
Register Address: 119 (Decimal); 77 (Hex)
BIT
NAME
FUNCTION
Upper bits of the X accelerometer offset cancellation. +/- 16g Offset cancellation
in all Full Scale modes, 15 bit 0.98-mg steps
[7:0] XA_OFFS[14:7]
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Register Name: XA_OFFSET_L
Register Type: READ/WRITE
Register Address: 120 (Decimal); 78 (Hex)
BIT
NAME
FUNCTION
Lower bits of the X accelerometer offset cancellation. +/- 16g Offset cancellation
in all Full Scale modes, 15 bit 0.98-mg steps
[7:1] XA_OFFS[6:0]
[0]
Reserved
-
Register Name: YA_OFFSET_H
Register Type: READ/WRITE
Register Address: 122 (Decimal); 7A (Hex)
BIT
NAME
FUNCTION
Upper bits of the Y accelerometer offset cancellation. +/- 16g Offset cancellation
in all Full Scale modes, 15 bit 0.98-mg steps
[7:0] YA_OFFS[14:7]
Register Name: YA_OFFSET_L
Register Type: READ/WRITE
Register Address: 123 (Decimal); 7B (Hex)
BIT
NAME
FUNCTION
Lower bits of the Y accelerometer offset cancellation. +/- 16g Offset cancellation
in all Full Scale modes, 15 bit 0.98-mg steps
[7:1] YA_OFFS[6:0]
[0]
Reserved
-
Register Name: ZA_OFFSET_H
Register Type: READ/WRITE
Register Address: 125 (Decimal); 7D (Hex)
BIT
NAME
FUNCTION
Upper bits of the Z accelerometer offset cancellation. +/- 16g Offset cancellation
in all Full Scale modes, 15 bit 0.98-mg steps
[7:0] ZA_OFFS[14:7]
Register Name: ZA_OFFSET_L
Register Type: READ/WRITE
Register Address: 126 (Decimal); 7E (Hex)
BIT
NAME
FUNCTION
Lower bits of the Z accelerometer offset cancellation. +/- 16g Offset cancellation
in all Full Scale modes, 15 bit 0.98-mg steps
[7:1] ZA_OFFS[6:0]
[0]
Reserved
-
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ICM-20609
12 REFERENCE
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:
• Manufacturing Recommendations
o
o
o
o
Assembly Guidelines and Recommendations
PCB Design Guidelines and Recommendations
MEMS Handling Instructions
ESD Considerations
o
Reflow Specification
o
Storage Specifications
o
o
o
Package Marking Specification
Tape & Reel Specification
Reel & Pizza Box Label
o
Packaging
o
Representative Shipping Carton Label
• Compliance
o
o
o
Environmental Compliance
DRC Compliance
Compliance Declaration Disclaimer
Page 55 of 57
Rev Date: 03/15/2018
Document Number: DS-000106
Revision: 1.5
ICM-20609
13 DOCUMENT INFORMATION
13.1 REVISION HISTORY
REVISION
REVISION DESCRIPTION
DATE
11/13/2015
12/24/2015
01/20/2016
03/09/2016
04/04/2016
03/15/2018
1.0
1.1
1.2
1.3
1.4
1.5
Initial Release
Updated Sections 1, 2, 3, 4
Updated Section 3
Updated Section 3
Updated Sections 1, 2, 4, 5, 10, 11
Updated Sections 5, 10, 11
Page 56 of 57
Rev Date: 03/15/2018
Document Number: DS-000106
Revision: 1.5
ICM-20609
This information furnished by InvenSense, Inc. (“InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense for its use,
or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. InvenSense reserves
the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. InvenSense makes
no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. InvenSense assumes no responsibility for any
claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to,
claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any
patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the
property of their respective companies. InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or
mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment,
transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2018 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP, AAR, and the InvenSense
logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and product names may be trademarks of the respective
companies with which they are associated.
©2018 InvenSense. All rights reserved.
Page 57 of 57
Rev Date: 03/15/2018
Document Number: DS-000106
Revision: 1.5
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