ICM-40609-D [TDK]
IMU (惯性测量设备);
| 型号： | ICM-40609-D |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | IMU (惯性测量设备) |
| 文件： | 总86页 (文件大小：1679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICM-40609-D
A TDK SmartMotion™ Solution Designed for Drone Market
GENERAL DESCRIPTION
FEATURES
The ICM-40609-D is a 6-axis MEMS MotionTracking™
device that combines a 3-axis gyroscope and a 3-axis
accelerometer designed for the drone market. The
ICM-40609-D is form factor compatible with our
legacy drone devices – making the transition to the
latest offering incredibly simple.
•
•
•
•
•
•
•
•
•
•
•
Gyro Noise: 4.5mdps/√Hz
Gyro Offset Stability TC: ±10mdps/C
Gyro Sensitivity Error: ±0.5%
Gyro Sensitivity/temp: ±0.045%/C
Accel Noise: 100μg/√Hz
Accel Offset Stability TC: ±0.15mg/C
Accel Sensitivity Error: ±0.5%
Accel Sensitivity/temp: ±0.007%/C
Gyro + Accel Combo current: 0.77mA
Extended Accel Full Scale Range: 32g
Improved ODR Latency: 32KHz
The ICM-40609-D takes advantage of a state-of-the-
art architecture design that enhances the IMU’s
performance and accuracy over temperature,
making it the ideal drone solution to control the
stability of the platform during long flight times that
may experience high temperature shifts.
Custom architecture for Improved Thermal
Gradient Behavior
The ICM-40609-D has a max ODR of 32 KHz, making
it the best sampling rate available in a consumer
device. The ability to capture data at such a high
ODR allows for customers to easily find any
anomalies or errors that need to be addressed
during flight. The accel Full Scale Range has also
been increased to 32g, allowing for substantial linear
movement to be easily tracked.
•
Best-in-class accuracy over temperature
Increased ODR/FSR for max data collection
•
•
32g Accel Full Scale Range
32 KHz ODR Sample Rate
Other industry-leading features include on-chip 16-
bit ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts.
The device features I2C and SPI serial interfaces, a
VDD operating range of 1.71V to 3.6V, and a
Form Factor Compatible with Legacy Products
•
•
Easily transition from ICM-20602 and MPU-6500
Only minor pinout changes required
separate VDDIO operating range of 1.71V to 3.6V.
APPLICATIONS
•
Drones, Flight Controller
PART NUMBER
PACKAGE SIZE
TARGET MARKETS
FULL SCALE RANGE
ODR & SAMPLE SYNCH
STATUS
G: 8KHz/ A: 4KHz
16-bit
G: 8KHz/ A: 4KHz
16-bit
32KHz
G: 19-bit / A: 18-bit
MPU-6500
ICM-20602
3x3x0.9mm 24-pin QFN
Various
Various
±2000dps/16g
NR/ND
3x3x0.75mm 16-pin LGA
2.5x3 14mm-pin LGA
±2000dps/16g
±2000dps/16g
±2000dps/32g
NR/ND
Active
ICM-42688-P
ICM-40609-D
Robotics/HMD/IoT/Drones
Enhanced Drone
Performance
32KHz
16-bit
3x3x0.91mm 24-pin LGA
2H 2022
InvenSense, Inc. reserves the right to change
specifications and information herein without
notice unless the product is in mass production
and the datasheet has been designated by
InvenSense in writing as subject to a specified
Product / Process Change Notification Method
regulation.
InvenSense, a TDK Group Company
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 988–7339
Document Number: DS-000330
Revision: 1.2
Rev. Date: 06/07/2022
invensense.tdk.com
ICM-40609-D
TABLE OF CONTENTS
General Description............................................................................................................................................ 1
Features.............................................................................................................................................................. 1
Applications........................................................................................................................................................ 1
Introduction........................................................................................................................................................ 8
1.1 Purpose and Scope .................................................................................................................................. 8
1.2 Product Overview .................................................................................................................................... 8
1.3 Applications ............................................................................................................................................. 8
Features.............................................................................................................................................................. 9
2.1 Gyroscope Features................................................................................................................................. 9
2.2 Accelerometer Features .......................................................................................................................... 9
2.3 Additional Features.................................................................................................................................. 9
Electrical Characteristics................................................................................................................................... 10
3.1 Gyroscope Specifications....................................................................................................................... 10
3.2 Accelerometer Specifications ................................................................................................................11
3.3 Electrical Specifications ......................................................................................................................... 12
3.4 I2C Timing Characterization ...................................................................................................................14
3.5 SPI Timing Characterization – 4-Wire SPI Mode....................................................................................15
3.6 SPI Timing Characterization – 3-Wire SPI Mode....................................................................................16
3.7 Absolute Maximum Ratings...................................................................................................................17
Applications Information.................................................................................................................................. 18
4.1 Pin Out Diagram and Signal Description................................................................................................18
4.2 Typical Operating Circuit........................................................................................................................ 19
4.3 Bill of Materials for External Components.............................................................................................20
4.4 System Block Diagram ........................................................................................................................... 21
4.5 Overview................................................................................................................................................ 21
4.6 Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning..............................................21
4.7 Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning .......................................21
4.8 I2C and SPI Host Interface ...................................................................................................................... 21
4.9 Self-Test ................................................................................................................................................. 21
1
2
3
4
4.10
4.11
4.12
4.13
4.14
4.15
4.16
Clocking ............................................................................................................................................. 22
Sensor Data Registers........................................................................................................................ 22
Interrupts........................................................................................................................................... 22
Digital-Output Temperature Sensor..................................................................................................22
Bias and LDOs .................................................................................................................................... 22
Charge Pump ..................................................................................................................................... 22
Standard Power Modes.....................................................................................................................23
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5
6
Signal Path ........................................................................................................................................................ 24
5.1 Notch Filter ............................................................................................................................................ 24
5.2 Anti-Alias Filter ...................................................................................................................................... 25
5.3 User Programmable Offset....................................................................................................................27
5.4 UI Filter Block......................................................................................................................................... 28
5.5 ODR And FSR Selection .......................................................................................................................... 33
FIFO................................................................................................................................................................... 36
6.1 Packet Structure .................................................................................................................................... 36
6.2 FIFO Header ........................................................................................................................................... 37
6.3 Maximum FIFO Storage ......................................................................................................................... 38
6.4 FIFO Configuration Registers .................................................................................................................38
Programmable Interrupts................................................................................................................................. 40
7.1 Wake-On Motion Interrupt....................................................................................................................40
Digital Interface ................................................................................................................................................ 41
8.1 I2C and SPI Serial Interfaces ...................................................................................................................41
8.2 I2C Interface ........................................................................................................................................... 41
8.3 I2C Communications Protocol ................................................................................................................41
8.4 I2C Terms................................................................................................................................................ 43
8.5 SPI Interface........................................................................................................................................... 44
Assembly .......................................................................................................................................................... 45
9.1 Orientation of Axes................................................................................................................................ 45
9.2 Package Dimensions .............................................................................................................................. 46
Part Number Package Marking......................................................................................................................... 48
Use Notes ......................................................................................................................................................... 49
7
8
9
10
11
11.1
11.2
11.3
11.4
11.5
Accelerometer Mode Transitions......................................................................................................49
Accelerometer Low Power (LP) Mode Averaging Filter Setting ........................................................49
Settings for I2C, and SPI Operation....................................................................................................49
Notch Filter and Anti-Alias Filter Operation......................................................................................49
Register Values Modification.............................................................................................................49
12
13
Register Map .................................................................................................................................................... 50
12.1
12.2
12.3
12.4
User Bank 0 Register Map .................................................................................................................50
User Bank 1 Register Map .................................................................................................................51
User Bank 2 Register Map .................................................................................................................52
User Bank 4 Register Map .................................................................................................................52
User Bank 0 Register Map – Descriptions.........................................................................................................53
13.1
13.2
DEVICE_CONFIG ................................................................................................................................ 53
DRIVE_CONFIG .................................................................................................................................. 53
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ICM-40609-D
13.3
INT_CONFIG....................................................................................................................................... 54
FIFO_CONFIG..................................................................................................................................... 54
TEMP_DATA1 .................................................................................................................................... 54
TEMP_DATA0 .................................................................................................................................... 55
ACCEL_DATA_X1................................................................................................................................ 55
ACCEL_DATA_X0................................................................................................................................ 55
ACCEL_DATA_Y1................................................................................................................................ 55
ACCEL_DATA_Y0................................................................................................................................ 55
ACCEL_DATA_Z1................................................................................................................................ 56
ACCEL_DATA_Z0................................................................................................................................ 56
GYRO_DATA_X1................................................................................................................................. 56
GYRO_DATA_X0................................................................................................................................. 56
GYRO_DATA_Y1................................................................................................................................. 56
GYRO_DATA_Y0................................................................................................................................. 57
GYRO_DATA_Z1................................................................................................................................. 57
GYRO_DATA_Z0................................................................................................................................. 57
TMST_FSYNCH................................................................................................................................... 57
TMST_FSYNCL.................................................................................................................................... 57
INT_STATUS....................................................................................................................................... 58
FIFO_COUNTH ................................................................................................................................... 58
FIFO_COUNTL.................................................................................................................................... 58
FIFO_DATA......................................................................................................................................... 59
INT_STATUS2..................................................................................................................................... 59
SIGNAL_PATH_RESET ........................................................................................................................ 59
INTF_CONFIG0................................................................................................................................... 59
INTF_CONFIG1................................................................................................................................... 61
PWR_MGMT0.................................................................................................................................... 61
GYRO_CONFIG0................................................................................................................................. 62
ACCEL_CONFIG0................................................................................................................................ 63
GYRO_CONFIG1................................................................................................................................. 64
GYRO_ACCEL_CONFIG0.....................................................................................................................65
ACCEL_CONFIG1................................................................................................................................ 66
TMST_CONFIG................................................................................................................................... 66
WOM_CONFIG................................................................................................................................... 67
FIFO_CONFIG1................................................................................................................................... 67
FIFO_CONFIG2................................................................................................................................... 67
FIFO_CONFIG3................................................................................................................................... 68
13.4
13.5
13.6
13.7
13.8
13.9
13.10
13.11
13.12
13.13
13.14
13.15
13.16
13.17
13.18
13.19
13.20
13.21
13.22
13.23
13.24
13.25
13.26
13.27
13.28
13.29
13.30
13.31
13.32
13.33
13.34
13.35
13.36
13.37
13.38
13.39
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ICM-40609-D
13.40
13.41
13.42
13.43
13.44
13.45
13.46
13.47
13.48
13.49
13.50
13.51
FSYNC_CONFIG.................................................................................................................................. 68
INT_CONFIG0..................................................................................................................................... 69
INT_CONFIG1..................................................................................................................................... 69
INT_SOURCE0.................................................................................................................................... 70
INT_SOURCE1.................................................................................................................................... 70
INT_SOURCE3.................................................................................................................................... 71
INT_SOURCE4.................................................................................................................................... 71
FIFO_LOST_PKT0 ............................................................................................................................... 71
FIFO_LOST_PKT1 ............................................................................................................................... 72
SELF_TEST_CONFIG ........................................................................................................................... 72
WHO_AM_I ....................................................................................................................................... 72
REG_BANK_SEL.................................................................................................................................. 73
14
User Bank 1 Register Map – Descriptions.........................................................................................................74
14.1
SENSOR_CONFIG0 ............................................................................................................................. 74
GYRO_CONFIG_STATIC2....................................................................................................................74
GYRO_CONFIG_STATIC3....................................................................................................................74
GYRO_CONFIG_STATIC4....................................................................................................................75
GYRO_CONFIG_STATIC5....................................................................................................................75
GYRO_CONFIG_STATIC6....................................................................................................................75
GYRO_CONFIG_STATIC7....................................................................................................................75
GYRO_CONFIG_STATIC8....................................................................................................................76
GYRO_CONFIG_STATIC9....................................................................................................................76
GYRO_CONFIG_STATIC10..................................................................................................................76
XG_ST_DATA...................................................................................................................................... 77
YG_ST_DATA...................................................................................................................................... 77
ZG_ST_DATA...................................................................................................................................... 77
TMSTVAL0 ......................................................................................................................................... 77
TMSTVAL1 ......................................................................................................................................... 77
TMSTVAL2 ......................................................................................................................................... 78
INTF_CONFIG4................................................................................................................................... 78
INTF_CONFIG5................................................................................................................................... 78
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.12
14.13
14.14
14.15
14.16
14.17
14.18
15
User Bank 2 Register Map – Descriptions.........................................................................................................79
15.1
15.2
15.3
15.4
15.5
ACCEL_CONFIG_STATIC2...................................................................................................................79
ACCEL_CONFIG_STATIC3...................................................................................................................79
ACCEL_CONFIG_STATIC4...................................................................................................................79
XA_ST_DATA...................................................................................................................................... 79
YA_ST_DATA...................................................................................................................................... 80
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15.6
ZA_ST_DATA...................................................................................................................................... 80
16
User Bank 4 Register Map – Descriptions.........................................................................................................81
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
16.10
16.11
16.12
ACCEL_WOM_X_THR......................................................................................................................... 81
ACCEL_WOM_Y_THR......................................................................................................................... 81
ACCEL_WOM_Z_THR......................................................................................................................... 81
OFFSET_USER0 .................................................................................................................................. 81
OFFSET_USER1 .................................................................................................................................. 82
OFFSET_USER2 .................................................................................................................................. 82
OFFSET_USER3 .................................................................................................................................. 82
OFFSET_USER4 .................................................................................................................................. 82
OFFSET_USER5 .................................................................................................................................. 83
OFFSET_USER6 .................................................................................................................................. 83
OFFSET_USER7 .................................................................................................................................. 83
OFFSET_USER8 .................................................................................................................................. 83
17
18
Reference ......................................................................................................................................................... 84
Revision History................................................................................................................................................ 85
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ICM-40609-D
TABLE OF FIGURES
Figure 1. I2C Bus Timing Diagram.................................................................................................................................14
Figure 2. 4-Wire SPI Mode-3 Bus Timing Diagram.......................................................................................................15
Figure 3. 4-Wire SPI Mode-0 Bus Timing Diagram.......................................................................................................15
Figure 4. 3-Wire Mode-3 SPI Bus Timing Diagram.......................................................................................................16
Figure 5. 3-Wire Mode-0 SPI Bus Timing Diagram.......................................................................................................16
Figure 6. Pin Out Diagram for ICM-40609-D 3x3.0x0.91 mm LGA...............................................................................18
Figure 7. ICM-40609-D Application Schematic (I2C Interface to Host) ........................................................................19
Figure 8. ICM-40609-D Application Schematic (SPI Interface to Host)........................................................................19
Figure 9. ICM-40609-D System Block Diagram............................................................................................................21
Figure 10. ICM-40609-D Signal Path............................................................................................................................24
Figure 11. FIFO Packet Structure .................................................................................................................................36
Figure 12. Maximum FIFO Storage ..............................................................................................................................38
Figure 13. START and STOP Conditions .......................................................................................................................41
Figure 14. Acknowledge on the I2C Bus .......................................................................................................................42
Figure 15. Complete I2C Data Transfer ........................................................................................................................42
Figure 16. Typical SPI Master/Slave Configuration......................................................................................................44
Figure 17. Orientation of Axes of Sensitivity and Polarity of Rotation........................................................................45
TABLE OF TABLES
Table 1. Gyroscope Specifications ...............................................................................................................................10
Table 2. Accelerometer Specifications ........................................................................................................................11
Table 3. D.C. Electrical Characteristics.........................................................................................................................12
Table 4. A.C. Electrical Characteristics.........................................................................................................................13
Table 5. I2C Timing Characteristics...............................................................................................................................14
Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation).................................................................................15
Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation).................................................................................16
Table 8. Absolute Maximum Ratings ...........................................................................................................................17
Table 9. Signal Descriptions.........................................................................................................................................18
Table 10. Bill of Materials ............................................................................................................................................20
Table 11. Standard Power Modes for ICM-40609-D....................................................................................................23
Table 12. I2C Terms......................................................................................................................................................43
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ICM-40609-D
1 INTRODUCTION
1.1 PURPOSE AND SCOPE
This document is a product specification, providing a description, specifications, and design related information on
the ICM-40609-D Single-Interface MotionTracking device. The device is housed in a small 3x3x0.91 mm 24-pin LGA
package.
1.2 PRODUCT OVERVIEW
The ICM-40609-D is a 6-axis MotionTracking device that combines a 3-axis gyroscope, and a 3-axis accelerometer
in a small 3x3x0.91 mm (24-pin LGA) package. It also features a 2 KB FIFO that can lower the traffic on the serial
bus interface and reduce power consumption by allowing the system processor to burst read sensor data and then
go into a low-power mode. ICM-40609-D, with its 6-axis integration, enables manufacturers to eliminate the costly
and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal motion
performance for consumers.
The gyroscope supports eight programmable full-scale range settings from ±15.625 dps to ±2000 dps, and the
accelerometer supports four programmable full-scale range settings from ±4g to ±32g.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts. The device features I2C and SPI serial interfaces, a VDD
operating range of 1.71V to 3.6V, and a separate VDDIO operating range of 1.71V to 3.6V.
The host interface can be configured to support I2C slave or SPI slave modes. The I2C interface supports speeds up
to 1 MHz, and the SPI interface supports speeds up to 24 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers
with companion CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a
footprint and thickness of 3x3x0.91 mm (24-pin LGA), to provide a very small yet high-performance low-cost
package. The device provides high robustness by supporting 20,000g shock reliability.
1.3 APPLICATIONS
•
•
•
Drones
Robotics
IoT Applications
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ICM-40609-D
2 FEATURES
2.1 GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICM-40609-D includes a wide range of features:
•
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with programmable full-scale range of
±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees/sec
•
•
•
•
Low Noise (LN) power mode support
Digitally programmable low-pass filters
Factory calibrated sensitivity scale factor
Self-test
2.2 ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in ICM-40609-D includes a wide range of features:
•
Digital-output X-, Y-, and Z-axis accelerometer with programmable full-scale range of ±4g, ±8g, ±16g and
±32g
•
•
•
•
Low Noise (LN) and Low Power (LP) power modes support
User-programmable interrupts
Wake-on-motion interrupt for low power operation of applications processor
Self-test
2.3 ADDITIONAL FEATURES
ICM-40609-D includes the following additional features:
•
•
•
•
•
•
•
•
•
2KB FIFO buffer enables the applications processor to read the data in bursts
User-programmable digital filters for gyroscope, accelerometer, and temperature sensor
Wake on Motion: Detects motion when accelerometer data exceeds a programmable threshold
1 MHz I2C / 24 MHz SPI slave host interface
Digital-output temperature sensor
Smallest and thinnest LGA package for portable devices: 3 x 3 x 0.91 mm (24-pin LGA)
20,000g shock tolerant
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
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ICM-40609-D
3 ELECTRICAL CHARACTERISTICS
3.1 GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
GYROSCOPE SENSITIVITY
GYRO_FS_SEL=0
GYRO_FS_SEL =1
GYRO_FS_SEL =2
GYRO_FS_SEL =3
GYRO_FS_SEL =4
GYRO_FS_SEL =5
GYRO_FS_SEL =6
GYRO_FS_SEL =7
±2000
±1000
±500
±250
±125
±62.5
±31.25
±15.625
16
º/s
º/s
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
º/s
º/s
Full-Scale Range
º/s
º/s
º/s
º/s
Gyroscope ADC Word Length
Sensitivity Scale Factor
bits
GYRO_FS_SEL=0
GYRO_FS_SEL =1
GYRO_FS_SEL =2
GYRO_FS_SEL =3
GYRO_FS_SEL =4
GYRO_FS_SEL =5
GYRO_FS_SEL =6
GYRO_FS_SEL =7
16.4
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
%
32.8
65.5
131
262
524.3
1048.6
2097.2
±0.5
Sensitivity Scale Factor Initial Tolerance
25°C
1
Sensitivity Scale Factor Variation Over
Temperature
-40°C to +85°C
±0.045
%/ºC
3
Nonlinearity
Best fit straight line; 25°C
±0.1
±1
%
%
3
3
Cross-Axis Sensitivity
ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance
Board-level, 25°C
-40°C to +85°C
±1
º/s
3
3
ZRO Variation vs. Temperature
±0.01
º/s/ºC
OTHER PARAMETERS
Rate Noise Spectral Density
Total RMS Noise
@ 10 Hz
0.0045
0.045
27
º/s /√Hz
º/s-rms
KHz
1
4
1
2
Bandwidth = 100 Hz
Gyroscope Mechanical Frequencies
25
5
29
ODR < 1kHz
500
995
Hz
Low Pass Filter Response
ODR ≥ 1kHz
Time from gyro enable to gyro drive ready
5
Hz
ms
Hz
2
3
2
Gyroscope Start-Up Time
Output Data Rate
30
12.5
32000
Table 1. Gyroscope Specifications
Notes:
1.
2.
3.
4.
Tested in production.
Guaranteed by design.
Derived from validation or characterization of parts, not guaranteed in production.
Calculated from Rate Noise Spectral Density.
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ICM-40609-D
3.2 ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ACCELEROMETER SENSITIVITY
ACCEL_FS_SEL =0
ACCEL_FS_SEL =1
ACCEL_FS_SEL =2
ACCEL_FS_SEL =3
±32
±16
g
g
2
2
2
2
2
2
2
2
2
Full-Scale Range
±8
g
±4
g
ADC Word Length
Output in two’s complement format
ACCEL_FS_SEL =0
16
bits
LSB/g
LSB/g
LSB/g
LSB/g
%
1,024
2,048
4,096
8,192
±0.5
±0.007
±0.1
±1
ACCEL_FS_SEL =1
Sensitivity Scale Factor
ACCEL_FS_SEL =2
ACCEL_FS_SEL =3
Component-level
Sensitivity Scale Factor Initial Tolerance
Sensitivity Change vs. Temperature
Nonlinearity
1
3
3
3
-40°C to +85°C
%/ºC
%
Best Fit Straight Line, ±2g
Cross-Axis Sensitivity
%
ZERO-G OUTPUT
Initial Tolerance
Board-level, all axes
-40°C to +85°C
±40
mg
3
3
Zero-G Level Change vs. Temperature
±0.15
mg/ºC
OTHER PARAMETERS
Power Spectral Density
RMS Noise
@ 10 Hz
100
µg/√Hz
mg-rms
Hz
1
4
2
Bandwidth = 100 Hz
ODR < 1kHz
1.00
5
5
500
995
Low-Pass Filter Response
ODR ≥ 1kHz
From sleep mode to valid data
Hz
ms
Hz
2
3
2
Accelerometer Startup Time
Output Data Rate
10
1.5625
32000
Table 2. Accelerometer Specifications
Notes:
1. Tested in production.
2. Guaranteed by design.
3. Derived from validation or characterization of parts, not guaranteed in production.
4. Calculated from Power Spectral Density.
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ICM-40609-D
3.3 ELECTRICAL SPECIFICATIONS
3.3.1
D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
SUPPLY VOLTAGES
MIN
TYP
MAX
UNITS
NOTES
VDD
1.71
1.71
1.8
1.8
3.6
3.6
V
V
1
1
VDDIO
SUPPLY CURRENTS
6-Axis Gyroscope + Accelerometer
0.77
0.27
0.61
mA
mA
mA
2
2
2
3-Axis Accelerometer
3-Axis Gyroscope
Low-Noise Mode
Accelerometer Low -Power Mode
(Gyroscope disabled)
200Hz ODR, 1x averaging
At 25ºC
0.06
11
mA
µA
2
2
Full-Chip Sleep Mode
TEMPERATURE RANGE
Specified Temperature Range
Performance parameters are not applicable
beyond Specified Temperature Range
-40
+85
°C
1
Table 3. D.C. Electrical Characteristics
Notes:
1. Guaranteed by design.
2. Derived from validation or characterization of parts, not guaranteed in production.
Page 12 of 86
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ICM-40609-D
3.3.2
A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLIES
Monotonic ramp. Ramp rate is 10% to 90% of
the final value
Supply Ramp Time
0.01
3
ms
1
1
mV
peak-peak
Power Supply Noise
10
TEMPERATURE SENSOR
Operating Range
25°C Output
ADC Resolution
ODR
Room Temperature Offset
Stabilization Time
Sensitivity
Ambient
-40
85
°C
LSB
bits
Hz
°C
µs
1
3
2
2
3
2
1
1
0
16
With Filter
25°C
25
-5
8000
5
14000
Untrimmed
132.48
2.07
LSB/°C
LSB/°C
Sensitivity for FIFO data
POWER-ON RESET
I2C ADDRESS
1
ms
Start-up time for register read/write
From power-up
1
1
1
AP_AD0 = 0
AP_AD0 = 1
1101000
1101001
I2C ADDRESS
DIGITAL INPUTS (FSYNC, SCLK, SDI, CS)
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
0.7*VDDIO
V
V
0.3*VDDIO
< 10
pF
DIGITAL OUTPUT (SDO, INT1, INT2)
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT, INT Low-Level Output Voltage
RLOAD=1 MΩ;
RLOAD=1 MΩ;
0.9*VDDIO
V
V
V
0.1*VDDIO
0.1
OPEN=1, 0.3 mA sink
Current
Output Leakage Current
tINT, INT Pulse Width
OPEN=1
100
nA
µs
int_tpulse_duration= 0 , 1 (100us, 8us ) ;
I2C I/O (SCL, SDA)
8
100
VIL, LOW-Level Input Voltage
VIH, HIGH-Level Input Voltage
-0.5 V
0.3*VDDIO
V
V
0.7*VDDIO
VDDIO +
0.5 V
Vhys, Hysteresis
0.1*VDDIO
V
V
VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current
3 mA sink current
0
0.4
1
VOL=0.4 V
VOL=0.6 V
3
6
mA
mA
Output Leakage Current
100
nA
ns
tof, Output Fall Time from VIHmax to VILmax
Cb bus capacitance in pf
20+0.1Cb
300
INTERNAL CLOCK SOURCE
CLKSEL=`2b00 or gyro inactive; 25°C
-3
-1
+3
+1
±3
±2
%
%
%
%
1
1
1
1
Clock Frequency Initial Tolerance
CLK_SEL=`2b01 and gyro active; 25°C
CLK_SEL=`2b00 or gyro inactive; -40°C to +85°C
CLK_SEL=`2b01 and gyro active; -40oC to +85oC
Frequency Variation over Temperature
Table 4. A.C. Electrical Characteristics
Notes:
1. Expected results based on design, will be updated after characterization. Not guaranteed in production.
2. Guaranteed by design.
3. To be Production tested.
Page 13 of 86
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ICM-40609-D
3.4 I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERS
I2C TIMING
CONDITIONS
I2C FAST-MODE PLUS
MIN
TYPICAL
MAX
UNITS
NOTES
fSCL, SCL Clock Frequency
tHD.STA, (Repeated) START Condition Hold Time
1
MHz
µs
1
1
0.26
0.5
0.26
0.26
0
tLOW, SCL Low Period
µs
µs
µs
µs
ns
ns
ns
µs
1
1
1
1
1
1
1
1
tHIGH, SCL High Period
tSU.STA, Repeated START Condition Setup Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
50
120
120
Cb bus cap. from 10 to 400 pF
Cb bus cap. from 10 to 400 pF
tf, SDA and SCL Fall Time
0.5
0.5
tSU.STO, STOP Condition Setup Time
tBUF, Bus Free Time Between STOP and START
Condition
µs
1
Cb, Capacitive Load for each Bus Line
tVD.DAT, Data Valid Time
< 400
pF
µs
µs
1
1
1
0.45
0.45
tVD.ACK, Data Valid Acknowledge Time
Table 5. I2C Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
tf
tSU.DAT
tr
SDA
SCL
70%
30%
70%
30%
continued below at
9th clock cycle
A
tf
tr
t
VD.DAT
70%
30%
70%
30%
tHD.DAT
tHD.STA
1/fSCL
tLOW
1st clock cycle
S
t
HIGH
tBUF
SDA
SCL
70%
30%
A
tSU.STO
t
SU.STA
tHD.STA
tVD.ACK
70%
30%
9th clock cycle
S
P
Sr
Figure 1. I2C Bus Timing Diagram
Page 14 of 86
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ICM-40609-D
3.5 SPI TIMING CHARACTERIZATION – 4-WIRE SPI MODE
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
NOTES
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING
fSPC, SCLK Clock Frequency
tLOW, SCLK Low Period
tHIGH, SCLK High Period
tSU.CS, CS Setup Time
Default
24
MHz
ns
1
1
1
1
1
1
1
1
1
1
24.5
24.5
ns
39
18
13
8
ns
tHD.CS, CS Hold Time
ns
tSU.SDI, SDI Setup Time
tHD.SDI, SDI Hold Time
ns
ns
tVD.SDO, SDO Valid Time
tHD.SDO, SDO Hold Time
tDIS.SDO, SDO Output Disable Time
Cload = 20 pF
Cload = 20 pF
21.5
28
ns
9.5
ns
ns
Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
2. Based on other parameter values
CS
70%
30%
tFall
tRise
t
HD;CS
t
SU;CS
70%
t
HIGH
1/fCLK
SCLK
30%
tSU;SDI
tHD;SDI
t
LOW
70%
30%
SDI
LSB IN
MSB IN
tDIS;SDO
t
VD;SDO
t
HD;SDO
70%
30%
SDO
MSB OUT
LSB OUT
Figure 2. 4-Wire SPI Mode-3 Bus Timing Diagram
Figure 3. 4-Wire SPI Mode-0 Bus Timing Diagram
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ICM-40609-D
3.6 SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
NOTES
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING
fSPC, SCLK Clock Frequency
tLOW, SCLK Low Period
Default
24
MHz
ns
1
1
1
1
1
1
1
1
1
1
24.5
24.5
tHIGH, SCLK High Period
ns
39
5
tSU.CS, CS Setup Time
ns
tHD.CS, CS Hold Time
ns
13
8
tSU.SDIO, SDIO Input Setup Time
tHD.SDIO, SDIO Input Hold Time
tVD.SDIO, SDIO Output Valid Time
tHD.SDIO, SDIO Output Hold Time
tDIS.SDIO, SDIO Output Disable Time
ns
ns
Cload = 20 pF
Cload = 20 pF
18.5
28
ns
9.5
ns
ns
Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
2. Based on other parameter values
CS
70%
30%
tFall
tRise
t
HD;CS
tSU;CS
tHIGH
1/fCLK
SCLK
70%
30%
tSU;SDIO
tHD;SDIO
t
LOW
70%
30%
I
LSB IN
MSB IN
tDIS;SDIO
tVD;SDIO
tHD;SDIO
70%
30%
O
MSB OUT
LSB OUT
Figure 4. 3-Wire Mode-3 SPI Bus Timing Diagram
Figure 5. 3-Wire Mode-0 SPI Bus Timing Diagram
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ICM-40609-D
3.7 ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the
absolute maximum ratings conditions for extended periods may affect device reliability.
PARAMETER
RATING
-0.5V to +4V
Supply Voltage, VDD
Supply Voltage, VDDIO
-0.5V to +4V
Input Voltage Level (FSYNC, SCL, SDA)
Acceleration (Any Axis, unpowered)
Operating Temperature Range
Storage Temperature Range
-0.5V to VDDIO + 0.5V
20,000g for 0.2 ms
-40°C to +85°C
-40°C to +125°C
2 kV (HBM);
200V (MM)
Electrostatic Discharge (ESD) Protection
Latch-up
JEDEC Class II (2),125°C
±100 mA
Table 8. Absolute Maximum Ratings
Page 17 of 86
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ICM-40609-D
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
PIN NUMBER
PIN NAME
PIN DESCRIPTION
Digital I/O supply voltage
AD0: I2C Slave Address LSB
8
VDDIO
9
AD0 / SDO
RESV
SDO: SPI serial data output (4-wire mode)
11
12
RESV: Connect to GND
INT1: Interrupt 1
INT: Interrupt if all interrupts mapped to pin 12
INT1 / INT
13
18
VDD
GND
Power supply voltage
Power supply ground
INT2: Interrupt 2
FSYNC: Frame sync input; Connect to GND if FSYNC selected but
FSYNC signal not input
19
INT2 / FSYNC
20
22
RESV
nCS
Reserved, connect to GND
Chip select (SPI mode only)
SCL: I2C serial clock
SCLK: SPI serial clock
23
SCL / SCLK
SDA: I2C serial data
24
SDA / SDI / SDIO
NC
SDI: SPI serial data input (4-wire mode)
SDIO: SPI serial data I/O (3-wire mode)
1 – 7, 10, 14 – 17, 21
No Connect pins. Do not connect.
Table 9. Signal Descriptions
GND
18
NC
1
2
3
4
5
6
17
NC
NC
NC
NC
NC
NC
16
NC
ICM-40609-D
15
14
NC
NC
13 VDD
Figure 6. Pin Out Diagram for ICM-40609-D 3x3.0x0.91 mm LGA
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ICM-40609-D
4.2 TYPICAL OPERATING CIRCUIT
VDDIO
SCL
SDA
GND
NC
NC
1
2
3
4
5
6
18
17
16
15
14
13
NC
NC
NC
NC
ICM-40609-D
NC
NC
NC
NC
1.71 – 3.6VDC
VDD
C1, 0.1 µF C2, 2.2 µF
1.71 – 3.6VDC
C3, 10 nF
AD0
Figure 7. ICM-40609-D Application Schematic (I2C Interface to Host)
Note: I2C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required.
nCS
SCLK
SDI / SDIO
GND
NC
NC
1
2
3
4
5
6
18
17
16
15
14
13
NC
NC
NC
NC
ICM-40609-D
NC
NC
NC
NC
1.71 – 3.6VDC
VDD
C1, 0.1 µF C2, 2.2 µF
1.71 – 3.6VDC
C3, 10 nF
SDO
Figure 8. ICM-40609-D Application Schematic (SPI Interface to Host)
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ICM-40609-D
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS
COMPONENT
LABEL
SPECIFICATION
QUANTITY
C1
C2
X7R, 0.1µF ±10%
X7R, 2.2µF ±10%
1
1
VDD Bypass Capacitors
VDDIO Bypass Capacitor
C3
X7R, 10nF ±10%
1
Table 10. Bill of Materials
Page 20 of 86
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Revision: 1.2
ICM-40609-D
4.4 SYSTEM BLOCK DIAGRAM
Figure 9. ICM-40609-D System Block Diagram
Note: The block diagram in Figure 9 is an example. Please refer to the pin-out (section 4.1) for other configuration
options.
4.5 OVERVIEW
The ICM-40609-D is comprised of the following key blocks and functions:
•
•
•
•
•
•
•
•
•
•
•
•
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
I2C and SPI serial communications interfaces to Host
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes
4.6 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-40609-D includes a vibratory MEMS rate gyroscope, which detects rotation about the X-, Y-, and Z- Axes.
When the gyroscope is rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected
by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is
proportional to the angular rate. This voltage is digitized using on-chip Analog-to-Digital Converters (ADCs) to
sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±15.625, ±31.25, ±62.5,
±125, ±250, ±500, ±1000, and ±2000 degrees per second (dps).
4.7 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-40609-D includes a 3-Axis MEMS accelerometer. Acceleration along a particular axis induces displacement
of a proof mass in the MEMS structure, and capacitive sensors detect the displacement. The ICM-40609-D
architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When
the device is placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The
accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. The full-
scale range of the digital output can be adjusted to ±4g, ±8g, ±16g and ±32g.
4.8 I2C AND SPI HOST INTERFACE
The ICM-40609-D communicates to the application processor using an I2C, or SPI serial interface. The ICM-40609-D
always acts as a slave when communicating to the application processor.
4.9 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each
measurement axis can be activated by means of the gyroscope and accelerometer self-test registers.
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ICM-40609-D
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The
output signal is used to observe the self-test response.
The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED
When the value of the self-test response is within the specified min/max limits of the product specification, the
part has passed self-test. When the self-test response exceeds the min/max values, the part is deemed to have
failed self-test.
4.10 CLOCKING
The ICM-40609-D has a flexible clocking scheme, allowing the following internal clock sources to be used for the
internal synchronous circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various
control circuits and registers.
a) An internal relaxation oscillator
b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available
source
The only setting supporting specified performance in all modes is option b). It is recommended that option b) be
used when using internal clock source.
4.11 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They
are read-only registers and are accessed via the serial interface. Data from these registers may be read anytime.
4.12 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the
interrupt pins configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that
can trigger an interrupt are (1) Clock generator locked to new reference oscillator (used when switching clock
sources); (2) new data is available to be read (from the FIFO and Data registers); (3) accelerometer event
interrupts; (4) FIFO watermark; (5) FIFO overflow. The interrupt status can be read from the Interrupt Status
register.
4.13 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICM-40609-D die temperature. The readings
from the ADC can be read from the FIFO or the Sensor Data registers.
Temperature data value from the sensor data registers can be converted to degrees centigrade by using the
following formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25
Temperature data stored in FIFO is an 8-bit quantity, FIFO_TEMP_DATA. It can be converted to degrees centigrade
by using the following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25
4.14 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the
ICM-40609-D.
4.15 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
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ICM-40609-D
4.16 STANDARD POWER MODES
Table 11 lists the user-accessible power modes for ICM-40609-D.
MODE NAME
GYRO
Off
Drive On
Off
ACCEL
Off
Off
Duty-Cycled
On
1
2
3
4
5
6
Sleep Mode
Standby Mode
Accelerometer Low-Power Mode
Accelerometer Low-Noise Mode
Gyroscope Low-Noise Mode
6-Axis Low-Noise Mode
Off
On
On
Off
On
Table 11. Standard Power Modes for ICM-40609-D
Page 23 of 86
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Revision: 1.2
ICM-40609-D
5 SIGNAL PATH
Figure 10 shows a block diagram of the signal path for ICM-40609-D.
Gyro Only
Decimation
UI Interface
Anti-Alias
Filter (AAF)
User
Programmable
Offset
UI Filter Block
(order, BW, ODR)
Sensor
Registers
0
1
ADC
Filter
0
1
Notch Filter
(32kHz)
FSR Selection
GYRO_NF_DIS
AAF_DIS
Figure 10. ICM-40609-D Signal Path
The signal path starts with independent 16-bit ADCs for each axis of gyroscope and accelerometer. The ADC output
goes through a Decimation Filter that has fixed bandwidth of 32 kHz for ICM-40609-D. Other components of the
signal path are described below in further detail.
5.1 NOTCH FILTER
The Notch Filter is supported only for the gyroscope signal path. The following steps can be used to program the
notch filter. Note that the notch filter is specific to each axis in the gyroscope, so the X, Y, and Z axis can be
programmed independently.
5.1.1
Frequency of Notch Filter (each axis)
To operate the Notch filter, two parameters NF_COSWZ, and NF_COSWZ_SEL must be programmed for each
gyroscope axis.
Parameters NF_COSWZ are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ (register bank 1, register
0x0Fh & register 0x12h), GYRO_Y_NF_COSWZ (register bank 1, register 0x10h & register 0x12h),
GYRO_Z_NF_COSWZ (register bank 1, register 0x11h & register 0x12h). Note that the parameters have 9-bit values
across two different registers.
Parameters NF_COSWZ_SEL are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ_SEL (register bank
1, register 0x12h, bit 3), GYRO_Y_NF_COSWZ_SEL (register bank 1, register 0x12h, bit 4), GYRO_Z_NF_COSWZ_SEL
(register bank 1, register 0x12h, bit 5).
Each value must be calculated using the steps described below and programmed into the corresponding register
locations mentioned above.
fdesired is the desired frequency of the Notch Filter in kHz. The lower bound for fdesired is 1 kHz, and the upper
bound is 3 kHz. Operating the notch filter outside this range is not supported.
Step1: COSWZ = cos(2*pi*fdesired/32)
Step2:
If abs(COSWZ)≤0.875
NF_COSWZ = round[COSWZ*256]
NF_COSWZ_SEL = 0
else
NF_COSWZ_SEL = 1
if COSWZ > 0.875
NF_COSWZ = round [8*(1-COSWZ)*256]
else if COSWZ < -0.875
NF_COSWZ = round [-8*(1+COSWZ)*256]
end
End
Page 24 of 86
Document Number: DS-000330
Revision: 1.2
ICM-40609-D
5.1.2
Bandwidth of Notch Filter (common to all axes)
The notch filter allows the user to control the width of the notch from eight possible values using a 3-bit parameter
GYRO_NF_BW_SEL in register bank 1, register 0x13h, bits 6:4. This parameter is common to all three axes.
GYRO_NF_BW_SEL
Notch Filter Bandwidth (Hz)
0
1
2
3
4
5
6
7
1449
680
329
162
80
40
20
10
The notch filter can be selected or bypassed by using the parameter GYRO_NF_DIS in register bank 1, register
0x0Bh, bit 0 as shown below.
GYRO_NF_DIS
Function
0
1
Enable notch filter
Disable notch filter
5.2 ANTI-ALIAS FILTER
Anti-alias filters for gyroscope and accelerometer can be independently programmed to have bandwidths ranging
from 10 Hz to 995 Hz. To program the anti-alias filter for a required bandwidth, use the table below to map the
bandwidth to register values as shown:
a. Register bank 2, register 0x03h, bits 6:1, ACCEL_AAF_DELT: Code from 1 to 63 that allows
programming the bandwidth for accelerometer anti-alias filter
b. Register bank 2, register 0x04h, bits 7:0 and Bank 2, register 0x05h, bits 3:0,
ACCEL_AAF_DELTSQR: Square of the delt value for accelerometer
c. Register bank 2, register 0x05h, bits 7:4, ACCEL_AAF_BITSHIFT: Bitshift value for accelerometer
used in hardware implementation
d. Register bank 1, register 0x0Ch, bits 5:0, GYRO_AAF_DELT: Code from 1 to 63 that allows
programming the bandwidth for gyroscope anti-alias filter
e. Register bank 1, register 0x0Dh, bits 7:0 and Bank 1, register 0x0Eh, bits 3:0,
GYRO_AAF_DELTSQR: Square of the delt value for gyroscope
f. Register bank 1, register 0x0Eh, bits 7:4, GYRO_AAF_BITSHIFT: Bitshift value for gyroscope used
in hardware implementation
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ICM-40609-D
ACCEL_AAF_DELT; ACCEL_AAF_DELTSQR; ACCEL_AAF_BITSHIFT;
GYRO_AAF_DELT GYRO_AAF_DELTSQR GYRO_AAF_BITSHIFT
3dB Bandwidth (Hz)
42
1
2
3
4
5
6
7
1
4
9
16
25
36
49
15
13
12
11
10
10
9
84
126
170
213
258
303
348
8
64
9
394
9
81
9
441
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
100
122
144
170
196
224
256
288
324
360
400
440
488
528
576
624
680
736
784
848
896
960
1024
1088
1152
1232
1296
1376
1440
1536
1600
8
8
8
8
7
7
7
7
7
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
4
4
4
4
488
536
585
634
684
734
785
837
890
943
997
1051
1107
1163
1220
1277
1336
1395
1454
1515
1577
1639
1702
1766
1830
1896
1962
2029
2097
2166
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Revision: 1.2
ICM-40609-D
2235
2306
2377
2449
2522
2596
2671
2746
2823
2900
2978
3057
3137
3217
3299
3381
3464
3548
3633
3718
3805
3892
3979
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
1696
1760
1856
1952
2016
2112
2208
2304
2400
2496
2592
2720
2816
2944
3008
3136
3264
3392
3456
3584
3712
3840
3968
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
The anti-alias filter can be selected or bypassed for the gyroscope by using the parameter GYRO_AAF_DIS in
register bank 1, register 0x0Bh, bit 1 as shown below.
GYRO_AAF_DIS
Function
0
1
Enable gyroscope anti-aliasing filter
Disable gyroscope anti-aliasing filter
The anti-alias filter can be selected or bypassed for the accelerometer by using the parameter ACCEL_AAF_DIS in
register bank 2, register 0x03h, bit 0 as shown below.
ACCEL_AAF_DIS
Function
0
1
Enable accelerometer anti-aliasing filter
Disable accelerometer anti-aliasing filter
5.3 USER PROGRAMMABLE OFFSET
Gyroscope and accelerometer offsets can be programmed by the user by using registers OFFSET_USER0, through
OFFSET_USER8, in bank 0, registers 0x77h through 0x7Fh (bank 4) as shown below.
Page 27 of 86
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Revision: 1.2
ICM-40609-D
REGISTER ADDRESS
REGISTER NAME
BITS
7:0
3:0
7:4
7:0
7:0
3:0
7:4
7:0
7:0
3:0
7:4
7:0
FUNCTION
Lower bits of X-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of X-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of Y-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Lower bits of Y-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Lower bits of Z-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of Z-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of X-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Lower bits of X-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Lower bits of Y-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Upper bits of Y-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Upper bits of Z-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
0x77h
OFFSET_USER0
0x78h
OFFSET_USER1
0x79h
0x7Ah
OFFSET_USER2
OFFSET_USER3
0x7Bh
OFFSET_USER4
0x7Ch
0x7Dh
OFFSET_USER5
OFFSET_USER6
0x7Eh
OFFSET_USER7
OFFSET_USER8
Lower bits of Z-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
0x7Fh
5.4 UI FILTER BLOCK
The UI filter block can be programmed to select filter order and bandwidth independently for gyroscope and
accelerometer.
Gyroscope filter order can be selected by programming the parameter GYRO_UI_FILT_ORD in register bank 0,
register 0x51h, bits 3:2, as shown below.
GYRO_UI_FILT_ORD
Filter Order
00
01
10
11
1st order
2nd order
3rd order
Reserved
Accelerometer filter order can be selected by programming the parameter ACCEL_UI_FILT_ORD in register bank 0,
register 0x53h, bits 4:3, as shown below.
ACCEL_UI_FILT_ORD
Filter Order
00
01
10
11
1st order
2nd order
3rd order
Reserved
Page 28 of 86
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Revision: 1.2
ICM-40609-D
Gyroscope and accelerometer filter 3dB bandwidth can be selected by programming the parameter
GYRO_UI_FILT_BW in register bank 0, register 0x52h, bits 3:0, and the parameter ACCEL_UI_FILT_BW in register
bank 0, register 0x52h, bits 7:4, as shown below. The values shown in bold correspond to low noise and the values
shown in italics correspond to low latency. User can select the appropriate setting based on the application
requirements for power and latency. Corresponding Noise Bandwidth (NBW) and Group Delay values are also
shown.
5.4.1
1st Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
ODR(Hz)
32000
16000
8000
4000
2000
1000
500
0
1
2
3
4
5
6
7
14
15
GYRO/ACCEL_ODR
1
2
3
4
5
8400.0
4194.1
2096.3
1048.1
524.0
6
498.3 227.2 188.9 111.0 92.4 59.6 48.8 23.9 262.0 2096.3
249.1 113.6
15
7
94.4
75.5
75.5
75.5
75.5
75.5
55.5 46.2 29.8 24.4 11.9 131.0 1048.1
200
100
50
25
99.6
49.8
24.9
12.5
12.5
90.9
90.9
90.9
90.9
90.9
44.4 37.0 23.8 19.5 9.6 104.8
44.4 37.0 23.8 19.5 9.6 104.8
44.4 37.0 23.8 19.5 9.6 104.8
44.4 37.0 23.8 19.5 9.6 104.8
419.2
209.6
104.8
52.4
8
9
10
11
12.5
44.4 37.0 23.8 19.5
9.6 104.8
52.4
NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
ODR(Hz)
32000
16000
8000
4000
2000
1000
500
0
1
2
3
4
5
6
7
14
15
GYRO/ACCEL_ODR
1
2
3
4
5
8831.7
4410.6
2204.6
1102.2
551.1
6
551.1 230.8 196.3 126.5 108.9 75.8 64.1 34.1 275.6 2204.6
280.5 115.4
15
7
98.2
78.5
78.5
78.5
78.5
78.5
63.3
50.6
50.6
50.6
50.6
50.6
54.5 37.9 32.1 17.1 137.8 1102.2
200
100
50
25
112.2
56.1
28.1
14.1
14.1
92.4
92.4
92.4
92.4
92.4
43.6 30.3 25.7 13.7 110.3
43.6 30.3 25.7 13.7 110.3
43.6 30.3 25.7 13.7 110.3
43.6 30.3 25.7 13.7 110.3
43.6 30.3 25.7 13.7 110.3
440.9
220.5
110.3
55.2
8
9
10
11
12.5
55.2
Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
ODR(Hz)
32000
0
1
2
3
4
5
0.1
6
7
14
15
GYRO/ACCEL_ODR
1
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ICM-40609-D
2
3
4
5
6
16000
8000
4000
2000
1000
500
200
100
50
25
0.1
0.2
0.4
0.8
0.6 1.8 2.0 2.8 3.1
1.1 3.6 4.0 5.5 6.1
2.7 4.4 5.0 6.8 7.6
5.3 4.4 5.0 6.8 7.6
10.5 4.4 5.0 6.8 7.6
21.0 4.4 5.0 6.8 7.6
21.0 4.4 5.0 6.8 7.6
4.1
8.1
4.7
9.3
8.1 1.5 0.2
16.2 3.0 0.4
20.3 3.8 1.0
20.3 3.8 1.9
20.3 3.8 3.8
20.3 3.8 7.5
20.3 3.8 7.5
15
7
10.2
10.2
10.2
10.2
10.2
11.7
11.7
11.7
11.7
11.7
8
9
10
11
12.5
5.4.2
2nd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
ODR(Hz)
32000
16000
8000
4000
2000
1000
500
GYRO/ACCEL_ODR
0
1
2
3
4
5
6
7
14
15
1
2
3
4
5
8400.0
4194.1
2096.3
1048.1
524.0
6
493.3 230.7 191.6 117.5
246.7 115.3
97.1 59.6 48.0 21.3 262.0 2096.3
48.5 29.8 24.0 10.6 131.0 1048.1
38.8 23.8 19.2 8.5 104.8
38.8 23.8 19.2 8.5 104.8
38.8 23.8 19.2 8.5 104.8
38.8 23.8 19.2 8.5 104.8
15
7
95.8
76.6
76.6
76.6
76.6
76.6
58.8
47.0
47.0
47.0
47.0
47.0
200
100
50
25
98.7
49.3
24.7
12.3
12.3
92.3
92.3
92.3
92.3
92.3
419.2
209.6
104.8
52.4
8
9
10
11
12.5
38.8 23.8 19.2
8.5 104.8
52.4
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ICM-40609-D
NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
ODR(Hz)
32000
16000
8000
4000
2000
1000
500
GYRO/ACCEL_ODR
0
1
2
3
4
5
6
7
14
15
1
2
3
4
5
8831.7
4410.6
2204.6
1102.2
551.1
6
551.1 223.7 189.9 122.7 102.8 64.7 52.5 23.7 275.6 2204.6
259.6 111.9
15
7
95.0
76.0
76.0
76.0
76.0
76.0
61.4
49.1
49.1
49.1
49.1
49.1
51.4 32.4 26.3 11.9 137.8 1102.2
200
100
50
25
103.9
52.0
26.0
13.0
13.0
89.5
89.5
89.5
89.5
89.5
41.2 25.9 21.0 9.5 110.3
41.2 25.9 21.0 9.5 110.3
41.2 25.9 21.0 9.5 110.3
41.2 25.9 21.0 9.5 110.3
440.9
220.5
110.3
55.2
8
9
10
11
12.5
41.2 25.9 21.0
9.5 110.3
55.2
Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
0
1
2
3
4
5
6
7
14
15
1
2
3
4
5
32000
16000
8000
4000
2000
1000
500
200
100
50
25
0.1
0.1
0.2
0.4
0.8
6
0.7 2.1 2.4 3.2 3.7
1.3 4.1 4.7 6.4 7.3
3.3 5.1 5.8 8.0 9.1
6.5 5.1 5.8 8.0 9.1
12.9 5.1 5.8 8.0 9.1
25.7 5.1 5.8 8.0 9.1
25.7 5.1 5.8 8.0 9.1
5.2
6.1
12.0 1.5 0.2
24.0 3.0 0.4
30.0 3.8 1.0
30.0 3.8 1.9
30.0 3.8 3.8
30.0 3.8 7.5
30.0 3.8 7.5
15
7
10.4
12.9
12.9
12.9
12.9
12.9
12.2
15.3
15.3
15.3
15.3
15.3
8
9
10
11
12.5
Page 31 of 86
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5.4.3
3rd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=2 (3rd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
32000
16000
8000
4000
2000
1000
500
200
100
50
25
0
1
2
3
4
5
6
7
14
15
1
2
3
4
5
8400.0
4194.1
2096.3
1048.1
524.0
6
492.9 234.7 195.8 118.9 97.9 60.8 46.8 25.2 262.0 2096.3
246.4 117.4
15
7
97.9
78.3
78.3
78.3
78.3
78.3
59.5 48.9 30.4 23.4 12.6 131.0 1048.1
98.6
49.3
24.6
12.3
12.3
93.9
93.9
93.9
93.9
93.9
47.6 39.2 24.3 18.7 10.1 104.8
47.6 39.2 24.3 18.7 10.1 104.8
47.6 39.2 24.3 18.7 10.1 104.8
47.6 39.2 24.3 18.7 10.1 104.8
47.6 39.2 24.3 18.7 10.1 104.8
419.2
209.6
104.8
52.4
8
9
10
11
12.5
52.4
NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR ODR(Hz)
0
1
2
3
4
5
6
7
14
15
1
2
3
4
5
32000
16000
8000
4000
2000
1000
500
200
100
50
25
8831.7
4410.6
2204.6
1102.2
551.1
6
551.1 221.3 188.5 120.1 100.0 62.9 48.6 26.4 275.6 2204.6
15
7
252.0 110.7
94.3
75.4
75.4
75.4
75.4
75.4
60.1
48.1
48.1
48.1
48.1
48.1
50.0 31.5 24.3 13.2 137.8 1102.2
100.8
50.4
25.2
12.6
12.6
88.6
88.6
88.6
88.6
88.6
40.0 25.2 19.5 10.6 110.3
40.0 25.2 19.5 10.6 110.3
40.0 25.2 19.5 10.6 110.3
40.0 25.2 19.5 10.6 110.3
40.0 25.2 19.5 10.6 110.3
440.9
220.5
110.3
55.2
8
9
10
11
12.5
55.2
Page 32 of 86
Document Number: DS-000330
Revision: 1.2
ICM-40609-D
Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=2 (3rd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
32000
16000
8000
4000
2000
1000
500
200
100
50
25
0
1
2
3
4
5
6
7
14
15
1
2
3
4
5
0.1
0.1
0.2
0.4
0.8
6
0.8 2.3 2.7 4.0
1.6 4.6 5.4 7.9
4.0 5.8 6.8 9.8
8.0 5.8 6.8 9.8
15.9 5.8 6.8 9.8
31.8 5.8 6.8 9.8
31.8 5.8 6.8 9.8
4.6
6.6
8.2
14.1 1.5 0.2
28.1 3.0 0.4
35.2 3.8 1.0
35.2 3.8 1.9
35.2 3.8 3.8
35.2 3.8 7.5
35.2 3.8 7.5
15
7
9.2
11.4
11.4
11.4
11.4
11.4
13.2
16.5
16.5
16.5
16.5
16.5
16.3
20.4
20.4
20.4
20.4
20.4
8
9
10
11
12.5
5.5 ODR AND FSR SELECTION
Gyroscope ODR can be selected by programming the parameter GYRO_ODR in register bank 0, register 0x4Fh, bits
3:0 as shown below.
GYRO_ODR
Gyroscope ODR Value
Reserved
32 kHz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
16 kHz
8 kHz
4 kHz
2 kHz
1 kHz (default)
200 Hz
100 Hz
50 Hz
25 Hz
12.5 Hz
Reserved
Reserved
Reserved
500 Hz
Page 33 of 86
Document Number: DS-000330
Revision: 1.2
ICM-40609-D
Gyroscope FSR can be selected by programming the parameter GYRO_FS_SEL in register bank 0, register 0x4Fh,
bits 7:5 as shown below.
GYRO_FS_SEL
Gyroscope FSR Value
000
001
010
011
100
101
110
111
±2000 dps
±1000 dps
±500 dps
±250 dps
±125 dps
±62.5 dps
±31.25 dps
±15.625 dps
Accelerometer ODR can be selected by programming the parameter ACCEL_ODR in register bank 0, register 0x50h,
bits 3:0 as shown below.
ACCEL_ODR
Accelerometer ODR Value
Reserved
32 kHz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
16 kHz
8 kHz
4 kHz
2 kHz
1 kHz (default)
200 Hz
100 Hz
50 Hz
25 Hz
12.5 Hz
6.25 Hz
3.125 Hz
1.5625 Hz
500 Hz
Page 34 of 86
Document Number: DS-000330
Revision: 1.2
ICM-40609-D
Accelerometer FSR can be selected by programming the parameter ACCEL_FS_SEL in register bank 0, register
0x50h, bits 7:5 as shown below.
ACCEL_FS_SEL
Accelerometer FSR Value
000
001
010
011
100
101
110
111
±32g
±16g
±8g
±4g
Reserved
Reserved
Reserved
Reserved
Page 35 of 86
Document Number: DS-000330
Revision: 1.2
ICM-40609-D
6 FIFO
The ICM-40609-D contains a 2 KB FIFO register that is accessible via the serial interface. The FIFO configuration
register determines which data is written into the FIFO. Possible choices include gyroscope data, accelerometer
data, temperature readings, and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are
contained in the FIFO.
6.1 PACKET STRUCTURE
The following figure shows the FIFO packet structures supported in ICM-40609-D.
Header
(1 byte)
Header
(1 byte)
Header
(1 byte)
Accelerometer Data
(6 bytes)
Gyroscope Data
(6 bytes)
Accelerometer Data
(6 bytes)
Temperature Data
(1 byte)
Temperature Data
(1 byte)
Gyroscope Data
(6 bytes)
Packet 1
Packet 2
Temperature Data
(1 byte)
TimeStamp
(2 bytes)
Packet 3
Figure 11. FIFO Packet Structure
The rest of this sub-section describes how individual data is packaged in the different FIFO packet structures.
Packet 1: Individual data is packaged in Packet 1 as shown below.
Byte
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Content
FIFO Header
Accel X [15:8]
Accel X [7:0]
Accel Y [15:8]
Accel Y [7:0]
Accel Z [15:8]
Accel Z [7:0]
Temperature[7:0]
Page 36 of 86
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Revision: 1.2
ICM-40609-D
Packet 2: Individual data is packaged in Packet 2 as shown below.
Byte
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Content
FIFO Header
Gyro X [15:8]
Gyro X [7:0]
Gyro Y [15:8]
Gyro Y [7:0]
Gyro Z [15:8]
Gyro Z [7:0]
Temperature[7:0]
Packet 3: Individual data is packaged in Packet 3 as shown below.
Byte
Content
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
FIFO Header
Accel X [15:8]
Accel X [7:0]
Accel Y [15:8]
Accel Y [7:0]
Accel Z [15:8]
Accel Z [7:0]
Gyro X [15:8]
Gyro X [7:0]
Gyro Y [15:8]
Gyro Y [7:0]
Gyro Z [15:8]
Gyro Z [7:0]
Temperature[7:0]
TimeStamp[15:8]
TimeStamp[7:0]
6.2 FIFO HEADER
The following table shows the structure of the 1-byte FIFO header.
BIT FIELD
ITEM
DESCRIPTION
1: FIFO is empty
0: Packet contains sensor data
7
HEADER_MSG
1: Packet is sized so that accel data have location in the packet, FIFO_ACCEL_EN
must be 1
0: Packet does not contain accel sample
1: Packet is sized so that gyro data have location in the packet, FIFO_GYRO_EN must
6
5
HEADER_ACCEL
HEADER_GYRO
be 1
0: Packet does not contain gyro sample
00: Packet does not contain timestamp or FSYNC time data
01: Reserved
3:2
1
HEADER_TIMESTAMP_FSYNC 10: Packet contains ODR Timestamp
11: Packet contains FSYNC time, and this packet is flagged as first ODR after FSYNC
(only if FIFO_TMST_FSYNC_EN is 1)
1: The ODR for accel is different for this accel data packet compared to the previous
accel packet
HEADER_ODR_ACCEL
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ICM-40609-D
0: The ODR for accel is the same as the previous packet with accel
1: The ODR for gyro is different for this gyro data packet compared to the previous
gyro packet
0
HEADER_ODR_GYRO
0: The ODR for gyro is the same as the previous packet with gyro
Note at least HEADER_ACCEL or HEADER_GYRO must be set for a sensor data packet to be set.
6.3 MAXIMUM FIFO STORAGE
The maximum number of packets that can be stored in FIFO is a variable quantity depending on the use case. As
shown in the figure below, the physical FIFO size is 2048 bytes. A number of bytes equal to the packet size selected
(see section 6.1) is reserved to prevent reading a packet during write operation. Additionally, a read cache 2
packets wide is available.
When there is no serial interface operation, the read cache is not available for storing packets, being fed by the
serial interface clock.
When serial interface operation happens, depending on the operation length and the packet size chosen, either 1
or 2 of the packet entries in read cache may become available for storing packets. In that case the total storage
available is up to the maximum number of packets that can be accommodated in 2048 bytes + 1 packet size,
depending on the packet size used.
Due to the non-deterministic nature of system operation, driver memory allocation should always be the largest
size of 2080 bytes.
2 Packet Size
FIFO 2048 Bytes
Read Cache
2048 Bytes – 1 packet size
1 Packet Size
Reserved to prevent reading a
packet during write operation
Figure 12. Maximum FIFO Storage
6.4 FIFO CONFIGURATION REGISTERS
The following control bits in bank 0, register 0x5Fh determine what data is placed into the FIFO. The values of
these bits may change while the FIFO is being filled without corruption of the FIFO.
BIT
NAME
FUNCTION
0: FIFO will only contain ODR timestamp information
1: FIFO can also contain FSYNC time and FSYNC tag for one ODR after an
FSYNC event
3
FIFO_TMST_FSYNC_EN
0: Default setting; Gyroscope data not placed into FIFO
1: Enables gyroscope data packets of 6-bytes to be placed in FIFO
0: Default setting; Accelerometer data not placed into FIFO
1: Enables accelerometer data packets of 6-bytes to be placed in FIFO
1
0
FIFO_GYRO_EN
FIFO_ACCEL_EN
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ICM-40609-D
Configuration register settings above impact FIFO header and FIFO packet size as follows:
FIFO_TMST_
FSYNC_EN
FIFO_ACCEL_EN FIFO_GYRO_EN
Header
Packet size
1
1
1
0
0
1
1
0
1
0
0
1
X
X
X
8’b_0110_10xx
8’b_0110_1xxx
8’b_0100_00xx
8’b_0010_00xx
No FIFO writes
16 Bytes
16 Bytes
8 Bytes
8 Bytes
No FIFO writes
Page 39 of 86
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ICM-40609-D
7 PROGRAMMABLE INTERRUPTS
The ICM-40609-D has a programmable interrupt system that can generate an interrupt signal on the INT pins.
Status flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. There
are two interrupt outputs. Any interrupt may be mapped to either interrupt pin as explained in the register
section. The following configuration options are available for the interrupts
•
•
•
INT1 and INT2 can be push-pull or open drain
Level or pulse mode
Active high or active low
7.1 WAKE-ON MOTION INTERRUPT
The ICM-40609-D provides motion detection capability. A qualifying motion sample is one where the high passed
sample from any axis has an absolute value exceeding a user-programmable threshold. The following steps explain
how to configure the Wake-on-Motion Interrupt.
•
Wake on Motion configuration parameters
1. WOM_X_TH (Register 0x4Ah in Bank 4)
2. WOM_Y_TH (Register 0x4Bh in Bank 4)
3. WOM_Z_TH (Register 0x4Ch in Bank 4)
4. WOM_INT_MODE (Register 0x57h in Bank 0)
5. WOM_MODE (Register 0x57h in Bank 0)
6. WOM_MODE1 (Register 0x57h in Bank 0)
•
•
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 9 for 50 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Wait 1 millisecond
Initialize Wake on Motion hardware
1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4)
2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4)
3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4)
4. Wait 1 millisecond
5. Set WOM_INT_MODE to 0 (Register 0x57h in Bank 0)
6. Set WOM_MODE to 1 (Register 0x57h in Bank 0)
7. Set WOM_MODE1 to 1 (Register 0x57h in Bank 0)
8. Wait 1 millisecond
9. Enable all 3 axes as WOM sources for INT1 by setting bits 2:0 in register INT_SOURCE1
(Register 0x66h in Bank 0) to 1. Or if INT2 is selected for WOM, enable all 3 axes as WOM
sources by setting bits 2:0 in register INT_SOURCE4 (Register 0x69h in Bank 0) to 1.
10. Wait 50 milliseconds
•
Output registers
1. Read interrupt register (Register 0x37h in Bank 0) for WOM_X_INT
2. Read interrupt register (Register 0x37h in Bank 0) for WOM_Y_INT
3. Read interrupt register (Register 0x37h in Bank 0) for WOM_Z_INT
Page 40 of 86
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ICM-40609-D
8 DIGITAL INTERFACE
8.1 I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICM-40609-D can be accessed using I2C at 1 MHz or SPI at 24 MHz. SPI
operates in 3-wire or 4-wire mode. Pin assignments for serial interfaces are described in Section 4.1.
8.2 I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are
open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or a
slave. The master device puts the slave address on the bus, and the slave device with the matching address
acknowledges the master.
The ICM-40609-D always operates as a slave device when communicating to the system processor, which thus acts
as the master. SDA and SCL lines typically need pull-up resistors to VDDIO. The maximum bus speed is 1 MHz.
The slave address of the ICM-40609-D is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is
determined by the logic level on pin AP_AD0. This allows two ICM-40609-Ds to be connected to the same I2C bus.
When used in this configuration, the address of one of the devices should be b1101000 (pin AP_AD0 is logic low)
and the address of the other should be b1101001 (pin AP_AD0 is logic high).
8.3 I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as
a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be
busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the
SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
P
START condition
STOP condition
Figure 13. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data
transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge
signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA
and holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it
can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready,
and releases the clock line (refer to the following figure).
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ICM-40609-D
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
8
SCL FROM
MASTER
1
2
9
clock pulse for
acknowledgement
START
condition
Figure 14. Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by
an 8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to
the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave
device. Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the
SDA line LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the
master with a STOP condition (P), thus freeing the communications line. However, the master can generate a
repeated START condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to
HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place
when SCL is low, with the exception of start and stop conditions.
SDA
SCL
1 – 7
8
9
1 – 7
8
9
1 – 7
8
9
S
P
START
STOP
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
condition
condition
Figure 15. Complete I2C Data Transfer
To write the internal ICM-40609-D registers, the master transmits the start condition (S), followed by the I2C
address and the write bit (0). At the 9th clock cycle (when the clock is high), the ICM-40609-D acknowledges the
transfer. Then the master puts the register address (RA) on the bus. After the ICM-40609-D acknowledges the
reception of the register address, the master puts the register data onto the bus. This is followed by the ACK signal,
and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the
master can continue outputting data rather than transmitting a stop signal. In this case, the ICM-40609-D
automatically increments the register address and loads the data to the appropriate register. The following figures
show single and two-byte write sequences.
Single-Byte Write Sequence
Master
Slave
S
AD+W
RA
DATA
P
ACK
ACK
ACK
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ICM-40609-D
Burst Write Sequence
Master
Slave
S
AD+W
RA
DATA
DATA
P
ACK
ACK
ACK
ACK
To read the internal ICM-40609-D registers, the master sends a start condition, followed by the I2C address and a
write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the ICM-
40609-D, the master transmits a start signal followed by the slave address and read bit. As a result, the ICM-40609-
D sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit
from master. The NACK condition is defined such that the SDA line remains high at the 9th clock cycle. The
following figures show single- and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
RA
RA
S
AD+R
AD+R
NACK
P
ACK
ACK
ACK
ACK
ACK
DATA
Burst Read Sequence
Master
Slave
S
AD+W
S
ACK
NACK
P
ACK DATA
DATA
8.4 I2C TERMS
Signal
Description
S
AD
W
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
Write bit (0)
R
ACK
Read bit (1)
Acknowledge: SDA line is low while the SCL line is high at the 9th clock
cycle
NACK
RA
Not-Acknowledge: SDA line stays high at the 9th clock cycle
ICM-40609-D internal register address
DATA
P
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 12. I2C Terms
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ICM-40609-D
8.5 SPI INTERFACE
The ICM-40609-D supports 3-wire or 4-wire SPI for the host interface. The ICM-40609-D always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO), the Serial Data Input
(SDI), and the Serial Data IO (SDIO) are shared among the Slave devices. Each SPI slave device requires its own Chip
Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active
at a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices
are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interfere
with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 24 MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first
byte contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first
byte contains the Read/Write bit and indicates the Read (1) or Write (0) operation. The following 7 bits
contain the Register Address. In cases of multiple-byte Read/Writes, data is two or more bytes:
SPI Address format
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
SPI Data format
MSB
LSB
D7
D6 D5 D4 D3 D2 D1 D0
6. Supports Single or Burst Read/Writes.
SCLK
SDIO
SPI Master
SPI Slave 1
CS1
CS2
nCS
SCLK
SDIO
SPI Slave 2
nCS
Figure 16. Typical SPI Master/Slave Configuration
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ICM-40609-D
9 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS)
gyros packaged in LGA package.
9.1 ORIENTATION OF AXES
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1
identifier (•) in the figure.
+Z
+Y
+Z
+Y
+X
+X
Figure 17. Orientation of Axes of Sensitivity and Polarity of Rotation
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ICM-40609-D
9.2 PACKAGE DIMENSIONS
24 Lead LGA (3x3x0.91) mm NiAu pad finish
Page 46 of 86
Document Number: DS-000330
Revision: 1.2
ICM-40609-D
DIMENSIONS IN MILLIMETERS
SYMBOLS
MIN
0.85
NOM
0.91
0.105
0.8
3
MAX
0.97
REF
REF
3.1
A
A1
A2
D
2.9
2.9
E
3
3.1
W
L
e
0.15
0.25
0.2
0.3
0.4
24
0.25
0.35
BSC
n
D1
E1
SD
SE
b
2
2
0.2
0.2
---
BSC
BSC
BSC
BSC
---
---
e1
n1
aaa
bbb
ddd
eee
fff
H
---
---
0.1
0.2
0.08
---
---
0.1
0.2
0.184
REF
REF
REF
P
S
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ICM-40609-D
10 PART NUMBER PACKAGE MARKING
The part number package marking for ICM-40609-D devices is summarized below:
Part Number
Part Number Package Marking
ICM-40609-D
I469D
TOP VIEW
I469D
XX X XX X
YYWW
Part Number
Lot Traceability Code
Y Y = Year Code
W W = Work Week
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Revision: 1.2
ICM-40609-D
11 USE NOTES
11.1 ACCELEROMETER MODE TRANSITIONS
When transitioning from accelerometer Low Power (LP) mode to accelerometer Low Noise (LN) mode, if ODR is
6.25 Hz or lower, software should change ODR to a value of 12.5 Hz or higher, because accelerometer LN mode
does not support ODR values below 12.5 Hz.
When transitioning from accelerometer LN mode to accelerometer LP mode, if ODR is greater than 500 Hz,
software should change ODR to a value of 500Hz or lower, because accelerometer LP mode does not support ODR
values above 500 Hz.
11.2 ACCELEROMETER LOW POWER (LP) MODE AVERAGING FILTER SETTING
Software drivers provided with the device use Averaging Filter setting of 16x. This setting is recommended for
meeting Android noise requirements in LP mode, and to minimize accelerometer offset variation when
transitioning from LP to Low Noise (LN) mode. 1x averaging filter can be used by following the setting configuration
shown in section 14.38.
11.3 SETTINGS FOR I2C, AND SPI OPERATION
Upon bootup the device comes up in SPI mode. The following settings should be used for I2C, and SPI operation.
Register Field
I2C Driver
Setting
SPI Driver
Setting
I2C_SLEW_RATE (bits 5:3, register DRIVE_CONFIG, address
0x13, bank 0)
SPI_SLEW_RATE (bits 2:0, register DRIVE_CONFIG, address
0x13, bank 0)
1
1
0
5
11.4 NOTCH FILTER AND ANTI-ALIAS FILTER OPERATION
Use of Notch Filter and Anti-Alias Filter is supported only for Low Noise (LN) mode operation. The host is
responsible for keeping the UI path in LN mode while Notch Filter and Anti-Alias Filter are turned on.
11.5 REGISTER VALUES MODIFICATION
The only register settings that user can modify during sensor operation are for ODR selection, FSR selection, and
sensor mode changes (register parameters GYRO_ODR, ACCEL_ODR, GYRO_FS_SEL, ACCEL_FS_SEL, GYRO_MODE,
ACCEL_MODE). User must not modify any other register values during sensor operation. The following procedure
must be used for other register values modification.
•
•
•
Turn Accel and Gyro Off
Modify register values
Turn Accel and/or Gyro On
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ICM-40609-D
12 REGISTER MAP
This section lists the register map for the ICM-40609-D, for user banks 0, 1, 2, 4.
12.1 USER BANK 0 REGISTER MAP
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SOFT_RESET_
CONFIG
11
13
14
17
19
20
DEVICE_CONFIG
DRIVE_CONFIG
INT_CONFIG
R/W
R/W
R/W
-
SPI_MODE
-
-
I2C_SLEW_RATE
SPI_SLEW_RATE
INT2_DRIVE_
CIRCUIT
INT2_POLARI
TY
INT1_DRIVE_
CIRCUIT
INT1_POLARI
TY
-
INT2_MODE
INT1_MODE
16
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
22
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
FIFO_CONFIG
TEMP_DATA1
R/W
FIFO_MODE
-
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
SYNCR
TEMP_DATA[15:8]
TEMP_DATA0
TEMP_DATA[7:0]
ACCEL_DATA_X[15:8]
ACCEL_DATA_X[7:0]
ACCEL_DATA_Y[15:8]
ACCEL_DATA_Y[7:0]
ACCEL_DATA_Z[15:8]
ACCEL_DATA_Z[7:0]
GYRO _DATA_X[15:8]
GYRO _DATA_X[7:0]
GYRO _DATA_Y[15:8]
GYRO _DATA_Y[7:0]
GYRO_DATA_Z[15:8]
GYRO_DATA_Z[7:0]
TMST_FSYNC_DATA[15:8]
TMST_FSYNC_DATA[7:0]
ACCEL_DATA_X1
ACCEL_DATA_X0
ACCEL_DATA_Y1
ACCEL_DATA_Y0
ACCEL_DATA_Z1
ACCEL_DATA_Z0
GYRO_DATA_X1
GYRO _DATA_X0
GYRO _DATA_Y1
GYRO _DATA_Y0
GYRO _DATA_Z1
GYRO _DATA_Z0
TMST_FSYNCH
TMST_FSYNCL
UI_FSYNC_IN
T
RESET_DONE
_INT
DATA_RDY_I
NT
FIFO_THS_IN
T
FIFO_FULL_I
NT
AGC_RDY_IN
T
2D
45
INT_STATUS
R/C
PLL_RDY_INT
2E
2F
30
37
46
47
48
55
FIFO_COUNTH
FIFO_COUNTL
FIFO_DATA
R
R
FIFO_COUNT[15:8]
FIFO_COUNT[7:0]
FIFO_DATA
R
INT_STATUS2
R/C
-
WOM_Z_INT
WOM_Y_INT
FIFO_FLUSH
WOM_X_INT
-
ABORT_AND
_RESET
TMST_STROB
E
4B
4C
4D
75
76
77
SIGNAL_PATH_RESET
INTF_CONFIG0
W/C
R/W
R/W
-
FIFO_HOLD_L
AST_DATA_E
N
FIFO_COUNT
_REC
FIFO_COUNT
_ENDIAN
SENSOR_DAT
A_ENDIAN
-
UI_SIFS_CFG
ACCEL_LP_CL
K_SEL
INTF_CONFIG1
EN_TEST_MODE
-
-
CLKSEL
4E
4F
50
51
52
53
78
79
80
81
82
83
PWR_MGMT0
GYRO_CONFIG0
R/W
R/W
R/W
R/W
R/W
R/W
-
TEMP_DIS
IDLE
GYRO_MODE
ACCEL_MODE
GYRO_FS_SEL
ACCEL_FS_SEL
TEMP_FILT_BW
-
-
-
GYRO_ODR
ACCEL_ODR
ACCEL_CONFIG0
GYRO_CONFIG1
GYRO_UI_FILT_ORD
GYRO_DEC2_M2_ORD
GYRO_ACCEL_CONFIG0
ACCEL_CONFIG1
ACCEL_UI_FILT_BW
-
GYRO_UI_FILT_BW
ACCEL_UI_FILT_ORD
ACCEL_DEC2_M2_ORD
-
TMST_TO_RE
GS_EN
TMST_DELTA
_EN
TMST_FSYNC
_EN
54
57
84
87
TMST_CONFIG
WOM_CONFIG
R/W
R/W
-
TMST_RES
TMST_EN
WOM_INT_
MODE
-
WOM_MODE
WOM_MODE1
FIFO_RESUM
E_PARTIAL_R
D
FIFO_WM_G
T_TH
FIFO_TMST_F
SYNC_EN
FIFO_TEMP_
EN
FIFO_GYRO_
EN
FIFO_ACCEL_
EN
5F
95
FIFO_CONFIG1
R/W
-
-
60
61
96
97
FIFO_CONFIG2
FIFO_CONFIG3
R/W
R/W
FIFO_WM[7:0]
-
FIFO_WM[11:8]
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ICM-40609-D
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
FSYNC_UI_FL
AG_CLEAR_S
EL
FSYNC_POLA
RITY
62
98
FSYNC_CONFIG
R/W
-
FSYNC_UI_SEL
-
63
64
99
INT_CONFIG0
INT_CONFIG1
R/W
R/W
-
UI_DRDY_INT_CLEAR
FIFO_THS_INT_CLEAR
FIFO_FULL_INT_CLEAR
INT_TPULSE_
DURATION
INT_TDEASSE
RT_DISABLE
INT_ASYNC_
RESET
100
-
-
-
UI_FSYNC_IN
T1_EN
PLL_RDY_INT
1_EN
RESET_DONE
_INT1_EN
UI_DRDY_INT
1_EN
FIFO_THS_IN
T1_EN
FIFO_FULL_I
NT1_EN
UI_AGC_RDY
_INT1_EN
65
66
68
69
101
102
104
105
INT_SOURCE0
INT_SOURCE1
INT_SOURCE3
INT_SOURCE4
R/W
R/W
R/W
R/W
WOM_Z_INT
1_EN
WOM_Y_INT
1_EN
WOM_X_INT
1_EN
-
UI_FSYNC_IN
T2_EN
PLL_RDY_INT
2_EN
RESET_DONE
_INT2_EN
UI_DRDY_INT
2_EN
FIFO_THS_IN
T2_EN
FIFO_FULL_I
NT2_EN
UI_AGC_RDY
_INT2_EN
-
WOM_Z_INT
2_EN
WOM_Y_INT
2_EN
WOM_X_INT
2_EN
-
6C
6D
108
109
FIFO_LOST_PKT0
FIFO_LOST_PKT1
R
R
FIFO_LOST_PKT_CNT[15:8]
FIFO_LOST_PKT_CNT[7:0]
ACCEL_ST_P
OWER
70
112
SELF_TEST_CONFIG
R/W
EN_AZ_ST
-
EN_AY_ST
EN_AX_ST
EN_GZ_ST
EN_GY_ST
BANK_SEL
EN_GX_ST
75
76
117
118
WHO_AM_I
R
WHOAMI
REG_BANK_SEL
R/W
12.2 USER BANK 1 REGISTER MAP
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
SENSOR_CONFIG0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
03
0B
03
11
R/W
R/W
-
-
ZG_DISABLE
YG_DISABLE
XG_DISABLE
ZA_DISABLE
YA_DISABLE
XA_DISABLE
GYRO_AAF_D
IS
GYRO_NF_DI
S
GYRO_CONFIG_STATIC2
-
0C
0D
0E
0F
10
11
12
13
14
15
16
17
GYRO_CONFIG_STATIC3
GYRO_CONFIG_STATIC4
GYRO_CONFIG_STATIC5
GYRO_CONFIG_STATIC6
GYRO_CONFIG_STATIC7
GYRO_CONFIG_STATIC8
R/W
R/W
R/W
R/W
R/W
R/W
GYRO_AAF_DELT
GYRO_AAF_DELTSQR[7:0]
GYRO_AAF_BITSHIFT
GYRO_AAF_DELTSQR[11:8]
GYRO_X_NF_COSWZ[7:0]
GYRO_Y_NF_COSWZ[7:0]
GYRO_Z_NF_COSWZ[7:0]
GYRO_Z_NF_
COSWZ_SEL[
0]
GYRO_Y_NF_
COSWZ_SEL[
0]
GYRO_X_NF_
COSWZ_SEL[
0]
GYRO_Z_NF_
COSWZ[8]
GYRO_Y_NF_
COSWZ[8]
GYRO_X_NF_
COSWZ[8]
12
13
18
19
GYRO_CONFIG_STATIC9
GYRO_CONFIG_STATIC10
R/W
R/W
-
GYRO_HPF_O
RD_IND
-
GYRO_NF_BW_SEL
GYRO_HPF_BW_IND
5F
60
61
62
63
64
95
96
XG_ST_DATA
YG_ST_DATA
ZG_ST_DATA
TMSTVAL0
R/W
R/W
R/W
R
XG_ST_DATA
YG_ST_DATA
ZG_ST_DATA
97
98
TMST_VALUE[7:0]
TMST_VALUE[15:8]
99
TMSTVAL1
R
100
TMSTVAL2
R
-
-
-
TMST_VALUE[19:16]
SPI_AP_4WIR
E
7A
7B
122
123
INTF_CONFIG4
INTF_CONFIG5
R/W
R/W
-
-
PIN19_FUNCTION
Page 51 of 86
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Revision: 1.2
ICM-40609-D
12.3 USER BANK 2 REGISTER MAP
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ACCEL_AAF_
DIS
03
03
ACCEL_CONFIG_STATIC2
R/W
-
ACCEL_AAF_DELT
04
05
3B
3C
3D
04
05
59
60
61
ACCEL_CONFIG_STATIC3
ACCEL_CONFIG_STATIC4
XA_ST_DATA
R/W
R/W
R/W
R/W
R/W
ACCEL_AAF_DELTSQR[7:0]
ACCEL_AAF_BITSHIFT
ACCEL_AAF_DELTSQR[11:8]
XA_ST_DATA
YA_ST_DATA
ZA_ST_DATA
YA_ST_DATA
ZA_ST_DATA
12.4 USER BANK 4 REGISTER MAP
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
4A
4B
4C
77
78
79
7A
7B
7C
7D
7E
7F
74
ACCEL_WOM_X_THR
ACCEL_WOM_Y_THR
ACCEL_WOM_Z_THR
OFFSET_USER0
OFFSET_USER1
OFFSET_USER2
OFFSET_USER3
OFFSET_USER4
OFFSET_USER5
OFFSET_USER6
OFFSET_USER7
OFFSET_USER8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WOM_X_TH
WOM_Y_TH
WOM_Z_TH
75
76
119
120
121
122
123
124
125
126
127
GYRO_X_OFFUSER[7:0]
GYRO_Y_OFFUSER[11:8]
ACCEL_X_OFFUSER[11:8]
ACCEL_Z_OFFUSER[11:8]
GYRO_X_OFFUSER[11:8]
GYRO_Z_OFFUSER[11:8]
ACCEL_Y_OFFUSER[11:8]
GYRO_Y_OFFUSER[7:0]
GYRO_Z_OFFUSER[7:0]
ACCEL_X_OFFUSER[7:0]
ACCEL_Y_OFFUSER[7:0]
ACCEL_Z_OFFUSER[7:0]
Detailed register descriptions are provided in the sections that follow. Please note the following regarding Clock
Domain for each register:
1. Clock Domain: SCLK_UI means that the register is controlled from the UI interface
Register fields marked as Reserved must not be modified by the user. The Reset Value of the register can be used
to determine the default value of reserved register fields, and unless otherwise noted this default value must be
maintained even if the values of other register fields are modified by the user.
Page 52 of 86
Document Number: DS-000330
Revision: 1.2
ICM-40609-D
13 USER BANK 0 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 0.
Note: The device powers up in sleep mode.
13.1 DEVICE_CONFIG
Name: DEVICE_CONFIG
Address: 17 (11h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:5
4
-
Reserved
SPI mode selection
0: Mode 0 and Mode 3 (default)
1: Mode 1 and Mode 2
SPI_MODE
3:1
0
-
Reserved
Software reset configuration
0: Normal (default)
SOFT_RESET_CONFIG
1: Enable reset
After writing 1 to this bitfield, wait 1ms for soft reset to be effective, before
attempting any other register access
13.2 DRIVE_CONFIG
Name: DRIVE_CONFIG
Address: 19 (13h)
Serial IF: R/W
Reset value: 0x05
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:6
-
Reserved
Controls slew rate for output pin 14 in I2C mode only
000: 20ns-60ns
001: 12ns-36ns
010: 6ns-18ns
011: 4ns-12ns
5:3 I2C_SLEW_RATE
100: 2ns-6ns
101: < 2ns
110: Reserved
111: Reserved
Controls slew rate for output pin 14 in SPI mode, and for all other output
pins
000: 20ns-60ns
001: 12ns-36ns
010: 6ns-18ns
011: 4ns-12ns
100: 2ns-6ns
101: < 2ns
2:0 SPI_SLEW_RATE
110: Reserved
111: Reserved
Page 53 of 86
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Revision: 1.2
ICM-40609-D
13.3 INT_CONFIG
Name: INT_CONFIG
Address: 20 (14h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_OIS1
BIT NAME
FUNCTION
7:6
-
Reserved
INT2 interrupt mode
0: Pulsed mode
1: Latched mode
INT2 drive circuit
0: Open drain
5
INT2_MODE
4
3
2
1
0
INT2_DRIVE_CIRCUIT
INT2_POLARITY
1: Push pull
INT2 interrupt polarity
0: Active low (default)
1: Active high
INT1 interrupt mode
0: Pulsed mode
1: Latched mode
INT1 drive circuit
0: Open drain
INT1_MODE
INT1_DRIVE_CIRCUIT
INT1_POLARITY
1: Push pull
INT1 interrupt polarity
0: Active low (default)
1: Active high
13.4 FIFO_CONFIG
Name: FIFO_CONFIG
Address: 22 (16h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:6 FIFO_MODE
00: Bypass Mode (default)
01: Stream-to-FIFO Mode
10: STOP-on-FULL Mode
11: STOP-on-FULL Mode
Reserved
5:0
-
13.5 TEMP_DATA1
Name: TEMP_DATA1
Address: 29 (1Dh)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 TEMP_DATA[15:8]
Upper byte of temperature data
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Revision: 1.2
ICM-40609-D
13.6 TEMP_DATA0
Name: TEMP_DATA0
Address: 30 (1Eh)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 TEMP_DATA[7:0]
Lower byte of temperature data
Temperature data value from the sensor data registers can be converted to degrees centigrade by using the
following formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25
Temperature data stored in FIFO is an 8-bit quantity, FIFO_TEMP_DATA. It can be converted to degrees centigrade
by using the following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25
13.7 ACCEL_DATA_X1
Name: ACCEL_DATA_X1
Address: 31 (1Fh)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 ACCEL_DATA_X[15:8]
Upper byte of Accel X-axis data
13.8 ACCEL_DATA_X0
Name: ACCEL_DATA_X0
Address: 32 (20h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 ACCEL_DATA_X[7:0]
Lower byte of Accel X-axis data
13.9 ACCEL_DATA_Y1
Name: ACCEL_DATA_Y1
Address: 33 (21h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 ACCEL_DATA_Y[15:8]
Upper byte of Accel Y-axis data
13.10ACCEL_DATA_Y0
Name: ACCEL_DATA_Y0
Address: 34 (22h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
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BIT NAME
FUNCTION
7:0 ACCEL_DATA_Y[7:0]
Lower byte of Accel Y-axis data
13.11ACCEL_DATA_Z1
Name: ACCEL_DATA_Z1
Address: 35 (23h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 ACCEL_DATA_Z[15:8]
Upper byte of Accel Z-axis data
13.12ACCEL_DATA_Z0
Name: ACCEL_DATA_Z0
Address: 36 (24h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 ACCEL_DATA_Z[7:0]
Lower byte of Accel Z-axis data
13.13GYRO_DATA_X1
Name: GYRO_DATA_X1
Address: 37 (25h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 GYRO_DATA_X[15:8]
Upper byte of Gyro X-axis data
13.14GYRO_DATA_X0
Name: GYRO_DATA_X0
Address: 38 (26h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 GYRO_DATA_X[7:0]
Lower byte of Gyro X-axis data
13.15GYRO_DATA_Y1
Name: GYRO_DATA_Y1
Address: 39 (27h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 GYRO_DATA_Y[15:8]
Upper byte of Gyro Y-axis data
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Revision: 1.2
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13.16GYRO_DATA_Y0
Name: GYRO_DATA_Y0
Address: 40 (28h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 GYRO_DATA_Y[7:0]
Lower byte of Gyro Y-axis data
13.17GYRO_DATA_Z1
Name: GYRO_DATA_Z1
Address: 41 (29h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 GYRO_DATA_Z[15:8]
Upper byte of Gyro Z-axis data
13.18GYRO_DATA_Z0
Name: GYRO_DATA_Z0
Address: 42 (2Ah)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 GYRO_DATA_Z[7:0]
Lower byte of Gyro Z-axis data
13.19TMST_FSYNCH
Name: TMST_FSYNCH
Address: 43 (2Bh)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Stores the upper byte of the time delta from the rising edge of FSYNC to
the latest ODR until the UI Interface reads the FSYNC tag in the status
register
7:0 TMST_FSYNC_DATA[15:8]
13.20TMST_FSYNCL
Name: TMST_FSYNCL
Address: 44 (2Ch)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Stores the lower byte of the time delta from the rising edge of FSYNC to
the latest ODR until the UI Interface reads the FSYNC tag in the status
register
7:0 TMST_FSYNC_DATA[7:0]
Page 57 of 86
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Revision: 1.2
ICM-40609-D
13.21INT_STATUS
Name: INT_STATUS
Address: 45 (2Dh)
Serial IF: R/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7
-
Reserved
This bit automatically sets to 1 when a UI FSYNC interrupt is generated. The
bit clears to 0 after the register has been read.
6
UI_FSYNC_INT
This bit automatically sets to 1 when a PLL Ready interrupt is generated. The
bit clears to 0 after the register has been read.
This bit automatically sets to 1 when software reset is complete. The bit
clears to 0 after the register has been read.
This bit automatically sets to 1 when a Data Ready interrupt is generated.
The bit clears to 0 after the register has been read.
This bit automatically sets to 1 when the FIFO buffer reaches the threshold
value. The bit clears to 0 after the register has been read.
This bit automatically sets to 1 when the FIFO buffer is full. The bit clears to
0 after the register has been read.
5
4
3
2
1
0
PLL_RDY_INT
RESET_DONE_INT
DATA_RDY_INT
FIFO_THS_INT
FIFO_FULL_INT
AGC_RDY_INT
This bit automatically sets to 1 when an AGC Ready interrupt is generated.
The bit clears to 0 after the register has been read.
13.22FIFO_COUNTH
Name: FIFO_COUNTH
Address: 46 (2Eh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
High Bits, count indicates the number of records or bytes available in FIFO
according to FIFO_COUNT_REC setting.
Note: Must read FIFO_COUNTL to latch new data for both FIFO_COUNTH
and FIFO_COUNTL.
7:0 FIFO_COUNT[15:8]
13.23FIFO_COUNTL
Name: FIFO_COUNTL
Address: 47 (2Fh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Low Bits, count indicates the number of records or bytes available in FIFO
according to FIFO_COUNT_REC setting.
Reading this byte latches the data for both FIFO_COUNTH, and
FIFO_COUNTL.
7:0 FIFO_COUNT[7:0]
Page 58 of 86
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ICM-40609-D
13.24FIFO_DATA
Name: FIFO_DATA
Address: 48 (30h)
Serial IF: R
Reset value: 0xFF
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 FIFO_DATA
FIFO data port
13.25INT_STATUS2
Name: INT_STATUS2
Address: 55 (37h)
Serial IF: R/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:3
2
1
-
Reserved
WOM_Z_INT
WOM_Y_INT
WOM_X_INT
Wake on Motion Interrupt on Z-axis, clears on read
Wake on Motion Interrupt on Y-axis, clears on read
Wake on Motion Interrupt on X-axis, clears on read
0
13.26SIGNAL_PATH_RESET
Name: SIGNAL_PATH_RESET
Address: 75 (4Bh)
Serial IF: W/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:4
-
Reserved
When this bit is set to 1, the signal path is reset by restarting the ODR
counter and signal path controls
3
ABORT_AND_RESET
When this bit is set to 1, the time stamp counter is latched into the time
stamp register. This is a write on clear bit.
When set to 1, FIFO will get flushed.
Reserved
2
TMST_STROBE
1
0
FIFO_FLUSH
-
13.27INTF_CONFIG0
Name: INTF_CONFIG0
Address: 76 (4Ch)
Serial IF: R/W
Reset value: 0x30
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Setting 0 corresponds to the following:
Sense Registers from Power on Reset till first sample:
FIFO_HOLD_LAST_DATA_E
N
7
•
Invalid Samples Value: -32768
Sense Registers after first sample received:
Page 59 of 86
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Revision: 1.2
ICM-40609-D
•
•
Sense Registers Valid Sample Values:
o
o
o
Range limited from -32766 to +32767 when FSYNC tag is
disabled, or for sensor not selected for FSYNC tag
Range limited from -32765 to +32767 (odd values) for
sensor selected for FSYNC tag, and FSYNC is tagged
Range limited from -32766 to +32766 (even values) for
sensor selected for FSYNC tag, but FSYNC is not tagged
Sense Registers Invalid Sample Values:
o
-32768 when FSYNC tag is disabled, or for sensor not
selected for FSYNC tag, or for sensor selected for FSYNC
tag but FSYNC is not tagged
o
-32767 for sensor selected for FSYNC tag, and FSYNC is
tagged
FIFO:
•
•
Invalid Sample Value: -32768
Valid Sample Values: -32766 to +32767
Setting 1 corresponds to the following:
Sense Registers from Power on Reset till first sample:
•
Invalid Samples Value: 0
Sense Registers after first sample received:
•
•
Sense Registers Valid Sample Values:
o
o
o
Range limited from -32768 to +32767 when FSYNC tag is
disabled, or for sensor not selected for FSYNC tag
Range limited from -32767 to +32767 (odd values) for
sensor selected for FSYNC tag, and FSYNC is tagged
Range limited from -32768 to +32766 (even values) for
sensor selected for FSYNC tag, but FSYNC is not tagged
Sense Registers Invalid Sample Values:
Registers hold last valid sample until new one arrives
o
FIFO:
•
•
Invalid Sample Value: Copy last valid sample
Valid Sample Values: -32768 to +32767
0: FIFO count is reported in bytes
1: FIFO count is reported in records (1 record = 16 bytes for header + gyro +
accel + temp sensor data + time stamp, or 8 bytes for header + gyro/accel +
temp sensor data)
0: FIFO count is reported in Little Endian format
1: FIFO count is reported in Big Endian format (default)
0: Sensor data is reported in Little Endian format
1: Sensor data is reported in Big Endian format (default)
Reserved
6
5
FIFO_COUNT_REC
FIFO_COUNT_ENDIAN
4
SENSOR_DATA_ENDIAN
-
3:2
1:0 UI_SIFS_CFG
0x: Reserved
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ICM-40609-D
10: Disable SPI
11: Disable I2C
Invalid Data Generation: FIFO/Sense Registers may contain invalid data under the following conditions:
a) From power on reset to first ODR sample of any sensor (accel, gyro, temp sensor)
b) When any sensor is disabled (accel, gyro, temp sensor)
c) When accel and gyro are enabled with different ODRs. In this case, the sensor with lower ODR will
generate invalid samples when it has no new data.
Invalid data can take special values or can hold last valid sample received. For -32768 to be used as a flag for
invalid accel/gyro samples, the valid accel/gyro sample range is limited in such case as well. Bit 7 of INTF_CONFIG0
controls what values invalid (and valid) samples can take as shown above.
13.28INTF_CONFIG1
Name: INTF_CONFIG1
Address: 77 (4Dh)
Serial IF: R/W
Reset value: 0x91
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:6 EN_TEST_MODE
Enables test mode. Must be set to 01 for normal device operation.
Reserved
5:4
-
0: Accelerometer LP mode uses Wake Up oscillator clock
1: Accelerometer LP mode uses RC oscillator clock
Reserved
3
ACCEL_LP_CLK_SEL
-
2
00: Always select internal RC oscillator
01: Select PLL when available, else select RC oscillator (default)
10: Reserved
1:0 CLKSEL
11: Disable all clocks
13.29PWR_MGMT0
Name: PWR_MGMT0
Address: 78 (4Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:6
-
Reserved
0: Temperature sensor is enabled (default)
1: Temperature sensor is disabled
5
TEMP_DIS
If this bit is set to 1, the RC oscillator is powered on even if Accel and Gyro
are powered off.
Nominally this bit is set to 0, so when Accel and Gyro are powered off,
the chip will go to OFF state, since the RC oscillator will also be powered off
00: Turns gyroscope off (default)
4
IDLE
01: Places gyroscope in Standby Mode
10: Reserved
11: Places gyroscope in Low Noise (LN) Mode
3:2 GYRO_MODE
Gyroscope needs to be kept ON for a minimum of 45ms. When transitioning
from OFF to any of the other modes, do not issue any register writes for
200µs.
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ICM-40609-D
00: Turns accelerometer off (default)
01: Turns accelerometer off
10: Places accelerometer in Low Power (LP) Mode
11: Places accelerometer in Low Noise (LN) Mode
1:0 ACCEL_MODE
When transitioning from OFF to any of the other modes, do not issue any
register writes for 200µs.
13.30GYRO_CONFIG0
Name: GYRO_CONFIG0
Address: 79 (4Fh)
Serial IF: R/W
Reset value: 0x07
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Full scale select for gyroscope UI interface output
000: ±2000dps (default)
001: ±1000dps
010: ±500dps
011: ±250dps
7:5 GYRO_FS_SEL
100: ±125dps
101: ±62.5dps
110: ±31.25dps
111: ±15.625dps
Reserved
4
-
Gyroscope ODR selection for UI interface output
0000: Reserved
0001: 32kHz
0010: 16kHz
0011: 8kHz
0100: 4kHz
0101: 2kHz
0110: 1kHz (default)
0111: 200Hz
3:0 GYRO_ODR
1000: 100Hz
1001: 50Hz
1010: 25Hz
1011: 12.5Hz
1100: Reserved
1101: Reserved
1110: Reserved
1111: 500Hz
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13.31ACCEL_CONFIG0
Name: ACCEL_CONFIG0
Address: 80 (50h)
Serial IF: R/W
Reset value: 0x07
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Full scale select for accelerometer UI interface output
000: ±32g (default)
001: ±16g
010: ±8g
011: ±4g
7:5 ACCEL_FS_SEL
100: Reserved
101: Reserved
110: Reserved
111: Reserved
4
-
Reserved
Accelerometer ODR selection for UI interface output
0000: Reserved
0001: 32kHz (LN mode)
0010: 16kHz (LN mode)
0011: 8kHz (LN mode)
0100: 4kHz (LN mode)
0101: 2kHz (LN mode)
0110: 1kHz (LN mode) (default)
0111: 200Hz (LP or LN mode)
1000: 100Hz (LP or LN mode)
1001: 50Hz (LP or LN mode)
1010: 25Hz (LP or LN mode)
1011: 12.5Hz (LP or LN mode)
1100: 6.25Hz (LP mode)
1101: 3.125Hz (LP mode)
1110: 1.5625Hz (LP mode)
1111: 500Hz (LP or LN mode)
3:0 ACCEL_ODR
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13.32GYRO_CONFIG1
Name: GYRO_CONFIG1
Address: 81 (51h)
Serial IF: R/W
Reset value: 0x1A
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Sets the bandwidth of the temperature signal DLPF
000: DLPF BW = 4000Hz; DLPF Latency = 0.125ms (default)
001: DLPF BW = 170Hz; DLPF Latency = 1ms
010: DLPF BW = 82Hz; DLPF Latency = 2ms
011: DLPF BW = 40Hz; DLPF Latency = 4ms
100: DLPF BW = 20Hz; DLPF Latency = 8ms
101: DLPF BW = 10Hz; DLPF Latency = 16ms
110: DLPF BW = 5Hz; DLPF Latency = 32ms
111: DLPF BW = 5Hz; DLPF Latency = 32ms
Reserved
7:5 TEMP_FILT_BW
4
-
Selects order of GYRO UI filter
00: 1st Order
3:2 GYRO_UI_FILT_ORD
1:0 GYRO_DEC2_M2_ORD
01: 2nd Order
10: 3rd Order
11: Reserved
Selects order of GYRO DEC2_M2 Filter
00: Reserved
01: Reserved
10: 3rd Order
11: Reserved
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13.33GYRO_ACCEL_CONFIG0
Name: GYRO_ACCEL_CONFIG0
Address: 82 (52h)
Serial IF: R/W
Reset value: 0x11
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
LN Mode:
Bandwidth for Accel LPF
0 BW=ODR/2
1 BW=max(400Hz, ODR)/4 (default)
2 BW=max(400Hz, ODR)/5
3 BW=max(400Hz, ODR)/8
4 BW=max(400Hz, ODR)/10
5 BW=max(400Hz, ODR)/16
6 BW=max(400Hz, ODR)/20
7 BW=max(400Hz, ODR)/40
8 to 13: Reserved
7:4 ACCEL_UI_FILT_BW
14 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(400Hz, ODR)
15 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(200Hz, 8*ODR)
LP Mode:
0 Reserved
1 1x AVG filter (default)
2 to 5 Reserved
6 16x AVG filter
7 to 15 Reserved
LN Mode:
Bandwidth for Gyro LPF
0 BW=ODR/2
1 BW=max(400Hz, ODR)/4 (default)
2 BW=max(400Hz, ODR)/5
3 BW=max(400Hz, ODR)/8
4 BW=max(400Hz, ODR)/10
5 BW=max(400Hz, ODR)/16
6 BW=max(400Hz, ODR)/20
7 BW=max(400Hz, ODR)/40
8 to 13: Reserved
3:0 GYRO_UI_FILT_BW
14 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(400Hz, ODR)
15 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(200Hz, 8*ODR)
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13.34ACCEL_CONFIG1
Name: ACCEL_CONFIG1
Address: 83 (53h)
Serial IF: R/W
Reset value: 0x15
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:5
-
Reserved
Selects order of ACCEL UI filter
00: 1st Order
4:3
ACCEL_UI_FILT_ORD
01: 2nd Order
10: 3rd Order
11: Reserved
Order of Accelerometer DEC2_M2 filter
00: Reserved
2:1 ACCEL_DEC2_M2_ORD
01: Reserved
10: 3rd order
11: Reserved
0
-
Reserved
13.35TMST_CONFIG
Name: TMST_CONFIG
Address: 84 (54h)
Serial IF: R/W
Reset value: 0x20
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:5
-
Reserved
0: TMST_VALUE[19:0] read always returns 0s
4
TMST_TO_REGS_EN
1: TMST_VALUE[19:0] read returns timestamp value
Time Stamp resolution: When set to 0 (default), time stamp resolution is 1
µs. When set to 1, resolution is 16µs
Time Stamp delta enable: When set to 1, the time stamp field contains the
measurement of time since the last occurrence of ODR.
Time Stamp register FSYNC enable (default). When set to 1, the contents of
the Timestamp feature of FSYNC is enabled. The user also needs to select
FIFO_TMST_FSYNC_EN in order to propagate the timestamp value to the
FIFO.
3
2
TMST_RES
TMST_DELTA_EN
1
0
TMST_FSYNC_EN
TMST_EN
0: Time Stamp register disable
1: Time Stamp register enable (default)
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ICM-40609-D
13.36WOM_CONFIG
Name: WOM_CONFIG
Address: 87 (57h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:4
-
Reserved
0: Set WoM interrupt on the OR of all enabled accelerometer thresholds
1: Set WoM interrupt on the AND of all enabled accelerometer threshold
0: Initial sample is stored. Future samples are compared to initial sample
1: Compare current sample to previous sample
00: Reserved
3
WOM_INT_MODE
2
WOM_MODE
01: Set to 1 for WOM interrupt configuration
10: Reserved
1:0 WOM_MODE1
11: Reserved
13.37FIFO_CONFIG1
Name: FIFO_CONFIG1
Address: 95 (5Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7
-
Reserved
0: Partial FIFO read disabled, requires re-reading of the entire FIFO
1: FIFO read can be partial, and resume from last read point
Trigger FIFO watermark interrupt on every ODR (DMA write) if
FIFO_COUNT ≥ FIFO_WM_TH
6
FIFO_RESUME_PARTIAL_RD
5
FIFO_WM_GT_TH
4
3
2
1
0
-
Reserved
FIFO_TMST_FSYNC_EN
FIFO_TEMP_EN
FIFO_GYRO_EN
FIFO_ACCEL_EN
Must be set to 1 for all FIFO use cases when FSYNC is used
Enable temperature sensor packets to go to FIFO
Enable gyroscope packets to go to FIFO
Enable accelerometer packets to go to FIFO
13.38FIFO_CONFIG2
Name: FIFO_CONFIG2
Address: 96 (60h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Lower bits of FIFO watermark. Generate interrupt when the FIFO reaches
or exceeds FIFO_WM size in bytes or records according to
FIFO_COUNT_REC setting. FIFO_WM_EN must be zero before writing this
register. Interrupt only fires once. This register should be set to non-zero
value, before choosing this interrupt source.
7:0 FIFO_WM[7:0]
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13.39FIFO_CONFIG3
Name: FIFO_CONFIG3
Address: 97 (61h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:4
-
Reserved
Upper bits of FIFO watermark. Generate interrupt when the FIFO reaches
or exceeds FIFO_WM size in bytes or records according to
FIFO_COUNT_REC setting. FIFO_WM_EN must be zero before writing this
register. Interrupt only fires once. This register should be set to non-zero
value, before choosing this interrupt source.
3:0 FIFO_WM[11:8]
Note: Do not set FIFO_WM to value 0.
13.40FSYNC_CONFIG
Name: FSYNC_CONFIG
Address: 98 (62h)
Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7
-
Reserved
000: Do not tag FSYNC flag
001: Tag FSYNC flag to TEMP_OUT LSB
010: Tag FSYNC flag to GYRO_XOUT LSB
011: Tag FSYNC flag to GYRO_YOUT LSB
100: Tag FSYNC flag to GYRO_ZOUT LSB
101: Tag FSYNC flag to ACCEL_XOUT LSB
110: Tag FSYNC flag to ACCEL_YOUT LSB
111: Tag FSYNC flag to ACCEL_ZOUT LSB
Reserved
6:4 FSYNC_UI_SEL
3:2
1
-
0: FSYNC flag is cleared when UI sensor register is updated
1: FSYNC flag is cleared when UI interface reads the sensor register LSB of
FSYNC tagged axis
FSYNC_UI_FLAG_CLEAR_SE
L
0: Start from Rising edge of FSYNC pulse to measure FSYNC interval
1: Start from Falling edge of FSYNC pulse to measure FSYNC interval
0
FSYNC_POLARITY
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13.41INT_CONFIG0
Name: INT_CONFIG0
Address: 99 (63h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:6
-
Reserved
Data Ready Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
01: Clear on Status Bit Read
5:4 UI_DRDY_INT_CLEAR
3:2 FIFO_THS_INT_CLEAR
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read AND on FIFO data 1 byte read
FIFO Threshold Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
01: Clear on Status Bit Read
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read AND on FIFO data 1 byte read
FIFO Full Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
1:0 FIFO_FULL_INT_CLEAR
01: Clear on Status Bit Read
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read AND on FIFO data 1 byte read
13.42INT_CONFIG1
Name: INT_CONFIG1
Address: 100 (64h)
Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7
-
Reserved
Interrupt pulse duration
0: Interrupt pulse duration is 100µs. Use only if ODR < 4kHz. (Default)
1: Interrupt pulse duration is 8 µs. Required if ODR ≥ 4kHz, optional for ODR
6
INT_TPULSE_DURATION
< 4kHz.
Interrupt de-assertion duration
0: The interrupt de-assertion duration is set to a minimum of 100µs. Use
only if ODR < 4kHz. (Default)
5
INT_TDEASSERT_DISABLE
1: Disables de-assert duration. Required if ODR ≥ 4kHz, optional for ODR <
4kHz.
User should change setting to 0 from default setting of 1, for proper INT1
and INT2 pin operation
Reserved
4
INT_ASYNC_RESET
-
3:0
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13.43INT_SOURCE0
Name: INT_SOURCE0
Address: 101 (65h)
Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7
-
Reserved
0: UI FSYNC interrupt not routed to INT1
1: UI FSYNC interrupt routed to INT1
0: PLL ready interrupt not routed to INT1
1: PLL ready interrupt routed to INT1
0: Reset done interrupt not routed to INT1
1: Reset done interrupt routed to INT1
0: UI data ready interrupt not routed to INT1
1: UI data ready interrupt routed to INT1
0: FIFO threshold interrupt not routed to INT1
1: FIFO threshold interrupt routed to INT1
0: FIFO full interrupt not routed to INT1
1: FIFO full interrupt routed to INT1
6
UI_FSYNC_INT1_EN
5
4
3
2
1
0
PLL_RDY_INT1_EN
RESET_DONE_INT1_EN
UI_DRDY_INT1_EN
FIFO_THS_INT1_EN
FIFO_FULL_INT1_EN
UI_AGC_RDY_INT1_EN
0: UI AGC ready interrupt not routed to INT1
1: UI AGC ready interrupt routed to INT1
13.44INT_SOURCE1
Name: INT_SOURCE1
Address: 102 (66h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:3
-
Reserved
0: Z-axis WOM interrupt not routed to INT1
1: Z-axis WOM interrupt routed to INT1
0: Y-axis WOM interrupt not routed to INT1
1: Y-axis WOM interrupt routed to INT1
0: X-axis WOM interrupt not routed to INT1
1: X-axis WOM interrupt routed to INT1
2
WOM_Z_INT1_EN
1
0
WOM_Y_INT1_EN
WOM_X_INT1_EN
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13.45INT_SOURCE3
Name: INT_SOURCE3
Address: 104 (68h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7
-
Reserved
0: UI FSYNC interrupt not routed to INT2
1: UI FSYNC interrupt routed to INT2
0: PLL ready interrupt not routed to INT2
1: PLL ready interrupt routed to INT2
0: Reset done interrupt not routed to INT2
1: Reset done interrupt routed to INT2
0: UI data ready interrupt not routed to INT2
1: UI data ready interrupt routed to INT2
0: FIFO threshold interrupt not routed to INT2
1: FIFO threshold interrupt routed to INT2
0: FIFO full interrupt not routed to INT2
1: FIFO full interrupt routed to INT2
6
UI_FSYNC_INT2_EN
5
4
3
2
1
0
PLL_RDY_INT2_EN
RESET_DONE_INT2_EN
UI_DRDY_INT2_EN
FIFO_THS_INT2_EN
FIFO_FULL_INT2_EN
UI_AGC_RDY_INT2_EN
0: UI AGC ready interrupt not routed to INT2
1: UI AGC ready interrupt routed to INT2
13.46INT_SOURCE4
Name: INT_SOURCE4
Address: 105 (69h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:3
-
Reserved
0: Z-axis WOM interrupt not routed to INT2
1: Z-axis WOM interrupt routed to INT2
0: Y-axis WOM interrupt not routed to INT2
1: Y-axis WOM interrupt routed to INT2
0: X-axis WOM interrupt not routed to INT2
1: X-axis WOM interrupt routed to INT2
2
WOM_Z_INT2_EN
1
0
WOM_Y_INT2_EN
WOM_X_INT2_EN
13.47FIFO_LOST_PKT0
Name: FIFO_LOST_PKT0
Address: 108 (6Ch)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 FIFO_LOST_PKT_CNT[7:0]
Low byte, number of packets lost in the FIFO
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13.48FIFO_LOST_PKT1
Name: FIFO_LOST_PKT1
Address: 109 (6Dh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 FIFO_LOST_PKT_CNT[15:8] High byte, number of packets lost in the FIFO
13.49SELF_TEST_CONFIG
Name: SELF_TEST_CONFIG
Address: 112 (70h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7
-
Reserved
Set to 1 for accel self-test
Otherwise set to 0; Set to 0 after self-test is completed
Enable Z-accel self-test
Enable Y-accel self-test
Enable X-accel self-test
Enable Z-gyro self-test
Enable Y-gyro self-test
Enable X-gyro self-test
6
ACCEL_ST_POWER
5
4
3
2
1
0
EN_AZ_ST
EN_AY_ST
EN_AX_ST
EN_GZ_ST
EN_GY_ST
EN_GX_ST
13.50WHO_AM_I
Name: WHO_AM_I
Address: 117 (75h)
Serial IF: R
Reset value: 0x3B
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 WHOAMI
Register to indicate to user which device is being accessed
Description:
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default
value of the register is 0x3B. This is different from the I2C address of the device as seen on the slave I2C controller
by the applications processor.
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Revision: 1.2
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13.51REG_BANK_SEL
Note: This register is accessible from all register banks
Name: REG_BANK_SEL
Address: 118 (76h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: ALL
BIT NAME
7:3
FUNCTION
Reserved
-
Register bank selection
000: Bank 0 (default)
001: Bank 1
010: Bank 2
011: Bank 3
2:0 BANK_SEL
100: Bank 4
101: Reserved
110: Reserved
111: Reserved
Page 73 of 86
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Revision: 1.2
ICM-40609-D
14 USER BANK 1 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 1.
14.1 SENSOR_CONFIG0
Name: SENSOR_CONFIG0
Address: 03 (03h)
Serial IF: R/W
Reset value: 0x40
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:6
-
Reserved
0: Z gyroscope is on
1: Z gyroscope is disabled
5
ZG_DISABLE
0: Y gyroscope is on
1: Y gyroscope is disabled
0: X gyroscope is on
1: X gyroscope is disabled
0: Z accelerometer is on
1: Z accelerometer is disabled
0: Y accelerometer is on
1: Y accelerometer is disabled
0: X accelerometer is on
1: X accelerometer is disabled
4
3
2
1
0
YG_DISABLE
XG_DISABLE
ZA_DISABLE
YA_DISABLE
XA_DISABLE
14.2 GYRO_CONFIG_STATIC2
Name: GYRO_CONFIG_STATIC2
Address: 11 (0Bh)
Serial IF: R/W
Reset value: 0x03
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:2
1
-
Reserved
0: Enable Anti-Aliasing/Low Pass Filter
1: Disable Anti-Aliasing/Low Pass Filter (default)
0: Enable Notch Filter
GYRO_AAF_DIS
0
GYRO_NF_DIS
1: Disable Notch Filter (default)
14.3 GYRO_CONFIG_STATIC3
Name: GYRO_CONFIG_STATIC3
Address: 12 (0Ch)
Serial IF: R/W
Reset value: 0x3F
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:6
-
Reserved
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details
5:0 GYRO_AAF_DELT
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14.4 GYRO_CONFIG_STATIC4
Name: GYRO_CONFIG_STATIC4
Address: 13 (0Dh)
Serial IF: R/W
Reset value: 0x81
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details
7:0 GYRO_AAF_DELTSQR[7:0]
14.5 GYRO_CONFIG_STATIC5
Name: GYRO_CONFIG_STATIC5
Address: 14 (0Eh)
Serial IF: R/W
Reset value: 0x3F
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details
7:4 GYRO_AAF_BITSHIFT
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details
3:0 GYRO_AAF_DELTSQR[11:8]
14.6 GYRO_CONFIG_STATIC6
Name: GYRO_CONFIG_STATIC6
Address: 15 (0Fh)
Serial IF: R/W
Reset value: 0xEA
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Used for gyroscope X-axis notch filter frequency selection
See section 5.1 for details
7:0 GYRO_X_NF_COSWZ[7:0]
14.7 GYRO_CONFIG_STATIC7
Name: GYRO_CONFIG_STATIC7
Address: 16 (10h)
Serial IF: R/W
Reset value: 0x28
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Used for gyroscope Y-axis notch filter frequency selection
See section 5.1 for details
7:0 GYRO_Y_NF_COSWZ[7:0]
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14.8 GYRO_CONFIG_STATIC8
Name: GYRO_CONFIG_STATIC8
Address: 17 (11h)
Serial IF: R/W
Reset value: 0x07
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Used for gyroscope Z-axis notch filter frequency selection
See section 5.1 for details
7:0 GYRO_Z_NF_COSWZ[7:0]
14.9 GYRO_CONFIG_STATIC9
Name: GYRO_CONFIG_STATIC9
Address: 18 (12h)
Serial IF: R/W
Reset value: 0x01
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:6
5
-
Reserved
Used for gyroscope Z-axis notch filter frequency selection
See section 5.1 for details
GYRO_Z_NF_COSWZ_SEL[0]
Used for gyroscope Y-axis notch filter frequency selection
See section 5.1 for details
Used for gyroscope X-axis notch filter frequency selection
See section 5.1 for details
Used for gyroscope Z-axis notch filter frequency selection
See section 5.1 for details
Used for gyroscope Y-axis notch filter frequency selection
See section 5.1 for details
4
3
2
1
0
GYRO_Y_NF_COSWZ_SEL[0]
GYRO_X_NF_COSWZ_SEL[0]
GYRO_Z_NF_COSWZ[8]
GYRO_Y_NF_COSWZ[8]
GYRO_X_NF_COSWZ[8]
Used for gyroscope X-axis notch filter frequency selection
See section 5.1 for details
14.10GYRO_CONFIG_STATIC10
Name: GYRO_CONFIG_STATIC10
Address: 19 (13h)
Serial IF: R/W
Reset value: 0x11
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7
-
Reserved
Selects bandwidth for gyroscope notch filter
See section 5.1 for details
Selects HPF 3dB cutoff frequency bandwidth
See section 5.6 for details
Selects HPF filter order (see section 5.6 for details)
0: 1st order HPF
6:4 GYRO_NF_BW_SEL
3:1 GYRO_HPF_BW_IND
0
GYRO_HPF_ORD_IND
1: 2nd order HPF
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14.11XG_ST_DATA
Name: XG_ST_DATA
Address: 95 (5Fh)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 XG_ST_DATA
X-gyro self-test data
14.12YG_ST_DATA
Name: YG_ST_DATA
Address: 96 (60h)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 YG_ST_DATA
Y-gyro self-test data
14.13ZG_ST_DATA
Name: ZG_ST_DATA
Address: 97 (61h)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 ZG_ST_DATA
Z-gyro self-test data
14.14TMSTVAL0
Name: TMSTVAL0
Address: 98 (62h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
When TMST_STROBE is programmed, the current value of the internal
counter is latched to this register. Allows the full 20-bit precision of the time
stamp to be read back.
7:0 TMST_VALUE[7:0]
14.15TMSTVAL1
Name: TMSTVAL1
Address: 99 (63h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
When TMST_STROBE is programmed, the current value of the internal
counter is latched to this register. Allows the full 20-bit precision of the time
stamp to be read back.
7:0 TMST_VALUE[15:8]
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14.16TMSTVAL2
Name: TMSTVAL2
Address: 100 (64h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:4
-
Reserved
3:0 TMST_VALUE[19:16]
When TMST_STROBE is programmed, the current value of the internal
counter is latched to this register. Allows the full 20-bit precision of the time
stamp to be read back.
14.17INTF_CONFIG4
Name: INTF_CONFIG4
Address: 122 (7Ah)
Serial IF: R/W
Reset value: 0x02
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:2
-
Reserved
0: AP interface uses 3-wire SPI mode
1: AP interface uses 4-wire SPI mode (default)
Reserved
1
SPI_AP_4WIRE
-
0
14.18INTF_CONFIG5
Name: INTF_CONFIG5
Address: 123 (7Bh)
Serial IF: R/W
Reset value: 0x24
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:3
-
Reserved
Selects among the following functionalities for pin 9
00: INT2
2:1 PIN19_FUNCTION
01: FSYNC
10: Reserved
11: Reserved
Reserved
0
-
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15 USER BANK 2 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 2.
15.1 ACCEL_CONFIG_STATIC2
Name: ACCEL_CONFIG_STATIC2
Address: 03 (03h)
Serial IF: R/W
Reset value: 0x7F
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7
-
Reserved
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
0: Enable accelerometer anti-aliasing filter
1: Disable accelerometer anti-aliasing filter (default)
6:1 ACCEL_AAF_DELT
ACCEL_AAF_DIS
0
15.2 ACCEL_CONFIG_STATIC3
Name: ACCEL_CONFIG_STATIC3
Address: 04 (04h)
Serial IF: R/W
Reset value: 0x81
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
7:0 ACCEL_AAF_DELTSQR[7:0]
15.3 ACCEL_CONFIG_STATIC4
Name: ACCEL_CONFIG_STATIC4
Address: 05 (05h)
Serial IF: R/W
Reset value: 0x3F
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
7:4 ACCEL_AAF_BITSHIFT
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
3:0 ACCEL_AAF_DELTSQR[11:8]
15.4 XA_ST_DATA
Name: XA_ST_DATA
Address: 59 (3Bh)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 XA_ST_DATA
X-accel self-test data
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15.5 YA_ST_DATA
Name: YA_ST_DATA
Address: 60 (3Ch)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 YA_ST_DATA
Y-accel self-test data
15.6 ZA_ST_DATA
Name: ZA_ST_DATA
Address: 61 (3Dh)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 ZA_ST_DATA
Z-accel self-test data
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16 USER BANK 4 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 4.
16.1 ACCEL_WOM_X_THR
Name: ACCEL_WOM_X_THR
Address: 74 (4Ah)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Threshold value for the Wake on Motion Interrupt for X-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9mg
7:0 WOM_X_TH
16.2 ACCEL_WOM_Y_THR
Name: ACCEL_WOM_Y_THR
Address: 75 (4Bh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Threshold value for the Wake on Motion Interrupt for Y-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9mg
7:0 WOM_Y_TH
16.3 ACCEL_WOM_Z_THR
Name: ACCEL_WOM_Z_THR
Address: 76 (4Ch)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Threshold value for the Wake on Motion Interrupt for Z-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9mg
7:0 WOM_Z_TH
16.4 OFFSET_USER0
Name: OFFSET_USER0
Address: 119 (77h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Lower bits of X-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
7:0 GYRO_X_OFFUSER[7:0]
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16.5 OFFSET_USER1
Name: OFFSET_USER1
Address: 120 (78h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Upper bits of Y-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
Upper bits of X-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
7:4 GYRO_Y_OFFUSER[11:8]
3:0 GYRO_X_OFFUSER[11:8]
16.6 OFFSET_USER2
Name: OFFSET_USER2
Address: 121 (79h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Lower bits of Y-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
7:0 GYRO_Y_OFFUSER[7:0]
16.7 OFFSET_USER3
Name: OFFSET_USER3
Address: 122 (7Ah)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Lower bits of Z-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
7:0 GYRO_Z_OFFUSER[7:0]
16.8 OFFSET_USER4
Name: OFFSET_USER4
Address: 123 (7Bh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Upper bits of X-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
Upper bits of Z-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
7:4 ACCEL_X_OFFUSER[11:8]
3:0 GYRO_Z_OFFUSER[11:8]
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16.9 OFFSET_USER5
Name: OFFSET_USER5
Address: 124 (7Ch)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Lower bits of X-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
7:0 ACCEL_X_OFFUSER[7:0]
16.10OFFSET_USER6
Name: OFFSET_USER6
Address: 125 (7Dh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Lower bits of Y-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
7:0 ACCEL_Y_OFFUSER[7:0]
16.11OFFSET_USER7
Name: OFFSET_USER7
Address: 126 (7Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Upper bits of Z-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
Upper bits of Y-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
7:4 ACCEL_Z_OFFUSER[11:8]
3:0 ACCEL_Y_OFFUSER[11:8]
16.12OFFSET_USER8
Name: OFFSET_USER8
Address: 127 (7Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Lower bits of Z-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
7:0 ACCEL_Z_OFFUSER[7:0]
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ICM-40609-D
17 REFERENCE
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:
• Manufacturing Recommendations
o
o
o
o
Assembly Guidelines and Recommendations
PCB Design Guidelines and Recommendations
MEMS Handling Instructions
ESD Considerations
o
Reflow Specification
o
Storage Specifications
o
o
o
Package Marking Specification
Tape & Reel Specification
Reel & Pizza Box Label
o
Packaging
o
Representative Shipping Carton Label
• Compliance
o
o
o
Environmental Compliance
DRC Compliance
Compliance Declaration Disclaimer
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Revision: 1.2
ICM-40609-D
18 REVISION HISTORY
Revision Date
Revision
Description
08/01/2019
10/24/2019
06/07/2022
1.0
1.1
1.2
Initial Release
Updated Section 9
Formatting updates
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ICM-40609-D
This information furnished by InvenSense or its affiliates (“TDK InvenSense”) is believed to be accurate and reliable. However, no responsibility
is assumed by TDK InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use.
Specifications are subject to change without notice. TDK InvenSense reserves the right to make changes to this product, including its circuits
and software, in order to improve its design and/or performance, without prior notice. TDK InvenSense makes no warranties, neither expressed
nor implied, regarding the information and specifications contained in this document. TDK InvenSense assumes no responsibility for any claims
or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is
not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or
otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied.
Trademarks that are registered trademarks are the property of their respective companies. TDK InvenSense sensors should not be used or sold
in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life
threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear
instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2019—2022 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps,
DMP, AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and
product names may be trademarks of the respective companies with which they are associated.
©2019—2022 InvenSense. All rights reserved.
Page 86 of 86
Document Number: DS-000330
Revision: 1.2
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