MSP3430GPS_技术文档

PRELIMINARY DATA SHEET

MICRONAS

INTERMETALL

MSP 34x0G

Multistandard

Sound Processor Family

Edition Oct. 6, 1999

6251-476-3PD

MSP 34x0G

PRELIMINARY DATA SHEET

Contents

Page

Section

Title

5

6

7

1.

Introduction

1.1.

1.2.

1.3.

Features of the MSP 34x0G Family and Differences to MSPD

MSP 34x0G Version List

MSP 34x0G Versions and their Application Fields

8

2.

Functional Description

9

2.1.

Architecture of the MSP 34x0G Family

Sound IF Processing

9

2.2.

9

2.2.1.

2.2.2.

2.2.3.

2.2.4.

2.3.

Analog Sound IF Input

9

Demodulator: Standards and Features

Preprocessing of Demodulator Signals

Automatic Sound Select

Preprocessing for SCART and I²S Input Signals

Source Selection and Output Channel Matrix

Audio Baseband Processing

Automatic Volume Correction (AVC)

Loudspeaker and Headphone Outputs

Subwoofer Output

10

12

13

14

2.4.

2.5.

2.5.1.

2.5.2.

2.5.3.

2.5.4.

2.6.

Quasi-Peak Detector

SCART Signal Routing

2.6.1.

2.6.2.

2.7.

SCART DSP In and SCART Out Select

Stand-by Mode

I²S Bus Interface

2.8.

ADR Bus Interface

2.9.

Digital Control I/O Pins and Status Change Indication

Clock PLL Oscillator and Crystal Specifications

2.10.

15

16

17

18

19

22

23

24

25

26

27

3.

Control Interface

3.1.

I²C Bus Interface

3.1.1.

3.1.2.

3.1.3.

3.1.4.

3.1.4.1.

3.1.4.2.

3.1.4.3.

3.1.4.4.

3.2.

Device and Subaddresses

Description of CONTROL Register

Protocol Description

Proposals for General MSP 34x0G I²C Telegrams

Symbols

Write Telegrams

Read Telegrams

Examples

Start-Up Sequence: Power-Up and I²C Controlling

MSP 34x0G Programming Interface

User Registers Overview

3.3.

3.3.1.

3.3.2.

3.3.2.1.

3.3.2.2.

3.3.2.3.

3.3.2.4.

3.3.2.5.

3.3.2.6.

Description of User Registers

STANDARD SELECT Register

Refresh of STANDARD SELECT Register

STANDARD RESULT Register

Write Registers on I²C Subaddress 10_hex

Read Registers on I²C Subaddress 11_hex

Write Registers on I²C Subaddress 12_hex

2

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PRELIMINARY DATA SHEET

MSP 34x0G

Contents, continued

Page

Section

Title

38

39

40

3.3.2.7.

3.4.

Read Registers on I²C Subaddress 13_hex

Programming Tips

3.5.

Examples of Minimum Initialization Codes

B/G-FM (A2 or NICAM)

3.5.1.

3.5.2.

3.5.3.

3.5.4.

3.5.5.

3.5.6.

BTSC-Stereo

BTSC-SAP with SAP at Loudspeaker Channel

FM-Stereo Radio

Automatic Standard Detection

Software Flow for Interrupt driven STATUS Check

42

44

47

50

54

56

57

58

59

60

61

62

63

64

65

67

68

71

4.

Specifications

4.1.

Outline Dimensions

4.2.

Pin Connections and Short Descriptions

Pin Descriptions

4.3.

4.4.

Pin Configurations

4.5.

Pin Circuits

4.6.

Electrical Characteristics

4.6.1.

4.6.2.

4.6.2.1.

4.6.2.2.

4.6.2.3.

4.6.2.4.

4.6.3.

4.6.3.1.

4.6.3.2.

4.6.3.3.

4.6.3.4.

4.6.3.5.

4.6.3.6.

4.6.3.7.

4.6.3.8.

4.6.3.9.

4.6.3.10.

Absolute Maximum Ratings

Recommended Operating Conditions (T_A= 0 to 70 °C)

General Recommended Operating Conditions

Analog Input and Output Recommendations

Recommendations for Analog Sound IF Input Signal

Crystal Recommendations

Characteristics

General Characteristics

Digital Inputs, Digital Outputs

Reset Input and Power-Up

I²C-Bus Characteristics

I²S-Bus Characteristics

Analog Baseband Inputs and Outputs, AGNDC

Sound IF Inputs

Power Supply Rejection

Analog Performance

Sound Standard Dependent Characteristics

74

75

76

77

5.

Appendix A: Overview of TV-Sound Standards

NICAM 728

5.1.

5.2.

5.3.

5.4.

5.5.

5.6.

A2-Systems

BTSC-Sound System

Japanese FM Stereo System (EIA-J)

FM Satellite Sound

FM-Stereo Radio

MICRONAS INTERMETALL

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MSP 34x0G

PRELIMINARY DATA SHEET

Contents, continued

Page

Section

Title

78

79

80

81

82

83

84

86

88

89

90

91

93

6.

Appendix B: Manual/Compatibility Mode

6.1.

Demodulator Write and Read Registers for Manual/Compatibility Mode

DSP Write and Read Registers for Manual/Compatibility Mode

Manual/Compatibility Mode: Description of Demodulator Write Registers

Automatic Switching between NICAM and Analog Sound

Function in Automatic Sound Select Mode

Function in Manual Mode

6.2.

6.3.

6.3.1.

6.3.1.1.

6.3.1.2.

6.3.2.

6.3.3.

6.3.4.

6.3.5.

6.3.6.

6.3.7.

6.4.

A2 Threshold

Carrier-Mute Threshold

Register AD_CV

Register MODE_REG

FIR-Parameter, Registers FIR1 and FIR2

DCO-Registers

Manual/Compatibility Mode: Description of Demodulator Read Registers

NICAM Mode Control/Additional Data Bits Register

Additional Data Bits Register

6.4.1.

6.4.2.

6.4.3.

6.4.4.

6.4.5.

6.4.6.

6.4.7.

6.5.

CIB Bits Register

NICAM Error Rate Register

PLL_CAPS Readback Register

AGC_GAIN Readback Register

Automatic Search Function for FM-Carrier Detection in Satellite Mode

Manual/Compatibility Mode: Description of DSP Write Registers

Additional Channel Matrix Modes

6.5.1.

6.5.2.

6.5.3.

6.5.4.

6.5.5.

6.5.6.

6.5.7.

6.6.

Volume Modes of SCART1/2 Outputs

FM Fixed Deemphasis

FM Adaptive Deemphasis

NICAM Deemphasis

Identification Mode for A2 Stereo Systems

FM DC Notch

Manual/Compatibility Mode: Description of DSP Read Registers

Stereo Detection Register for A2 Stereo Systems

DC Level Register

6.6.1.

6.6.2.

6.7.

Demodulator Source Channels in Manual Mode

Terrestric Sound Standards

6.7.1.

6.7.2.

6.8.

SAT Sound Standards

Exclusions of Audio Baseband Features

Phase Relationship of Analog Outputs

6.9.

94

95

96

7.

8.

9.

Appendix D: MSP 34x0G Version History

Appendix E: Application Circuit

Data Sheet History

4

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

Multistandard Sound Processor Family

Other processed standards are the Japanese FM-FM

multiplex standard (EIA-J) and the FM Stereo Radio

standard.

Release Note: Revision bars indicate significant

changes to the previous edition. The hardware and

software description in this document is valid for

the MSP 34x0G version B5 and following versions.

Current ICs have to perform adjustment procedures in

order to achieve good stereo separation for BTSC and

EIA-J. The MSP 34x0G has optimum stereo perfor-

mance without any adjustments.

1. Introduction

All MSP 34x0G versions are pin and software down-

ward-compatible to the MSP 34x0D. The MSP 34x0G

further simplifies controlling software. Standard selec-

tion requires a single I²C transmission only.

The MSP 34x0G family of single-chip Multistandard

Sound Processors covers the sound processing of all

analog TV-Standards worldwide, as well as the NICAM

digital sound standards. The full TV sound processing,

starting with analog sound IF signal-in, down to pro-

cessed analog AF-out, is performed on a single chip.

Figure 1–1 shows a simplified functional block diagram

of the MSP 34x0G.

The MSP 34x0G has built-in automatic functions: The

IC is able to detect the actual sound standard automat-

ically (Automatic Standard Detection). Furthermore,

pilot levels and identification signals can be evaluated

internally with subsequent switching between mono/

stereo/bilingual; no I²C interaction is necessary (Auto-

matic Sound Selection).

This new generation of TV sound processing ICs now

includes versions for processing the multichannel tele-

vision sound (MTS) signal conforming to the standard

recommended by the Broadcast Television Systems

Committee (BTSC). The DBX noise reduction, or alter-

natively, MICRONAS Noise Reduction (MNR) is per-

formed alignment free.

The ICs are produced in submicron CMOS technology.

The MSP 34x0G is available in the following pack-

ages: PLCC68, PSDIP64, PSDIP52, PQFP80, and

PLQFP64.

Loud-

speaker

Loud-

speaker

Sound

Sound IF1

De-

modulator

Pre-

processing

ADC

DAC

Sound IF2

Subwoofer

Processing

Headphone

Sound

Processing

Headphone

2

I S1

Prescale

2

I S2

2

I S

SCART1

SCART2

SCART3

DAC

SCART

DSP

Input

SCART1

SCART2

ADC

SCART

Output

Select

SCART4

MONO

Fig. 1–1: Simplified functional block diagram of the MSP 34x0G

MICRONAS INTERMETALL

5

MSP 34x0G

PRELIMINARY DATA SHEET

1.1. Features of the MSP 34x0G Family and Differences to MSPD

Feature (New features not available for MSPD are shaded gray.)

3400

X

3410

X

3420

X

3430

X

3440

X

3450

X

2

Standard Selection with single I C transmission

Automatic Standard Detection of terrestrial TV standards

Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS

Two selectable sound IF (SIF) inputs

X

Automatic Carrier Mute function

X

Interrupt output programmable (indicating status change)

Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness

AVC: Automatic Volume Correction

X

Subwoofer output with programmable low-pass and complementary high-pass filter

5-band graphic equalizer for loudspeaker channel

X

Spatial effect for loudspeaker channel

X

Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs

Complete SCART in/out switching matrix

X

2

Two I S inputs; one I S output

X

Dolby Pro Logic with DPL 351xA coprocessor

X

All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard

Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM

Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification)

ASTRA Digital Radio (ADR) together with DRP 3510A

All NICAM standards

X

Demodulation of the BTSC multiplex signal and the SAP channel

Alignment free digital DBX noise reduction for BTSC Stereo and SAP

Alignment free digital MICRONAS Noise Reduction (MNR) for BTSC Stereo and SAP

BTSC stereo separation (MSP 3420/40G also EIA-J) significantly better than spec.

SAP and stereo detection for BTSC system

X

Korean FM-Stereo A2 standard

X

Alignment-free Japanese standard EIA-J

Demodulation of the FM-Radio multiplex signal

X

1.2. MSP 34x0G Version List

Version

Status

Description

MSP 3400G

MSP 3410G

MSP 3420G

MSP 3430G

MSP 3440G

MSP 3450G

planned

available

FM Stereo (A2) Version

NICAM and FM Stereo (A2) Version

NTSC Version (A2 Korea, BTSC with MICRONAS Noise Reduction (MNR), and Japanese EIA-J system)

BTSC Version

NTSC Version (A2 Korea, BTSC with DBX noise reduction, and Japanese EIA-J system)

Global Version (all sound standards)

6

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

1.3. MSP 34x0G Versions and their Application Fields

Table 1–1 provides an overview of TV sound stan-

dards that can be processed by the MSP 34x0G fam-

ily. In addition, the MSP 34x0G is able to handle the

terrestrial FM-Radio standard. With the MSP 34x0G, a

complete multimedia receiver covering all TV sound

standards together with terrestrial and satellite radio

sound can be built; even ASTRA Digital Radio can be

processed (with a DRP 3510A coprocessor).

Table 1–1: TV Stereo Sound Standards covered by the MSP 34x0G IC Family (details see Appendix A)

TV-

System

Position of Sound

Carrier /MHz

Sound

Modulation

Color

System

Broadcast e.g. in:

MSP Version

5.5/5.7421875

5.5/5.85

FM-Stereo (A2)

PAL

Germany

B/G

FM-Mono/NICAM

AM-Mono/NICAM

FM-Mono/NICAM

FM-Stereo (A2, D/K1)

FM-Stereo (A2, D/K2)

FM-Stereo (A2, D/K3)

PAL

Scandinavia, Spain

France

L

I

6.5/5.85

SECAM-L

PAL

6.0/6.552

UK, Hong Kong

Slovak. Rep.

currently no broadcast

Poland

6.5/6.2578125

6.5/6.7421875

6.5/5.7421875

6.5/5.85

SECAM-East

PAL

D/K

SECAM-East

FM-Mono/NICAM (D/K, NICAM) PAL

FM-Mono

China, Hungary

6.5

7.02/7.2

7.38/7.56

etc.

FM-Stereo

Europe Sat.

ASTRA

Satellite

PAL

ASTRA Digital Radio (ADR)

with DRP 3510A

4.5/4.724212

FM-Stereo (A2)

FM-FM (EIA-J)

NTSC

Korea

M/N

4.5

NTSC

Japan

4.5

BTSC-Stereo + SAP

FM-Stereo Radio

NTSC, PAL

USA, Argentina

USA, Europe

FM-Radio

10.7

33 34 39 MHz

4.5 9 MHz

SAW Filter

Sound

IF

Mixer

Tuner

Loudspeaker

Subwoofer

1

Mono

Vision

Demo-

dulator

MSP 34x0G

2

SCART1

SCART2

SCART3

SCART4

Headphone

SCART

Inputs

2

SCART1

SCART2

Composite

Video

SCART

Outputs

2

I S1

ADR

I S2

Dolby

ADR

Decoder

DRP 3510A

Pro Logic

Processor

DPL 351xA

Fig. 1–2: Typical MSP 34x0G application

MICRONAS INTERMETALL

7

PRELIMINARY DATA SHEET

MSP 34x0G

2.1. Architecture of the MSP 34x0G Family

BTSC-Mono + SAP: Detection and FM demodulation

of the aural carrier resulting in the MTS/MPX signal.

Detection and evaluation of the pilot carrier, detection

and FM demodulation of the SAP subcarrier. Process-

ing of DBX noise reduction or MICRONAS Noise

Reduction (MNR).

Fig. 2–1 on page 8 shows a simplified block diagram of

the IC. The block diagram contains all features of the

MSP 3450G. Other members of the MSP 34x0G fam-

ily do not have the complete set of features: The

demodulator handles only a subset of the standards

presented in the demodulator block; NICAM process-

ing is only possible in the MSP 3410G and

MSP 3450G.

Japan Stereo: Detection and FM demodulation of the

aural carrier resulting in the MPX signal. Demodulation

and evaluation of the identification signal and FM

demodulation of the (L−R)-carrier.

2.2. Sound IF Processing

FM-Satellite Sound: Demodulation of one or two FM

carriers. Processing of high-deviation mono or narrow

bandwidth mono, stereo, or bilingual satellite sound

according to the ASTRA specification.

2.2.1. Analog Sound IF Input

The input pins ANA_IN1+, ANA_IN2+, and ANA_IN−

offer the possibility to connect two different sound IF

(SIF) sources to the MSP 34x0G. The analog-to-digital

conversion of the preselected sound IF signal is done

by an A/D-converter. An analog automatic gain circuit

(AGC) allows a wide range of input levels. The high-

pass filters formed by the coupling capacitors at pins

ANA_IN1+ and ANA_IN2+ see Section 8. “Appendix

E: Application Circuit” on page 95 are sufficient in most

cases to suppress video components. Some combina-

tions of SAW filters and sound IF mixer ICs, however,

show large picture components on their outputs. In this

case, further filtering is recommended.

FM-Stereo-Radio: Detection and FM demodulation of

the aural carrier resulting in the MPX signal. Detection

and evaluation of the pilot carrier and AM demodula-

tion of the (L−R)-carrier.

The demodulator blocks of all MSP 34x0G versions

have identical user interfaces. Even completely differ-

ent systems like the BTSC and NICAM systems are

controlled the same way. Standards are selected by

means of MSP Standard Codes. Automatic processes

handle standard detection and identification without

controller interaction. The key features of the

MSP 34x0G demodulator blocks are

2.2.2. Demodulator: Standards and Features

Standard Selection: The controlling of the demodula-

tor is minimized: All parameters, such as tuning fre-

quencies or filter bandwidth, are adjusted automati-

cally by transmitting one single value to the

STANDARD SELECT register. For all standards, spe-

cific MSP standard codes are defined.

The MSP 34x0G is able to demodulate all TV-sound

standards worldwide including the digital NICAM sys-

tem. Depending on the MSP 34x0G version, the fol-

lowing demodulation modes can be performed:

A2 Systems: Detection and demodulation of two sep-

arate FM carriers (FM1 and FM2), demodulation and

evaluation of the identification signal of carrier FM2.

Automatic Standard Detection: If the TV sound stan-

dard is unknown, the MSP 34x0G can automatically

detect the actual standard, switch to that standard, and

respond the actual MSP standard code.

NICAM Systems: Demodulation and decoding of the

NICAM carrier, detection and demodulation of the ana-

log (FM or AM) carrier. For D/K-NICAM, the FM carrier

may have a maximum deviation of 384 kHz.

Automatic Carrier Mute: To prevent noise effects or

FM identification problems in the absence of an FM

carrier, the MSP 34x0G offers a carrier mute feature,

which is activated automatically if the TV sound stan-

dard is selected by means of the STANDARD SELECT

register. If no FM carrier is available at one of the two

MSP demodulator channels, the corresponding

demodulator output is muted.

Very high deviation FM-Mono: Detection and robust

demodulation of one FM carrier with a maximum devi-

ation of 540 kHz.

BTSC-Stereo: Detection and FM demodulation of the

aural carrier resulting in the MTS/MPX signal. Detec-

tion and evaluation of the pilot carrier, AM demodula-

tion of the (L−R)-carrier and detection of the SAP sub-

carrier. Processing of DBX noise reduction or

MICRONAS Noise Reduction (MNR).

MICRONAS INTERMETALL

9

MSP 34x0G

PRELIMINARY DATA SHEET

2.2.3. Preprocessing of Demodulator Signals

– “Stereo or A” channel: Analog or digital mono

sound, stereo if available. In case of bilingual broad-

cast, it contains language A (on left and right).

The NICAM signals must be processed by a deempha-

sis filter and adjusted in level. The analog demodu-

lated signals must be processed by a deemphasis fil-

ter, adjusted in level, and dematrixed. The correct

deemphasis filters are already selected by setting the

standard in the STANDARD SELECT register. The

level adjustment has to be done by means of the FM/

AM and NICAM prescale registers. The necessary

dematrix function depends on the selected sound stan-

dard and the actual broadcasted sound mode (mono,

stereo, or bilingual). It can be manually set by the FM

Matrix Mode register or automatically set by the Auto-

matic Sound Selection.

– “Stereo or B” channel: Analog or digital mono

sound, stereo if available. In case of bilingual broad-

cast, it contains language B (on left and right).

Fig 2–2 shows the source channel assignment of the

demodulated signals in case of manual mode. If man-

ual mode is required, more information can be found in

the section “Demodulator Source Channels in Manual

Mode” on page 91. Fig 2–3 and Table 2–2 show the

source channel assignment of the demodulated sig-

nals in case of Automatic Sound Select mode for all

sound standards.

Note: The analog primary input channel contains the

signal of the mono FM/AM carrier or the L+R signal of

the MPX carrier. The secondary input channel contains

the signal of the 2nd FM carrier, the L−R signal of the

MPX carrier, or the SAP signal.

2.2.4. Automatic Sound Select

In the Automatic Sound Select mode, the dematrix

function is automatically selected based on the identifi-

cation information in the STATUS register. No I²C

interaction is necessary when the broadcasted sound

mode changes (e.g. from mono to stereo).

2.3. Preprocessing for SCART and

I²S Input Signals

The demodulator supports the identification check by

switching between mono compatible standards (stan-

dards that have the same FM mono carrier) automati-

cally and non-audible. If B/G-FM or B/G-NICAM is

selected, the MSP will switch between these stan-

dards. The same action is performed for the stan-

dards: D/K1-FM, D/K2-FM, and D/K-NICAM. Switching

is only done in the absence of any stereo or bilingual

identification. If identification is found, the MSP keeps

the detected standard.

The SCART and I²S inputs need only be adjusted in

level by means of the SCART and I²S prescale regis-

ters.

LS Ch.

Matrix

primary

channel

FM/AM

Prescale

FM-Matrix

FM/AM

0

1

Output-Ch.

Matrices

must be set

according

the standard

secondary

channel

In case of high bit-error rates, the MSP 34x0G auto-

matically falls back from digital NICAM sound to ana-

log FM or AM mono.

NICAM A

NICAM B

NICAM

(Stereo or A/B)

Prescale

SC2 Ch.

Matrix

Table 2–1 summarizes all actions that take place when

Automatic Sound Select is switched on.

Fig. 2–2: Source channel assignment of demodulated

signals in Manual Mode

To provide more flexibility, the Automatic Sound Select

block prepares four different source channels of

demodulated sound (Fig 2–3). By choosing one of the

four demodulator channels, the preferred sound mode

can be selected for each of the output channels (loud-

speaker, headphone, etc.). This is done by means of

the Source Select registers.

LS Ch.

Matrix

primary

channel

FM/AM

0

1

FM/AM

Prescale

secondary

channel

Automatic

Sound

Select

Output-Ch.

Matricesmust

be set once to

stereo

Stereo or A/B

The following source channels of demodulated sound

are defined:

NICAM A

NICAM B

NICAM

Stereo or A

Stereo or B

3

4

– “FM/AM” channel: Analog mono sound, stereo if

available. In case of NICAM, analog mono only

(FM or AM mono).

Prescale

SC2 Ch.

Matrix

Fig. 2–3: Source channel assignment of demodulated

signals in Automatic Sound Select Mode

– “Stereo or A/B” channel: Analog or digital mono

sound, stereo if available. In case of bilingual broad-

cast, it contains both languages A (left) and B

(right).

10

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

Table 2–1: Performed actions of the Automatic Sound Selection

Selected TV Sound Standard

Performed Actions

B/G-FM, D/K-FM, M-Korea,

and M-Japan

Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four

demodulator source channels according to Table 2–2. Identification is acquired after 500 ms.

B/G-NICAM, L-NICAM, I-NICAM,

and D/K-NICAM

Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four

demodulator source channels according to Table 2–2. NICAM detection is acquired within 150 ms.

In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches

back to NICAM if possible. A hysteresis prevents periodical switching.

B/G-FM, B/G-NICAM

or

D/K1-FM, D/K2-FM, D/K3-FM,

and D/K-NICAM

Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and non-

audible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-Mono sound

carrier.

Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the

absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP

keeps the corresponding standard.

BTSC-STEREO, FM Radio

BTSC-SAP

Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator

source channels according to Table 2–2. Detection of the SAP carrier. Pilot detection is acquired after

200 ms.

In the absence of SAP, the MSP switches to BTSC-Stereo if available. If SAP is detected, the MSP

switches automatically to SAP (see Table 2–2).

Table 2–2: Sound modes for the demodulator source channels with Automatic Sound Select

Source Channels in Automatic Sound Select Mode

Broadcasted Selected

Broadcasted

Sound Mode

FM/AM

(source select: 0)

Stereo or A/B

(source select: 1)

Stereo or A

(source select: 3)

Stereo or B

(source select: 4)

Sound

MSP Standard

Standard

Code³⁾

M-Korea

B/G-FM

D/K-FM

M-Japan

02

MONO

Mono

Stereo

A

Mono

Stereo

B

03, 08¹⁾

04, 05, 07, 0B¹⁾

30

STEREO

Stereo

BILINGUAL:

Left = A

Languages A and B

Right = B

B/G-NICAM

L-NICAM

08, 03²⁾

09

NICAM not available or analog Mono

error rate too high

analog Mono

I-NICAM

0A

0B, 04²⁾, 05²⁾

0C

MONO

analog Mono

NICAM Mono

NICAM Stereo

NICAM Mono

NICAM Stereo

NICAM A

NICAM Mono

NICAM Stereo

NICAM B

D/K-NICAM

(with high

STEREO

deviation FM)

BILINGUAL:

Languages A and B

Left = NICAM A

Right = NICAM B

20, 21

20

MONO

Mono

Stereo

Mono

Stereo

Mono

Stereo

Mono

Stereo

Mono

Stereo

Mono

Stereo

Mono

Stereo

Mono

Stereo

SAP

STEREO

MONO+SAP

STEREO+SAP

MONO+SAP

BTSC

21

Left = Mono

Right = SAP

Left = Mono

Right = SAP

STEREO+SAP

Left = Mono

Right = SAP

Left = Mono

Right = SAP

Mono

SAP

FM Radio

40

MONO

Mono

STEREO

Stereo

1)

The Automatic Sound Select process will automatically switch to the mono compatible analog standard.

The Automatic Sound Select process will automatically switch to the mono compatible digital standard.

The MSP Standard Codes are defined in Table 3–7 on page 22.

2)

3)

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11

MSP 34x0G

PRELIMINARY DATA SHEET

2.4. Source Selection and Output Channel Matrix

output level

[dBr]

The Source Selector makes it possible to distribute all

source signals (one of the demodulator source chan-

nels, SCART, or I²S input) to the desired output chan-

nels (loudspeaker, headphone, etc.). All input and out-

put signals can be processed simultaneously. Each

source channel is identified by a unique source

address.

−12

−18

−24

For each output channel, the sound mode can be set

to sound A, sound B, stereo, or mono by means of the

output channel matrix.

−30

−24

−18

−12

−6

0

+6

input level

[dBr]

If Automatic Sound Select is on, the output channel

matrix can stay fixed to stereo (transparent) for

demodulated signals.

Fig. 2–4: Simplified AVC characteristics

2.5. Audio Baseband Processing

2.5.2. Loudspeaker and Headphone Outputs

2.5.1. Automatic Volume Correction (AVC)

The following baseband features are implemented in

the loudspeaker and headphone output channels:

bass/treble, loudness, balance, and volume. A square

wave beeper can be added to the loudspeaker and

headphone channel. The loudspeaker channel addi-

tionally performs: equalizer (not simultaneously with

bass/treble), spatial effects, and a subwoofer cross-

over filter.

Different sound sources (e.g. terrestrial channels, SAT

channels, or SCART) fairly often do not have the same

volume level. Advertisements during movies usually

have a higher volume level than the movie itself. This

results in annoying volume changes. The Automatic

Volume Correction (AVC) solves this problem by

equalizing the volume level.

To prevent clipping, the AVC’s gain decreases quickly

in dynamic boost conditions. To suppress oscillation

effects, the gain increases rather slowly for low level

inputs. The decay time is programmable by means of

the AVC register (see page 31).

2.5.3. Subwoofer Output

The subwoofer signal is created by combining the left

and right channels directly behind the loudness block

using the formula (L+R)/2. Due to the division by 2, the

D/A converter will not be overloaded, even with full

scale input signals. The subwoofer signal is filtered by

a third-order low-pass with programmable corner fre-

quency followed by a level adjustment. At the loud-

speaker channels, a complementary high-pass filter

can be switched on. Subwoofer and loudspeaker out-

put use the same volume (Loudspeaker Volume Reg-

ister).

For input signals ranging from −24 dBr to 0 dBr, the

AVC maintains a fixed output level of −18 dBr. Fig. 2–4

shows the AVC output level versus its input level. For

prescale and volume registers set to 0 dB, a level of

0 dBr corresponds to full scale input/output. This is

– SCART input/output 0 dBr = 2.0 V_rms

– Loudspeaker and Aux output 0 dBr = 1.4 V_rms

2.5.4. Quasi-Peak Detector

The quasi-peak readout register can be used to read

out the quasi-peak level of any input source. The fea-

ture is based on following filter time constants:

attack time: 1.3 ms

decay time: 37 ms

12

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PRELIMINARY DATA SHEET

MSP 34x0G

2.6. SCART Signal Routing

2.7. I²S Bus Interface

2.6.1. SCART DSP In and SCART Out Select

It is possible to route in an external coprocessor for

special effects, like surround processing and sound

field processing. Routing can be done with each input

source and output channel via the I²S inputs and out-

puts.

The SCART DSP Input Select and SCART Output

Select blocks include full matrix switching facilities. To

design a TV set with four pairs of SCART-inputs and

two pairs of SCART-outputs, no external switching

hardware is required. The switches are controlled by

the ACB user register (see page 37).

Two possible interface formats are supported:

1. The SONY format: I2S_WS changes at the word

boundaries.

2.6.2. Stand-by Mode

2. The PHILIPS format: I2S_WS changes one I2S_CL

period before the word boundaries.

If the MSP 34x0G is switched off by first pulling

STANDBYQ low and then (after >1 µs delay) switching

off the 5-V, but keeping the 8-V power supply (‘Stand-

by’-mode), the SCART switches maintain their posi-

tion and function. This allows the copying from

selected SCART-inputs to SCART-outputs in the TV

set’s stand-by mode.

The I²S bus interface consists of five pins:

1. I2S_DA_IN1, I2S_DA_IN2:

For input, four channels (two channels per line,

2*16 bits) per sampling cycle (32 kHz) are transmit-

ted.

2. I2S_DA_OUT:

In case of power on or starting from stand-by (switch-

ing on the 5-V supply, RESETQ going high 2 ms later),

all internal registers except the ACB register (page 37)

are reset to the default configuration (see Table 3–5 on

page 20). The reset position of the ACB register

becomes active after the first I²C transmission into the

Baseband Processing part (subaddress 12_hex). By

transmitting the ACB register first, the reset state can

be redefined.

For output, two channels (2*16 bits) per sampling

cycle (32 kHz) are transmitted.

3. I2S_CL:

Gives the timing for the transmission of I²S serial

data (1.024 MHz).

4. I2S_WS:

The I2S_WS word strobe line defines the left and

right sample.

The MSP 34x0G normally serves as the master on the

I²S interface. In this case, the clock and word strobe

lines are driven by the MSP 34x0G. In slave mode,

these lines are input to the MSP 34x0G and the master

clock is synchronized to 576 times the I2S_WS rate

(32 kHz). NICAM operation is not possible in this

mode.

All I²S options can be set by means of the MODUS

register (see page 25).

A precise I²S timing diagram is shown in Fig. 4–26 on

page 65.

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13

MSP 34x0G

PRELIMINARY DATA SHEET

2.8. ADR Bus Interface

2.10. Clock PLL Oscillator and Crystal Specifications

For the ASTRA Digital Radio System (ADR), the

MSP 3400G, MSP 3410G and MSP 3450G performs

preprocessing such as carrier selection and filtering.

Via the 3-line ADR-bus, the resulting signals are trans-

ferred to the DRP 3510A coprocessor, where the

source decoding is performed. To be prepared for an

upgrade to ADR with an additional DRP board, the fol-

lowing lines of MSP 34x0G should be provided on a

feature connector:

The MSP 34x0G derives all internal system clocks

from the 18.432-MHz oscillator. In NICAM or in I²S-

Slave mode, the clock is phase-locked to the corre-

sponding source. Therefore, it is not possible to use

NICAM and I²S-Slave mode at the same time.

For proper performance, the MSP clock oscillator

requires a 18.432-MHz crystal. Note that for the

phase-locked modes (NICAM, I²S-Slave), crystals with

tighter tolerance are required.

– AUD_CL_OUT

Remark on using the crystal:

– I2S_DA_IN1 or I2S_DA_IN2

– I2S_DA_OUT

External capacitors at each crystal pin to ground are

required. They are necessary for tuning the open-loop

frequency of the internal PLL and for stabilizing the fre-

quency in closed-loop operation. The higher the

capacitors, the lower the resulting clock frequency.

The nominal free running frequency should match

18.432 MHz as closely as possible.

– I2S_WS

– I2S_CL

– ADR_CL, ADR_WS, ADR_DA

For more details, please refer to the DRP 3510A data

sheet.

Clock measurements should be done at pin

AUD_CL_OUT. This pin must be activated for this pur-

pose (see Table 3–9 on page 25).

2.9. Digital Control I/O Pins and

Status Change Indication

The static level of the digital input/output pins

D_CTR_I/O_0/1 is switchable between HIGH and

LOW via the I²C-bus by means of the ACB register

(see page 37). This enables the controlling of external

hardware switches or other devices via I²C-bus.

The digital input/output pins can be set to high imped-

ance by means of the MODUS register (see page 25).

In this mode, the pins can be used as input. The cur-

rent state can be read out of the STATUS register (see

page 26).

Optionally, the pin D_CTR_I/O_1 can be used as an

interrupt request signal to the controller, indicating any

changes in the read register STATUS. This makes poll-

ing unnecessary, I²C bus interactions are reduced to a

minimum (see STATUS register on page 26 and

MODUS register on page 25).

14

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PRELIMINARY DATA SHEET

MSP 34x0G

3. Control Interface

performed some other function (for example, servicing

an internal interrupt), it will hold the clock line I2C_CL

LOW to force the transmitter into a wait state. The

positions within a transmission where this may happen

are indicated by ’Wait’ in section 3.1.3. The maximum

wait period of the MSP during normal operation mode

is less than 1 ms.

3.1. I²C Bus Interface

3.1.1. Device and Subaddresses

The MSP 34x0G is controlled via the I²C bus slave

interface.

The IC is selected by transmitting one of the

MSP 34x0G device addresses. In order to allow up to

three MSP ICs to be connected to a single bus, an

address select pin (ADR_SEL) has been implemented.

With ADR_SEL pulled to high, low, or left open, the

MSP 34x0G responds to different device addresses. A

device address pair is defined as a write address (80,

84, or 88 hex) and a read address (81, 85, or 89 hex)

(see Table 3–1).

Internal hardware error handling:

In case of any internal hardware error (e.g. interruption

of the power supply of the MSP), the MSP’s wait

period is extended to 1.8 ms. After this time period

elapses, the MSP releases data and clock lines.

Indication and solving of the error status:

Writing is done by sending the device write address,

followed by the subaddress byte, two address bytes,

and two data bytes. Reading is done by sending the

write device address, followed by the subaddress byte

and two address bytes. Without sending a stop condi-

tion, reading of the addressed data is completed by

sending the device read address (81, 85, or 89 hex)

and reading two bytes of data. Refer to section 3.1.3.

for the I²C bus protocol and to section “Programming

Tips” on page 39 for proposals of MSP 34x0G I²C tele-

grams. See Table 3–2 for a list of available subad-

dresses.

1. MSP 34x0G-versions until B5: To indicate the

error status, all further acknowledge bits will be left

high. The MSP can then be reset by transmitting the

reset condition to CONTROL while ignoring the miss-

ing acknowledge bits.

2. MSP 34x0G-versions from B6 on: To indicate the

error status, the remaining acknowledge bits of the ac-

tual I²C-protocol will be left high. Additionally, bit[14] of

CONTROL is set to one. The MSP can then be reset

via the I²C bus by transmitting the reset condition to

CONTROL.

Besides the possibility of hardware reset, the MSP can

also be reset by means of the RESET bit in the CON-

TROL register by the controller via I²C bus.

Indication of reset (only versions from B6 on):

Any reset, even caused by an unstable reset line etc.,

is indicated in bit[15] of CONTROL.

Due to the internal architecture of the MSP 34x0G, the

IC cannot react immediately to an I²C request. The

typical response time is about 0.3 ms. If the MSP can-

not accept another complete byte of data until it has

A general timing diagram of the I²C bus is shown in

Fig. 4–25 on page 63.

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MSP 34x0G

PRELIMINARY DATA SHEET

Table 3–1: I²C Bus Device Addresses

ADR_SEL

Low

High

Read

Left Open

Mode

Write

Read

Write

Read

MSP device address

80 hex

81 hex

84 hex

85 hex

88 hex

89 hex

Table 3–2: I²C Bus Subaddresses

Name

Binary Value

Hex Value

Mode

Function

CONTROL

0000 0000

00

Read/Write

Write: Software reset of MSP (see Table 3–3)

Read: Hardware error status of MSP

TEST

0000 0001

0001 0000

0001 0001

0001 0010

0001 0011

01

10

11

12

13

Write

only for internal use

WR_DEM

RD_DEM

WR_DSP

RD_DSP

write address demodulator

read address demodulator

write address DSP

read address DSP

3.1.2. Description of CONTROL Register

Table 3–3: CONTROL as a Write Register

Name

Subaddress

Bit[15] (MSB)

Bits[14:0]

CONTROL 00 hex

1 : RESET

0 : normal

0

Table 3–4: CONTROL as a Read Register (only MSP 34x0G-versions from B6 on)

Name Subaddress Bit[15] (MSB) Bit[14]

CONTROL 00 hex Reset status after last reading of CONTROL: Internal hardware status:

Bits[13:0]

not of interest

0 : no reset occured

1 : reset occured

0 : no error occured

1 : internal error occured

Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be

read once to be resetted.

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MSP 34x0G

3.1.3. Protocol Description

Write to DSP or Demodulator

S

write

device

address

Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte- ACK data-byte ACK

high low high low

P

Read from DSP or Demodulator

S

write

device

address

Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK

high low

S

read

device

address

Wait ACK data-byte- ACK data-byte NAK

high low

P

Write to Control or Test Registers

S

write

device

address

Wait ACK sub-addr ACK data-byte ACK data-byte ACK P

high

low

Note: S =

P =

I²C-Bus Start Condition from master

I²C-Bus Stop Condition from master

ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray)

or master (= controller dark gray)

NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’

or from MSP indicating internal error state

Wait = I²C-Clock line is held low, while the MSP is processing the I²C command. This waiting time is

max. 1 ms

1

0

I2C_DA

S

P

I2C_CL

Fig. 3–1: I²C bus protocol (MSB first; data must be stable while clock is high)

MICRONAS INTERMETALL

17

MSP 34x0G

PRELIMINARY DATA SHEET

3.1.4. Proposals for General MSP 34x0G I²C Telegrams

3.1.4.1. Symbols

daw

dar

<

write device address (80_hex, 84_hexor 88_hex

)

read device address (81_hex, 85_hexor 89_hex

Start Condition

)

>

Stop Condition

aa

dd

Address Byte

Data Byte

3.1.4.2. Write Telegrams

write to CONTROL register

write data into demodulator

write data into DSP

3.1.4.3. Read Telegrams

read data from demodulator

read data from DSP

3.1.4.4. Examples

<80 00 80 00>

<80 00 00 00>

RESET MSP statically

Clear RESET

<80 10 00 20 00 03>

<80 11 02 00 <81 dd dd>

<80 12 00 08 01 20>

Set demodulator to stand. 03_hex

Read STATUS

Set loudspeaker channel source to NICAM and Matrix to STEREO

More examples of typical application protocols are listed in section “Programming Tips” on page 39.

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MSP 34x0G

3.2. Start-Up Sequence:

Power-Up and I²C Controlling

After POWER ON or RESET (see Fig. 4–24), the IC is

in an inactive state. All registers are in the reset posi-

tion (see tables 3–5 and 3–6), the analog outputs are

muted. The controller has to initialize all registers for

which a non-default setting is necessary.

3.3. MSP 34x0G Programming Interface

3.3.1. User Registers Overview

The MSP 34x0G is controlled by means of user regis-

ters. The complete list of all user registers is given in

the following tables. The registers are partitioned into

the Demodulator section (Subaddress 10_hexfor writ-

ing, 11_hexfor reading) and the Baseband Processing

sections (Subaddress 12_hexfor writing, 13_hexfor read-

ing).

Write and read registers are 16-bit wide, whereby the

MSB is denoted bit [15]. Transmissions via I²C bus

have to take place in 16-bit words (two byte transfers, with

the most significant byte transferred first). All write regis-

ters, except the demodulator write registers, are readable.

Unused parts of the 16-bit write registers must be zero.

Addresses not given in this table must not be written.

For reasons of software compatibility to the

MSP 34x0D, an Manual/Compatibility Mode is avail-

able. More read and write registers together with a

detailed description of this mode can be found in the

“Appendix B: Manual/Compatibility Mode” on page 78.

An overview of all MSP 34x0G Write Registers is

shown in Table 3–5; all Read Registers are given in

Table 3–6.

MICRONAS INTERMETALL

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MSP 34x0G

PRELIMINARY DATA SHEET

Table 3–5: List of MSP 34x0G Write Registers

Write Register

Address Bits

(hex)

Description and Adjustable Range

Reset

See

Page

2

I C Subaddress = 10

; Registers are not readable

hex

STANDARD SELECT

MODUS

00 20

00 30

[15..0]

Initial Programming of complete Demodulator

00 00

23

25

2

Demodulator, Automatic and I S options

2

I C Subaddress = 12

; Registers are all readable by using I C Subaddress = 13

hex

Volume loudspeaker channel

00 00

[15..8]

[7..0]

[+12 dB ... −114 dB, MUTE]

MUTE

30

31

Volume / Mode loudspeaker channel

1/8 dB Steps,

Reduce Volume / Tone Control / Compromise

00

hex

Balance loudspeaker channel [L/R]

00 01

[15..8]

[0...100 / 100% and 100 / 0...100%]

100%/100%

[−127...0 / 0 and 0 / −127...0 dB]

Balance mode loudspeaker

Bass loudspeaker channel

Treble loudspeaker channel

Loudness loudspeaker channel

Loudness filter characteristic

[7..0]

[Linear mode / logarithmic mode]

[+20 dB ... −12 dB]

linear mode

0 dB

00 02

00 03

00 04

[15..8]

[7..0]

32

33

34

[+15 dB ... −12 dB]

0 dB

[0 dB ... +17 dB]

0 dB

[NORMAL, SUPER_BASS]

[−100%...OFF...+100%]

[SBE, SBE+PSE]

NORMAL

OFF

Spatial effect strength loudspeaker ch. 00 05

Spatial effect mode/customize

[15..8]

[7..0]

35

30

SBE+PSE

MUTE

Volume headphone channel

Volume / Mode headphone channel

Volume SCART1 output channel

Loudspeaker source select

Loudspeaker channel matrix

Headphone source select

Headphone channel matrix

SCART1 source select

00 06

[15..8]

[7..0]

[+12 dB ... −114 dB, MUTE]

1/8 dB Steps, Reduce Volume / Tone Control

[+12 dB ... −114 dB, MUTE]

00

hex

00 07

00 08

[15..8]

[7..0]

MUTE

36

29

28

27

28

37

28

32

2

[FM/AM, NICAM, SCART, I S1, I S2]

FM/AM

[SOUNDA, SOUNDB, STEREO, MONO...]

SOUNDA

FM/AM

2

00 09

00 0A

00 0B

00 0C

[15..8]

[7..0]

[FM/AM, NICAM, SCART, I S1, I S2]

[SOUNDA, SOUNDB, STEREO, MONO...]

SOUNDA

FM/AM

2

[15..8]

[7..0]

[FM/AM, NICAM, SCART, I S1, I S2]

SCART1 channel matrix

[SOUNDA, SOUNDB, STEREO, MONO...]

SOUNDA

FM/AM

2

I S source select

[15..8]

[7..0]

[FM/AM, NICAM, SCART, I S1, I S2]

2

I S channel matrix

[SOUNDA, SOUNDB, STEREO, MONO...]

SOUNDA

FM/AM

2

Quasi-peak detector source select

Quasi-peak detector matrix

Prescale SCART input

Prescale FM/AM

[15..8]

[7..0]

[FM/AM, NICAM, SCART, I S1, I S2]

[SOUNDA, SOUNDB, STEREO, MONO...]

SOUNDA

00 0D

00 0E

[15..8]

[7..0]

[00

... 7F

]

00

hex

FM matrix

[NO_MAT, GSTEREO, KSTEREO]

NO_MAT

Prescale NICAM

00 10

00 12

[15..8]

[15..0]

[15..8]

[00

... 7F ] (MSP 3410G, MSP 3450G only)

00

10

00

hex

2

Prescale I S2

... 7F

]

hex

ACB : SCART Switches a. D_CTR_I/O 00 13

Bits [15..0]

Beeper

00 14

00 16

00 20

[00

... 7F ]/[00

... 7F

]

00/00

hex

2

Prescale I S1

[00

... 7F

]

10

hex

Mode tone control

[BASS/TREBLE, EQUALIZER]

BASS/TREB

20

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MSP 34x0G

Table 3–5: List of MSP 34x0G Write Registers, continued

Write Register

Address Bits

(hex)

Description and Adjustable Range

Reset

See

Page

Equalizer loudspeaker ch. band 1

Equalizer loudspeaker ch. band 2

Equalizer loudspeaker ch. band 3

Equalizer loudspeaker ch. band 4

Equalizer loudspeaker ch. band 5

Automatic Volume Correction

Subwoofer level adjust

00 21

00 22

00 23

00 24

00 25

00 29

00 2C

00 2D

[15..8] [+12 dB ... −12 dB]

0 dB

off

33

31

36

[15..8] [+12 dB ... −12 dB]

[15..8] [off, on, decay time]

[15..8] [0 dB ... −30 dB, mute]

[15..8] [50 Hz ... 400 Hz]

0 dB

Subwoofer corner frequency

00

off

hex

Subwoofer complementary high-pass

Balance headphone channel [L/R]

[7..0]

[off, on]

00 30

[15..8] [0...100 / 100% and 100 / 0...100%]

100 %/100 % 31

[−127...0 / 0 and 0 / −127...0 dB]

Balance mode headphone

Bass headphone channel

Treble headphone channel

Loudness headphone channel

Loudness filter characteristic

Volume SCART2 output channel

SCART2 source select

[7..0]

[Linear mode / logarithmic mode]

linear mode

00 31

00 32

00 33

[15..8] [+20 dB ... −12 dB]

[15..8] [+15 dB ... −12 dB]

[15..8] [0 dB ... +17 dB]

0 dB

32

33

34

0 dB

[7..0]

[NORMAL, SUPER_BASS]

NORMAL

00 40

00 41

[15..8] [+12 dB ... −114 dB, MUTE]

00

36

29

hex

2

[15..8] [FM, NICAM, SCART, I S1, I S2]

FM

SCART2 channel matrix

[7..0]

[SOUNDA, SOUNDB, STEREO, MONO...]

SOUNDA

Table 3–6: List of MSP 34x0G Read Registers

Read Register

Address Bits

(hex)

Description and Adjustable Range

See

Page

2

I C Subaddress = 11

; Registers are not writable

hex

STANDARD RESULT

00 7E

[15..0] Result of Automatic Standard Detection (see Table 3–8)

[15..0] Monitoring of internal settings e.g. Stereo, Mono, Mute etc. .

26

STATUS

02 00

; Registers are not writable

00 19

2

I C Subaddress = 13

hex

Quasi peak readout left

Quasi peak readout right

[15..0] [00

[15..8] [00

... 7FFF ]16 bit two’s complement

38

hex

00 1A

... 7FFF ]16 bit two’s complement

hex

MSP hardware version code

MSP major revision code

MSP product code

00 1E

... FF

]

hex

[7..0]

[15..8] [00

[7..0] [00

[00

]

hex

00 1F

]

hex

MSP ROM version code

]

hex

MICRONAS INTERMETALL

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MSP 34x0G

PRELIMINARY DATA SHEET

3.3.2. Description of User Registers

Table 3–7: Standard Codes for STANDARD SELECT register

MSP Standard Code TV Sound Standard

(Data in hex)

Sound Carrier

Frequencies in MHz

MSP 34x0G Version

Automatic Standard Detection

Start Automatic Standard Detection

00 01

all

Standard Selection

00 02

00 03

00 04

00 05

00 06

M-Dual FM-Stereo

4.5/4.724212

5.5/5.7421875

6.5/6.2578125

6.5/6.7421875

6.5

3400, -10, -20, -40, -50

3400, -10, -50

1)

B/G -Dual FM-Stereo

2)

D/K1-Dual FM-Stereo

D/K2-Dual FM-Stereo

3)

D/K -FM-Mono with HDEV3 , not detectable by Automatic

Standard Detection,

3)

HDEV3 SAT-Mono (i.e. Eutelsat, s. Table 6–17)

00 07

00 08

00 09

00 0A

00 0B

00 0C

D/K3-Dual FM-Stereo

6.5/5.7421875

5.5/5.85

1)

B/G -NICAM-FM

3410, -50

L -NICAM-AM

I -NICAM-FM

6.5/5.85

6.0/6.552

6.5/5.85

2)

D/K -NICAM-FM

4)

D/K -NICAM-FM with HDEV2 , not detectable by Automatic

6.5/5.85

Standard Detection, for China

3)

00 0D

D/K -NICAM-FM with HDEV3 , not detectable by Automatic

6.5/5.85

4.5

Standard Detection, for China

00 20

00 21

00 30

00 40

00 50

00 51

BTSC-Stereo

3420, -30, -40, -50

BTSC-Mono + SAP

M-EIA-J Japan Stereo

FM-Stereo Radio

4.5

3420, -40, -50

10.7

6.5

3420, -30, -40, -50

3400, -10, -50

SAT-Mono (s. Table 6–17)

SAT-Stereo (s. Table 6–17)

SAT ADR (Astra Digital Radio)

7.02/7.20

7.2

00 60

1)

In case of Automatic Sound Select, the B/G-codes 3

and 8

are equivalent.

hex

2)

3)

4)

In case of Automatic Sound Select, the D/K-codes 4 , 5

and B

are equivalent.

hex hex

hex

HDEV3: Max. FM deviation must not exceed 540 kHz

HDEV2: Max. FM deviation must not exceed 360 kHz

22

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

3.3.2.1. STANDARD SELECT Register

3.3.2.2. Refresh of STANDARD SELECT Register

The TV sound standard of the MSP 34x0G demodula-

tor is determined by the STANDARD SELECT register.

There are two ways to use the STANDARD SELECT

register:

A general refresh of the STANDARD SELECT register

is not allowed. However, the following method

enables watching the MSP 34x0G “alive” status and

detection of accidental resets (only versions B6 and

later):

– Setting up the demodulator for a TV sound standard

by sending the corresponding standard code with a

single I²C-Bus transmission.

– After Power-on, bit[15] of CONTROL will be set; it

must be read once to enable the reset-detection

feature.

– Starting the Automatic Standard Detection for ter-

restrial TV standards. This is the most comfortable

way to set up the demodulator. Within 0.5 s, the

detection and set-up of the actual TV sound stan-

dard is performed. The detected standard can be

read out of the STANDARD RESULT register by the

control processor. This feature is recommended for

the primary set-up of a TV set. Outputs should be

muted during Automatic Standard Detection.

– Reading of the CONTROL register and checking

the reset indicator bit[15] .

– If bit[15] is “0”, any refresh of the STANDARD

SELECT register is not allowed.

– If bit[15] is “1”, indicating a reset, a refresh of the

STANDARD SELECT register and all other MSPG

registers is necessary.

The Standard Codes are listed in Table 3–7.

Selecting a TV sound standard via the STANDARD

SELECT register initializes the demodulator. This

includes: AGC, tuning frequency, band-pass filters,

demodulation mode (FM, AM, or NICAM), carrier

mute, deemphasis, and identification mode.

If a present sound standard is impossible for a specific

MSP version, it switches to the analog mono sound of

this standard. In that case stereo or bilingual process-

ing will not be possible.

For a complete setup of the TV sound processing from

analog IF input to the source selection, the transmis-

sions as shown in Section 3.5. are necessary.

Note: The FM matrix is set automatically if Automatic

Sound Select is active (MODUS[0]=1). In this case, the

FM matrix will be initialized with “Sound A Mono”. Dur-

ing operation, the FM matrix will be automatically

selected according to the actual identification informa-

tion.

For reasons of software compatibility to the

MSP 34x0D, an Manual/Compatibility Mode is avail-

able. A detailed description of this mode can be found

on page 78.

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23

MSP 34x0G

PRELIMINARY DATA SHEET

3.3.2.3. STANDARD RESULT Register

Table 3–8: Results of the Automatic Standard

Detection

If Automatic Standard Detection is selected in the

STANDARD SELECT register, status and result of the

Automatic Standard Detection process can be read out

of the STANDARD RESULT register. The possible

results are based on the mentioned Standard Code

and are listed in Table 3–8.

Broadcasted Sound

Standard

STANDARD RESULT Register

Read 007E_hex

Automatic Standard

Detection could not

find a sound standard

0000_hex

In cases where no sound standard has been detected

(no standard present, too much noise, strong interfer-

ers, etc.) the STANDARD RESULT register contains

00 00_hex. In that case, the controller has to start further

actions (for example, set the standard according to a

preference list or by manual input).

B/G-FM

B/G-NICAM

I

0003_hex

0008_hex

000A_hex

FM-Radio

0040_hex

As long as the STANDARD RESULT register contains

a value greater than 07 FF_hex, the Automatic Standard

Detection is still active. During this period, the MODUS

and STANDARD SELECT register must not be written.

The STATUS register will be updated when the Auto-

matic Standard Detection has finished.

M-Korea

M-Japan

BTSC

0002_hex(if MODUS[14,13]=00)

0020_hex(if MODUS[14,13]=01)

0030_hex(if MODUS[14,13]=10)

0009_hex(if MODUS[12]=0)

0004_hex(if MODUS[12]=1)

0009_hex(if MODUS[12]=0)

000B_hex(if MODUS[12]=1)

>07FF_hex

L-AM

D/K1

D/K2

If a present sound standard is impossible for a specific

MSP version, it detects and switches to the analog

mono sound of this standard.

L-NICAM

D/K-NICAM

Example:

Automatic Standard

Detection still active

The MSPs 3430G and 3440G will detect a B/G-NICAM

signal as standard 3 and will switch to the analog FM-

Mono sound.

24

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

3.3.2.4. Write Registers on I²C Subaddress 10_hex

Table 3–9: Write Registers on I²C Subaddress 10_hex

Register

Address

Function

Name

STANDARD SELECTION

00 20_hex

STANDARD SELECTION Register

STANDARD_SEL

Defines TV Sound or FM-Radio Standard

bit [15:0] 00 01_hexstart Automatic Standard Detection

00 02_hexStandard Codes (see Table 3–7))

...

00 60_hex

MODUS

00 30_hex

MODUS Register

MODUS

General MSP 34x0G Options

bit [0]

bit [1]

0/1

off/on: Automatic Sound Select

disable/enable STATUS change indication by means of

the digital I/O pin D_CTR_I/O_1

Necessary condition: MODUS[3] = 0 (active)

bit [2]

bit [3]

0

undefined, must be 0

state of digital output pins D_CTR_I/O_0 and _1

active: D_CTR_I/O_0 and _1 are output pins

(can be set by means of the ACB register.

see also: MODUS[1])

1

tristate: D_CTR_I/O_0 and _1 are input pins

(level can be read out of STATUS[4,3])

bit [4]

bit [5]

0/1

active/tristate state of I²S output pins

master/slave mode of I²S interface (must be set to 0

(= Master) in case of NICAM mode)

bit [6]

bit [7]

0/1

Sony/Philips format of I²S word strobe

active/tristate state of audio clock output pin

AUD_CL_OUT

bit [8]

0/1

0

ANA_IN_1+/ANA_IN_2+;

select analog sound IF input pin

bit [11:9]

undefined, must be 0

Preference in Automatic Standard Detection:

bit [12]

detected 6.5 MHz carrier is interpreted as:¹⁾

0

1

standard L (SECAM)

standard D/K1, D/K2 or D/K NICAM

bit [14:13]

detected 4.5 MHz carrier is interpreted as:¹⁾

standard M (Korea)

standard M (BTSC)

standard M (Japan)

carrier at 4.5 MHz is ignored (chroma carrier)

0

1

2

3

bit [15]

0

undefined, must be 0

¹⁾Valid at the next start of Automatic Standard Detection.

MICRONAS INTERMETALL

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MSP 34x0G

PRELIMINARY DATA SHEET

3.3.2.5. Read Registers on I²C Subaddress 11_hex

Table 3–10: Read Registers on I²C Subaddress 11_hex

Register

Address

Function

Name

STANDARD RESULT

00 7E_hex

STANDARD RESULT Register

STANDARD_RES

Readback of the detected TV Sound or FM-Radio Standard

bit [15:0] 00 00_hexAutomatic Standard Detection could not find

a sound standard

00 02_hexMSP Standard Codes (see Table 3–8)

...

00 40_hex

>07 FF_hexAutomatic Standard Detection still active

STATUS

02 00_hex

STATUS Register

STATUS

Contains all user relevant internal information about the status of the MSP

bit [0]

bit [1]

undefined

0

1

detected primary carrier (Mono or MPX carrier)

no primary carrier detected

bit [2]

0

1

detected secondary carrier (2nd A2 or SAP carrier)

no secondary carrier detected

bit [3]

0/1

low/high level of digital I/O pin D_CTR_I/O_0

low/high level of digital I/O pin D_CTR_I/O_1

bit [4]

bit [5,9]

00

01

10

analog sound standard (FM or AM) active

not obtainable

digital sound (NICAM) available (MSP 3410G and

MSP 3450G only)

11

bad reception condition of digital sound (NICAM) due to:

a. high error rate

b. unimplemented sound code

c. data transmission only

bit [6]

bit [7]

0/1

mono/stereo indication

“1” indicates independent mono sound

(only for NICAM on MSP 3410G and MSP 3450G)

bit [8]

0/1

“1” indicates bilingual sound mode or SAP present

undefined

bit [15:10]

If STATUS change indication is activated by means of MODUS[1]: Each

change in the STATUS register sets the digital I/O pin D_CTR_I/O_1 to high

level. Reading the STATUS register resets D_CTR_I/O_1.

26

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PRELIMINARY DATA SHEET

MSP 34x0G

3.3.2.6. Write Registers on I²C Subaddress 12_hex

Table 3–11: Write Registers on I²C Subaddress 12_hex

Register

Address

Function

Name

PREPROCESSING

00 0E_hexFM/AM Prescale

PRE_FM

bit [15:8] 00_hex

Defines the input prescale gain for the demodulated

FM or AM signal

...

7F_hex

00_hex

off (RESET condition)

For all FM modes except satellite FM and AM-mode, the combinations of pres-

cale value and FM deviation listed below lead to internal full scale.

FM mode

bit [15:8] 7F_hex

48_hex

28 kHz FM deviation

50 kHz FM deviation

75 kHz FM deviation

100 kHz FM deviation

150 kHz FM deviation

180 kHz FM deviation (limit)

30_hex

24_hex

18_hex

13_hex

FM high deviation mode (HDEV2, MSP Standard Code = C_hex

)

bit [15:8] 30_hex

14_hex

150 kHz FM deviation

360 kHz FM deviation (limit)

FM very high deviation mode (HDEV3, MSP Standard Code = 6 and D_hex

)

bit [15:8] 20_hex

1A_hex

450 kHz FM deviation

540 kHz FM deviation (limit)

Satellite FM with adaptive deemphasis

bit [15:8] 10_hexrecommendation

AM mode (MSP Standard Code = 9)

bit [15:8] 7C_hexrecommendation for SIF input levels from

0.1 V_ppto 0.8 V_pp

(Due to the AGC being switched on, the AM-output level

remains stable and independent of the actual SIF-level in

the mentioned input range)

MICRONAS INTERMETALL

27

MSP 34x0G

PRELIMINARY DATA SHEET

Table 3–11: Write Registers on I²C Subaddress 12_hex, continued

Register

Address

Function

Name

(continued)

FM Matrix Modes

FM_MATRIX

00 0E_hex

Defines the dematrix function for the demodulated FM signal

bit [7:0]

00_hex

01_hex

02_hex

03_hex

no matrix (used for bilingual and unmatrixed stereo sound)

German stereo (Standard B/G)

Korean stereo (also used for BTSC, EIA-J and FM Radio)

sound A mono (left and right channel contain the mono

sound of the FM/AM mono carrier)

04_hex

sound B mono

In case of Automatic Sound Select, the FM Matrix Mode is set automatically,

i.e. the low-part of any I²C transmission to the register 00 0E_hexis ignored.

To enable a Forced Mono Mode for all analog stereo systems by overriding the

internal pilot or identification evaluation, the following steps must be transmitted:

1. MODUS with bit[0] = 0 (Automatic Sound Select off)

2. FM Presc./Matrix with FM Matrix = Sound A Mono (SAP: Sound B Mono)

3. Select FM/AM source channel, with channel matrix set to “Stereo” (transparent)

00 10_hex

NICAM Prescale

PRE_NICAM

Defines the input prescale value for the digital NICAM signal

bit [15:8] 00_hex... 7F_hexprescale gain

examples:

00_hex

20_hex

5A_hex

7F_hex

off

0 dB gain

9 dB gain (recommendation)

+12 dB gain (maximum gain)

00 16_hex

00 12_hex

I2S1 Prescale

I2S2 Prescale

PRE_I2S1

PRE_I2S2

Defines the input prescale value for digital I²S input signals

bit [15:8] 00_hex... 7F_hexprescale gain

examples:

00_hex

10_hex

7F_hex

off

0 dB gain (recommendation)

+18 dB gain (maximum gain)

00 0D_hex

SCART Input Prescale

PRE_SCART

Defines the input prescale value for the analog SCART input signal

bit [15:8] 00_hex... 7F_hexprescale gain

examples:

00_hex

19_hex

7F_hex

off

0 dB gain (2 V_RMSinput leads to digital full scale)

+14 dB gain (400 mV_RMSinput leads to digital full scale)

28

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MSP 34x0G

Table 3–11: Write Registers on I²C Subaddress 12_hex, continued

Register

Address

Function

Name

SOURCE SELECT AND OUTPUT CHANNEL MATRIX

Source for:

00 08_hex

00 09_hex

00 0A_hex

00 41_hex

00 0B_hex

00 0C_hex

Loudspeaker Output

Headphone Output

SCART1 DA Output

SCART2 DA Output

I²S Output

SRC_MAIN

SRC_AUX

SRC_SCART1

SRC_SCART2

SRC_I2S

Quasi-Peak Detector

SRC_QPEAK

bit [15:8]

0

“FM/AM”: demodulated FM or AM mono signal

1

“Stereo or A/B”: demodulator Stereo or A/B signal

(in manual mode, this source is identical to the NICAM

source in the MSP 3410D)

3

4

“Stereo or A”: demodulator Stereo Sound or

Language A (only defined for Automatic Sound Select)

“Stereo or B”: demodulator Stereo Sound or

Language B (only defined for Automatic Sound Select)

2

5

6

SCART input

I²S1 input

I²S2 input

For demodulator sources, see Table 2–2.

Matrix Mode for:

Loudspeaker Output

Headphone Output

SCART1 DA Output

SCART2 DA Output

I²S Output

00 08_hex

00 09_hex

00 0A_hex

00 41_hex

00 0B_hex

00 0C_hex

MAT_MAIN

MAT_AUX

MAT_SCART1

MAT_SCART2

MAT_I2S

Quasi-Peak Detector

MAT_QPEAK

bit [7:0]

00_hex

10_hex

20_hex

30_hex

Sound A Mono (or Left Mono)

Sound B Mono (or Right Mono)

Stereo (transparent mode)

Mono (sum of left and right inputs divided by 2)

special modes are available (see Section 6.5.1. on page 90)

In Automatic Sound Select mode, the demodulator source channels are set

according to Table 2–2. Therefore, the matrix modes of the corresponding out-

put channels should be set to “Stereo” (transparent).

MICRONAS INTERMETALL

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MSP 34x0G

PRELIMINARY DATA SHEET

Table 3–11: Write Registers on I²C Subaddress 12_hex, continued

Register

Address

Function

Name

LOUDSPEAKER AND HEADPHONE PROCESSING

00 00_hex

00 06_hex

Volume Loudspeaker

Volume Headphone

VOL_MAIN

VOL_AUX

bit [15:8] volume table with 1 dB step size

7F_hex

7E_hex

...

+12 dB (maximum volume)

+11 dB

74_hex

73_hex

72_hex

...

+1 dB

0 dB

−1 dB

02_hex

01_hex

00_hex

FF_hex

−113 dB

−114 dB

Mute (reset condition)

Fast Mute (needs about 75 ms until the signal is com-

pletely ramped down)

bit [7:5]

higher resolution volume table

0

+0 dB

1

+0.125 dB increase in addition to the volume table

...

7

+0.875 dB increase in addition to the volume table

bit [4]

0

must be set to 0

bit [3:0]

clipping mode

0

1

2

reduce volume

reduce tone control

compromise mode

With large scale input signals, positive volume settings may lead to signal clipping.

The MSP 34x0G loudspeaker and headphone volume function is divided into a

digital and an analog section. With Fast Mute, volume is reduced to mute posi-

tion by digital volume only. Analog volume is not changed. This reduces any

audible DC plops. To turn volume on again, the volume step that has been used

before Fast Mute was activated must be transmitted.

If the clipping mode is set to “Reduce Volume”, the following rule is used: To

prevent severe clipping effects with bass, treble, or equalizer boosts, the inter-

nal volume is automatically limited to a level where, in combination with either

bass, treble, or equalizer setting, the amplification does not exceed 12 dB.

If the clipping mode is “Reduce Tone Control”, the bass or treble value is

reduced if amplification exceeds 12 dB. If the equalizer is switched on, the gain

of those bands is reduced, where amplification together with volume exceeds

12 dB.

If the clipping mode is “Compromise Mode”, the bass or treble value and volume

are reduced half and half if amplification exceeds 12 dB. If the equalizer is

switched on, the gain of those bands is reduced half and half, where amplifica-

tion together with volume exceeds 12 dB.

Example:

Vol.: +6 dB

Bass: +9 dB Treble: +5 dB

Red. Volume

Red. Tone Con.

Compromise

3

6

4.5

9

6

7.5

5

30

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

Table 3–11: Write Registers on I²C Subaddress 12_hex, continued

Register

Address

Function

Name

00 29_hex

Automatic Volume Correction (AVC) Loudspeaker Channel

AVC

bit [15:12] 00_hex

08_hex

AVC off (and reset internal variables)

AVC on

bit [11:8] 08_hex

04_hex

8 sec decay time

4 sec decay time

02_hex

2 sec decay time

01_hex

20 ms decay time (intended for quick adaptation to the

average volume level after channel change)

Note: To reset the internal variables, the AVC should be switched off and then

on again during any channel or source change. For standard applications, the

recommended decay time is 4 sec.

Note: AVC should not be used in any Dolby Prologic mode (with DPL 35xx),

except in PANORAMA or 3D-PANORAMA mode, when only the loudspeaker

output is active.

00 01_hex

00 30_hex

Balance Loudspeaker Channel

Balance Headphone Channel

BAL_MAIN

BAL_AUX

bit [3:0]

Balance Mode

0_hex

1_hex

linear

logarithmic

bit [15:8] Linear Mode

7F_hex

7E_hex

...

Left muted, Right 100%

Left 0.8%, Right 100%

01_hex

00_hex

FF_hex

...

Left 99.2%, Right 100%

Left 100%, Right 100%

Left 100%, Right 99.2%

82_hex

81_hex

Left 100%, Right 0.8%

Left 100%, Right muted

bit [15:8] Logarithmic Mode

7F_hex

7E_hex

...

Left −127 dB, Right 0 dB

Left −126 dB, Right 0 dB

01_hex

00_hex

FF_hex

...

Left −1 dB, Right 0 dB

Left 0 dB, Right 0 dB

Left 0 dB, Right −1 dB

81_hex

80_hex

Left 0 dB, Right −127 dB

Left 0 dB, Right −128 dB

Positive balance settings reduce the left channel without affecting the right

channel; negative settings reduce the right channel leaving the left channel

unaffected.

MICRONAS INTERMETALL

31

MSP 34x0G

PRELIMINARY DATA SHEET

Table 3–11: Write Registers on I²C Subaddress 12_hex, continued

Register

Address

Function

Name

00 20_hex

Tone Control Mode Loudspeaker Channel

TONE_MODE

bit [15:8] 00_hex

FF_hex

bass and treble is active

equalizer is active

Defines whether Bass/Treble or Equalizer is activated for the loudspeaker chan-

nel. Bass and Equalizer cannot work simultaneously. If Equalizer is used, Bass,

and Treble coefficients must be set to zero and vice versa.

00 02_hex

00 31_hex

Bass Loudspeaker Channel

Bass Headphone Channel

BASS_MAIN

BASS_AUX

bit [15:8] normal range

60_hex

58_hex

...

+12 dB

+11 dB

08_hex

00_hex

F8_hex

...

+1 dB

0 dB

−1 dB

A8_hex

A0_hex

−11 dB

−12 dB

bit [15:8] extended range

7F_hex

78_hex

70_hex

68_hex

+20 dB

+18 dB

+16 dB

+14 dB

Higher resolution is possible: an LSB step in the normal range results in a gain

step of about 1/8 dB, in the extended range about 1/4 dB.

With positive bass settings, internal clipping may occur even with overall volume

less than 0 dB. This will lead to a clipped output signal. Therefore, it is not rec-

ommended to set bass to a value that, in conjunction with volume, would result

in an overall positive gain.

32

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

Table 3–11: Write Registers on I²C Subaddress 12_hex, continued

Register

Address

Function

Name

00 03_hex

00 32_hex

Treble Loudspeaker Channel

Treble Headphone Channel

TREB_MAIN

TREB_AUX

bit [15:8] 78_hex

+15 dB

+14 dB

70_hex

...

08_hex

00_hex

F8_hex

...

+1 dB

0 dB

−1 dB

A8_hex

A0_hex

−11 dB

−12 dB

Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB.

With positive treble settings, internal clipping may occur even with overall vol-

ume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not

recommended to set treble to a value that, in conjunction with volume, would

result in an overall positive gain.

00 21_hex

00 22_hex

00 23_hex

00 24_hex

00 25_hex

Equalizer Loudspeaker Channel Band 1 (below 120 Hz)

Equalizer Loudspeaker Channel Band 2 (center: 500 Hz)

Equalizer Loudspeaker Channel Band 3 (center: 1.5 kHz)

Equalizer Loudspeaker Channel Band 4 (center: 5 kHz)

Equalizer Loudspeaker Channel Band 5 (above: 10 kHz)

EQUAL_BAND1

EQUAL_BAND2

EQUAL_BAND3

EQUAL_BAND4

EQUAL_BAND5

bit [15:8] 60_hex

+12 dB

+11 dB

58_hex

...

08_hex

00_hex

F8_hex

...

+1 dB

0 dB

−1 dB

A8_hex

A0_hex

−11 dB

−12 dB

Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB.

With positive equalizer settings, internal clipping may occur even with overall

volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is

not recommended to set equalizer bands to a value that, in conjunction with vol-

ume, would result in an overall positive gain.

MICRONAS INTERMETALL

33

MSP 34x0G

PRELIMINARY DATA SHEET

Table 3–11: Write Registers on I²C Subaddress 12_hex, continued

Register

Address

Function

Name

00 04_hex

00 33_hex

Loudness Loudspeaker Channel

Loudness Headphone Channel

LOUD_MAIN

LOUD_AUX

bit [15:8] Loudness Gain

44_hex

40_hex

...

+17 dB

+16 dB

04_hex

00_hex

+1 dB

0 dB

bit [7:0]

Loudness Mode

00_hex

04_hex

normal (constant volume at 1 kHz)

Super Bass (constant volume at 2 kHz)

Higher resolution of Loudness Gain is possible: An LSB step results in a gain

step of about 1/4 dB.

Loudness increases the volume of low- and high-frequency signals, while keep-

ing the amplitude of the 1-kHz reference frequency constant. The intended loud-

ness has to be set according to the actual volume setting. Because loudness

introduces gain, it is not recommended to set loudness to a value that, in con-

junction with volume, would result in an overall positive gain.

The corner frequency for bass amplification can be set to two different values. In

Super Bass mode, the corner frequency is shifted up. The point of constant vol-

ume is shifted from 1 kHz to 2 kHz.

34

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MSP 34x0G

Table 3–11: Write Registers on I²C Subaddress 12_hex, continued

Register

Address

Function

Name

00 05_hex

Spatial Effects Loudspeaker Channel

SPAT_MAIN

bit [15:8] Effect Strength

7F_hex

3F_hex

...

Enlargement 100%

Enlargement 50%

01_hex

00_hex

FF_hex

...

Enlargement 1.5%

Effect off

reduction 1.5%

C0_hex

80_hex

reduction 50%

reduction 100%

bit [7:4]

bit [3:0]

Spatial Effect Mode

0_hexStereo Basewidth Enlargement (SBE) and

Pseudo Stereo Effect (PSE). (Mode A)

2_hex

Stereo Basewidth Enlargement (SBE) only. (Mode B)

Spatial Effect High-Pass Gain

0_hex

2_hex

4_hex

6_hex

8_hex

max. high-pass gain

2/3 high-pass gain

1/3 high-pass gain

min. high-pass gain

automatic

There are several spatial effect modes available:

In mode A (low byte = 00_hex), the spatial effect depends on the source mode. If

the incoming signal is mono, Pseudo Stereo Effect is active; for stereo signals,

Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The

strength of the effect is controllable by the upper byte. A negative value reduces

the stereo image. A strong spatial effect is recommended for small TV sets

where loudspeaker spacing is rather close. For large screen TV sets, a more

moderate spatial effect is recommended.

In mode B, only Stereo Basewidth Enlargement is effective. For mono input sig-

nals, the Pseudo Stereo Effect has to be switched on.

It is worth mentioning, that all spatial effects affect amplitude and phase

response. With the lower 4 bits, the frequency response can be customized. A

value of 0_hexyields a flat response for center signals (L = R), but a high-pass

function for L or R only signals. A value of 6_hexhas a flat response for L or R

only signals, but a low-pass function for center signals. By using 8_hex, the fre-

quency response is automatically adapted to the sound material by choosing an

optimal high-pass gain.

MICRONAS INTERMETALL

35

MSP 34x0G

PRELIMINARY DATA SHEET

Table 3–11: Write Registers on I²C Subaddress 12_hex, continued

Register

Address

Function

Name

SUBWOOFER OUTPUT CHANNEL

00 2C_hexSubwoofer Level Adjustment

SUBW_LEVEL

bit [15:8] 00_hex

0 dB

FF_hex

...

−1 dB

E3_hex

E2_hex

...

−29 dB

−30 dB

80_hex

Mute

00 2D_hex

Subwoofer Corner Frequency

SUBW_FREQ

SUBW_HP

bit [15:8] 5...40

corner frequency in 10-Hz steps

(range: 50...400 Hz)

Subwoofer Complementary High-Pass Filter

bit [7:0]

00_hex

01_hex

loudspeaker channel unfiltered

a complementary high-pass is processed in the loud-

speaker output channel

SCART OUTPUT CHANNEL

00 07_hex

00 40_hex

Volume SCART1 Output Channel

Volume SCART2 Output Channel

VOL_SCART1

VOL_SCART2

bit [15:8] volume table with 1 dB step size

7F_hex

7E_hex

...

+12 dB (maximum volume)

+11 dB

74_hex

73_hex

72_hex

...

+1 dB

0 dB

−1 dB

02_hex

01_hex

00_hex

−113 dB

−114 dB

Mute (reset condition)

bit [7:5]

bit [4:0]

higher resolution volume table

0

+0 dB

1

+0.125 dB increase in addition to the volume table

...

7

+0.875 dB increase in addition to the volume table

01_hex

this must be 01_hex

36

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PRELIMINARY DATA SHEET

MSP 34x0G

Table 3–11: Write Registers on I²C Subaddress 12_hex, continued

Register

Address

Function

Name

SCART SWITCHES AND DIGITAL I/O PINS

00 13_hex

ACB Register

ACB_REG

Defines the level of the digital output pins and the position of the SCART switches

bit [15]

0/1

low/high of digital output pin D_CTR_I/O_0

(MODUS[3]=0)

bit [14]

0/1

low/high of digital output pin D_CTR_I/O_1

(MODUS[3]=0)

bit [13:5] SCART DSP Input Select

xxxx00xx0 SCART1 to DSP input (RESET position)

xxxx01xx0 MONO to DSP input (Sound A Mono must be selected in

the channel matrix mode for the corresponding output

channels)

xxxx10xx0 SCART2 to DSP input

xxxx11xx0 SCART3 to DSP input

xxxx00xx1 SCART4 to DSP input

xxxx11xx1 mute DSP input

bit [13:5] SCART1 Output Select

xx00xxx0x SCART3 input to SCART1 output (RESET position)

xx01xxx0x SCART2 input to SCART1 output

xx10xxx0x MONO input to SCART1 output

xx11xxx0x SCART1 DA to SCART1 output

xx00xxx1x SCART2 DA to SCART1 output

xx01xxx1x SCART1 input to SCART1 output

xx10xxx1x SCART4 input to SCART1 output

xx11xxx1x mute SCART1 output

bit [13:5] SCART2 Output Select

00xxxx0xx SCART1 DA to SCART2 output (RESET position)

01xxxx0xx SCART1 input to SCART2 output

10xxxx0xx MONO input to SCART2 output

00xxxx1xx SCART2 DA to SCART2 output

01xxxx1xx SCART2 input to SCART2 output

10xxxx1xx SCART3 input to SCART2 output

11xxxx1xx SCART4 input to SCART2 output

11xxxx0xx mute SCART2 output

The RESET position becomes active at the time of the first write transmission

on the control bus to the audio processing part. By writing to the ACB register

first, the RESET state can be redefined.

BEEPER

00 14_hex

Beeper Volume and Frequency

BEEPER

bit [15:8] Beeper Volume

00_hex

7F_hex

off

maximum volume

bit [7:0]

Beeper Frequency

01_hex

40_hex

FF_hex

16 Hz (lowest)

1 kHz

4 kHz

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37

MSP 34x0G

PRELIMINARY DATA SHEET

3.3.2.7. Read Registers on I²C Subaddress 13_hex

Table 3–12: Read Registers on I²C Subaddress 13_hex

Register

Address

Function

Name

QUASI-PEAK DETECTOR READOUT

00 19_hex

00 1a_hex

Quasi-Peak Detector Readout Left

Quasi-Peak Detector Readout Right

QPEAK_L

QPEAK_R

bit [15..0] 0_hex... 7FFF_hexvalues are 16 bit two’s complement (only positive)

MSP 34X0G VERSION READOUT REGISTERS

00 1E_hexMSP Hardware Version Code

MSP_HARD

bit [15..8] 02_hex

MSP 34x0G - B6

A change in the hardware version code defines hardware optimizations that

may have influence on the chip’s behavior. The readout of this register is iden-

tical to the hardware version code in the chip’s imprint.

MSP Major Revision Code

MSP_REVISION

MSP_PRODUCT

bit [7..0] 07_hex

MSP 34x0G - B6

The major revision code of the MSP 34x0G is 7.

00 1F_hex

MSP Product Code

bit [15..8] 00_hex

0A_hex

MSP 3400G - B6

MSP 3410G - B6

MSP 3430G - B6

MSP 3440G - B6

MSP 3450G - B6

1E_hex

28_hex

32_hex

By means of the MSP-Product Code, the control processor is able to decide

which TV sound standards have to be considered.

MSP ROM Version Code

MSP_ROM

bit [7..0] 45_hex

46_hex

MSP 34x0G - B5

MSP 34x0G - B6

A change in the ROM version code defines internal software optimizations,

that may have influence on the chip’s behavior, e.g. new features may have

been included. While a software change is intended to create no compatibility

problems, customers that want to use the new functions can identify new

MSP 34x0G versions according to this number.

To avoid compatibility problems with MSP 3410B and MSP 34x0D, an offset of

40_hexis added to the ROM version code of the chip’s imprint.

38

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

3.4. Programming Tips

3.5. Examples of Minimum Initialization Codes

This section describes the preferred method for initial-

izing the MSP 34x0G. The initialization is grouped into

four sections: analog signal path, demodulator input,

input processing for SCART and I²S, and output pro-

cessing. See Fig. 2–1 on page 8 for a complete signal

flow.

Initialization of the MSP 34x0G according to these list-

ings reproduces sound of the selected standard on the

loudspeaker output. All numbers are hexadecimal. The

examples have the following structure:

1. Perform an I²C controlled reset of the IC.

2. Write MODUS register

(with Automatic Sound Select).

SCART Signal Path

3. Set Source Selection for loudspeaker channel

(with matrix set to STEREO).

1. Select analog input for the SCART baseband pro-

cessing (SCART DSP Input Select) by means of the

ACB register.

4. Set Prescale

(FM and/or NICAM and dummy FM matrix).

2. Select the source for each analog SCART output

(SCART Output Select) by means of the ACB regis-

ter.

5. Write STANDARD SELECT register.

6. Set Volume loudspeaker channel to 0 dB.

Demodulator Input

3.5.1. B/G-FM (A2 or NICAM)

<80 00 80 00>

<80 00 00 00>

// Softreset

For a complete setup of the TV sound processing from

analog IF input to the source selection, the following

steps must be performed:

<80 10 00 30 20 03> // MODUS-Register: Automatic = on

<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St

1. Set MODUS register to the preferred mode and

Sound IF input.

<80 12 00 0E 24 03> // FM/AM-Prescale = 24hex,

FM-Matrix = MONO/SOUNDA

<80 12 00 10 00 5A> // NICAM-Prescale = 5A

hex

<80 10 00 20 00 03> // Standard Select: A2 B/G or NICAM B/G

2. Choose preferred prescale (FM and NICAM) values.

3. Write STANDARD SELECT register.

or

<80 10 00 20 00 08>

If Automatic Sound Select is not active, the following

step has to be done repeatedly:

<80 12 00 00 73 00> // Loudspeaker Volume 0 dB

4. Choose FM matrix according to the sound mode

indicated in the STATUS register.

3.5.2. BTSC-Stereo

<80 00 80 00>

<80 00 00 00>

// Softreset

SCART and I²S Inputs

<80 10 00 30 20 03> // MODUS-Register: Automatic = on

<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St

1. Select preferred prescale for SCART.

2. Select preferred prescale for I²S inputs

(set to 0 dB after RESET).

<80 12 00 0E 24 03> // FM/AM-Prescale = 24

,

hex

FM-Matrix = Sound A Mono

<80 10 00 20 00 20> // Standard Select: BTSC-STEREO

<80 12 00 00 73 00> // Loudspeaker Volume 0 dB

Output Channels

3.5.3. BTSC-SAP with SAP at Loudspeaker Channel

1. Select the source channel and matrix for each out-

put channel.

<80 00 80 00>

<80 00 00 00>

// Softreset

2. Set audio baseband processing.

<80 10 00 30 20 03> // MODUS-Register: Automatic = on

<80 12 00 08 04 20> // Source Sel. = (St or B) & Ch. Matr. = St

3. Select volume for each output channel.

<80 12 00 0E 24 03> // FM/AM-Prescale = 24

,

hex

FM-Matrix = Sound A Mono

<80 10 00 20 00 21> // Standard Select: BTSC-SAP

<80 12 00 00 73 00> // Loudspeaker Volume 0 dB

MICRONAS INTERMETALL

39

MSP 34x0G

PRELIMINARY DATA SHEET

3.5.4. FM-Stereo Radio

<80 00 80 00>

// Softreset

<80 00 00 00>

<80 10 00 30 20 03> // MODUS-Register: Automatic = on

<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St

<80 12 00 0E 24 03> // FM/AM-Prescale = 24

,

hex

FM-Matrix = Sound A Mono

<80 10 00 20 00 40> // Standard Select: FM-STEREO-RADIO

<80 12 00 00 73 00> // Loudspeaker Volume 0 dB

3.5.5. Automatic Standard Detection

A detailed software flow diagram is shown in Fig. 3–2

on page 41.

<80 00 80 00>

<80 00 00 00>

// Softreset

<80 10 00 30 20 03> // MODUS-Register: Automatic = on

<80 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St

<80 12 00 0E 24 03> // FM/AM-Prescale = 24

,

hex

FM-Matrix = Sound A Mono

<80 12 00 10 00 5A> // NICAM-Prescale = 5A

hex

<80 10 00 20 00 01> // Standard Select:

Automatic Standard Detection

// Wait till STANDARD RESULT contains a value ≤ 07FF

// IF STANDARD RESULT contains 0000

// do some error handling

// ELSE

<80 12 00 00 73 00> // Loudspeaker Volume 0 dB

3.5.6. Software Flow for Interrupt driven STATUS

Check

A detailed software flow diagram is shown in Fig. 3–2

on page 41.

If the D_CTR_I/O_1 pin of the MSP 34x0G is con-

nected to an interrupt input pin of the controller, the fol-

lowing interrupt handler can be applied to be automati-

cally called with each status change of the

MSP 34x0G. The interrupt handler may adjust the TV

display according to the new status information.

Interrupt Handler:

<80 11 02 00 <81 dd dd> // Read STATUS

// adjust TV display with given status information

// Return from Interrupt

40

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

Write MODUS Register

:

Example for the essential bits:

[0] = 1

[1] = 1

[8] = 0

Automatic Sound Select = on

Enable interrupt if STATUS changes

ANA_IN1+ is selected

Define Preference for Automatic Standard

Detection:

[12] = 0

If 6.5 MHz, set SECAM-L

[14:13] = 3 Ignore 4.5 MHz carrier

Write SOURCE SELECT Settings

Example:

set loudspeaker Source Select to "Stereo or A"

set headphone Source Select to "Stereo or B"

set SCART_Out Source Select to "Stereo or A/B"

set Channel Matrix mode for all outputs to "Stereo"

Write FM/AM-Prescale

Write NICAM-Prescale

Write 01 into

STANDARD SELECT Register

(Start Automatic Standard Detection)

set previous standard or

set standard manually according

picture information

Result = 0

yes

?

no

expecting MSPG-interrupt

In case of MSPG-

Interrupt to Controller:

Read STATUS

Adjust TV-Display

If Bilingual, adjust Source Select setting if required

Fig. 3–2: Software flow diagram for a Minimum demodulator setup for a European Multistandard TV set applying the

Automatic Sound Select feature

MICRONAS INTERMETALL

41

MSP 34x0G

PRELIMINARY DATA SHEET

4. Specifications

4.1. Outline Dimensions

± 0.1

16 x 1.27 = 20.32

1.27

1.2 x 45°

1.1 x 45 °

9

1

61

10

60

2

9

7.5

9

26

44

±0.05

1.9

27

43

±0.1

4.05

± 0.1

24.2

± 0.12

25.14

0.1

±0.15

4.75

SPGS0027-2(P68)/1E

Fig. 4–1:

68-Pin Plastic Leaded Chip Carrier Package

(PLCC68)

Weight approximately 4.8 g

Dimensions in mm

SPGS0016-5(P52)/1E

SPGS0016-5(P64)/1E

52

27

26

64

33

1

32

±0.1

15.6

±0.1

47.0

±0.1

14

±0.1

19.3

±0.1

57.7

±0.05

18

±0.06

0.28

±1

±0.05

16.3

1

±0.06

0.28

±0.06

0.48

1.778

25 x 1.778 = 44.4

±0.5

±0.05

20.3

1

±0.1

±0.06

0.48

1.778

31 x 1.778 = 55.1

±0.1

Fig. 4–3:

52-Pin Plastic Shrink Dual-Inline Package

(PSDIP52)

Weight approximately 5.5 g

Dimensions in mm

Fig. 4–2:

64-Pin Plastic Shrink Dual-Inline Package

(PSDIP64)

Weight approximately 9.0 g

Dimensions in mm

42

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

± 0.1

23 x 0.8 = 18.4

± 0.04

0.17

0.8

64

41

40

65

8

5

1.8

10.3

9.8

16

25

80

± 0.05

1.3

1

24

± 0.1

2.7

± 0.1

20

± 0.15

23.2

0.1

±0.2

3

SPGS705000-1(P80)/1E

Fig. 4–4:

80-Pin Plastic Quad Flat Pack

(PQFP80)

Weight approximately 1.61 g

Dimensions in mm

± 0.1

15 x 0.5 = 7.5

0.5

± 0.055

0.145

48

33

49

64

32

17

1

16

± 0.05

1.4

1.75

± 0.1

± 0.2

10

12

0.1

± 0.1

1.5

D0025/3E

Fig. 4–5:

64-Pin Plastic Low-Profile Quad Flat Pack

(PLQFP64)

Weight approximately 0.35 g

Dimensions in mm

MICRONAS INTERMETALL

43

MSP 34x0G

PRELIMINARY DATA SHEET

4.2. Pin Connections and Short Descriptions

NC = not connected; leave vacant

LV = if not used, leave vacant

OBL = obligatory; connect as described in circuit diagram

DVSS: if not used, connect to DVSS

AHVSS: connect to AHVSS

Pin No.

Pin Name

Type

Connection

(if not used)

Short Description

PLCC

68-pin

PSDIP

64-pin

PSDIP

52-pin

PQFP

80-pin

PLQFP

64-pin

1

16

−

14

−

9

8

ADR_WS

NC

OUT

LV

ADR word strobe

Not connected

ADR data output

I²S1 data input

I²S data output

I²S word strobe

I²S clock

2

−

3

15

14

13

12

11

10

9

13

12

11

10

9

8

7

ADR_DA

I2S_DA_IN1

I2S_DA_OUT

I2S_WS

I2S_CL

OUT

IN

4

7

6

5

6

5

OUT

6

5

4

IN/OUT LV

IN/OUT OBL

LV

7

4

3

8

3

2

I2C_DA

I²C data

9

7

2

1

I2C_CL

I²C clock

10

11

12

13

14

15

16

17

18

8

−

1

64

63

62

61

60

59

58

−

NC

Not connected

Stand-by (low-active)

I²C Bus address select

D_CTR_I/O_0

D_CTR_I/O_1

Not connected

7

6

80

79

78

77

76

75

−

STANDBYQ

ADR_SEL

D_CTR_I/O_0

D_CTR_I/O_1

NC

IN

OBL

6

5

4

IN/OUT LV

4

3

IN/OUT LV

3

−

LV

2

−

NC

−

NC

1

2

74

57

AUD_CL_OUT

OUT

LV

Audio clock output

(18.432 MHz)

19

20

21

22

23

64

63

62

61

60

1

73

72

71

70

69

56

55

54

53

52

TP

LV

Test pin

52

51

50

49

XTAL_OUT

XTAL_IN

TESTEN

ANA_IN2+

OUT

IN

OBL

Crystal oscillator

Test pin

IN

AVSS via

56 pF / LV

IF input 2 (can be left

vacant, only if IF input 1 is

also not in use)

24

59

48

68

51

ANA_IN−

IN

AVSS via

56 pF / LV

IF common (can be left

vacant, only if IF input 1 is

also not in use)

44

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

Pin No.

Pin Name

Type

Connection

(if not used)

Short Description

PLCC

68-pin

PSDIP

64-pin

PSDIP

52-pin

PQFP

80-pin

PLQFP

64-pin

25

26

−

58

57

−

47

46

−

67

66

65

64

63

62

61

60

59

58

50

49

−

ANA_IN1+

AVSUP

NC

IN

LV

IF input 1

OBL

LV

Analog power supply 5 V

Not connected

Analog ground

Mono input

−

NC

LV

27

−

56

−

45

−

48

−

AVSS

OBL

LV

AVSS

28

−

55

−

44

−

47

−

MONO_IN

NC

IN

LV

Not connected

29

54

43

46

VREFTOP

OBL

Reference voltage IF

A/D converter

30

31

32

33

34

35

36

37

38

39

40

41

42

53

52

51

50

49

48

47

46

45

44

43

−

42

41

−

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

−

SC1_IN_R

SC1_IN_L

ASG1

IN

LV

SCART 1 input, right

SCART 1 input, left

Analog Shield Ground 1

SCART 2 input, right

SCART 2 input, left

Analog Shield Ground 2

SCART 3 input, right

SCART 3 input, left

Analog Shield Ground 4

SCART 4 input, right

SCART 4 input, left

LV

AHVSS

LV

40

39

−

SC2_IN_R

SC2_IN_L

ASG2

IN

LV

AHVSS

LV

38

37

−

SC3_IN_R

SC3_IN_L

ASG4

IN

LV

AHVSS

LV

−

SC4_IN_R

SC4_IN_L

NC

IN

−

LV

−

LV or AHVSS Not connected

42

36

34

AGNDC

OBL

Analog reference

voltage

43

−

41

−

35

−

44

43

42

41

40

39

38

33

−

AHVSS

NC

OBL

LV

Analog ground

−

Not connected

−

NC

LV

Not connected

44

45

46

40

39

38

34

33

32

31

30

CAPL_M

AHVSUP

CAPL_A

OBL

Volume capacitor MAIN

Analog power supply 8 V

Volume capacitor AUX

MICRONAS INTERMETALL

45

MSP 34x0G

PRELIMINARY DATA SHEET

Pin No.

Pin Name

Type

Connection

(if not used)

Short Description

PLCC

68-pin

PSDIP

64-pin

PSDIP

52-pin

PQFP

80-pin

PLQFP

64-pin

47

48

49

50

51

52

53

54

55

56

57

58

59

60

−

37

36

35

34

33

−

31

30

29

28

27

−

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

29

28

27

26

25

−

SC1_OUT_L

SC1_OUT_R

VREF1

SC2_OUT_L

SC2_OUT_R

NC

OUT

LV

SCART output 1, left

SCART output 1, right

Reference ground 1

SCART output 2, left

SCART output 2, right

Not connected

LV

OBL

LV

OUT

LV

32

31

30

29

28

27

26

25

−

24

23

22

21

20

19

18

17

−

NC

LV

Not connected

26

−

DACM_SUB

NC

OUT

LV

Subwoofer output

Not connected

LV

25

24

23

22

21

−

DACM_L

DACM_R

VREF2

DACA_L

DACA_R

NC

OUT

LV

Loudspeaker out, left

Loudspeaker out, right

Reference ground 2

Headphone out, left

Headphone out, right

Not connected

LV

OBL

LV

OUT

LV

−

NC

LV

Not connected

61

62

63

64

65

66

−

24

23

22

21

20

19

−

20

−

16

15

14

13

12

11

−

RESETQ

NC

IN

OBL

LV

Power-on-reset

Not connected

−

NC

LV

Not connected

19

18

17

−

NC

LV

Not connected

I2S_DA_IN2

DVSS

LV

I²S2-data input

OBL

LV

Digital ground

DVSS

Digital ground

−

DVSS

Digital ground

67

−

18

−

16

−

10

−

DVSUP

ADR_CL

Digital power supply 5 V

ADR clock

−

68

17

15

9

OUT

¹⁾Due to the compatibility with MSP 3410B, it is possible to connect with DVSS as well.

46

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

4.3. Pin Descriptions

Pin numbers refer to the 80-pin PQFP package.

Pin 1, NC – Pin not connected.

Pins 22, 23, NC – Pins not connected.

Pins 24, 25, DACA_R/L – Headphone Outputs

(Fig. 4–21)

Output of the headphone signal. A 1-nF capacitor to

AHVSS must be connected to these pins. The DC off-

set on these pins depends on the selected headphone

volume.

Pin 2, I2C_CL – I²C Clock Input/Output (Fig. 4–12)

Via this pin, the I²C-bus clock signal has to be sup-

plied. The signal can be pulled down by the MSP in

case of wait conditions.

Pin 3, I2C_DA – I²C Data Input/Output (Fig. 4–12)

Via this pin, the I²C-bus data is written to or read from

the MSP.

Pin 26, VREF2 – Reference Ground 2

Reference analog ground. This pin must be connected

separately to the single ground point (AHVSS). VREF2

serves as a clean ground and should be used as the

reference for analog connections to the loudspeaker

and headphone outputs.

Pin 4, I2S_CL – I²S Clock Input/Output (Fig. 4–15)

Clock line for the I²S bus. In master mode, this line is

driven by the MSP; in slave mode, an external I²S

clock has to be supplied.

Pins 27, 28, DACM_R/L – Loudspeaker Outputs

(Fig. 4–21)

Output of the loudspeaker signal. A 1-nF capacitor to

AHVSS must be connected to these pins. The DC off-

set on these pins depends on the selected loud-

speaker volume.

Pin 5, I2S_WS – I²S Word Strobe Input/Output

(Fig. 4–15)

Word strobe line for the I²S bus. In master mode, this

line is driven by the MSP; in slave mode, an external

I²S word strobe has to be supplied.

Pin 29, NC – Pin not connected.

Pin 6, I2S_DA_OUT – I²S Data Output (Fig. 4–11)

Output of digital serial sound data of the MSP on the

I²S bus.

Pin 30, DACM_SUB – Subwoofer Output (Fig. 4–21)

Output of the subwoofer signal. A 1-nF capacitor to

AHVSS must be connected to this pin. Due to the low

frequency content of the subwoofer output, the value

of the capacitor may be increased for better suppres-

sion of high-frequency noise. The DC offset on this pin

depends on the selected loudspeaker volume.

Pin 7, I2S_DA_IN1 – I²S Data Input 1 (Fig. 4–13)

First input of digital serial sound data to the MSP via

the I²S bus.

Pin 8, ADR_DA – ADR Bus Data Output (Fig. 4–11)

Output of digital serial data to the DRP 3510A via the

ADR bus.

Pins 31, 32 NC – Pin not connected.

Pins 33, 34, SC2_OUT_R/L – SCART2 Outputs

(Fig. 4–23)

Output of the SCART2 signal. Connections to these

pins must use a 100-Ω series resistor and are intended

to be AC-coupled.

Pin 9, ADR_WS – ADR Bus Word Strobe Output

(Fig. 4–11)

Word strobe output for the ADR bus.

Pin 10, ADR_CL – ADR Bus Clock Output (Fig. 4–11)

Clock line for the ADR bus.

Pin 35, VREF1 – Reference Ground 1

Reference analog ground. This pin must be connected

separately to the single ground point (AHVSS). VREF1

serves as a clean ground and should be used as the

reference for analog connections to the SCART out-

puts.

Pins 11, 12, 13, DVSUP* – Digital Supply Voltage

Power supply for the digital circuitry of the MSP. Must

be connected to a +5 V power supply.

Pins 14, 15, 16, DVSS* – Digital Ground

Ground connection for the digital circuitry of the MSP.

Pins 36, 37, SC1_OUT_R/L – SCART1 Outputs

(Fig. 4–23)

Output of the SCART1 signal. Connections to these

pins must use a 100-Ω series resistor and are intended

to be AC-coupled.

Pin 17, I2S_DA_IN2 – I²S Data Input 2 (Fig. 4–13)

Second input of digital serial sound data to the MSP

via the I²S bus.

Pins 18, 19, 20, NC – Pins not connected.

Pin 21, RESETQ – Reset Input (Fig. 4–13)

In the steady state, high level is required. A low level

resets the MSP 34x0G.

MICRONAS INTERMETALL

47

MSP 34x0G

PRELIMINARY DATA SHEET

Pin 38, CAPL_A – Volume Capacitor Headphone

(Fig. 4–18)

Pins 53, 54 SC2_IN_L/R – SCART2 Inputs (Fig. 4–20)

The analog input signal for SCART2 is fed to this pin.

Analog input connection must be AC-coupled.

A 10-µF capacitor to AHVSUP must be connected to

this pin. It serves as a smoothing filter for headphone

volume changes in order to suppress audible plops.

The value of the capacitor can be lowered to 1-µF if

faster response is required. The area encircled by the

trace lines should be minimized; keep traces as short

as possible. This input is sensitive for magnetic induc-

tion.

Pin 55, ASG1 – Analog Shield Ground 1

Analog ground (AHVSS) should be connected to this

pin to reduce cross-coupling between SCART inputs.

Pins 56, 57 SC1_IN_L/R – SCART1 Inputs (Fig. 4–20)

The analog input signal for SCART1 is fed to this pin.

Analog input connection must be AC-coupled.

Pin 39, AHVSUP* – Analog Power Supply High Volt-

age

Power is supplied via this pin for the analog circuitry of

the MSP (except IF input). This pin must be connected

to the +8 V supply.

Pin 58, VREFTOP – Reference Voltage IF A/D Con-

verter (Fig. 4–17)

Via this pin, the reference voltage for the IF A/D con-

verter is decoupled. It must be connected to AVSS

pins with a 10-µF and a 100-nF capacitor in parallel.

Traces must be kept short.

Pin 40, CAPL_M – Volume Capacitor Loudspeaker

(Fig. 4–18)

A 10-µF capacitor to AHVSUP must be connected to

this pin. It serves as a smoothing filter for loudspeaker

volume changes in order to suppress audible plops.

The value of the capacitor can be lowered to 1 µF if

faster response is required. The area encircled by the

trace lines should be minimized; keep traces as short

as possible. This input is sensitive for magnetic induc-

tion.

Pin 59, NC – Pin not connected.

Pin 60 MONO_IN – Mono Input (Fig. 4–20)

The analog mono input signal is fed to this pin. Analog

input connection must be AC-coupled.

Pins 61, 62, AVSS* – Analog Power Supply Voltage

Ground connection for the analog IF input circuitry of

the MSP.

Pins 41, 42, NC – Pins not connected.

Pins 63, 64, NC – Pins not connected.

Pins 43, 44, AHVSS* – Analog Power Supply High

Voltage

Ground connection for the analog circuitry of the MSP

(except IF input).

Pins 65, 66, AVSUP* – Analog Power Supply Voltage

Power is supplied via this pin for the analog IF input

circuitry of the MSP. This pin must be connected to the

+5 V supply.

Pin 45, AGNDC – Internal Analog Reference Voltage

This pin serves as the internal ground connection for

the analog circuitry (except IF input). It must be con-

nected to the VREF pins with a 3.3-µF and a 100-nF

capacitor in parallel. This pins shows a DC level of typ-

ically 3.73 V.

Pin 67, ANA_IN1+ – IF Input 1 (Fig. 4–17)

The analog sound IF signal is supplied to this pin.

Inputs must be AC-coupled. This pin is designed as

symmetrical input: ANA_IN1+ is internally connected

to one input of a symmetrical op amp, ANA_IN- to the

other.

Pin 46, NC – Pin not connected.

Pin 68, ANA_IN− – IF Common (Fig. 4–17)

This pins serves as a common reference for ANA_IN1/

2+ inputs.

Pins 47, 48, SC4_IN_L/R – SCART4 Inputs

(Fig. 4–20)

The analog input signal for SCART4 is fed to this pin.

Analog input connection must be AC-coupled.

Pin 69, ANA_IN2+ – IF Input 2 (Fig. 4–17)

The analog sound if signal is supplied to this pin.

Inputs must be AC-coupled. This pin is designed as

symmetrical input: ANA_IN2+ is internally connected

to one input of a symmetrical op amp, ANA_IN− to the

other.

Pin 49, ASG4 – Analog Shield Ground 4

Analog ground (AHVSS) should be connected to this

pin to reduce cross-coupling between SCART inputs.

Pins 50, 51, SC3_IN_L/R – SCART3 Inputs

(Fig. 4–20)

The analog input signal for SCART3 is fed to this pin.

Analog input connection must be AC-coupled.

Pin 70, TESTEN – Test Enable Pin (Fig. 4–13)

This pin enables factory test modes. For normal opera-

tion, it must be connected to ground.

Pin 52, ASG2 – Analog Shield Ground 2

Analog ground (AHVSS) should be connected to this

pin to reduce cross-coupling between SCART inputs.

48

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

Pins 71, 72 XTAL_IN, XTAL_OUT – Crystal Input and

Output Pins (Fig. 4–16)

These pins are connected to an 18.432 MHz crystal

oscillator which is digitally tuned by integrated shunt

capacitances. An external clock can be fed into

XTAL_IN.

The

audio

clock

output

signal

AUD_CL_OUT is derived from the oscillator. External

capacitors at each crystal pin to ground (AVSS) are

required. It should be verified by layout, that no supply

current for the digital circuitry is flowing through the

ground connection point.

Pin 73, TP – This pin enables factory test modes. For

normal operation, it must be left vacant.

Pin 74, AUD_CL_OUT – Audio Clock Output

(Fig. 4–16)

This is the 18.432 MHz main clock output.

Pins 75, 76, NC – Pins not connected.

Pins 77, 78, D_CTR_I/O_1/0 – Digital Control Input/

Output Pins (Fig. 4–15)

These pins serve as general purpose input/output

pins. Pin D_CTR_I/O_1 can be used as an interrupt

request pin to the controller.

Pin 79, ADR_SEL – I²C Bus Address Select

(Fig. 4–14)

By means of this pin, one of three device addresses

for the MSP can be selected. The pin can be con-

nected to ground (I²C device addresses 80/81_hex), to

+5 V supply (84/85_hex), or left open (88/89_hex).

Pin 80, STANDBYQ – Stand-by

In normal operation, this pin must be High. If the

MSP 34x0G is switched off by first pulling STANDBYQ

low and then (after >1 µs delay) switching off the 5 V,

but keeping the 8-V power supply (‘Stand-by’-mode),

the SCART switches maintain their position and func-

tion.

* Application Note:

All ground pins should be connected to one low-resis-

tive ground plane. All supply pins should be connected

separately with short and low-resistive lines to the

power supply. Decoupling capacitors from DVSUP to

DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are

recommended as closely as possible to these pins.

Decoupling of DVSUP and DVSS is most important.

We recommend using more than one capacitor. By

choosing different values, the frequency range of

active decoupling can be extended. In our application

boards we use: 220 pF, 470 pF, 1.5 nF, and 10 µF. The

capacitor with the lowest value should be placed near-

est to the DVSUP and DVSS pins.

MICRONAS INTERMETALL

49

MSP 34x0G

PRELIMINARY DATA SHEET

4.4. Pin Configurations

ADR_WS

NC

ADR_CL

DVSUP

DVSS

I2S_DA_IN2

NC

ADR_DA

I2S_DA_IN1

I2S_DA_OUT

I2S_WS

I2S_CL

I2C_DA

NC

I2C_CL

RESETQ

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

NC 10

STANDBYQ 11

ADR_SEL 12

D_CTR_I/O_0 13

D_CTR_I/O_1 14

NC 15

60 DACA_R

59 DACA_L

58 VREF2

57 DACM_R

56 DACM_L

55 NC

NC 16

54 DACM_SUB

53 NC

NC 17

AUD_CL_OUT 18

TP 19

52 NC

MSP 34x0G

51 SC2_OUT_R

50 SC2_OUT_L

49 VREF1

XTAL_OUT 20

XTAL_IN 21

TESTEN 22

ANA_IN2+ 23

ANA_IN− 24

ANA_IN1+ 25

AVSUP 26

48 SC1_OUT_R

47 SC1_OUT_L

46 CAPL_A

45 AHVSUP

44 CAPL_M

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

AVSS

AHVSS

MONO_IN

VREFTOP

SC1_IN_R

SC1_IN_L

ASG1

SC2_IN_R

SC2_IN_L

AGNDC

NC

SC4_IN_L

SC4_IN_R

ASG4

SC3_IN_L

SC3_IN_R

ASG2

Fig. 4–6: 68-pin PLCC package

50

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

AUD_CL_OUT

NC

1

2

3

4

5

6

7

8

9

64 TP

TP

AUD_CL_OUT

D_CTR_I/O_1

D_CTR_I/O_0

ADR_SEL

1

2

3

4

5

6

7

8

9

52 XTAL_OUT

51 XTAL_IN

50 TESTEN

49 ANA_IN2+

48 ANA_IN−

47 ANA_IN1+

46 AVSUP

63 XTAL_OUT

62 XTAL_IN

61 TESTEN

60 ANA_IN2+

59 ANA_IN−

58 ANA_IN+

57 AVSUP

NC

D_CTR_I/O_1

D_CTR_I/O_0

ADR_SEL

STANDBYQ

NC

STANDBYQ

I2C_CL

I2C_DA

45 AVSS

I2C_CL

56 AVSS

I2S_CL

44 MONO_IN

43 VREFTOP

42 SC1_IN_R

41 SC1_IN_L

40 SC2_IN_R

39 SC2_IN_L

38 SC3_IN_R

37 SC3_IN_L

36 AGNDC

I2C_DA 10

I2S_CL 11

I2S_WS 12

I2S_DA_OUT 13

I2S_DA_IN1 14

ADR_DA 15

ADR_WS 16

ADR_CL 17

DVSUP 18

DVSS 19

55 MONO_IN

54 VREFTOP

53 SC1_IN_R

52 SC1_IN_L

51 ASG1

I2S_WS 10

I2S_DA_OUT 11

I2S_DA_IN1 12

ADR_DA 13

ADR_WS 14

ADR_CL 15

DVSUP 16

50 SC2_IN_R

49 SC2_IN_L

48 ASG2

DVSS 17

47 SC3_IN_R

46 SC3_IN_L

45 ASG4

I2S_DA_IN2 18

NC 19

35 AHVSS

34 CAPL_M

33 AHVSUP

32 CAPL_A

31 SC1_OUT_L

30 SC1_OUT_R

29 VREF1

I2S_DA_IN2 20

NC 21

RESETQ 20

DACA_R 21

DACA_L 22

VREF2 23

44 SC4_IN_R

43 SC4_IN_L

42 AGNDC

41 AHVSS

NC 22

NC 23

RESETQ 24

DACA_R 25

DACA_L 26

VREF2 27

DACM_R 28

DACM_L 29

NC 30

DACM_R 24

DACM_L 25

DACM_SUB 26

40 CAPL_M

39 AHVSUP

38 CAPL_A

37 SC1_OUT_L

36 SC1_OUT_R

35 VREF1

28 SC2_OUT_L

27 SC2_OUT_R

Fig. 4–8: 52-pin PSDIP package

DACM_SUB 31

NC 32

34 SC2_OUT_L

33 SC2_OUT_R

Fig. 4–7: 64-pin PSDIP package

MICRONAS INTERMETALL

51

MSP 34x0G

PRELIMINARY DATA SHEET

SC2_IN_L

SC2_IN_R

ASG1

SC1_IN_L

SC1_IN_R

VREFTOP

NC

ASG2

SC3_IN_R

SC3_IN_L

ASG4

SC4_IN_R

SC4_IN_L

NC

MONO_IN

AVSS

AGNDC

AHVSS

NC

AVSS

NC

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

AVSUP 65

40 CAPL_M

39 AHVSUP

38 CAPL_A

37 SC1_OUT_L

36 SC1_OUT_R

35 VREF1

AVSUP 66

ANA_IN1+ 67

ANA_IN− 68

ANA_IN2+ 69

TESTEN 70

XTAL_IN 71

XTAL_OUT 72

TP 73

34 SC2_OUT_L

33 SC2_OUT_R

32 NC

MSP 34x0G

AUD_CL_OUT 74

NC 75

31 NC

30 DACM_SUB

29 NC

NC 76

D_CTR_I/O_1 77

D_CTR_I/O_0 78

ADR_SEL 79

STANDBYQ 80

28 DACM_L

27 DACM_R

26 VREF2

25 DACA_L

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

NC

DACA_R

I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

ADR_CL

DVSUP

NC

RESETQ

NC

I2S_DA_IN2

DVSS

DVSUP

Fig. 4–9: 80-pin PQFP package

52

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

SC2_IN_L

ASG2

SC3_IN_R

SC3_IN_L

ASG4

SC4_IN_R

SC4_IN_L

AGNDC

SC2_IN_R

ASG1

SC1_IN_L

SC1_IN_R

VREFTOP

MONO_IN

AVSS

AHVSS

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

AVSUP 49

ANA_IN1+ 50

ANA_IN− 51

ANA_IN2+ 52

TESTEN 53

XTAL_IN 54

XTAL_OUT 55

TP 56

32 CAPL_M

31 AHVSUP

30 CAPL_A

29 SC1_OUT_L

28 SC1_OUT_R

27 VREF1

26 SC2_OUT_L

25 SC2_OUT_R

24 NC

MSP 34x0G

AUD_CL_OUT 57

NC 58

23 DACM_SUB

22 NC

NC 59

D_CTR_I/OUT1 60

D_CTR_I/OUT0 61

ADR_SEL 62

STANDBYQ 63

NC 64

21 DACM_L

20 DACM_R

19 VREF2

18 DACA_L

17 DACA_R

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

I2C_CL

RESETQ

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

NC

I2S_DA_IN2

DVSS

DVSUP

ADR_CL

Fig. 4–10: 64-pin PLQFP package

MICRONAS INTERMETALL

53

MSP 34x0G

PRELIMINARY DATA SHEET

4.5. Pin Circuits

Pin numbers refer to the PQFP80 package.

DVSUP

P

DVSUP

GND

P

N

GND

Fig. 4–11: Output Pins 6, 8, 9, and 10

Fig. 4–15: Input/Output Pins 4, 5, 77, and 78

(I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL)

(I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0)

P

N

GND

500 kΩ

Fig. 4–12: Input/Output Pins 2 and 3

3−30 pF

N

(I2C_CL, I2C_DA)

2.5 V

3−30 pF

Fig. 4–16: Output/Input Pins 71, 72, and 74

(XTAL_IN, XTAL_OUT, AUD_CL_OUT)

Fig. 4–13: Input Pins 7, 17, 21, 70, and 80

(I2S_DA_IN1, I2S_DA_IN2, RESETQ, TESTEN,

STANDBYQ)

ANA_IN1+

ANA_IN2+

A

D

DVSUP

23 kΩ

ANA_IN−

VREFTOP

23 kΩ

GND

ADR_SEL

Fig. 4–17: Input Pins 58, 67, 68, and 69

(VREFTOP, ANA_IN1+, ANA_IN-, ANA_IN2+)

Fig. 4–14: Input Pin 79 (ADR_SEL)

54

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

125 kΩ

0...2 V

≈ 3.75 V

Fig. 4–18: Capacitor Pins 38 and 40

Fig. 4–22: Pin 45 (AGNDC)

(CAPL_A, CAPL_M)

26 pF

24 kΩ

≈ 3.75 V

120 kΩ

300 Ω

Fig. 4–19: Input Pin 60 (MONO_IN)

≈ 3.75 V

Fig. 4–23: Output Pins 33, 34, 36, and 37

(SC_2_OUT_R/L, SC_1_OUT_R/L)

40 kΩ

≈ 3.75 V

Fig. 4–20: Input Pins 47, 48, 50, 51, 53, 54, 56, and 57

(SC4-1_IN_L/R)

AHVSUP

0...1.2 mA

3.3 kΩ

Fig. 4–21: Output Pins 24, 25, 27, 28 and 30

(DACA_R/L, DACM_R/L, DACM_SUB)

MICRONAS INTERMETALL

55

MSP 34x0G

PRELIMINARY DATA SHEET

4.6. Electrical Characteristics

4.6.1. Absolute Maximum Ratings

Symbol

T_A

Parameter

Pin Name

−

Min.

0

Max.

70¹⁾

125

9.0

Unit

°C

V

Ambient Operating Temperature

Storage Temperature

First Supply Voltage

Second Supply Voltage

Third Supply Voltage

T_S

−

−40

−0.3

−0.5

V_SUP1

V_SUP2

V_SUP3

dV_SUP23

AHVSUP

DVSUP

AVSUP

6.0

V

6.0

V

Voltage between AVSUP

and DVSUP

AVSUP,

DVSUP

0.5

V

P_TOT

Power Dissipation

PLCC68

PSDIP64

AHVSUP,

DVSUP,

AVSUP

1200

1300

1200

1000

mW

PSDIP52

PQFP80

PLQFP64

960¹⁾

V_Idig

I_Idig

Input Voltage, all Digital Inputs

Input Current, all Digital Pins

Input Voltage, all Analog Inputs

−0.3

−20

V

_SUP2+0.3

V

−

+20

mA²⁾

V

V_Iana

SCn_IN_s,³⁾

MONO_IN

−0.3

V

_SUP1+0.3

I_Iana

Input Current, all Analog Inputs

SCn_IN_s,³⁾

MONO_IN

−5

+5

mA²⁾

4) 5)

I_Oana

Output Current, all SCART Outputs SCn_OUT_s³⁾

,

4)

Output Current, all Analog Outputs

except SCART Outputs

DACp_s³⁾

I_Cana

Output Current, other pins

connected to capacitors

CAPL_p,³⁾

AGNDC

1)

PLQFP64: 65 °C

2)

3)

4)

5)

positive value means current flowing into the circuit

“n” means “1”, “2”, “3”, or “4”, “s” means “L” or “R”, “p” means “M” or “A”

The analog outputs are short-circuit proof with respect to First Supply Voltage and ground.

Total chip power dissipation must not exceed absolute maximum rating.

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in

the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute

maximum ratings conditions for extended periods may affect device reliability.

56

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

4.6.2. Recommended Operating Conditions (T_A= 0 to 70 °C)

4.6.2.1. General Recommended Operating Conditions

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

V_SUP1

First Supply Voltage

(8-V Operation)

AHVSUP

7.6

8.0

8.7

V

First Supply Voltage

(5-V Operation)

4.75

5.0

5.25

V

V_SUP2

V_SUP3

t_STBYQ1

Second Supply Voltage

Third Supply Voltage

DVSUP

AVSUP

4.75

1

5.0

5.25

V

STANDBYQ Setup Time before

Turn-off of Second Supply Voltage

STANDBYQ,

DVSUP

µs

4.6.2.2. Analog Input and Output Recommendations

Symbol

Parameter

Pin Name

Min.

Typ.

3.3

Max.

Unit

µF

C_AGNDC

AGNDC-Filter-Capacitor

Ceramic Capacitor in Parallel

AGNDC

−20%

100

330

nF

C_inSC

DC-Decoupling Capacitor in front of SCn_IN_s¹⁾

SCART Inputs

nF

V_inSC

SCART Input Level

2.0

V_RMS

kΩ

V_inMONO

R_LSC

Input Level, Mono Input

SCART Load Resistance

SCART Load Capacitance

Main/AUX Volume Capacitor

MONO_IN

SCn_OUT_s¹⁾

10

C_LSC

6.0

nF

C_VMA

CAPL_M,

CAPL_A

10

1

µF

C_FMA

Main/AUX Filter Capacitor

DACM_s,

DACA_s¹⁾

−10%

+10%

nF

1)

“n” means “1”, “2”, or “3”, “s” means “L” or “R”, “p” means “M” or “A”

MICRONAS INTERMETALL

57

MSP 34x0G

PRELIMINARY DATA SHEET

4.6.2.3. Recommendations for Analog Sound IF Input Signal

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

µF

C_VREFTOP

VREFTOP-Filter-Capacitor

Ceramic Capacitor in Parallel

VREFTOP

−20 % 10

−20 % 100

0

nF

F_{IF_FMTV}

Analog Input Frequency Range

for TV Applications

ANA_IN1+,

ANA_IN2+,

ANA_IN−

9

MHz

F_{IF_FMRADIO}

Analog Input Frequency for

FM-Radio Applications

10.7

MHz

V_{IF_FM}

V_{IF_AM}

R_FMNI

Analog Input Range FM/NICAM

Analog Input Range AM/NICAM

0.1

0.8

3

V_pp

0.45

0.8

Ratio: NICAM Carrier/FM Carrier

(unmodulated carriers)

BG:

I:

−20

−23

−7

−10

0

dB

R_AMNI

Ratio: NICAM Carrier/AM Carrier

(unmodulated carriers)

−25

−11

0

dB

R_FM

Ratio: FM-Main/FM-Sub Satellite

7

dB

R_FM1/FM2

Ratio: FM1/FM2

German FM-System

R_FC

R_FV

Ratio: Main FM Carrier/

Color Carrier

15

−

dB

Ratio: Main FM Carrier/

Luma Components

PR_IF

Passband Ripple

−

±2

dB

SUP_HF

Suppression of Spectrum

15

−

above 9.0 MHz (not for FM Radio)

FM_MAX

Maximum FM-Deviation (approx.)

normal mode

±180

±360

±540

kHz

HDEV2: high deviation mode

HDEV3: very high deviation mode

58

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

4.6.2.4. Crystal Recommendations

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

General Crystal Recommendations

f_P

Crystal Parallel Resonance Fre-

18.432

MHz

quency at 12 pF Load Capacitance

R_R

C₀

C_L

Crystal Series Resistance

8

25

Ω

Crystal Shunt (Parallel) Capacitance

External Load Capacitance¹⁾

6.2

7.0

pF

XTAL_IN,

XTAL_OUT

PSDIP approx. 1.5

PLCC approx. 3.3

P(L)QFP approx. 3.3

pF

Crystal Recommendations for Master-Slave Applications (MSP-clock must perform synchronization to I²S clock)

f_TOL

Accuracy of Adjustment

−20

+20

ppm

D_TEM

Frequency Variation

versus Temperature

C₁

Motional (Dynamic) Capacitance

19

24

fF

AUD_CL_OUT

f_CL

Required Open Loop Clock

18.431

18.433 MHz

Frequency (T_amb= 25 °C)

Crystal Recommendations for FM / NICAM Applications (No MSP-clock synchronization to I²S clock possible)

f_TOL

Accuracy of Adjustment

−30

+30

ppm

D_TEM

Frequency Variation

versus Temperature

C₁

Motional (Dynamic) Capacitance

15

fF

18.4305

18.4335

f_CL

Required Open Loop Clock

AUD_CL_OUT

MHz

Frequency (T_amb= 25 °C)

Crystal Recommendations for all analog FM/AM Applications (No MSP-clock synchronization to I²S clock possible)

f_TOL

Accuracy of Adjustment

−100

−50

+100

+50

ppm

D_TEM

Frequency Variation

versus Temperature

f_CL

Required Open Loop Clock

AUD_CL_OUT

18.429

18.435 MHz

Frequency (T_amb= 25 °C)

Amplitude Recommendation for Operation with External Clock Input (C_loadafter reset typ. 22 pF)

V_XCAExternal Clock Amplitude XTAL_IN 0.7

V_pp

¹⁾External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-

quency of the internal PLL and to stabilize the frequency in closed-loop operation.

Due to different layouts, the accurate capacitor size should be determined with the customer PCB. The sug-

gested values (1.5...3.3 pF) are figures based on experience and should serve as “start value”.

To define the capacitor size, reset the MSP without transmitting any further I2C telegrams. Measure the fre-

quency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz

as closely as possible. The higher the capacity, the lower the resulting clock frequency.

MICRONAS INTERMETALL

59

MSP 34x0G

PRELIMINARY DATA SHEET

4.6.3. Characteristics

at T_A= 0 to 70 °C, f_CLOCK= 18.432 MHz, V_SUP1= 7.6 to 8.7 V, V_SUP2= 4.75 to 5.25 V for min./max. values

at T_A= 60 °C, f_CLOCK= 18.432 MHz, V_SUP1= 8 V, V_SUP2= 5 V for typical values,

T_J= Junction Temperature

MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel

4.6.3.1. General Characteristics

Symbol

Supply

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

I

First Supply Current (active)

(8-V Operation)

AHVSUP

SUP1A

Analog Volume for Main and Aux at 0 dB

9.6

6.3

17.1

11.2

24.6

16.1

mA

Analog Volume for Main and Aux at −30 dB

First Supply Current (active)

(5-V Operation)

Analog Volume for Main and Aux at 0 dB

6.4

4.2

11.4

7.5

16.4

10.7

mA

Analog Volume for Main and Aux at −30 dB

I

Second Supply Current (active)

MSP 34x0G version A1 to A4

MSP 34x0G version B5 and later

DVSUP

AVSUP

AHVSUP

SUP2A

SUP3A

SUP1S

86

50

95

65

102

85

mA

Third Supply Current (active)

MSP 34x0G version A1 to A4

MSP 34x0G version B5 and later

15

20

25

35

45

mA

First Supply Current

(8-V Operation)

3.5

5.6

7.7

mA

STANDBYQ = low

(standby mode) at T = 27 °C

j

First Supply Current

(5-V Operation)

2.3

3.7

5.1

mA

(standby mode) at T = 27 °C

j

Clock

f

Clock Input Frequency

Clock High to Low Ratio

XTAL_IN

18.432

MHz

%

CLOCK

D

45

55

50

CLOCK

JITTER

t

Clock Jitter (Verification not

provided in Production Test)

ps

V

DC-Voltage Oscillator

2.5

0.4

V

xtalDC

t

Oscillator Startup Time at

XTAL_IN,

2

ms

Startup

VDD Slew-rate of 1 V/1 µs

XTAL_OUT

V

Audio Clock Output AC Voltage

Audio Clock Output DC Voltage

HF Output Resistance

AUD_CL_OUT

1.2

0.4

1.8

V

load = 40 pF

ACLKAC

pp

V

0.6

I

= 0.2 mA

ACLKDC

SUP3

max

r

140

Ω

outHF_ACL

60

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

4.6.3.2. Digital Inputs, Digital Outputs

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Digital Input Levels

V

Digital Input Low Voltage

STANDBYQ

D_CTR_I/O_0/1

0.2

V

DIGIL

SUP2

Digital Input High Voltage

DIGIH

MSP34x0G version A1 to A4

MSP34x0G version B5 and later

0.8

0.5

V

SUP2

Z

Input Impedance

5

1

pF

DIGI

I

Digital Input Leakage Current

−1

µA

0 V < U

< DVSUP

INPUT

DLEAK

D_CTR_I/O_0/1: tri-state

V

Digital Input Low Voltage

ADR_SEL

0.2

V

DIGIL

SUP2

Digital Input High Voltage

Input Current Address Select Pin

0.8

DIGIH

SUP2

I

−500

−220

µA

U

= DVSS

ADRSEL

ADR_SEL

220

500

0.4

= DVSUP

ADR_SEL

Digital Output Levels

V

Digital Output Low Voltage

Digital Output High Voltage

D_CTR_I/O_0

D_CTR_I/O_1

V

IDDCTR = 1 mA

DCTROL

DCTROH

4.0

IDDCTR = −1 mA

MICRONAS INTERMETALL

61

MSP 34x0G

PRELIMINARY DATA SHEET

4.6.3.3. Reset Input and Power-Up

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

RESETQ Input Levels

V

Reset High-Low Transition Voltage RESETQ

Reset Low-High Transition Voltage

Input Impedance

0.45

0.7

0.55

0.8

5

V

RHL

RLH

RES

SUP2

Z

pF

I

Input Pin Leakage Current

-1

1

µA

0 V < U

< DVSUP

INPUT

DVSUP

AVSUP

4.5V

t/ms

Low-to-High

Threshold

RESETQ

Note: The reset should

not reach high level

before the oscillator has

started. This requires a

reset delay of >2 ms

0.7×DVSUP

0.45...0.55×DVSUP

High-to-Low

Threshold

0.7 x DVSUP means

3.5 Volt with

DVSUP = 5.0 V

t/ms

Reset Delay

>2 ms

Internal

Reset

High

Low

t/ms

Fig. 4–24: Power-up sequence

62

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

4.6.3.4. I²C-Bus Characteristics

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

2

V

I C-Bus Input Low Voltage

I2C_CL,

I2C_DA

0.3

V

I2CIL

I2CIH

I2C1

SUP2

2

I C-Bus Input High Voltage

0.6

120

55

V

2

t

I C Start Condition Setup Time

ns

2

I C Stop Condition Setup Time

I2C2

2

I C-Data Setup Time

I2C5

before Rising Edge of Clock

2

t

I C-Data Hold Time

55

ns

I2C6

after Falling Edge of Clock

2

t

f

I C-Clock Low Pulse Time

I2C_CL

500

ns

I2C3

I2C4

I2C

2

I C-Clock High Pulse Time

ns

2

I C-BUS Frequency

1.0

0.4

1.0

MHz

V

2

V

I C-Data Output Low Voltage

I2C_CL,

I2C_DA

I

= 3 mA

I2COL

2

I

t

I C-Data Output

µA

V

= 5 V

I2COH

High Leakage Current

2

I C-Data Output Hold Time

15

ns

I2COL1

I2COL2

after Falling Edge of Clock

2

I C-Data Output Setup Time

100

f

= 1 MHz

I2C

before Rising Edge of Clock

1/F_I2C

T_I2C4

T_I2C3

I2C_CL

T_I2C1

T_I2C5

T_I2C6

T_I2C2

I2C_DA as input

I2C_DA as output

T_I2COL2

T_I2COL1

Fig. 4–25: I²C bus timing diagram

MICRONAS INTERMETALL

63

MSP 34x0G

PRELIMINARY DATA SHEET

4.6.3.5. I²S-Bus Characteristics

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

V

Input Low Voltage

MSP34x0G version A1 to A4

MSP34x0G version B5 and later

I2S_DA_IN1/2

I2S_CL

I2S_WS

I2SIL

I2SIH

0.25

0.2

V

SUP2

V

Input High Voltage

MSP34x0G version A1 to A4

MSP34x0G version B5 and later

0.75

0.5

V

SUP2

Z

Input Impedance

5

1

pF

I2SI

I

t

f

Input Leakage Current

−1

20

0

µA

0 V < U

I S slave mode

< DVSUP

INPUT

DLEAKI2SI

2

I S-Data Input Setup Time

I2S_DA_IN1/2,

I2S_CL

ns

I2S1

before Rising Edge of Clock

2

I S-Data Input Hold Time

ns

I2S2

after Falling Edge of Clock

2

I S-Word Strobe Input Frequency

I2S_WS

I2S_CL

32.0

kHz

MHz

I2SWS

I2SCL

2

when MSP in I S-Slave Mode

2

I S-Clock Input Frequency when

1.024

2

MSP in I S-Slave-Mode

2

R

I S-Clock Input Ratio when

0.9

60

1.1

I2SCL

2

MSP in I S-Slave-Mode

2

t

I S-Word Strobe Input Setup Time

I2S_WS,

I2S_CL

ns

I2SWS1

before Rising Edge of Clock when

MSP in I S-Slave-Mode

2

t

I S-Word Strobe Input Hold Time

0

I2SWS2

after Falling Edge of Clock when

2

MSP in I S-Slave-Mode

2

V

I S Output Low Voltage

I2S_WS,

I2S_CL,

I2S_DA_OUT

0.4

V

I

= 1 mA

I2SOL

I2SOH

I2SWS

I2SCL

I2SOL

2

I S Output High Voltage

4.0

V

= −1 mA

I2SOH

2

f

t

I S-Word Strobe Output Frequency I2S_WS

32.0

1024

1.0

kHz

NICAM-PLL closed

2

I S-Clock Output Frequency

I2S_CL

2

I S-Clock High/Low-Ratio

0.9

1.1

I2S1/I2S2

I2S3

2

I S-Data Setup Time

I2S_CL,

I2S_DA_OUT

200

ns

C = 30 pF

L

before Rising Edge of Clock

2

t

I S-Data Hold Time

180

I2S4

I2S5

I2S6

after Falling Edge of Clock

2

I S-Word Strobe Setup Time

I2S_CL,

I2S_WS

200

before Rising Edge of Clock

2

I S-Word Strobe Hold Time

180

after Falling Edge of Clock

64

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

(Data: MSB first)

F

I2SWS

I2S_WS

SONY Mode

PHILIPS Mode

PHILIPS/SONY Mode programmable by MODUS[6]

Detail C

I2S_CL

Detail A

Detail B

I2S_DAIN

R LSB L MSB

L LSB R MSB

R LSB L LSB

16 bit left channel

16 bit right channel

I2S_DAOUT

R LSB L MSB

L LSB R MSB

R LSB L LSB

16 bit right channel

Detail C

Detail A,B

F

I2SCL

I2S_CL

T

I2S2

I2S1

T

I2SWS1

I2SWS2

I2S_WS as INPUT

I2S_DA_IN

T

I2S3

I2S4

I2S5

I2S6

I2S_WS as OUTPUT

I2S_DA_OUT

Fig. 4–26: I²S bus timing diagram

4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Analog Ground

V

AGNDC Open Circuit Voltage

(8-V Operation)

AGNDC

R

≥10 MΩ

load

AGNDC0

MSP34x0G version A1 to A4

MSP34x0G version B5 and later

3.63

3.67

3.73

3.77

3.83

3.87

V

AGNDC Open Circuit Voltage

(5-V Operation)

MSP34x0G version A1 to A4

MSP34x0G version B5 and later

2.39

2.41

2.49

2.51

2.59

2.61

V

R

AGNDC Output Resistance

(8-V Operation)

70

47

125

83

180

120

kΩ

3 V ≤ V

≤ 4 V

outAGN

AGNDC

AGNDC Output Resistance

(5-V Operation)

Analog Input Resistance

1)

R

SCART Input Resistance

SCn_IN_s

25

15

40

24

58

35

kΩ

f

= 1 kHz, I = 0.05 mA

= 1 kHz, I = 0.1 mA

inSC

signal

from T = 0 to 70 °C

A

R

MONO Input Resistance

MONO_IN

inMONO

from T = 0 to 70 °C

A

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”

MICRONAS INTERMETALL

65

MSP 34x0G

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Audio Analog-to-Digital-Converter

1)

V

Effective Analog Input Clipping

Level for Analog-to-Digital-

Conversion

SCn_IN_s,

MONO_IN

2.00

2.25

V

f

= 1 kHz

AICL

RMS

signal

(8-V Operation)

Effective Analog Input Clipping

Level for Analog-to-Digital-

Conversion

1.13

1.51

(5-V Operation)

SCART Outputs

1)

R

SCART Output Resistance

at T = 27 °C

SCn_OUT_s

f = 1 kHz, I = 0.1 mA

signal

outSC

200

330

460

500

Ω

j

from T = 0 to 70 °C

A

dV

Deviation of DC-Level at SCART

Output from AGNDC Voltage

−70

+70

mV

dB

OUTSC

1)

A

Gain from Analog Input

to SCART Output

SCn_IN_s,

MONO_IN

→

−1.0

−0.5

+0.5

f

= 1 kHz

signal

SCtoSC

1)

SCn_OUT_s

f

Frequency Response from Analog

Input to SCART Output

Bandwidth: 0 to 20000 Hz

with resp. to 1 kHz

rSCtoSC

V

Effective Signal Level at

SCn_OUT_s

1.8

1.9

2.0

V

f = 1 kHz

signal

outSC

RMS

SCART-Output during full-scale

2

Digital Input Signal from I S

(8-V Operation)

Effective Signal Level at

1.17

1.27

1.37

V

SCART-Output during full-scale

2

Digital Input Signal from I S

(5-V Operation)

Main and AUX Outputs

1)

R

Main/AUX Output Resistance

at T = 27 °C

DACp_s

f

= 1 kHz, I = 0.1 mA

outMA

signal

2.1

3.3

4.6

5.0

kΩ

j

from T = 0 to 70 °C

A

V

DC-Level at Main/AUX-Output

for Analog Volume at 0 dB

for Analog Volume at −30 dB

(8-V Operation)

outDCMA

1.80

2.04

61

2.28

V

mV

DC-Level at Main/AUX-Output

for Analog Volume at 0 dB

for Analog Volume at −30 dB

(5-V Operation)

1.12

1.23

1.36

40

1.60

1.51

V

mV

V

Effective Signal Level at Main/

AUX-Output during full-scale

1.37

V

f

= 1 kHz

outMA

RMS

signal

2

Digital Input Signal from I S

for Analog Volume at 0 dB

(8-V Operation)

Effective Signal Level at Main/

AUX-Output during full-scale

Digital Input Signal from I S

0.76

0.90

1.04

V

RMS

2

for Analog Volume at 0 dB

(5-V Operation)

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”; “p” means “M” or “A”

66

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

4.6.3.7. Sound IF Inputs

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

R

Input Impedance

ANA_IN1+,

ANA_IN2+,

ANA_IN−

1.5

6.8

2

9.1

2.5

11.4

kΩ

Gain AGC = 20 dB

Gain AGC = 3 dB

IFIN

DC

DC Voltage at VREFTOP

MSP 34x0G Version A1 to A4

MSP 34x0G Version B5 and later

VREFTOP

ANA_IN

2.4

2.45

2.6

2.65

2.7

2.75

V

DC Voltage on IF Inputs

ANA_IN1+,

ANA_IN2+,

ANA_IN−

1.3

1.5

1.7

V

XTALK

Crosstalk Attenuation

3 dB Bandwidth

ANA_IN1+,

ANA_IN2+,

ANA_IN−

40

10

dB

f

= 1 MHz

signal

IF

Input Level = −2 dBr

BW

MHz

dB

IF

AGC

AGC Step Width

0.85

4.6.3.8. Power Supply Rejection

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

PSRR: Rejection of Noise on AHVSUP at 1 kHz

PSRR

AGNDC

80

70

dB

2

From Analog Input to I S Output

MONO_IN,

SCn_IN_s

1)

From Analog Input to

SCART Output

MONO_IN,

SCn_IN_s

SCn_OUT_s

70

dB

1)

2

From I S Input to SCART Output

SCn_OUT_s

60

80

dB

2

1)

From I S Input to MAIN or AUX

DACp_s

Output

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”; “p” means “M” or “A”

MICRONAS INTERMETALL

67

MSP 34x0G

PRELIMINARY DATA SHEET

4.6.3.9. Analog Performance

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Specifications for 8-V Operation

SNR

Signal-to-Noise Ratio

2

from Analog Input to I S Output

MONO_IN,

SCn_IN_s

85

93

85

88

96

88

dB

Input Level = −20 dB with

1)

resp. to V

, f = 1 kHz,

AICL sig

unweighted

20 Hz...16 kHz

from Analog Input to

SCART Output

MONO_IN,

Input Level = −20 dB,

1)

SCn_IN_s

→

f

= 1 kHz,

sig

unweighted

20 Hz...20 kHz

1)

SCn_OUT_s

2

from I S Input to SCART Output

SCn_OUT_s

Input Level = −20 dB,

f

= 1 kHz,

sig

unweighted

20 Hz...15 kHz

2

1)

from I S Input to Main/AUX-Output DACp_s

for Analog Volume at 0 dB

Input Level = −20 dB,

85

78

88

83

dB

f

= 1 kHz,

sig

for Analog Volume at −30 dB

unweighted

20 Hz...15 kHz

THD

Total Harmonic Distortion

2

from Analog Input to I S Output

MONO_IN,

SCn_IN_s

0.01

0.03

%

Input Level = −3 dBr with

1)

resp. to V

, f = 1 kHz,

AICL sig

unweighted

20 Hz...16 kHz

from Analog Input to

SCART Output

MONO_IN,

SCn_IN_s

→

Input Level = −3 dBr,

f

= 1 kHz,

sig

unweighted

20 Hz...20 kHz

1)

SCn_OUT_s

2

from I S Input to SCART Output

SCn_OUT_s

Input Level = −3 dBr,

f

= 1 kHz,

sig

unweighted

20 Hz...16 kHz

2

from I S Input to Main or AUX Out- DACA_s,

Input Level = −3 dBr,

1)

put

DACM_s

f

= 1 kHz,

sig

unweighted

20 Hz...16 kHz

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”; “p” means “M” or “A”

68

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Specifications for 5-V Operation

SNR

Signal-to-Noise Ratio

2

from Analog Input to I S Output

MONO_IN,

SCn_IN_s

82

90

82

85

93

85

dB

Input Level = −20 dB with

1)

resp. to V

, f = 1 kHz,

AICL sig

unweighted

20 Hz...16 kHz

from Analog Input to

SCART Output

MONO_IN,

Input Level = −20 dB,

1)

SCn_IN_s

→

f

= 1 kHz,

sig

unweighted

20 Hz...20 kHz

1)

SCn_OUT_s

2

from I S Input to SCART Output

SCn_OUT_s

Input Level = −20 dB,

f

= 1 kHz,

sig

unweighted

20 Hz...15 kHz

2

1)

from I S Input to Main/AUX-Output DACp_s

for Analog Volume at 0 dB

Input Level = −20 dB,

82

75

85

80

dB

f

= 1 kHz,

sig

for Analog Volume at −30 dB

unweighted

20 Hz...15 kHz

THD

Total Harmonic Distortion

2

from Analog Input to I S Output

MONO_IN,

SCn_IN_s

0.03

0.1

%

Input Level = −3 dBr with

1)

resp. to V

, f = 1 kHz,

AICL sig

unweighted

20 Hz...16 kHz

from Analog Input to

SCART Output

MONO_IN,

SCn_IN_s

→

Input Level = −3 dBr,

f

= 1 kHz,

sig

unweighted

20 Hz...20 kHz

1)

SCn_OUT_s

2

from I S Input to SCART Output

SCn_OUT_s

Input Level = −3 dBr,

f

= 1 kHz,

sig

unweighted

20 Hz...16 kHz

2

from I S Input to Main or AUX Out- DACA_s,

Input Level = −3 dBr,

1)

put

DACM_s

f

= 1 kHz,

sig

unweighted

20 Hz...16 kHz

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”; “p” means “M” or “A”

MICRONAS INTERMETALL

69

MSP 34x0G

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

XTALK Specifications for 8-V and 5-V Operation

XTALK

Crosstalk Attenuation

− PLCC68

Input Level = −3 dB,

f

= 1 kHz, unused ana-

sig

− PSDIP64

log inputs connected to

ground by Z < 1 kΩ

between left and right channel within

unweighted

SCART Input/Output pair (L→R, R→L)

20 Hz...20 kHz

1)

SCn_IN → SCn_OUT

PLCC68

PSDIP64

80

dB

2

SC1_IN or SC2_IN → I S Output

PLCC68

PSDIP64

80

dB

2

SC3_IN → I S Output

PLCC68

PSDIP64

80

dB

2

1)

I S Input → SCn_OUT

PLCC68

PSDIP64

80

dB

between left and right channel within

Main or AUX Output pair

unweighted

20 Hz...16 kHz

2

1)

I S Input → DACp

PLCC68

PSDIP64

80

75

dB

between SCART Input/Output pairs

(unweighted

20 Hz...20 kHz

D = disturbing program

O = observed program

same signal source on left

and right disturbing chan-

nel, effect on each

D: MONO/SCn_IN → SCn_OUT

O: MONO/SCn_IN → SCn_OUT

PLCC68

PSDIP64

100

dB

1)

observed output channel

D: MONO/SCn_IN → SCn_OUT or unsel.

O: MONO/SCn_IN → I S Output

PLCC68

PSDIP64

100

95

dB

2

D: MONO/SCn_IN → SCn_OUT

O: I S Input → SCn_OUT

PLCC68

PSDIP64

100

dB

2

1)

D: MONO/SCn_IN → unselected

O: I S Input → SC1_OUT

PLCC68

PSDIP64

100

dB

2

1)

Crosstalk between Main and AUX Output pairs

(unweighted

20 Hz...16 kHz)

same signal source on left

and right disturbing chan-

nel, effect on each

2

1)

I S Input → DACp

PLCC68

PSDIP64

95

90

dB

observed output channel

XTALK

Crosstalk from Main or AUX Output to SCART Output

and vice versa

(unweighted

20 Hz...20 kHz)

same signal source on left

and right disturbing chan-

nel, effect on each

D = disturbing program

O = observed program

observed output channel

D: MONO/SCn_IN/DSP → SCn_OUT

O: I S Input → DACp

PLCC68

PSDIP64

85

80

dB

SCART output load resis-

tance 10 kΩ

2

1)

D: MONO/SCn_IN/DSP → SCn_OUT

O: I S Input → DACp

PLCC68

PSDIP64

90

85

dB

SCART output load resis-

tance 30 kΩ

2

1)

2

D: I S Input → DACp

PLCC68

PSDIP64

100

95

dB

1)

O: MONO/SCn_IN → SCn_OUT

2

D: I S Input → DACM

PLCC68

PSDIP64

100

95

dB

2

1)

O: I S Input → SCn_OUT

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”; “p” means “M” or “A”

70

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

4.6.3.10. Sound Standard Dependent Characteristics

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

NICAM Characteristics (MSP Standard Code = 8)

dV

Tolerance of Output Voltage

of NICAM Baseband Signal

DACp_s,

SCn_OUT_s

−1.5

+1.5

dB

2.12 kHz, Modulator input

level = 0 dBref

NICAMOUT

1)

S/N

S/N of NICAM Baseband Signal

72

NICAM: −6 dB, 1 kHz, RMS

unweighted

NICAM

0 to 15 kHz, Vol = 9 dB

NIC_Presc = 7F

Output level 1 V

DACp_s

hex

at

RMS

THD

BER

Total Harmonic Distortion + Noise

of NICAM Baseband Signal

0.1

%

2.12 kHz, Modulator input

level = 0 dBref

NICAM

−7

NICAM: Bit Error Rate

1

10

FM+NICAM, norm conditions

fR

NICAM Frequency Response ,

20...15000 Hz

−1.0

80

+1.0

dB

Modulator input

level = −12 dB dBref; RMS

NICAM

XTALK

NICAM Crosstalk Attenuation

(Dual)

NICAM

SEP

NICAM Channel Separation

(Stereo)

80

NICAM

FM Characteristics (MSP Standard Code = 3)

dV

Tolerance of Output Voltage

of FM Demodulated Signal

DACp_s,

SCn_OUT_s

−1.5

+1.5

dB

1 FM-carrier, 50 µs, 1 kHz,

40 kHz deviation; RMS

FMOUT

1)

S/N

S/N of FM Demodulated Signal

73

dB

%

1 FM-carrier 5.5 MHz, 50 µs,

1 kHz, 40 kHz deviation;

RMS, unweighted

0 to 15 kHz (for S/N);

full input range, FM-Pres-

FM

THD

Total Harmonic Distortion + Noise

of FM Demodulated Signal

0.1

FM

cale = 46 , Vol = 0 dB

hex

→ Output Level 1 V

at

RMS

DACp_s

fR

FM Frequency Responses,

20...15000 Hz

−1.0

80

+1.0

dB

1 FM-carrier 5.5 MHz,

50 µs, Modulator input

level = −14.6 dBref; RMS

FM

XTALK

FM Crosstalk Attenuation (Dual)

FM Channel Separation (Stereo)

2 FM-carriers 5.5/5.74 MHz,

50 µs, 1 kHz, 40 kHz devia-

tion; Bandpass 1 kHz

FM

SEP

DACp_s,

SCn_OUT_s

50

2 FM-carriers 5.5/5.74 MHz,

50 µs, 1 kHz, 40 kHz devia-

tion; RMS

FM

1)

AM Characteristics (MSP Standard Code = 9)

S/N

S/N of AM Demodulated Signal

measurement condition: RMS/Flat

MSP 34x0G Version A1 to B5

MSP 34x0G Version B6 and later

DACp_s,

SCn_OUT_s

SIF level: 0.1−0.8 V

pp

AM(1)

AM-carrier 54% at 6.5 MHz

Vol = 0 dB, FM/AM

prescaler set for

44

55

dB

output = 0.5 V

at

RMS

Loudspeaker out;

S/N

S/N of AM Demodulated Signal

measurement condition: QP/CCIR

MSP 34x0G Version A1 to B5

MSP 34x0G Version B6 and later

AM(2)

Standard Code = 09

no video/chroma

components

hex

35

45

dB

THD

Total Harmonic Distortion + Noise

of AM Demodulated Signal

AM

MSP 34x0G Version A1 to B5

MSP 34x0G Version B6 and later

0.8

0.6

%

1) “n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”; “p” means “Loudspeaker (Main)’’ or ‘‘Headphone (AUX)’’

MICRONAS INTERMETALL

71

MSP 34x0G

PRELIMINARY DATA SHEET

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

BTSC Characteristics (MSP Standard Code = 20 , 21

)

hex

S/N

S/N of BTSC Stereo Signal

S/N of BTSC-SAP Signal

DACp_s,

SCn_OUT_s

68

57

dB

1 kHz L or R or SAP, 100%

modulation, 75 µs deempha-

sis, RMS unweighted 0 to 15

kHz

BTSC

1)

THD

THD+N of BTSC Stereo Signal

THD+N of BTSC SAP Signal

0.1

0.5

%

1 kHz L or R or SAP, 100%

75 µs EIM , DBX NR, RMS

unweighted

0 to 15 kHz

BTSC

2)

fR

Frequency Response of BTSC

Stereo, 50 Hz...12 kHz

−0.5

−1.0

0.5

0.6

dB

L or R or SAP,

1%...66% EIM , DBX NR

BTSC

2)

Frequency Response of BTSC-

SAP, 50 Hz...9 kHz

XTALK

Stereo → SAP

SAP → Stereo

76

80

dB

1 kHz L or R or SAP, 100%

modulation, 75 µs deempha-

sis, Bandpass 1 kHz

BTSC

2)

SEP

Stereo Separation

50 Hz...10 kHz

50 Hz...12 kHz

L or R 1%...66% EIM , DBX

NR

BTSC

35

30

dB

FM

Pilot deviation threshold

Stereo off → on

ANA_IN1+,

ANA_IN2+

4.5 MHz carrier modulated

pil

with f = 15.743 kHz

h

3.2

1.2

3.5

1.5

kHz

SIF level = 100 mV

pp

indication: STATUS Bit[6]

Stereo on → off

f

Pilot Frequency Range

ANA_IN1+

ANA_IN2+

15.563

15.843 kHz

standard BTSC stereo signal,

sound carrier only

Pilot

BTSC Characteristics (MSP Standard Code = 20 , 21

)

hex

with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal components)

S/N

S/N of BTSC Stereo Signal

S/N of BTSC-SAP Signal

DACp_s,

SCn_OUT_s

64

55

dB

1 kHz L or R or SAP, 100%

modulation, 75 µs deempha-

sis, RMS unweighted 0 to 15

kHz

BTSC

1)

THD

THD+N of BTSC Stereo Signal

THD+N of BTSC SAP Signal

0.15

0.8

%

1 kHz L or R or SAP, 100%

75 µs EIM , DBX NR, RMS

unweighted

0 to 15 kHz

BTSC

2)

fR

Frequency Response of BTSC

Stereo, 50 Hz...12 kHz

−0.5

−1.0

0.5

0.6

dB

L or R or SAP,

1%...66% EIM , DBX NR

BTSC

2)

Frequency Response of BTSC-

SAP, 50 Hz...9 kHz

XTALK

Stereo → SAP

SAP → Stereo

75

dB

1 kHz L or R or SAP, 100%

modulation, 75 µs deempha-

sis, Bandpass 1 kHz

BTSC

2)

SEP

Stereo Separation

50 Hz...10 kHz

50 Hz...12 kHz

L or R 1%...66% EIM , DBX

NR

BTSC

35

30

dB

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”; “p” means “M” or “A”

2)

EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation,

when the DBX encoding process is replaced by a 75-µs preemphasis network.

72

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

EIA-J Characteristics (MSP Standard Code = 30

)

hex

S/N

S/N of EIA-J Stereo Signal

S/N of EIA-J Sub-Channel

DACp_s,

SCn_OUT_s

60

dB

1 kHz L or R,

EIAJ

1)

100% modulation,

75 µs deemphasis,

RMS unweighted

0 to 15 kHz

THD

THD+N of EIA-J Stereo Signal

THD+N of EIA-J Sub-Channel

0.2

0.3

%

EIAJ

fR

Frequency Response of EIA-J

Stereo, 50 Hz...12 kHz

−0.5

−1.0

0.5

dB

100% modulation,

75 µs deemphasis

EIAJ

Frequency Response of EIA-J

Sub-Channel, 50 Hz...12 kHz

XTALK

Main → SUB

Sub → MAIN

66

80

dB

1 kHz L or R, 100% modula-

tion, 75 µs deemphasis,

Bandpass 1 kHz

EIAJ

SEP

Stereo Separation

50 Hz...5 kHz

50 Hz...10 kHz

EIA-J Stereo Signal, L or R

100% modulation

EIAJ

35

28

dB

FM-Radio Characteristics (MSP Standard Code = 40

)

hex

S/N

S/N of FM-Radio Stereo Signal

DACp_s,

SCn_OUT_s

68

dB

%

1 kHz L or R, 100% modula-

tion, 75 µs deemphasis, RMS

unweighted

UKW

1)

THD

THD+N of FM-Radio Stereo Signal

0.1

UKW

0 to 15 kHz

fR

Frequency Response of

FM-Radio Stereo

50 Hz...15 kHz

L or R, 1%...100% modula-

tion, 75 µs deemphasis

UKW

−1.0

45

+0.5

dB

SEP

Stereo Separation 50 Hz...15 kHz

Pilot Frequency Range

UKW

f

ANA_IN1+

ANA_IN2+

18.844

19.125 kHz

standard FM radio

stereo signal

Pilot

1)

“n” means “1”, “2”, “3”, or “4”;

“s” means “L” or “R”; “p” means “M” or “A”

MICRONAS INTERMETALL

73

MSP 34x0G

PRELIMINARY DATA SHEET

5. Appendix A: Overview of TV-Sound Standards

5.1. NICAM 728

Table 5–1: Summary of NICAM 728 sound modulation parameters

Specification

I

B/G

L

D/K

Carrier frequency of

digital sound

6.552 MHz

5.85 MHz

Transmission rate

Type of modulation

728 kbit/s

Differentially encoded quadrature phase shift keying (DQPSK)

by means of Roll-off filters

Spectrum shaping

Roll-off factor

1.0

0.4

6.5 MHz AM mono

0.4

Carrier frequency of

analog sound component

6.0 MHz

5.5 MHz

6.5 MHz

FM mono

terrestrial

10 dB

cable

16 dB

Power ratio between

vision carrier and

analog sound carrier

10 dB

13 dB

7 dB

13 dB

Power ratio between

analog and modulated

digital sound carrier

17 dB

11 dB

China/Hu

ngary

Poland

7 dB

12 dB

Table 5–2: Summary of NICAM 728 sound coding characteristics

Characteristics

Values

32 kHz

2

Audio sampling frequency

Number of channels

Initial resolution

14 bit/sample

Companding characteristics

Coding for compressed samples

Preemphasis

near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks

2’s complement

CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz)

+12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)

Audio overload level

74

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

5.2. A2-Systems

Table 5–3: Key parameters for A2 Systems of Standards B/G, D/K, and M

Characteristics

Sound Carrier FM1

Sound Carrier FM2

D/K

TV-Sound Standard

Carrier frequency in MHz

B/G

D/K

M

B/G

M

5.5

6.5

4.5

5.7421875 6.2578125 4.724212

6.7421875

5.7421875

Vision/sound power difference

Sound bandwidth

13 dB

20 dB

40 Hz to 15 kHz

Preemphasis

50 µs

±27/±50 kHz

75 µs

50 µs

75 µs

Frequency deviation (nom/max)

Transmission Modes

±17/±25 kHz

±27/±50 kHz

±15/±25 kHz

Mono transmission

mono

Stereo transmission

(L+R)/2

language A

(L+R)/2

R

(L−R)/2

Dual sound transmission

Identification of Transmission Mode

Pilot carrier frequency

language B

54.6875 kHz

±2.5 kHz

55.0699 kHz

Max. deviation portion

Type of modulation / modulation depth

Modulation frequency

AM / 50%

mono: unmodulated

stereo: 117.5 Hz

dual: 274.1 Hz

149.9 Hz

276.0 Hz

MICRONAS INTERMETALL

75

MSP 34x0G

PRELIMINARY DATA SHEET

5.3. BTSC-Sound System

Table 5–4: Key parameters for BTSC-Sound Systems

Aural

BTSC-MPX-Components

Carrier

(L+R)

Pilot

(L−R)

SAP

Prof. Ch.

Carrier frequency

4.5 MHz

Baseband

f_h

2 f_h

5 f_h

6.5 f_h

(f_hNTSC= 15.734 kHz)

(f_hPAL= 15.625 kHz)

Sound bandwidth in kHz

Preemphasis

0.05 - 15

75 µs

0.05 - 15

DBX

0.05 - 12

DBX

0.05 - 3.4

150 µs

3 kHz

Max. deviation to Aural Carrier

73 kHz

(total)

25 kHz¹⁾

5 kHz

50 kHz¹⁾

15 kHz

Max. Freq. Deviation of Subcarrier

Modulation Type

10 kHz

FM

3 kHz

FM

AM

¹⁾Sum does not exceed 50 kHz due to interleaving effects

5.4. Japanese FM Stereo System (EIA-J)

Table 5–5: Key parameters for Japanese FM-Stereo Sound System EIA-J

Aural

Carrier

FM

EIA-J-MPX-Components

(L+R)

(L−R)

Identification

Carrier frequency (f_h= 15.734 kHz)

Sound bandwidth

4.5 MHz

Baseband

0.05 - 15 kHz

75 µs

2 f_h

3.5 f_h

−

0.05 - 15 kHz

75 µs

Preemphasis

none

2 kHz

Max. deviation portion to Aural Carrier

47 kHz

25 kHz

20 kHz

Max. Freq. Deviation of Subcarrier

Modulation Type

10 kHz

FM

60%

AM

Transmitter-sided delay

Mono transmission

20 µs

0 µs

L+R

−

unmodulated

982.5 Hz

922.5 Hz

Stereo transmission

Bilingual transmission

L+R

L−R

Language A

Language B

76

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

5.5. FM Satellite Sound

Table 5–6: Key parameters for FM Satellite Sound

Carrier Frequency

Maximum

FM Deviation

Sound Mode

Bandwidth

Deemphasis

6.5 MHz

85 kHz

50 kHz

Mono

15 kHz

50 µs

7.02/7.20 MHz

7.38/7.56 MHz

7.74/7.92 MHz

Mono/Stereo/Bilingual

adaptive

5.6. FM-Stereo Radio

Table 5–7: Key parameters for FM-Stereo Radio Systems

Aural

Carrier

(L+R)

FM-Radio-MPX-Components

Pilot

(L−R)

2 f_p

RDS/ARI

Carrier frequency (f_p= 19 kHz)

Sound bandwidth in kHz

10.7 MHz

Baseband

0.05 - 15

f_p

3 f_h

0.05 - 15

Preemphasis:

− USA

− Europe

75 µs

50 µs

75 µs

50 µs

Max. deviation to Aural Carrier

75 kHz

(100%)

90%

10%

90%

5%

MICRONAS INTERMETALL

77

MSP 34x0G

PRELIMINARY DATA SHEET

6. Appendix B: Manual/Compatibility Mode

To adapt the modes of the STANDARD SELECT regis-

ter to individual requirements and for reasons of com-

patibility to the MSP 34x0D, the MSP 34x0G offers

an Manual/Compatibility Mode, which provides sophis-

ticated programming of the MSP 34x0G.

Using the STANDARD SELECT register generally pro-

vides

a more economic way to program the

MSP 34x0G and will result in optimal behavior. There-

fore, it is not recommended to use the Man-

ual/Compatibility mode. Only in those cases, where

compatibility with MSP 34x0D is strictly required,

should the Manual/Compatibility mode be used.

Note: In case of Automatic Sound Select

(MODUS[0]=1), any modifications of the demodulator

write registers listed below, except AUTO_FM/AM, are

ignored.

78

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode

Table 6–1: Demodulator Write Registers; Subaddress: 10_hex; these registers are not readable!

Demodulator

Write Registers

Address MSP-

Description

Reset

Mode

Page

(hex)

Version

AUTO_FM/AM

00 21

3410,

3450

1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of 00 00

Automatic Switching between NICAM and FM/AM in case of bad NICAM

reception

81

1)

2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic

Switching between NICAM and FM/AM in case of bad NICAM reception

A2_Threshold

CM_Threshold

AD_CV

00 22

00 24

00 BB

00 83

all

A2 Stereo Identification Threshold

00 19

82

83

84

hex

all

Carrier-Mute Threshold

00 2A

00 00

hex

all

SIF-input selection, configuration of AGC, and Carrier-Mute Function

MODE_REG

3410,

3450

Controlling of MSP-Demodulator and Interface options. As soon as this 00 00

register is applied, the MSP 34x0G works in the MSP 34x0D compatibility

mode.

1)

Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only

MSP 34x0D features are available; the use of MODUS and STATUS register

is not allowed.

The MSP 34x0G is reset to the normal mode by first programming the

MODUS register followed by transmitting a valid standard code to the

STANDARD SELECTION register.

FIR1

FIR2

00 01

00 05

FIR1-filter coefficients channel 1 (6 8 bit)

FIR2-filter coefficients channel 2 (6 8 bit), + 3 8 bit offset (total 72 bit)

00 00

86

DCO1_LO

DCO1_HI

00 93

00 9B

Increment channel 1 Low Part

Increment channel 1 High Part

DCO2_LO

DCO2_HI

00 A3

00 AB

Increment channel 2 Low Part

Increment channel 2 High Part

PLL_CAPS

00 1F

Not of interest for the customer

00 56

89

Switchable PLL capacitors to tune open-loop frequency

1)

not in BTSC, EIA-J, and FM-Radio mode

Table 6–2: Demodulator Read Registers; Subaddress: 11_hex; these registers are not writable!

Demodulator

Address MSP-

Description

Page

Read Registers

(hex)

00 23

00 38

00 3E

00 57

02 1F

02 1E

Version

C_AD_BITS

ADD_BITS

CIB_BITS

3410,

3450

NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits

NICAM: bit [10:3] of additional data bits

NICAM: CIB1 and CIB2 control bits

NICAM error rate, updated with 182 ms

Not for customer use

88

89

ERROR_RATE

PLL_CAPS

AGC_GAIN

Not for customer use

MICRONAS INTERMETALL

79

MSP 34x0G

PRELIMINARY DATA SHEET

6.2. DSP Write and Read Registers for Manual/Compatibility Mode

Table 6–3: DSP-Write Registers; Subaddress: 12_hex, all registers are readable as well

Write Register

Address Bits

(hex)

Operational Modes and Adjustable Range

Reset

Mode

Page

Volume SCART1 channel: Ctrl. mode

FM Fixed Deemphasis

00 07

00 0F

[7..0]

[15..8]

[7..0]

[Linear mode / logarithmic mode]

[50 µs, 75 µs, OFF]

[OFF, WP1]

00

90

91

90

hex

50 µs

OFF

B/G

FM Adaptive Deemphasis

Identification Mode

00 15

00 17

00 40

[B/G, M]

FM DC Notch

[ON, OFF]

ON

Volume SCART2 channel: Ctrl. mode

[Linear mode / logarithmic mode]

00

hex

Table 6–4: DSP Read Registers; Subaddress: 13_hex, all registers are not writable

Additional Read Registers

Address Bits

(hex)

Output Range

Page

Stereo detection register for

A2 Stereo Systems

00 18

[15..8]

[80

... 7F

]

8 bit two’s complement

91

hex

DC level readout FM1/Ch2-L

DC level readout FM2/Ch1-R

00 1B

00 1C

[15..0]

[8000 ... 7FFF

]

16 bit two’s complement

91

hex

[8000 ... 7FFF

]

hex

80

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

6.3. Manual/Compatibility Mode:

Individual configuration of the threshold can be done

using Table 6–5, whereby the bits 0 and 11 of

AUTO_FM are ignored. It is recommended to use the

internal setting used by the standard selection.

Description of Demodulator Write Registers

6.3.1. Automatic Switching between NICAM and

Analog Sound

The optimum NICAM sound can be assigned to the

MSP output channels by selecting one of the “Stereo or

A/B”, “Stereo or A”, or “Stereo or B” source channels.

In case of bad NICAM reception or loss of the

NICAM-carrier, the MSP 34x0G offers an Automatic

Switching (fall back) to the analog sound (FM/AM-

Mono), without the necessity of the controller reading

and evaluating any parameters. If a proper NICAM sig-

nal returns, switching back to this source is performed

automatically as well. The feature evaluates the NICAM

ERROR_RATE and switches, if necessary, all output

channels which are assigned to the NICAM source, to

the analog source, and vice versa.

6.3.1.2. Function in Manual Mode

If the manual mode (MODUS[0]=0) is required, the

activation and configuration of the Automatic Switching

feature has to be done as described in Table 6–5.

Note, that the channel matrix of the corresponding out-

put channels must be set according to the

NICAM mode and need not to be changed in the

FM/AM-fallback case.

An appropriate hysteresis algorithm avoids oscillating

effects (see Fig. 6–1). STATUS[9] and C_AD_BITS[11]

(Addr: 0023 hex) provide information about the actual

NICAM-FM/AM-status.

Example:

Required threshold = 500: bits [10:1]=00 1111 1010

6.3.1.1. Function in Automatic Sound Select Mode

Selected Sound

NICAM

The Automatic Sound Select feature (MODUS[0]=1)

includes the procedure mentioned above. By default, the

internal ERROR_RATE threshold is set to 700_dec. i.e. :

– NICAM → analog Sound if ERROR_RATE > 700

– analog Sound → NICAM if ERROR_RATE < 700/2

analog

ERROR_RATE

Sound

threshold/2

threshold

The ERROR_RATE value of 700 corresponds to a

BER of approximately 5.46*10^-3/s.

Fig. 6–1: Hysteresis for Automatic Switching

Table 6–5: Coding of Automatic NICAM/Analog Sound Switching; Reset Status: Mode 0

Mode

Description

AUTO_FM [11:0]

ERROR_RATE- Source Select:

Threshold/dec

Addr. = 00 21

Input at NICAM Path¹⁾

hex

0

Compatible to MSP 3410B, i.e.

automatic switching is disabled

Bit

[0]

= 0

none

always NICAM; Mute in

case of no NICAM available

Bits [10:1] = 0

Bit

[11] = 0

[0] = 1

[10:1] = 0

[11] = 0

1

2

Automatic Switching with

internal threshold

(Default, if Automatic Sound

Bit

700

NICAM or FM/AM,

depending on

ERROR_RATE

Select is on)

Automatic Switching with

external threshold

(Customizing of Automatic

Bit

[0]

= 1

set by customer;

recommended

range: 50...2000

[10:1] = 25..1000

= threshold/2

Sound Select)

Bit

[11]

= 0

3

Forced analog mono mode, i.e.

[0]

= 1

none

always FM/AM

Automatic Switching is disabled Bit

[10:1] = 0

[11] = 1

(Customizing of Automatic

Sound Select)

Bit

1)

In case of Automatic Sound Select (MODUS[0] = 1), the NICAM path may be assigned to “Stereo or A/B”, “Stereo or A”, or

“Stereo or B” source channels (see Table 2–2 on page 11).

In case of Automatic Sound Select (MODUS[0] = 1), bit [0] of AUTO_FM is ignored

MICRONAS INTERMETALL

81

MSP 34x0G

PRELIMINARY DATA SHEET

6.3.2. A2 Threshold

The threshold between Stereo/Bilingual and Mono

Identification for the A2 Standard has been made pro-

grammable according to the user’s preferences. An

internal hysteresis ensures robustness and stability.

Table 6–6: Write Register on I²C Subaddress 10_hex: A2 Threshold

Register

Address

Function

Name

THRESHOLDS

00 22_hex(write)

A2 THRESHOLD Register

A2_THRESH

Defines threshold of all A2 and EIA_J standards for Stereo and Bilingual

detection

bit [11..0] 7F0_hex

force Mono Identification

default setting after reset

minimum Threshold for stable detection

must be set to 0

...

190_hex

...

0A0_hex

bit [15..12]

recommended range : 0A0_hex...3C0_hex

6.3.3. Carrier-Mute Threshold

The Carrier-Mute threshold has been made program-

mable according to the user’s preferences. An internal

hysteresis ensures stable behavior.

Table 6–7: Write Register on I²C Subaddress 10_hex: Carrier-Mute Threshold

Register

Address

Function

Name

THRESHOLDS

00 24_hex(write)

Carrier-Mute THRESHOLD Register

CM_THRESH

Defines threshold for the carrier mute feature

bit [6..0] 00_hex

Carrier-Mute always ON (both channels muted)

...

2A_hex

...

default setting after reset

7F_hex

Carrier-Mute always OFF (both channels forced

on)

bit [15..7]

must be set to 0

recommended range : 14_hex...50_hex

82

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

6.3.4. Register AD_CV

The use of this register is no longer recommended.

Use it only in cases where compatibility to the

MSP 34x0D is required. Using the STANDARD

SELECTION register together with the MODUS regis-

ter provides a more economic way to program the

MSP 34x0G.

Table 6–8: AD_CV Register; reset status: all bits are “0”

AD_CV

(00 BB_hex

Automatic setting by

STANDARD SELECT Register

)

Bit

Function

Settings

2-8, 0A-60_hex

9

[0]

not used

must be set to 0

0

[1−6]

Reference level in case of Automatic Gain

Control = on (see Table 6–9). Constant gain

factor when Automatic Gain Control = off

(see Table 6–10).

101000

100011

[7]

[8]

[9]

Determination of Automatic Gain or

Constant Gain

0 = constant gain

1 = automatic gain

1

X

1

X

0

Selection of Sound IF source

(identical to MODUS[8])

0 = ANA_IN1+

1 = ANA_IN2+

MSP-Carrier-Mute Feature

0 = off: no mute

1 = on: mute as de-

scribed in section 2.2.2.

[10−15]

not used

must be set to 0

0

X : not affected while choosing the TV sound standard by means of the STANDARD SELECT Register

Table 6–9: Reference Values for Active AGC (AD_CV[7] = 1)

Application

Input Signal Contains

AD_CV [6:1]

Ref. Value

AD_CV [6:1]

in integer

Range of Input Signal

at pin ANA_IN1+

and ANA_IN2+

Terrestrial TV

− FM Standards

− NICAM/FM

− NICAM/AM

1)

1 or 2 FM Carriers

101000

100011

40

35

0.10 − 3 V_pp

1)

1 FM and 1 NICAM Carrier

1 AM and 1 NICAM Carrier

0.10 − 3 V_pp

0.10 − 1.4 V_pp

(recommended: 0.10 − 0.8 V_pp

)

− NICAM only

1 NICAM Carrier only

010100

100011

20

35

0.05 − 1.0 V_pp

1)

SAT

1 or more FM Carriers

FM and ADR carriers

0.10 − 3 V_pp

ADR

see DRP 3510A data sheet

1)

For signals above 1.4 V_pp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the

robustness of the internal processing, the IC works up to and even more than 3 V_pp, if norm conditions of FM/NICAM or

FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear.

MICRONAS INTERMETALL

83

MSP 34x0G

PRELIMINARY DATA SHEET

Table 6–10: AD_CV parameters for Constant Input Gain (AD_CV[7]=0)

Step

AD_CV [6:1]

Constant Gain

Gain

Input Level at pin ANA_IN1+ and ANA_IN2+

maximum input level: 3 V_pp(FM) or 1 V_pp(NICAM)¹⁾

0

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

3.00 dB

1

2

3

4

5

6

7

8

3.85 dB

4.70 dB

5.55 dB

6.40 dB

7.25 dB

8.10 dB

8.95 dB

9.80 dB

10.65 dB

11.50 dB

12.35 dB

13.20 dB

14.05 dB

14.90 dB

15.75 dB

16.60 dB

17.45 dB

18.30 dB

19.15 dB

20.00 dB

9

10

11

12

13

14

15

16

17

18

19

20

maximum input level: 0.14 V_pp

1)

For signals above 1.4 V_pp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result. Due to the

robustness of the internal processing, the IC works up to and even more than 3 V_pp, if norm conditions of FM/NICAM or

FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear.

6.3.5. Register MODE_REG

Note: The use of this register is no longer recom-

mended. It should be used only in cases where soft-

ware compatibility to the MSP 34x0D is required.

Using the STANDARD SELECTION register together

with the MODUS register provides a more economic

way to program the MSP 34x0G.

As soon as this register is applied, the MSP 34x0G

works in the MSP 34x0D Manual/Compatibility

Mode. In this mode: BTSC, EIA-J, and FM-Radio are

disabled. Only MSP 34x0D features are available; the

use of MODUS and STATUS register is not allowed.

The MSP 34x0G is reset to the normal mode by first

programming the MODUS register, followed by trans-

mitting a valid standard code to the STANDARD

SELECTION register.

The register ‘MODE_REG’ contains the control bits

determining the operation mode of the MSP 34x0G in

the MSP 34x0D Manual/Compatibility Mode; Table 6–

11 explains all bit positions.

84

MICRONAS INTERMETALL

PRELIMINARY DATA SHEET

MSP 34x0G

Table 6–11: Control word ‘MODE_REG’; reset status: all bits are “0”

MODE_REG 00 83_hex

Automatic setting by

STANDARD SELECT Register

Bit

[0]

[1]

Function

not used

Comment

Definition

2 - 5

0

8, A, B

9

0

X

0 : must be used

0

DCTR_TRI

Digital control out

0/1 tri-state

0 : active

1 : tri-state

X

[2]

I2S_TRI

I²S outputs tri-state

(I2S_CL, I2S_WS,

I2S_DA_OUT)

0 : active

1 : tri-state

X

[3]

[4]

[5]

I²S Mode¹⁾

Master/Slave mode

of the I²S bus

0 : Master

1 : Slave

X

I2S_WS Mode

Audio_CL_OUT

WS due to the Sony or

Philips-Format

0 : Sony

1 : Philips

Switch

Audio_Clock_Output

to tri-state

0 : on

1 : tri-state

[6]

NICAM¹⁾

Mode of MSP-Ch1

0 : FM

1 : Nicam

0

1

[7]

[8]

not used

FM AM

0 : must be used

0

1

Mode of MSP-Ch2

0 : FM

1 : AM

[9]

HDEV

High Deviation Mode

(channel matrix must be

sound A)

0 : normal

1 : high deviation mode

0

[11:10]

[12]

not used

0 : must be used

0

MSP-Ch1 Gain


型号：	MSP3430GPS
厂家：	TDK ELECTRONICS
描述：	Consumer Circuit, CMOS, PQCC68, PLASTIC, LCC-68 商用集成电路
文件：	总96页 (文件大小：653K)
中文：	中文翻译
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