TC7126CPL [TELCOM]
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS; 3-1 / 2位模拟 - 数字转换器
| 型号： | TC7126CPL |
| 厂家： | 
TELCOM SEMICONDUCTOR, INC |
| 描述： | 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS |
| 文件： | 总13页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3
TC7126
TC7126A
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS
GENERAL DESCRIPTION
FEATURES
The TC7126A is a 3-1/2 digit CMOS analog-to-digital
converter (ADC) containing all the active components nec-
essary to construct a 0.05% resolution measurement sys-
tem. Seven-segment decoders, digit and polarity drivers,
voltage reference, and clock circuit are integrated on-chip.
The TC7126A directly drives a liquid crystal display (LCD),
and includes a backplane driver.
A low-cost, high-resolution indicating meter requires
only a display, four resistors, and four capacitors. The
TC7126A's extremely low power drain and 9V battery
operation make it ideal for portable applications.
The TC7126A reduces linearity error to less than 1
count. Roll-over error (the difference in readings for equal
magnitude but opposite polarity input signals) is below ±1
count. High-impedance differential inputs offer 1 pA leak-
age current and a 1012Ω input impedance. The 15 µVP-P
noise performance guarantees a "rock solid" reading, and
the auto-zero cycle guarantees a zero display reading with
a 0V input.
■ Low Temperature Drift Internal Reference
TC7126 ....................................... 80 ppm/°C Typ
TC7126A ..................................... 35 ppm/°C Typ
■ Guaranteed Zero Reading With Zero Input
■ Low Noise.................................................... 15 µVP-P
■ High Resolution ..............................................0.05%
■ Low Input Leakage Current ...................... 1 pA Typ
10 pA Max
■ Precision Null Detectors With True Polarity at
Zero
■ High-Impedance Differential Input
■ Convenient 9V Battery Operation With
Low Power Dissipation ........................ 500 µW Typ
900 µW Max
TYPICAL APPLICATIONS
■ Thermometry
■ Bridge Readouts: Strain Gauges, Load Cells, Null
Detectors
■ Digital Meters and Panel Meters
— Voltage/Current/Ohms/Power, pH
■ Digital Scales, Process Monitors
The TC7126A features a precision, low-drift internal
voltagereferenceandisfunctionallyidenticaltotheTC7126.
A low-drift external reference is not normally required with
the TC7126A.
TYPICAL OPERATING CIRCUIT
ORDERING INFORMATION
PART CODE
TC7126X X XXX
0.1 µF
A or blank*
33
–
34
C
R (reversed pins) or blank (CPL pkg only)
* "A" parts have an improved reference TC
Package Code (see below):
LCD
+
C
REF
REF
1 MΩ
31
SEGMENT
DRIVE
+
2–19
+
V
IN
22–25
ANALOG
INPUT
–
0.01 µF
20
–
30
32
POL
BP
V
IN
MINUS SIGN
21
1
BACKPLANE
ANALOG
COMMON
Package
Code
Temperature
+
V
Package
Range
28
V
240 kΩ
BUFF
+
TC7126
TC7126A
CKW
CLW
CPL
IPL
44-Pin PQFP
0°C to +70°C
0°C to +70°C
9V
0.33
µF
180 kΩ
36
44-Pin PLCC
+
V
29
REF
10 kΩ
C
V
AZ
40-Pin PDIP
0°C to +70°C
–
35
26
0.15 µF
V
REF
27
40-Pin PDIP (non-A only)
– 25°C to +85°C
–
V
INT
1 CONVERSION/SEC
OSC OSC OSC
2
3
1
AVAILABLE PACKAGES
C
39
38
40
OSC
TO ANALOG COMMON
(PIN 32)
50 pF
R
OSC
NOTE: Pin numbers refer to 40-pin DIP.
560 kΩ
40-Pin Plastic DIP
44-Pin Plastic Quad Flat
Package Formed Leads
44-Pin Plastic Chip
Carrier PLCC
TC7126/A-8 11/6/96
TELCOM SEMICONDUCTOR, INC.
3-217
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V+ to V–)......................................... +15V
Analog Input Voltage (Either Input) (Note 1) ........ V+ to V–
Reference Input Voltage (Either Input)................. V+ to V–
Clock Input ...................................................... TEST to V+
Operating Temperature Range
C Devices .............................................. 0°C to +70°C
I Devices ........................................... – 25°C to +85°C
Storage Temperature Range ................ – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
Power Dissipation, (TA ≤ 70°C), (Note 2)
44-Pin PQFP ....................................................1.00W
44-Pin PLCC.....................................................1.23W
40-Pin Plastic PDIP ..........................................1.23W
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS: VS = +9V, fCLK = 16 kHz, and TA = +25°C, unless otherwise noted.
Symbol
Input
Parameter
Test Conditions
Min
Typ
Max
Unit
Zero Input Reading
VIN = 0V
–000.0
±000.0
+000.0
Digital
Full Scale = 200 mV
Reading
Zero Reading Drift
VIN = 0V, 0°C ≤ TA ≤ +70°C
VIN = VREF, VREF = 100 mV
—
0.2
1
µV/°C
Ratiometric Reading
999
999/1000
1000
Digital
Reading
NL
Linearity Error
Full Scale = 200 mV or 2V
Max Deviation From Best Fit
Straight Line
– 1
±0.2
1
Count
Roll-Over Error
Noise
–VIN = +VIN ≈ 200 mV
VIN = 0V, Full Scale = 200 mV
VIN = 0V
– 1
15
1
±0.2
—
1 Count
µVP-P
pA
eN
—
—
—
IL
Input Leakage Current
10
CMRR
Common-Mode Rejection
Ratio
VCM = ±1V, VIN = 0V,
Full Scale = 200 mV
50
—
µV/V
Scale Factor Temperature
Coefficient
VIN = 199 mV, 0°C ≤ TA ≤ +70°C
Ext Ref Temp Coeff = 0 ppm/°C
—
1
5
ppm/°C
Analog Common
VCTC Analog Common
250 kΩ Between Common and V+
0°C ≤ TA ≤ +70°C ("C" Devices):
TC7126
—
—
—
—
—
—
80
35
—
—
—
75
—
—
ppm/°C
ppm/°C
Temperature Coefficient
TC7126A
– 25°C ≤ TA ≤ +85°C ("I" Device):
TC7126A
—
35
100
ppm/°C
VC
Analog Common Voltage
250 kΩ Between Common and V+
2.7
3.05
3.35
V
LCD Drive
VSD
LCD Segment Drive Voltage
LCD Backplane Drive Voltage
V+ to V– = 9V
V+ to V– = 9V
4
4
5
5
6
6
VP-P
VP-P
VBD
Power Supply
IS
Power Supply Current
VIN = 0V, V+ to V– = 9V (Note 6)
—
55
100
µA
NOTES: 1. Input voltage may exceed supply voltages when input current is limited to 100 µA.
2. Dissipation rating assumes device is mounted with all leads soldered to PC board.
3. Refer to "Differential Input" discussion.
4. Backplane drive is in-phase with segment drive for "OFF" segment and 180° out-of-phase for "ON" segment. Frequency is 20 times
conversion rate. Average DC component is less than 50 mV.
5. See "Typical Operating Circuit."
6. During auto-zero phase, current is 10–20 µA higher. A 48 kHz oscillator increases current by 8 µA (typical). Common current not
included.
3-218
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
3
TC7126
TC7126A
PIN CONFIGURATIONS
+
+
6
5
4
3
2
1
44 43 42 41 40
44 43 42 41 40 39 38 37 36 35 34
–
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
NC
NC
NC
F
G
E
7
8
39
38
37
36
35
34
33
32
31
30
29
V
1
1
1
REF
+
G
2
C
C
REF
–
C
3
TEST
9
REF
A
3
OSC
3
D
C
10
COMMON
+
IN
2
2
G
3
NC
5
6
V
11
12
13
14
15
16
17
BP
OSC
2
NC
–
IN
NC
TC7126CLW
TC7126ACLW
(PLCC)
TC7126CKW
TC7126ACKW
(FLAT PACKAGE)
POL
7
OSC
1
B
2
V
+
AB
4
V
8
A
2
C
AZ
D
1
E
3
9
F
2
V
BUFF
F
3
10
11
C
1
E
2
V
INT
–
B
3
B
1
D
3
V
25 26 27 28
18 19 20 21 22 23 24
19 20 21 22
12 13 14 15 16 17 18
+
+
OSC
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OSC
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
D
C
V
D
C
1
2
1
2
3
NORMAL PIN
CONFIGURATION
REVERSE PIN
CONFIGURATION
OSC
OSC
OSC
OSC
1
1
1
1
1
1
1
1
1
1
1
1
3
3
3
TEST
B
A
F
4
4
B
A
F
TEST
+
+
V
5
5
1's
V
1's
REF
REF
–
–
V
6
6
V
REF
REF
+
+
C
G
G
E
C
7
7
1
REF
REF
–
–
C
E
C
8
8
1
REF
REF
ANALOG
COMMON
ANALOG
9
9
D
C
B
A
F
D
C
B
A
F
2
2
2
2
2
2
2
2
2
2
2
2
COMMON
+
+
V
V
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
IN
IN
TC7126CPL
TC7126ACPL
TC7126IPL
TC7126RCPL
TC7126ARCPL
TC7126RIPL
–
–
V
V
IN
IN
10's
10's
C
C
AZ
AZ
TC7126AIPL
TC7126ARIPL
V
V
BUFF
BUFF
V
E
E
V
INT
–
INT
–
D
B
V
V
D
B
3
3
3
3
G
2
G
2
100's
100's
C
3
F
E
F
E
C
3
3
3
4
3
3
100's
100's
A
A
3
3
3
3
G
AB
AB
1000's
G
1000's
4
BP
POL
(MINUS SIGN)
POL
(MINUS SIGN)
BP
(BACKPLANE)
(BACKPLANE)
NC = NO INTERNAL CONNECTION
TELCOM SEMICONDUCTOR, INC.
3-219
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
PIN DESCRIPTION
40-Pin PDIP
Pin Number
Normal
(Reverse)
Name
Description
1
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)
(14)
V+
D1
C1
B1
Positive supply voltage.
2
Activates the D section of the units display.
Activates the C section of the units display.
Activates the B section of the units display.
Activates the A section of the units display.
Activates the F section of the units display.
Activates the G section of the units display.
Activates the E section of the units display.
Activates the D section of the tens display.
Activates the C section of the tens display.
Activates the B section of the tens display.
Activates the A section of the tens display.
Activates the F section of the tens display.
Activates the E section of the tens display.
Activates the D section of the hundreds display.
Activates the B section of the hundreds display.
Activates the F section of the hundreds display.
Activates the E section of the hundreds display.
Activates both halves of the 1 in the thousands display.
Activates the negative polarity display.
3
4
5
A1
6
F1
7
G1
E1
8
9
D2
C2
B2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
A2
F2
E2
D3
B3
F3
E3
AB4
POL
BP
G3
A3
Backplane drive output.
Activates the G section of the hundreds display.
Activates the A section of the hundreds display.
Activates the C section of the hundreds display.
Activates the G section of the tens display.
Negative power supply voltage.
C3
G2
V–
VINT
The integrating capacitor should be selected to give the maximum voltage swing
that ensures component tolerance build-up will not allow the integrator output to
saturate. When analog common is used as a reference and the conversion rate is
3 readings per second, a 0.047 µF capacitor may be used. The capacitor must
have a low dielectric constant to prevent roll-over errors. See "Integrating Capaci-
tor" section for additional details.
28
29
(13)
(12)
VBUFF
CAZ
Integration resistor connection. Use a 180 kΩ resistor for a 200 mV full-scale
range and a 1.8 MΩ resistor for a 2V full-scale range.
The size of the auto-zero capacitor influences system noise. Use a 0.33 µF
capacitor for 200 mV full scale, and a 0.033 µF capacitor for 2V full scale. See
paragraph on auto-zero capacitor for more details.
–
30
31
32
(11)
(10)
(9)
VIN
The low input signal is connected to this pin.
The high input signal is connected to this pin.
+
VIN
ANALOG
COMMON
This pin is primarily used to set the analog common-mode voltage for battery
operation or in systems where the input signal is referenced to the power supply.
See paragraph on analog common for more details. It also acts as a reference
voltage source.
–
33
(8)
CREF
See pin 34.
3-220
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
3
TC7126
TC7126A
PIN DESCRIPTION (Cont.)
40-Pin PDIP
Pin Number
Normal
(Reverse)
Name
CR+EF
Description
34
(7)
A 0.1 µF capacitor is used in most applications. If a large common-mode voltage
exists (for example, the VIN– pin is not at analog common), and a 200 mV scale is
used, a 1 µF capacitor is recommended and will hold the roll-over error to 0.5
count.
35
36
(6)
(5)
VR–EF
VR+EF
See pin 36.
The analog input required to generate a full-scale output (1999 counts). Place 100
mV between pins 35 and 36 for 199.9 mV full scale. Place 1V between pins 35
and 36 for 2V full scale. See paragraph on reference voltage.
(4)
TEST
Lamp test. When pulled HIGH (to V+), all segments will be turned ON and the
display should read –1888. It may also be used as a negative supply for exter-
nally-generated decimal points. See paragraph under test for additional informa-
tion.
37
38
40
(3)
(2)
(1)
OSC3
OSC2
OSC1
See pin 40.
See pin 40.
Pins 40, 39 and 38 make up the oscillator section. For a 48 kHz clock (3 readings
39per second), connect pin 40 to the junction of a 180 kΩ resistor and a 50 pF
capacitor. The 180 kΩ resistor is tied to pin 39 and the 50 pF capacitor is tied to
pin 38.
GENERAL THEORY OF OPERATION
ANALOG
(All Pin Designations Refer to the 40-Pin DIP)
INPUT
INTEGRATOR
–
SIGNAL
COMPARATOR
Dual-Slope Conversion Principles
–
+
The TC7126A is a dual-slope, integrating analog-to-
digital converter. An understanding of the dual-slope con-
version technique will aid in following detailed TC7126A
operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
+
SWITCH
DRIVER
CLOCK
PHASE
CONTROL
REF
VOLTAGE
CONTROL
LOGIC
POLARITY CONTROL
(1) Input signal integration
(2) Reference voltage integration (deintegration)
COUNTER
DISPLAY
The input signal being converted is integrated for a
fixed time period (tSI), measured by counting clock pulses.
An opposite polarity constant reference voltage is then
integrated until the integrator output voltage returns to
zero. The reference integration time is directly proportional
to the input signal (tRI).
In a simple dual-slope converter, a complete conver-
sion requires the integrator output to "ramp-up" and "ramp-
down."
V
V
INϷ V
INϷ
FULL SCALE
1.2 V
FULL SCALE
FIXED VARIABLE
SIGNAL REFERENCE
INTEGRATE INTEGRATE
TIME TIME
Figure 1. Basic Dual-Slope Converter
Asimplemathematicalequationrelatestheinputsignal,
reference voltage, and integration time:
where:
VR = Reference voltage
tSI = Signal integration time (fixed)
tRI = Reference voltage integration time (variable).
tSI
1
VR tRI
RC
VIN(t) dt =
,
∫
RC
0
TELCOM SEMICONDUCTOR, INC.
3-221
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
analog gates close a feedback loop around the integrator
and comparator. This loop permits comparator offset volt-
age error compensation. The voltage level established on
CAZ compensates for device offset voltages. The auto-zero
phase residual is typically 10 µV to 15 µV.
30
20
10
The auto-zero cycle length is 1000 to 3000 clock
periods.
Signal Integration Phase
The auto-zero loop is entered and the internal differen-
+
tial inputs connect to VIN and VIN–. The differential input
t = MEASUREMENT PERIOD
1/t
signal is integrated for a fixed time period. The TC7126A
signal integration period is 1000 clock periods, or counts.
The externally-set clock frequency is Ϭ4 before clocking the
internal counters. The integration time period is:
0
0.1/t
10/t
INPUT FREQUENCY
4
Figure 2. Normal-Mode Rejection of Dual-Slope Converter
tSI
=
ϫ 1000,
fOSC
For a constant VIN:
where fOSC = external clock frequency.
tRI
tSI
VIN = VR
.
The differential input voltage must be within the device
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common, VIN– should be tied to analog com-
mon.
Polarity is determined at the end of signal integrate
phase. Thesignbitisatruepolarityindication, inthatsignals
less than 1 LSB are correctly determined. This allows
precision null detection limited only by device noise and
auto-zero residual offsets.
The dual-slope converter accuracy is unrelated to the
integratingresistorandcapacitorvalues, aslongastheyare
stable during a measurement cycle. Noise immunity is an
inherent benefit. Noise spikes are integrated, or averaged,
to zero during integration periods. Integrating ADCs are
immune to the large conversion errors that plague succes-
sive approximation converters in high-noise environments.
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set to a
multiple of the 50 Hz/60 Hz power line period.
Reference Integrate Phase
The third phase is reference integrate, or deintegrate.
VIN– is internally connected to analog common and VIN+ is
connectedacrossthepreviously-chargedreferencecapaci-
tor. Circuitrywithinthechipensuresthatthecapacitorwillbe
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
return to zero is proportional to the input signal and is
between 0 and 2000 internal clock periods. The digital
reading displayed is:
ANALOG SECTION
In addition to the basic integrate and deintegrate dual-
slope cycles discussed above, the TC7126A design incor-
porates an auto-zero cycle. This cycle removes buffer
amplifier, integrator, and comparator offset voltage error
termsfromtheconversion. Atruedigitalzeroreadingresults
without external adjusting potentiometers. A complete con-
version consists of three phases:
(1) Auto-zero phase
VIN
1000
(2) Signal integrate phase
(3) Reference integrate phase
VREF
DIGITAL SECTION
Auto-Zero Phase
The TC7126A contains all the segment drivers neces-
sary to directly drive a 3-1/2 digit LCD. An LCD backplane
driver is included. The backplane frequency is the external
clock frequency Ϭ800. For 3 conversions per second the
backplane frequency is 60 Hz with a 5V nominal amplitude.
During the auto-zero phase, the differential input signal
is disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero input condition. Additional
3-222
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
3
TC7126
TC7126A
Figure 3. TC7126A Block Diagram
TELCOM SEMICONDUCTOR, INC.
3-223
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
The TC7126A is a drop-in replacement for the TC7126
and ICL7126 that offers a greatly improved internal refer-
ence temperature coefficient. No external component value
changes are required to upgrade existing designs.
When a segment driver is in-phase with the backplane
signal, the segment is OFF. An out-of-phase segment drive
signalcausesthesegmenttobeON,orvisible.ThisACdrive
configuration results in negligible DC voltage across each
LCD segment, ensuring long LCD life. The polarity segment
driver is ON for negative analog inputs. If VIN+ and VIN– are
reversed, this indicator would reverse.
COMPONENT VALUE SELECTION
Auto-Zero Capacitor (CAZ)
On the TC7126A, when the TEST pin is pulled to V+, all
segments are turned ON. The display reads –1888. During
this mode, LCD segments have a constant DC voltage
impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE
FOR MORE THAN SEVERAL MINUTES; LCDS MAY BE
DESTROYED IF OPERATED WITH DC LEVELS FOR
EXTENDED PERIODS.
The CAZ size has some influence on system noise. A
0.33 µF capacitor is recommended for 200 mV full-scale
applications where 1 LSB is 100 µV. A 0.033 µF capacitor is
adequate for 2V full-scale applications. A Mylar-type dielec-
tric capacitor is adequate.
Reference Voltage Capacitor (CREF
)
The display font and segment drive assignment are
shown in Figure 4.
The reference voltage, used to ramp the integrator
output voltage back to zero during the reference integrate
phase, is stored on CREF. A 0.1 µF capacitor is acceptable
when VREF– is tied to analog common. If a large common-
System Timing
The oscillator frequency is Ϭ4 prior to clocking the
internal decade counters. The three-phase measurement
cycle takes a total of 4000 counts (16,000 clock pulses).
The 4000-count cycle is independent of input signal magni-
tude.
–
mode voltage exists (VREF ≠ analog common) and the
application requires a 200 mV full scale, increase CREF to
1 µF. Roll-over error will be held to less than 0.5 count. A
Mylar-type dielectric capacitor is adequate.
Each phase of the measurement cycle has the following
length:
Integrating Capacitor (CINT
)
(1) Auto-zero phase: 1000 to 3000 counts
(4000 to 12,000 clock pulses)
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Due to
the TC7126A's superior analog common temperature co-
efficient specification, analog common will normally sup-
ply the differential voltage reference. For this case, a ±2V
full-scale integrator output swing is satisfactory. For 3
readings per second (fOSC = 48 kHz), a 0.047 µF value is
suggested. For 1 reading per second, 0.15 µF is recom-
mended. If a different oscillator frequency is used, CINT
must be changed in inverse proportion to maintain the
nominal ±2V integrator swing.
Forsignalslessthanfullscale, theauto-zerophase
is assigned the unused reference integrate time
period.
(2) Signal integrate: 1000 counts
(4000 clock pulses)
This time period is fixed. The integration period is:
1
tSI = 4000
,
fOSC
An exact expression for CINT is:
where fOSC is the externally-set clock frequency.
1
VFS
(4000)
(3) Reference integrate: 0 to 2000 counts
(0 to 8000 clock pulses)
( )(R
)
fOSC
INT
CINT
=
,
VINT
DISPLAY FONT
where: fOSC = Clock frequency at pin 38
VFS = Full-scale input voltage
RINT = Integrating resistor
1000's
100's
10's
1's
VINT = Desired full-scale integrator output swing.
At 3 readings per second, a 750Ω resistor should be
placed in series with CINT. This increases accuracy by
compensating for comparator delay. CINT must have low
dielectric absorption to minimize roll-over error. A polypro-
pylene capacitor is recommended.
Figure 4. Display Font and Segment Assignment
3-224
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
3
TC7126
TC7126A
Integrating Resistor (RINT
)
input voltage by two, the reference voltage should be set to
200 mV. This permits the transducer input to be used
directly.
The differential reference can also be used where a
digital zero reading is required when VIN is not equal to zero.
This is common in temperature-measuring instrumentation.
A compensating offset voltage can be applied between
analog common and VIN–. The transducer output is con-
nected between VIN+ and analog common.
The input buffer amplifier and integrator are designed
with Class A output stages. The output stage idling current
is 6 µA. The integrator and buffer can supply 1 µA drive
current with negligible linearity errors. RINT is chosen to
remain in the output stage linear drive region, but not so
large that PC board leakage currents induce errors. For a
200 mV full scale, RINT is 180 kΩ. A 2V full scale requires
1.8 MΩ.
DEVICE PIN FUNCTIONAL DESCRIPTION
Component
Value
Nominal Full-Scale Voltage
(Pin Numbers Refer to 40-Pin DIP)
200 mV
2V
Differential Signal Inputs
VIN+ (Pin 31), VIN– (Pin 30)
CAZ
RINT
CINT
0.33 µF
180 kΩ
0.033 µF
1.8 MΩ
The TC7126A is designed with true differential inputs
and accepts input signals within the input stage common-
mode voltage range (VCM). Typical range is V+ –1V to V–
+1V.Common-modevoltagesareremovedfromthesystem
whentheTC7126Aoperatesfromabatteryorfloatingpower
source (isolated from measured system), and VIN– is con-
nected to analog common (VCOM). (See Figure 5.)
In systems where common-mode voltages exist, the
TC7126A's 86 dB common-mode rejection ratio minimizes
error. Common-mode voltages do, however, affect the inte-
grator output level. A worst-case condition exists if a large
positive VCM exists in conjunction with a full-scale negative
differential signal. The negative signal drives the integrator
output positive along with VCM (see Figure 6.) For such
applications, the integrator output swing can be reduced
below the recommended 2V full-scale swing. The integrator
output will swing within 0.3V of V+ or V– without increased
linearity error.
0.047 µF
0.047 µF
NOTE: fOSC = 48 kHz (3 readings per sec).
Oscillator Components
COSC should be 50 pF; ROSC is selected from the
equation:
0.45
RC
fOSC
=
.
For a 48 kHz clock (3 conversions per second), R = 180 kΩ.
Note that fOSC is Ϭ4 to generate the TC7126A's inter-
nal clock. The backplane drive signal is derived by dividing
fOSC by 800.
To achieve maximum rejection of 60 Hz noise pickup,
the signal integrate period should be a multiple of 60 Hz.
Oscillator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz,
40 kHz, etc. should be selected. For 50 Hz rejection,
oscillator frequencies of 200 kHz, 100 kHz, 66-2/3 kHz, 50
kHz, 40 kHz, etc. would be suitable. Note that 40 kHz (2.5
readings per second) will reject both 50 Hz and 60 Hz.
Differential Reference
VREF+ (Pin 36), VREF– (Pin 35)
The reference voltage can be generated anywhere
within the V+ to V– power supply range.
To prevent roll-over type errors being induced by large
common-mode voltages, CREF should be large compared to
stray node capacitance.
The TC7126A offers a significantly improved analog
common temperature coefficient. This potential provides a
very stable voltage, suitable for use as a voltage reference.
The temperature coefficient of analog common is typically
35 ppm/°C for the TC7126A and 80 ppm/°C for the TC7126.
Reference Voltage Selection
A full-scale reading (2000 counts) requires the input
signal be twice the reference voltage.
Required Full-Scale Voltage*
VREF
200 mV
2V
100 mV
1V
*VFS = 2 VREF
.
ANALOG COMMON (Pin 32)
The analog common pin is set at a voltage potential
approximately 3V below V+. The potential is guaranteed to
be between 2.7V and 3.35V below V+. Analog common is
tied internally to an N-channel FET capable of sinking
Insomeapplications, ascalefactorotherthanunitymay
exist between a transducer output voltage and the required
digitalreading. Assume, forexample, apressuretransducer
output for 2000 lb/in.2 is 400 mV. Rather than dividing the
TELCOM SEMICONDUCTOR, INC.
3-225
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
SEGMENT
DRIVE
LCD
MEASURED
SYSTEM
V
C
V
POL BP
BUFF
AZ
INT
OSC
+
1
V
IN
+
V
–
OSC
OSC
3
2
V
TC7126A
IN
–
V
GND
ANALOG
COMMON REF REF
–
+
+
–
V
V
V
V
+
–
V
V
GND
POWER
SOURCE
+
9V
Figure 5. Common-Mode Voltage Removed in Battery Operation With VIN = Analog Common
100 µA. This FET will hold the common line at 3V should an
external load attempt to pull the common line toward V+.
Analogcommonsourcecurrentislimitedto1 µA.Therefore,
analog common is easily pulled to a more negative voltage
(i.e., below V+ – 3V).
with respect to the TC7126A's power source. The analog
common potential of V+ –3V gives a 7V end of battery life
voltage. The common potential has a 0.001%/% voltage
coefficient and a 15Ω output impedance.
With sufficiently high total supply voltage (V+–V– >7V),
analog common is a very stable potential with excellent
temperature stability (typically 35 ppm/°c). This potential
can be used to generate the TC7126A's reference voltage.
An external voltage reference will be unnecessary in most
cases because of the 35 ppm/°C temperature coefficient.
See "TC7126A Internal Voltage Reference" discussion.
The TC7126A connects the internal V+IN and VI–N in-
puts to analog common during the auto-zero phase. During
the reference-integrate phase, VI–N is connected to analog
common. If V+IN is not externally connected to analog com-
mon, a common-mode voltage exists, but is rejected by the
converter's 86 dB common-mode rejection ratio. In battery
operation, analog common and VI–N are usually connected,
removingcommon-modevoltageconcerns.Insystemswhere
VI–N is connected to power supply ground or to a given
voltage, analog common should be connected to VI–N.
The analog common pin serves to set the analog sec-
tion reference, or common point. The TC7126A is specifi-
cally designed to operate from a battery or in any measure-
ment system where input signals are not referenced (float)
TEST (Pin 37)
The TEST pin potential is 5V less than V+. TEST may be
used as the negative power supply connection for external
CMOSlogic.TheTESTpinistiedtotheinternally-generated
negativelogicsupplythrougha500Ω resistor.TheTESTpin
load should not be more than 1 mA. See "Digital Section" for
additional information on using TEST as a negative digital
logic supply.
If TEST is pulled HIGH (to V+), all segments plus the
minus sign will be activated. DO NOT OPERATE IN THIS
MODE FOR MORE THAN SEVERAL MINUTES. With
TEST= V+, the LCD segments are impressed with a DC
voltage which will destroy the LCD.
C
INPUT
BUFFER
I
R
+
V
–
+
–
I
–
+
V
I
IN
INTEGRATOR
TC7126A Internal Voltage Reference
T
The TC7126A's analog common voltage temperature
stability has been significantly improved (Figure 7). The "A"
version of the industry-standard TC7126 device allows
users to upgrade old systems and design new systems
without external voltage references. External R and C val-
ues do not need to be changed. Figure 10 shows analog
common supplying the necessary voltage reference for the
TC7126A.
I
C
V =
V
V
IN
–
I
[
CM
[
R
V
I
I
CM
Where:
4000
T
Integration time
=
=
=
I
f
OSC
C
R
Integration capacitor
= Integration resistor
I
I
Figure 6. Common-Mode Voltage Reduces Available Integrator
Swing (VCOM ≠ VIN)
3-226
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
3
TC7126
TC7126A
9V
200
+
180
NO
MAXIMUM
SPECIFIED
160
140
120
100
26
1
+
–
240 kΩ
V
V
TYPICAL
TC7126A
NO
MAXIMUM
SPECIFIED
36
+
GUARANTEED
MAXIMUM
V
10 kΩ
REF
80
60
40
20
V
TYPICAL
REF
–
35
V
REF
TYPICAL
TC7126A
32
ANALOG
COMMON
ICL7126
ICL7136
SET V
= 1/2 V
REF
FULL SCALE
0
Figure 8. TC7126A Internal Voltage Reference Connection
Figure 7. Analog Common Temperature Coefficient
Flat Package
APPLICATIONS INFORMATION
Liquid Crystal Display Sources
The TC7126A is available in an epoxy 64-pin formed-
leadflatpackage.AtestsocketfortheTC7126ACBQdevice
is available:
Several manufacturers supply standard LCDs to inter-
face with the TC7126A 3-1/2 digit analog-to-digital con-
verter.
Part No.
IC 51-42
Manufacturer: Yamaichi
Distribution: Nepenthe Distribution
2471 East Bayshore
Suite 520
Representative
Manufacturer Address/Phone
Part Numbers*
Crystaloid
Electronics
5282 Hudson Dr.,
Hudson, OH 44236
216-655-2429
C5335, H5535,
T5135, SX440
Palo Alto, CA 94043
(415) 856-9332
AND
720 Palomar Avenue
Sunnyvale, CA 94086
408-523-8200
FE 0801,
FE 0203
Ratiometric Resistance Measurements
The TC7126A's true differential input and differential
reference make ratiometric readings possible. In ratiometric
operation, an unknown resistance is measured with respect
to a known standard resistance. No accurately-defined
reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current passed through the pair. The voltage
developed across the unknown is applied to the input and
the voltage across the known resistor applied to the refer-
ence input. If the unknown equals the standard, the display
will read 1000. The displayed reading can be determined
from the following expression:
VGI, Inc.
Hamlin, Inc.
1800 Vernon St., Ste. 2 I1048, I1126
Roseville, CA 95678
916-783-7878
612 E. Lake St.,
Lake Mills, WI 53551
414-648-2361
3902, 3933, 3903
*NOTE: Contact LCD manufacturer for full product listing/specifications.
Decimal Point and Annunciator Drive
The TEST pin is connected to the internally-generated
digital logic supply ground through a 500Ω resistor. The
TEST pin may be used as the negative supply for external
CMOS gate segment drivers. LCD annunciators for decimal
points, low battery indication, or function indication may be
added without adding an additional supply. No more than 1
mA should be supplied by the TEST pin: its potential is
approximately 5V below V+.
RUNKNOWN
Displayed reading =
ϫ 1000.
RSTANDARD
The display will overrange for RUNKNOWN
2ϫRSTANDARD
≥
.
TELCOM SEMICONDUCTOR, INC.
3-227
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
Simple Inverter for Fixed Decimal Point
or Display Annunciator
+
+
V
V
REF
–
+
V
V
R
REF
STANDARD
+
V
LCD
+
4049
V
IN
TC7126A
BP
R
TO LCD
DECIMAL
POINT
UNKNOWN
TC7126A
21
37
–
V
IN
GND
TEST
ANALOG
COMMON
TO
BACKPLANE
Multiple Decimal Point or
Annunciator Driver
Figure 10. Low Parts Count Ratiometric Resistance Measurement
+
V
+
V
BP
TO LCD
DECIMAL
POINTS
DECIMAL
POINT
SELECT
TC7126A
TEST
4030
GND
Figure 9. Decimal Point and Annunciator Drives
9V
+
26
1N4148
1 µF
200 mV
27
29
–
1
+
V
1 MΩ
10 MΩ
1
2
3
4
5
6
7
14
13
12
11
10
9
V
V
IN
9 MΩ
240 kΩ
10 kΩ
0.02
µF
C1
TC7126A
2V
36
35
+
AD636
V
V
REF
–
28
40
47 kΩ
1W
10%
6.8 µF
REF
C2
900 kΩ
90 kΩ
10 kΩ
+
32
31
ANALOG
COMMON
20V
1 MΩ 10%
+
IN
8
V
0.01
µF
2.2
µF
30
26
20 kΩ
10%
38
39
+
V
200V
OUT
–
V
BP
SEGMENT
DRIVE
C1 = 3 pF TO 10 pF, VARIABLE
C2 = 132 pF, VARIABLE
COM
LCD
Figure 11. 3-1/2 Digit True RMS AC DMM
3-228
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
3
TC7126
TC7126A
9V
+
+
9V
5.6 kΩ
160 kΩ
160 kΩ
300 kΩ
300 kΩ
+
–
+
–
V
–
V
V
–
V
V
V
R
V
V
1N4148
IN
1
IN
20 kΩ
+
R
+
1N4148
SENSOR
1
IN
IN
50 kΩ
0.7%/°C
PTC
TC7126A
R
2
20 kΩ
+
+
TC7126A
R
3
R
V
V
2
V
V
REF
REF
50 kΩ
–
–
REF
REF
COMMON
COMMON
Figure 12. Temperature Sensor
Figure 13. Positive Temperature Coefficient Resistor
Temperature Sensor
9V
2
+
CONSTANT 5V
+
V
V
+
V
REF
51 kΩ
51 kΩ
6
5
3
V
50 kΩ
OUT
ADJ
–
R
4
R
5
R
R
V
2
REF
8
2
3
–
NC
1
1/2
LM358
+
V
V
IN
REF02
TC7126A
TEMP
+
4
TEMPERATURE
DEPENDENT OUTPUT
–
IN
V
=
OUT
50 kΩ
1.86V @
+25°C
COMMON
V
1
–
GND
4
Figure 14. Integrated Circuit Temperature Sensor
TELCOM SEMICONDUCTOR, INC.
3-229
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