TC7136ACKW [TELCOM]
LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS; 低功耗， 3-1 / 2位模拟数字转换器
| 型号： | TC7136ACKW |
| 厂家： | 
TELCOM SEMICONDUCTOR, INC |
| 描述： | LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS |
| 文件： | 总12页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3
TC7136
TC7136A
LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS
FEATURES
GENERAL DESCRIPTION
■ Fast Overrange Recovery, Guaranteed First
Reading Accuracy
The TC7136 and TC7136A are low-power, 3-1/2 digit
with liquid crystal display (LCD) drivers with analog-to-
digital converters. These devices incorporate an "integra-
tor output zero" phase which guarantees overrange
recovery. The performance of existing TC7126, TC7126A
and ICL7126-based systems may be upgraded with minor
changes to external, passive components.
The TC7136A has an improved internal zener refer-
ence voltage circuit which maintains the analog common
temperature drift to 35 ppm/°C (typical) and 75 ppm/°C
(maximum). This represents an improvement of two to four
times over similar 3-1/2 digit converters. The costly, space-
consuming external reference source may be removed.
The TC7136/A limits linearity error to less than 1 count
on 200 mV or 2V full-scale ranges. Roll-over error — the
difference in readings for equal magnitude but opposite
polarity input signals — is below ±1 count. High-impedance
differential inputs offer 1 pA leakage currents and a 1012Ω
input impedance. The differential reference input allows
ratiometric measurements for ohms or bridge transducer
measurements. The 15 µVP-P noise performance guaran-
tees a "rock solid" reading. The auto-zero cycle guarantees
a zero display readout for a 0V input.
■ Low Temperature Drift Internal Reference
TC7136 ....................................... 70 ppm/°C Typ
TC7136A ..................................... 35 ppm/°C Typ
■ Guaranteed Zero Reading With Zero Input
■ Low Noise.................................................... 15 µVP-P
■ High Resolution .............................................. 0.05%
■ Low Input Leakage Current ...................... 1 pA Typ
10 pA Max
■ Precision Null Detectors With True Polarity at
Zero
■ High-Impedance Differential Input
■ Convenient 9V Battery Operation With
Low Power Dissipation ........................ 500 µW Typ
900 µW Max
TYPICAL APPLICATIONS
■ Thermometry
■ Bridge Readouts: Strain Gauges, Load Cells, Null
Detectors
■ Digital Meters: Voltage/Current/Ohms/Power, pH
■ Digital Scales, Process Monitors
■ Portable Instrumentation
TYPICAL OPERATING CIRCUIT
ORDERING INFORMATION
PART CODE
TC7136X X XXX
0.1 µF
A or blank*
33
–
34
C
LCD
+
C
REF
REF
R (reversed pins) or blank (CPL pkg only)
* "A" parts have an improved reference TC
Package Code (see below):
Package
1 MΩ
31
SEGMENT
DRIVE
+
9–19
+
V
IN
22–25
ANALOG
INPUT
–
0.01 µF
20
–
30
32
POL
BP
V
IN
MINUS SIGN
21
1
BACKPLANE
ANALOG
COMMON
Temperature
Range
+
V
Code
Package
Pin Layout
28
V
CKW
CLW
CPL
44-Pin PQFP
44-Pin PLCC
40-Pin PDIP
Formed Leads
—
0°C to +70°C
0°C to +70°C
0°C to +70°C
240 kΩ
BUFF
+
TC7136
TC7136A
9V
0.47
µF
180 kΩ
36
+
Normal
V
29
REF
10 kΩ
C
V
AZ
–
35
26
0.15 µF
V
AVAILABLE PACKAGES
REF
27
–
V
INT
1 CONVERSION/SEC
OSC OSC OSC
2
3
1
C
39
38
40
OSC
TO ANALOG COMMON
(PIN 32)
50 pF
R
OSC
44-Pin Plastic Quad Flat 44-Pin Plastic Chip
Package Formed Leads Carrier PLCC
40-Pin Plastic DIP
560 kΩ
TC7136-6 10/18/96
TELCOM SEMICONDUCTOR, INC.
3-247
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7136
TC7136A
Operating Temperature Range
ABSOLUTE MAXIMUM RATINGS*
C Devices ..............................................0°C to +70°C
I Devices ............................................ –25°C to +85°C
Storage Temperature Range ................. –65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
Supply Voltage (V+ to V–)............................................15V
Analog Input Voltage (Either Input) (Note 1) ........ V+ to V–
Reference Input Voltage (Either Input)................. V+ to V–
Clock Input ...................................................... TEST to V+
Package Power Dissipation (TA ≤ 70°C) (Note 2)
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
Plastic DIP ........................................................1.23W
Plastic Quad Flat Package ...............................1.00W
PLCC ................................................................1.23W
ELECTRICAL CHARACTERISTICS: VS = 9V, fCLK = 16 kHz, and TA = +25°C, unless otherwise noted.
Symbol
Input
Parameter
Test Conditions
Min
Typ
Max
Unit
Zero Input Reading
VIN = 0V
– 000.0
±000.0
+000.0
Digital
Full Scale = 200 mV
Reading
Zero Reading Drift
VIN = 0V, 0°C ≤ TA ≤ +70°C
—
0.2
1
µV/°C
Ratiometric Reading
VIN = VREF, VREF = 100 mV
999
999/1000
1000
Digital
Reading
NL
Nonlinearity Error
Full Scale = 200 mV or 2V
Max Deviation From Best
Straight Line
– 1
±0.2
1
Count
Roll-Over Error
Noise
–VIN = +VIN ≈ 200 mV
VIN = 0V, Full Scale = 200 mV
VIN = 0V
– 1
15
1
±0.2
—
1 Count
µVP-P
pA
eN
—
—
—
IL
Input Leakage Current
10
CMRR
Common-Mode Rejection
Ratio
VCM = ±1V, VIN = 0V,
Full Scale = 200 mV
50
—
µV/V
Scale Factor Temperature
Coefficient
VIN = 199 mV, 0°C ≤ TA ≤ +70°C
Ext Ref Temp Coeff = 0 ppm/°C
—
1
5
ppm/°C
Analog Common
VCTC
Analog Common
250 kΩ Between Common and V+
Temperature Coefficient
0°C ≤ TA ≤ +70°C
"C" Commercial Temp TC7136
Range Devices
TC7136A
—
—
35
70
75
150
ppm/°C
ppm/°C
– 25°C ≤ TA ≤ +85°C
"I" Industrial Temp
Range Devices
TC7136A
TC7136
—
—
35
70
100
150
ppm/°C
ppm/°C
VC
Analog Common Voltage
250 kW Between Common and V+
2.7
3.05
3.35
V
LCD Drive
VSD
LCD Segment Drive Voltage
LCD Backplane Drive Voltage
V+ to V– = 9V
V+ to V– = 9V
4
4
5
5
6
6
VP-P
VP-P
VBD
Power Supply
IS
Power Supply Current
VIN = 0V, V+ to V– = 9V (Note 6)
—
70
100
µA
NOTES: 1. Input voltages may exceed supply voltages when input current is limited to 100 µA.
2. Dissipation rating assumes device is mounted with all leads soldered to PC board.
3. Refer to "Differential Input" discussion.
4. Backplane drive is in-phase with segment drive for "OFF" segment and 180° out-of-phase for "ON" segment. Frequency is 20 times
conversion rate. Average DC component is less than 50 mV.
5. See "Typical Operating Circuit".
6. A 48 kHz oscillator increases current by 20 µA (typical). Common current not included.
3-248
TELCOM SEMICONDUCTOR, INC.
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
3
TC7136
TC7136A
PIN CONFIGURATIONS
6
5
4
3
2
1
44 43 42 41 40
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
NC
NC
NC
F
G
E
7
8
39
38
37
36
35
34
33
32
31
30
29
REF LO
+
1
1
1
G
2
C
REF
–
C
3
TEST
C
9
REF
A
3
OSC
3
D
C
10
COMMON
IN HI
NC
2
2
G
3
NC
5
6
11
12
13
14
15
16
17
BP
OSC
2
NC
TC7136CLW
TC7136ACLW
(PLCC)
TC7136CKW
TC7136ACKW
(PQFP)
POL
7
OSC
1
B
2
IN LO
AZ
+
AB
4
V
8
A
2
D
1
E
3
9
F
2
BUFF
INT
F
3
10
11
C
1
E
2
–
B
3
B
1
D
3
V
25 26 27 28
18 19 20 21 22 23 24
19 20 21 22
12 13 14 15 16 17 18
+
+
OSC
OSC
OSC
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OSC
OSC
OSC
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
D
C
V
D
C
1
2
1
2
3
NORMAL PIN
CONFIGURATION
REVERSE PIN
CONFIGURATION
1
1
1
1
1
1
1
1
1
1
3
3
3
TEST
B
A
F
4
4
B
A
F
TEST
+
+
V
5
5
1's
V
1's
REF
REF
–
–
V
6
6
V
REF
REF
+
+
C
G
G
1
C
7
7
1
REF
REF
–
–
C
E
E
C
8
8
1
1
REF
REF
ANALOG
COMMON
ANALOG
9
9
D
C
B
A
F
D
C
B
A
F
2
2
2
2
2
2
2
2
2
2
2
2
COMMON
+
V
+
V
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
IN
IN
TC7136CPL
TC7136ACPL
(PDIP)
–
–
TC7136RCPL
TC7136ARCPL
(Reversed)
PDIP
V
V
IN
IN
10's
10's
C
C
AZ
AZ
V
V
BUFF
BUFF
V
E
E
V
INT
INT
–
–
D
B
V
V
D
B
3
3
3
3
G
2
G
2
100's
100's
C
3
F
E
F
E
C
3
3
3
4
3
3
100's
100's
A
A
3
3
3
3
G
AB
AB
1000's
G
1000's
4
BP
(BACKPLANE)
POL
(MINUS SIGN)
POL
(MINUS SIGN)
BP
(BACKPLANE)
NC = NO INTERNAL CONNECTION
TELCOM SEMICONDUCTOR, INC.
3-249
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7136
TC7136A
TC7136/A PIN DESCRIPTION
Pin No.
40-Pin PDIP
Normal
(Reverse)
Name
Description
1
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)
(14)
V+
D1
C1
B1
Positive supply voltage.
2
Activates the D section of the units display.
Activates the C section of the units display.
Activates the B section of the units display.
Activates the A section of the units display.
Activates the F section of the units display.
Activates the G section of the units display.
Activates the E section of the units display.
Activates the D section of the tens display.
Activates the C section of the tens display.
Activates the B section of the tens display.
Activates the A section of the tens display
Activates the F section of the tens display.
Activates the E section of the tens display.
Activates the D section of the hundreds display.
Activates the B section of the hundreds display.
Activates the F section of the hundreds display.
Activates the E section of the hundreds display.
Activates both halves of the 1 in the thousands display.
Activates the negative polarity display.
3
4
5
A1
6
F1
7
G1
E1
8
9
D2
C2
B2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
A2
F2
E2
D3
B3
F3
E3
AB4
POL
BP
G3
A3
Backplane drive output.
Activates the G section of the hundreds display.
Activates the A section of the hundreds display.
Activates the C section of the hundreds display.
Activates the G section of the tens display.
Negative power supply voltage.
C3
G2
V–
VINT
The integrating capacitor should be selected to give the maximum voltage
swing that ensures component tolerance build-up will not allow the integrator
output to saturate. When analog common is used as a reference and the
conversion rate is 3 readings per second, a 0.047 µF capacitor may be used.
The capacitor must have a low dielectric constant to prevent roll-over errors.
See Integrating Capacitor section for additional details.
28
29
(13)
(12)
VBUFF
CAZ
Integration resistor connection. Use a 180 kΩ for a 200 mV full-scale range
and a 1.8 MΩ for 2V full-scale range.
The size of the auto-zero capacitor influences the system noise. Use a 0.47 µF
capacitor for a 200 mV full scale, and a 0.1 µF capacitor for a 2V full scale. See
paragraph on Auto-Zero Capacitor for more details.
30
31
32
(11)
(10)
(9)
VIN–
VIN+
The low input signal is connected to this pin.
The high input signal is connected to this pin.
ANALOG
COMMON
This pin is primarily used to set the analog common-mode voltage for battery
operation or in systems where the input signal is referenced to the power
supply. See paragraph on Analog Common for more details. It also acts as a
reference voltage source.
3-250
TELCOM SEMICONDUCTOR, INC.
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
3
TC7136
TC7136A
TC7136/A PIN DESCRIPTION (Cont.)
Pin No.
40-Pin PDIP
Normal
(Reverse)
Name
Description
33
34
(8)
(7)
C–REF
C+REF
See pin 34.
A 0.1 µF capacitor is used in most applications. If a large common-mode
voltage exists (for example, the VIN– pin is not at analog common), and a 200
mV scale is used, a 1 µF capacitor is recommended and will hold the roll-over
error to 0.5 count.
35
36
(6)
(5)
V–REF
V–REF
See pin 36.
The analog input required to generate a full-scale output (1999 counts). Place
100 mV between pins 35 and 36 for 199.9 mV full scale. Place 1V between
pins 35 and 36 for 2V full scale. See paragraph on Reference Voltage.
Lamp test. When pulled HIGH (to V+) all segments will be turned ON and the
display should read –1888. It may also be used as a negative supply for exter-
nally-generated decimal points. See paragraph under Test for additional informa-
tion.
(4)
TEST
37
38
39
(3)
(2)
(1)
OSC3
OSC2
OSC1
See pin 40.
See pin 40.
Pins 40, 39 and 38 make up the oscillator section. For a 48 kHz clock (3 readings per
second) connect pin 40 to the junction of a 180 kΩ resistor and a 50 pF capacitor. The
180 kΩ resistor is tied to pin 39 and the 50 pF capacitor is tied to pin 38.
C
INT
GENERAL THEORY OF OPERATION
(All Pin designations refer to 40-Pin Dip)
Dual-Slope Conversion Principles
ANALOG
INPUT
INTEGRATOR
SIGNAL
COMPARATOR
–
–
+
+
The TC7136/A is a dual-slope, integrating analog-to-
digital converter. An understanding of the dual-slope con-
version technique will aid in following detailed TC7136/A
operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
SWITCH
DRIVER
CLOCK
PHASE
CONTROL
REF
VOLTAGE
CONTROL
LOGIC
POLARITY CONTROL
(1) Input signal integration
COUNTER
DISPLAY
(2) Reference voltage integration (deintegration)
V
V
Ϸ V
Ϸ
IN
IN
FULL SCALE
1.2 V
The input signal being converted is integrated for a fixed
time period (tSI), measured by counting clock pulses. An
opposite polarity constant reference voltage is then inte-
grateduntiltheintegratoroutputvoltagereturnstozero. The
referenceintegrationtimeisdirectlyproportionaltotheinput
signal (tRI).
Inasimpledual-slopeconverter,acompleteconversion
requires the integrator output to "ramp-up" and "ramp-
down."
FULL SCALE
FIXED VARIABLE
SIGNAL REFERENCE
INTEGRATE INTEGRATE
TIME TIME
Figure 1. Basic Dual-Slope Converter
where:
VR = Reference voltage
tSI = Signal integration time (fixed)
tRI = Reference voltage integration time (variable).
Asimplemathematicalequationrelatestheinputsignal,
reference voltage, and integration time:
For a constant VIN:
tRI
tSI
1
VR tRI
RC
VIN(t) dt =
,
∫
VIN = VR
.
0
t
SI
RC
]
[
TELCOM SEMICONDUCTOR, INC.
3-251
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7136
TC7136A
30
20
10
Auto-Zero Phase
During the auto-zero phase, the differential input signal
is disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero input condition. Additional
analog gates close a feedback loop around the integrator
and comparator. This loop permits comparator offset volt-
age error compensation. The voltage level established on
CAZ compensates for device offset voltages. The auto-zero
phase residual is typically 10 µV to 15 µV.
t = MEASUREMENT PERIOD
1/t
0
0.1/t
10/t
The auto-zero duration is from 910 to 2900 counts for
non-overrange conversions and from 300 to 910 counts for
overrange conversions.
INPUT FREQUENCY
Figure 2. Normal-Mode Rejection of Dual-Slope Converter
The dual-slope converter accuracy is unrelated to the
integratingresistorandcapacitorvalues, aslongastheyare
stable during a measurement cycle. Noise immunity is an
inherent benefit. Noise spikes are integrated, or averaged,
to zero during integration periods. Integrating ADCs are
immune to the large conversion errors that plague succes-
sive approximation converters in high-noise environments.
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set to a
multiple of the 50 Hz/60 Hz power line period.
Signal Integration Phase
The auto-zero loop is entered and the internal differen-
tialinputsconnecttoVI+N andV– . Thedifferentialinputsignal
IN
is integrated for a fixed time period. The TC7136/A signal
integration period is 1000 clock periods or counts. The
externally-set clock frequency is divided by four before
clockingtheinternalcounters.Theintegrationtimeperiodis:
4
tSI
=
ϫ 1000,
fOSC
where fOSC = external clock frequency.
ANALOG SECTION
The differential input voltage must be within the device
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
In addition to the basic integrate and deintegrate dual-
slope cycles discussed above, the TC7136/A designs incor-
porate an "integrator output-zero cycle" and an "auto-zero
cycle." These additional cycles ensure the integrator starts
at0V(evenafterasevereoverrangeconversion)andthatall
offset voltage errors (buffer amplifier, integrator and com-
parator)areremovedfromtheconversion.Atruedigitalzero
reading is assured without any external adjustments.
A complete conversion consists of four distinct phases:
power supply common, V– should be tied to analog com-
IN
mon.
Polarity is determined at the end of signal integrate
phase. Thesignbitisatruepolarityindication, inthatsignals
less than 1 LSB are correctly determined. This allows
precision null detection limited only by device noise and
auto-zero residual offsets.
(1) Integrator output-zero phase
(2) Auto-zero phase
(3) Signal integrate phase
(4) Reference deintegrate phase
Reference Integrate Phase
Thethirdphaseisreferenceintegrateordeintegrate.VI–N
is internally connected to analog common and VI+N is con-
nected across the previously-charged reference capacitor.
Circuitry within the chip ensures that the capacitor will be
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
return to zero is proportional to the input signal and is
between 0 and 2000 internal clock periods. The digital
reading displayed is:
Integrator Output-Zero Phase
This phase guarantees the integrator output is at 0V
before the system-zero phase is entered. This ensures that
true system offset voltages will be compensated for even
after an overrange conversion. The count for this phase is a
function of the number of counts required by the deintegrate
phase.
Thecountlastsfrom11to140countsfornon-overrange
conversions and from 31 to 640 counts for overrange
conversions.
VIN
1000
VREF
3-252
TELCOM SEMICONDUCTOR, INC.
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
3
TC7136
TC7136A
Figure 3. TC7136A Block Diagram
TELCOM SEMICONDUCTOR, INC.
3-253
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7136
TC7136A
System Timing
1000
The oscillator frequency is divided by 4 prior to clocking
the internal decade counters. The four-phase measure-
ment cycle takes a total of 4000 counts, or 16,000 clock
INT
1–2000
DENT
DISPLAY FONT
11–140
ZI
AZ
910–2900
1000's
100's
10's
1's
4000
Figure 4. Conversion Timing During Normal Operation
Figure 6. Display FONT and Segment Assignment
1000
pulses. The 4000-count cycle is independent of input signal
INT
magnitude.
2001–2090
Each phase of the measurement cycle has the following
length:
DEINT
31–640
(1) Auto-zero phase: 3000 to 2900 counts
(1200 to 11,600 clock pulses)
ZI
AZ
300–910
(2) Signal integrate: 1000 counts
(4000 clock pulses)
4000
This time period is fixed. The integration period is:
1
Figure 5. Conversion Timing During Overrange Operation
tSI = 4000
,
fOSC
DIGITAL SECTION
where fOSC is the externally-set clock frequency.
The TC7136/A contains all the segment drivers neces-
sary to directly drive a 3-1/2 digit LCD. An LCD backplane
driver is included. The backplane frequency is the external
clock frequency divided by 800. For three conversions per
second the backplane frequency is 60 Hz with a 5V nominal
amplitude. When a segment driver is in-phase with the
backplane signal, the segment is OFF. An out-of-phase
segment drive signal causes the segment to be ON, or
visible. This AC drive configuration results in negligible DC
voltage across each LCD segment, ensuring long LCD life.
ThepolaritysegmentdriverisONfornegativeanaloginputs.
If VI+N and VI–N are reversed, this indicator would reverse.
On the TC7136/A, when the TEST pin is pulled to V+, all
segments are turned ON. The display reads –1888. During
this mode the LCD segments have a constant DC voltage
impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE
FOR MORE THAN SEVERAL MINUTES. LCDS MAY BE
DESTROYED IF OPERATED WITH DC LEVELS FOR
EXTENDED PERIODS.
(3) Reference integrate: 0 to 2000 counts
(4) Zero integrator: 11 to 640 counts
The TC7136 is a drop-in replacement for the TC7126
and ICL7126. The TC7136A offers a greatly-improved inter-
nal reference temperature coefficient. Minor component
value changes are required to upgrade existing designs and
improve the noise performance.
COMPONENT VALUE SELECTION
Auto-Zero Capacitor (CAZ)
The CAZ capacitor size has some influence on system
noise. A 0.47 µF capacitor is recommended for 200 mV full-
scaleapplicationswhere1LSBis100µV.A0.1µFcapacitor
is adequate for 2V full-scale applications. A Mylar-type
dielectric capacitor is adequate.
Reference Voltage Capacitor (CREF
)
The display font and segment drive assignment are
shown in Figure 6.
The reference voltage, used to ramp the integrator
3-254
TELCOM SEMICONDUCTOR, INC.
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
3
TC7136
TC7136A
output voltage back to zero during the reference integrate
phase, is stored on CREF. A 0.1 µF capacitor is acceptable
when VR–EF is tied to analog common. If a large common-
mode voltage exists (VR–EF ≠ analog common) and the
application requires a 200 mV full scale, increase CREF to
1 µF. Roll-over error will be held to less than 0.5 count. A
Mylar-type dielectric capacitor is adequate.
Oscillator Components
COSC should be 50 pF. ROSC is selected from the
equation:
0.45
RC
fOSC
=
.
Note that fOSC is Ϭ4 to generate the TC7136A's internal
clock. The backplane drive signal is derived by dividing fOSC
by 800.
To achieve maximum rejection of 60Hz noise pickup,
the signal integrate period should be a multiple of 60Hz.
Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,
40kHz, etc. should be selected. For 50 Hz rejection, oscil-
lator frequencies of 200kHz, 100kHz, 66-2/3 kHz, 50kHz,
40kHz, etc. would be suitable. Note that 40kHz (2.5 read-
ings per second) will reject both 50Hz and 60Hz.
Integrating Capacitor (CINT
)
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Analog
common will normally supply the differential voltage refer-
ence this case, a ±2V full-scale integrator output swing is
satisfactory. For 3 readings per second (fOSC = 48 kHz) a
0.047 µF value is suggested. For one reading per second,
0.15 µF is recommended. If a different oscillator frequency
is used, CINT must be changed in inverse proportion to
maintain the nominal ±2V integrator swing.
Reference Voltage Selection
An exact expression for CINT is:
A full-scale reading (2000 counts) requires the input
signal be twice the reference voltage.
1
VFS
(4000)
(f )(R
)
OSC
INT
CINT
=
,
Required Full-Scale Voltage*
VREF
VINT
200 mV
2V
100 mV
1V
where: fOSC = Clock frequency at pin 38
VFS = Full-scale input voltage
RINT = Integrating resistor
*VFS = 2 VREF
.
Insomeapplications, ascalefactorotherthanunitymay
exist between a transducer output voltage and the required
digitalreading. Assume, forexample, apressuretransducer
output for 2000 lb/in.2 is 400 mV. Rather than dividing the
input voltage by two, the reference voltage should be set to
200 mV. This permits the transducer input to be used
directly.
VINT = Desired full-scale integrator output swing.
CINT must have low dielectric absorption to minimize
roll-over error. A polypropylene capacitor is recommended.
Integrating Resistor (RINT
)
The input buffer amplifier and integrator are designed
with Class A output stages. The output stage idling current
is 6 µA. The integrator and buffer can supply 1 µA drive
currents with negligible linearity errors. RINT is chosen to
remain in the output stage linear drive region, but not so
large that PC board leakage currents induce errors. For a
200 mV full scale, RINT is 180 kΩ. A 2V full scale requires
1.8 MΩ.
The differential reference can also be used when a
digital zero reading is required when VIN is not equal to zero.
This is common in temperature measuring instrumentation.
A compensating offset voltage can be applied between
analogcommonandV– Thetransduceroutputisconnected
IN
between V+IN and analog common.
DEVICE PIN FUNCTIONAL DESCRIPTION
Differential Signal Inputs
Component
VI+N (Pin 31), V– (Pin 30)
IN
Value
Nominal Full-Scale Voltage
The TC7136/A is designed with true differential inputs
and accepts input signals within the input stage common-
mode voltage range (VCM). The typical range is V+ –1V to V–
+1V.Common-modevoltagesareremovedfromthesystem
whentheTC7136Aoperatesfromabatteryorfloatingpower
source (isolated from measured system), and VI–N is con-
nected to analog common (VCOM). (See Figure 7.)
200mV
2V
CAZ
RINT
CINT
0.47 µF
180 kΩ
0.1 µF
1.8 MΩ
0.047 µF
0.047 µF
NOTE:fOSC = 48 kHz (3 readings per sec). ROSC = 180kΩ, COSC = 50
TELCOM SEMICONDUCTOR, INC.
3-255
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7136
TC7136A
SEGMENT
DRIVE
LCD
MEASURED
SYSTEM
V
+
C
V
INT
POL BP
BUF
AZ
OSC
1
V
+
V
–
OSC
OSC
TC7136
TC7136A
3
2
V
–
V
GND
ANALOG
COMMON REF REF
–
+
+
–
V
V
V
V
+
–
V
V
GND
POWER
SOURCE
+
9V
Figure 7. Common-Mode Voltage Removed in Battery Operation With VIN = Analog Common
In systems where common-mode voltages exist, the
The TC7136/A offers a significantly improved analog
common temperature coefficient. This potential provides a
very stable voltage, suitable for use as a voltage reference.
The temperature coefficient of analog common is typically
35 ppm/°C.
86 dB common-mode rejection ratio minimizes error. Com-
mon-mode voltages do, however, affect the integrator out-
put level. A worst-case condition exists if a large positive
VCM exists in conjunction with a full-scale negative differ-
ential signal. The negative signal drives the integrator
output positive along with VCM (see Figure 8.) For such
applications, the integrator output swing can be reduced
below the recommended 2V full-scale swing. The integra-
tor output will swing within 0.3V of V+ or V– without in-
creased linearity error.
ANALOG COMMON (Pin 32)
The analog common pin is set at a voltage potential
approximately 3V below V+. The potential is guaranteed to
be between 2.7V and 3.35V below V+. Analog common is
tied internally to an N-channel FET capable of sinking
100µA. This FET will hold the common line at 3V below V+
if an external load attempts to pull the common line toward
V+.Analogcommonsourcecurrentislimitedto1 µA.Analog
common is therefore easily pulled to a more negative
voltage (i.e., below V+ – 3V).
Differential Reference
VR+EF (Pin 36), VR–EF (Pin 35)
The reference voltage can be generated anywhere
within the V+ to V– power supply range.
To prevent roll-over type errors being induced by large
common-mode voltages, CREF should be large compared to
stray node capacitance.
The TC7136/A connects the internal VIN+ and VI–N in-
puts to analog common during the auto-zero phase. During
the reference-integrate phase, VI–N is connected to analog
common. If VI–N is not externally connected to analog com-
mon, a common-mode voltage exists, but is rejected by the
converter's 86 dB common-mode rejection ratio. In battery
operation, analog common and VI–N are usually connected,
removingcommon-modevoltageconcerns.Insystemswhere
VI–N is connected to the power supply ground or to a given
C
INPUT
BUFFER
I
R
+
V
–
+
–
I
–
+
V
I
IN
voltage, analog common should be connected to V–
IN
INTEGRATOR
The analog common pin serves to set the analog sec-
tion reference, or common point. The TC7136A is specifi-
cally designed to operate from a battery or in any measure-
ment system where input signals are not referenced (float)
with respect to the TC7136A power source. The analog
common potential of V+ –3V gives a 7V end of battery life
voltage. The common potential has a 0.001%/% voltage
coefficient.
T
I
C
V
=
V
V
IN
–
I
I
[
CM
[
R
V
I
I
CM
Where:
4000
T
Integration time
=
=
=
f
OSC
C
R
Integration capacitor
= Integration resistor
I
I
With sufficiently high total supply voltage (V+–V– >7V),
Figure 8. Common-Mode Voltage Reduces Available Integrator
Swing (VCOM ≠ VIN)
3-256
TELCOM SEMICONDUCTOR, INC.
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
3
TC7136
TC7136A
analog common is a very stable potential with excellent
temperature stability (typically 35 ppm/°c). for TC7136A
This potential can be used to generate the TC7136A's
reference voltage. An external voltage reference will be
unnecessary in most cases because of the 35 ppm/°C
temperature coefficient. See TC7136A Internal Voltage
Reference discussion.
9V
+
26
1
+
–
240 kΩ
V
V
TC7136
TC7136A
TEST (Pin 37)
36
+
V
10 kΩ
The TEST pin potential is 5V less than V+. TEST may be
used as the negative power supply connection for external
CMOSlogic.TheTESTpinistiedtotheinternally-generated
negativelogicsupplythrougha500Ωresistor.TheTESTpin
load should not be more than 1 mA. See the Applications
Section for additional information on using TEST as a
negative digital logic supply.
REF
V
REF
–
35
V
REF
32
ANALOG
COMMON
SET V
= 1/2 V
REF
FULL SCALE
If TEST is pulled high (to V+), all segments plus the
minus sign will be activated. DO NOT OPERATE IN THIS
MODEFORMORETHANSEVERALMINUTES.WithTEST
= V+, the LCD segments are impressed with a DC voltage
which will destroy the LCD.
Figure 10. TC7136A Internal Voltage Reference Connection
APPLICATIONS INFORMATION
Liquid Crystal Display Sources
Several manufacturers supply standard LCDs to inter-
face with the TC7136A 3-1/2 digit analog-to-digital con-
verter.
TC7136A Internal Voltage Reference
The TC7136 analog common voltage temperature sta-
bility has been significantly improved (Figure 9). The "A"
version of the industry-standard TC7136 device allows
users to upgrade old systems and design new systems
without external voltage references. External R and C val-
ues do not need to be changed; however, noise perfor-
mance will be improved by increasing CAZ. (See Auto-Zero
Capacitor section.) Figure 10 shows analog common sup-
plying the necessary voltage reference for the TC7136/A.
Representative
Manufacturer Address/Phone
Part Numbers*
Crystaloid
Electronics
5282 Hudson Dr.
Hudson, OH 44236
216-655-2429
C5335, H5535,
T5135, SX440
AND
720 Palomar Ave.
FE 0201, 0501
Sunnyvale, CA 94086 FE 0203, 0701
408-523-8200 FE 2201
200
VGI, Inc.
Hamlin, Inc.
1800 Vernon St. Ste. 2 I1048, I1126
Roseville, CA 95678
180
916-783-7878
GUARANTEED
MAXIMUM
NO MAXIMUM
SPECIFIED
160
140
120
100
612 E. Lake St.
Lake Mills, WI 53551
414-648-2361
3902, 3933, 3903
TYPICAL
*NOTE: Contact LCD manufacturer for full product listing/specifications.
GUARANTEED
MAXIMUM
Decimal Point and Annunciator Drive
80
60
40
20
TYPICAL
TC7136
The TEST pin is connected to the internally-generated
digital logic supply ground through a 500Ω resistor. The
TEST pin may be used as the negative supply for external
CMOS gate segment drivers. LCD annunciators for decimal
points, low battery indication, or function indication may be
added without adding an additional supply. No more than 1
mA should be supplied by the TEST pin: its potential is
approximately 5V below V+.
TYPICAL
TC7136A
ICL7136
0
Figure 9. Analog Common Temperature Coefficient
TELCOM SEMICONDUCTOR, INC.
3-257
LOW POWER, 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7136
TC7136A
Ratiometric Resistance Measurements
+
+
The TC7136A's true differential input and differential
reference make ratiometric readings possible. In ratiometric
operation, an unknown resistance is measured with respect
to a known standard resistance. No accurately-defined
reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current passed through the pair. The voltage
developed across the unknown is applied to the input and
the voltage across the known resistor applied to the refer-
ence input. If the unknown equals the standard, the display
will read 1000. The displayed reading can be determined
from the following expression:
V
V
REF
–
V
R
REF
STANDARD
LCD
+
V
IN
R
UNKNOWN
TC7136
TC7136A
–
V
IN
ANALOG
COMMON
Figure 12. Low Parts Count Ratiometric Resistance
Measurement
RUNKNOWN
Displayed reading =
× 1000.
RSTANDARD
The display will overrange for RUNKNOWN
2×RSTANDARD
+
9V
≥
.
160 kΩ
300 kΩ
300 kΩ
+
–
V
–
V
V
V
IN
Simple Inverter for Fixed Decimal Point
or Display Annunciator
+
R
1N4148
SENSOR
1
IN
TC7136
TC7136A
50 kΩ
+
V
+
V
+
R
2
V
V
REF
50 kΩ
4049
–
REF
TC7136
TC7136A
TO LCD
DECIMAL
POINT
21
COMMON
BP
GND
37
TEST
Figure 13. Temperature Sensor
TO LCD
BLACK
PLANE
9V
+
Multiple Decimal Point or
Annunciator Driver
5.6 kΩ
160 kΩ
+
+
–
V
V
–
V
+
R
V
V
V
1N4148
1
BP
IN
20 kΩ
+
TC7136
TC7136A
IN
TO LCD
DECIMAL
POINTS
DECIMAL
POINT
SELECT
0.7%/°C
PTC
R
2
20 kΩ
+
R
V
V
3
TC7136
TC7136A
REF
–
REF
4030
TEST
COMMON
GND
Figure 14. Positive Temperature Coefficient Resistor
Temperature Sensor
Figure 11. Decimal Point and Annunciator Drives
3-258
TELCOM SEMICONDUCTOR, INC.
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