C4K-L67142L-55_技术文档

L67132/L67142

2 K × 8 CMOS Dual Port RAM 3.3 Volt

Introduction

The L67132/67142 are very low power CMOS dual port Using an array of eight transistors (8T) memory cell and

static RAMs organized as 2048 × 8. They are designed to fabricated with the state of the art 1.0 µm lithography

be used as a stand-alone 8 bit dual port RAM or as a named SCMOS, the L67132/67142 combine an

combination MASTER/SLAVE dual port for 16 bits or extremely low standby supply current (typ = 1.0 µA) with

more width systems. The MHS MASTER/SLAVE dual a fast access time at 45 ns over the full temperature range.

port approach in memory system applications results in All versions offer battery backup data retention capability

full speed, error free operation without the need for with a typical power consumption at less than 5 µW.

additional discrete logic.

For military/space applications that demand superior

Master and slave devices provide two independent ports

with separate control, address and I/O pins that permit

independent, asynchronous access for reads and writes to

any location in the memory. An automatic power down

feature controlled by CS permits the onchip circuitry of

each port in order to enter a very low stand by power

mode.

levels of performance and reliability the L67132/67142

is processed according to the methods of the latest

revision of the MIL STD 883 (class B or S) and/or ESA

SCC 9000.

Features

D Single 3.3 V ± 0.3 volt power supply

D Fast access time

D On chip arbitration logic

D BUSY output flag on master

D BUSY input flag on slave

D Fully asynchronous operation from either port

D Battery backup operation :

2 V data retention

45(*) ns to 70 ns

D 67132L/67142L low power

67132V/67142V very low power

D Expandable data bus to 16 bits or more using master/slave

devices when using more than one device

(*) Preliminary

MATRA MHS

1

Rev. D (19 Fev. 97)

L67132/L67142

Interface

Pin Configuration

52 PIN PLCC (top view)

48 PIN LCC (top view)

48 PIN DIL (top view), plastic,

ceramic 600 mils

64 PIN VQFP

(top view)

Block Diagram

A

10L

A

10R

Note :

1. L 67132 (MASTER) : BUSY is open drain output and requires pullup resistor

L 67142 (SLAVE) : BUSY in input

2

MATRA MHS

Rev. D (19 Fev. 97)

L67132/L67142

Pin Names

LEFT PORT

RIGHT PORT

NAMES

CS

L

CS

R

Chip select

R/W

Write Enable

Output Enable

Address

L

R

OE

R

L

A

0R – 10R

0L – 10L

I/O

Data Input/Output

Busy Flag

Power

0L – 7L

0R – 7R

BUSY

R

L

VCC

GND

Ground

Functional Description

The L67132/67142 has two ports with separate control, access (refer to table 2). The inhibited port’s BUSY flag

address and I/0 pins that permit independent read/write is set and will reset when the port granted access

access to any memory location. These devices have an completes its operation in both arbitration modes.

automatic power-down feature controlled by CS. CS

controls on-chip power-down circuitry which causes the

port concerned to go into stand-by mode when not

Data Bus Width Expansion

selected (CS high). When a port is selected access to the

full memory array is permitted. Each port has its own

Master/Slave Description

Output Enable control (OE). In read mode, the port’s OE

turns the Output drivers on when set LOW.

Non-conflicting READ/WRITE conditions are illustrated in

table 1.

Expanding the data bus width to 16 or more bits in a

dual-port RAM system means that several chips may be

active simultaneously. If every chip has a hardware

arbitrator, and the addresses for each chip arrive at the

same time one chip may activate its L BUSY signal while

another activates its R BUSY signal. Both sides are now

busy and the CPUs will wait indefinitely for their port to

become free.

Arbitration Logic

The arbitration logic will resolve an address match or a

chip select match down to a minimum of 5 ns and

determine which port has access. In all cases, an active

BUSY flag will be set for the inhibited port.

To overcome this “Busy Lock-Out” problem, MHS has

developed a MASTER/SLAVE system which uses a

single hardware arbitrator located on the MASTER. The

SLAVE has BUSY inputs which allow direct interface to

the MASTER with no external components, giving a

speed advantage over other systems.

The BUSY flags are required when both ports attempt to

access the same location simultaneously.Should this

conflict arise, on-chip arbitration logic will determine

which port has access and set the BUSY flag for the

inhibited port. BUSY is set at speeds that allow the

processor to hold the operation with its associated address

and data. It should be noted that the operation is invalid

for the port for which BUSY is set LOW. The inhibited

port will be given access when BUSY goes inactive.

When dual-port RAMs are expanded in width, the

SLAVE RAMs must be prevented from writing until the

BUSY input has been settled. Otherwise, the SLAVE chip

may begin a write cycle during a conflict situation. On the

opposite, the write pulse must extend a hold time beyond

BUSY to ensure that a write cycle occurs once the conflict

is resolved. This timing is inherent in all dual-port

memory systems where more than one chip is active at the

same time.

A conflict will occur when both left and right ports are

active and the two addresses coincide. The on-chip

arbitration determines access in these circumstances.

Two modes of arbitration are provided : (1) if the

addresses match and are valid before CS on-chip control The write pulse to the SLAVE must be inhibited by the

logic arbitrates between CS and CS for access ; or (2) MASTER’s maximum arbitration time. If a conflict then

L

R

if the CS are low before an address match, on-chip control occurs, the write to the SLAVE will be inhibited because

logic arbitrates between the left and right addresses for of the MASTER’s BUSY signal.

MATRA MHS

3

Rev. D (19 Fev. 97)

L67132/L67142

Truth Table

(4)

Table 1 : Non Contention Read/Write Control

LEFT OR RIGHT PORT⁽¹⁾

FUNCTION

R/W

X

CS

H

OE

X

D0–7

Z

Port Disabled and in Power Down Mode. ICCSB or ICCSB1

(2)

L

X

DATA

Data on Port Written into memory

IN

(3)

H

L

DATA

Z

Data in Memory Output on Port

OUT

H

L

H

High Impedance Outputs

Notes : 1. A – A

≠ A – A

.

OL

10L

0R

10R

2. If BUSY = L, data is not written.

3. If BUSY = L, data may not be valid, see t

and t

DDD

timing.

WDD

4. H = HIGH, L = LOW, X = DON’T CARE, Z = HIGH IMPEDANCE.

(5)

Table 2 : Arbitration

LEFT PORT

RIGHT PORT

FLAGS

BUSY_L

FUNCTION

CS_L

H

A_0L– A_10L

CS_R

A_0L– A_10R

BUSY_R

X

Any

X

H

L

X

H

No Contention

L

No Contention

H

Any

L

≠ A – A

0L 10L

0R

10R

ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH

L

LV5R

RV5L

Same

L

LV5R

RV5L

Same

H

L

H

L

H

L

L–Port Wins

R–Port Wins

Arbitration Resolved

H

CS ARBITRATION WITH ADDRESS MATCH BEFORE CS

LL5R

RL5L

LW5R

= A – A

LL5R

RL5L

LW5R

= A – A

10L

H

L

H

L

H

L

L–Port Wins

0R

10R

0L

= A – A

= A

A

R–Port Wins

0R

0L – 10L

= A

A

= A – A

Arbitration Resolved

0R – 10R

0L

10L

= A – A

H

0R

10R

0L

10L

Notes : 5. X = DON’T CARE, L = LOW, H = HIGH.

LV5R = Left Address Valid ≥ 5 ns before right address.

RV5L = Right address Valid ≥ 5 ns before left address.

Same = Left and Right Addresses match within 5 ns of each other.

LL5R = Left CS = LOW ≥ 5 ns before Right CS.

RL5L = Right CS = LOW ≥ 5 ns before left CS.

LW5R = Left and Right CS = LOW within 5 ns of each other.

4

MATRA MHS

Rev. D (19 Fev. 97)

L67132/L67142

Electrical Characteristics

* Notice

Absolute Maximum Ratings

Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device.This is a stress

rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating

conditions for extented periods may affect reliability.

Supply voltage (VCC–GND) : . . . . . . . . . . . . . . . . . . –0.3 V to 7.0 V

Input or output voltage applied : . . . (GND –0.3 V) to (VCC + 0.3 V)

Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C

OPERATING RANGE

Military

OPERATING SUPPLY VOLTAGE

OPERATING TEMPERATURE

o

V

= 3.3 V ± 0.3 V

– 55 C to + 125 C

CC

o

Automotive

– 40 C to + 125 C

o

Commercial

0 C to + 70 C

o

Industrial

– 40 C to + 85 C

DC Parameters

L67132/67142–4 L67132/67142–5 L67132/67142–7

5

0

IND

MIL

AUTO

Versio

n

Parameter

Description

Unit

Value

IND

MIL

AUTO

IND

MIL

AUTO

COM

PRELIMINARY

I

Standby supply current

(Both ports TTL level inputs)

V

L

1

5

1

10

1

5

1

10

1

5

1

10

mA

Max

CCSB (6)

CCSB1 (7)

CCOP (8)

CCOP1 (9)

Standby supply current

(Both ports CMOS level inputs)

V

L

10

100

20

200

10

100

20

200

10

100

20

200

µA

Max

Operating supply current

(Both ports active)

V

L

80

90

100

70

80

90

60

70

80

mA

Max

Operating supply current

(One port active – One port standby)

V

L

50

60

55

65

40

50

45

55

35

45

40

50

mA

Max

Notes : 6. CS = CS ≥ 2.2 V.

L

R

7. CS = CS ≥ VCC – 0.2 V.

L

R

8. Both ports active – Maximum frequency – Outputs open – OE = VIH.

9. One port active (f = MAX) – Output open – One port stand-by TTL or CMOS Level inputs – CS = CS ≥ 2.2 V.

L

R

L67132–45/55/70

L67142–45/55/70

PARAMETER

DESCRIPTION

UNIT

VALUE

II/O

VIL

Input/Output leakage current

Input low voltage

± 10

0.7

1.8

0.5

1.5

5

µA

V

Max

Min

Max

Min

Max

(10)

(11)

VIH

Input high voltage

V

(11)

VOL

Output low voltage (I/O –I/O )

V

(12)

(13)

0

7

Open drain output low voltage (BUSY)

Output high voltage

V

VOH

V

(12)

(17)

C IN

Input capacitance

pF

C OUT

Output capacitance

7

(17)

Notes : 10. V = 5 V, Vin = Gnd to V , CS = VIH, Vout = 0 to V .

CC

11. VIH max = V + 0.3 V, VIL min – 0.3 V or –1 V pulse width 50 ns.

CC

12. V min, IOL = 4 mA, IOH = –4 mA.

CC

13. I = 16 mA.

OL

MATRA MHS

Rev. D (19 Fev. 97)

5

L67132/L67142

Data-Retention Mode

MHS CMOS RAMs are designed with battery backup in 2 – CS must be kept between V – 0.2 V and 70 % of Vcc

CC

mind. Data retention voltage and supply current are during the power up and power down transitions.

guaranteed over temperature. The following rules insure

data retention :

3 – The RAM can begin operation > tRC after Vcc

reaches the minimum operating voltage (3 volts).

1 – Chip select (CS) must be held high during data

retention ; within Vcc to VCC

.

DR

Timing

MAX

MIL

IND

PARAMETER

TEST CONDITIONS (14)

UNIT

COM

AUTO

ICC

@ VCC = 2 V

10

20

µA

DR1

DR

Notes : 14. CS = Vcc, Vin = Gnd to Vcc.

AC Test Conditions

Input Pulse Levels : GND to 3.0 V

Input Rise/Fall Times : 5 ns

Output Reference Levels : 1.5 V

Output Load : see figures 1, 2

Input Timing Reference Levels : 1.5 V

Figure 1. Output Load.

Figure 2. Output load.

(For t , t , t , and t

)

HZ LZ WZ

OW

6

MATRA MHS

Rev. D (19 Fev. 97)

L67132/L67142

AC Parameters

L67132–45

L67142–45

L67132–55

L67142–55

L67132–70

L67142–70

READ CYCLE

PARAMETER

UNIT

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SYMBOL SYMBOL

(19)

(20)

PRELIMINARY

TAVAVR

TAVQV

TELQV

TGLQV

TAVQX

TELQZ

TEHQZ

TPU

t

Read cycle time

45

–

45

30

–

55

–

70

–

ns

RC

Address access time

–

0

5

–

0

–

55

35

–

0

5

–

0

–

70

40

–

AA

ACS

AOE

OH

LZ

Chip Select access time (18)

Output enable access time

–

Output hold from address change

Output low Z time (16, 17)

Output high Z time (16, 17)

Chip Select to power up time (17)

Chip disable to power down time (17)

0

5

–

20

–

30

–

35

–

HZ

0

PU

TPD

–

50

PD

Notes : 16. Transition is measured ± 500 mV from low or high impedance voltage with load (figures 1 and 2).

17. This parameter is guaranteed but not tested.

18. To access RAM CS = VIL.

19. STD symbol.

20. ALT symbol.

Timing Waveform of Read Cycle n^o1, Either Side ^{(21, 22, 24)}

Timing Waveform of Read Cycle n^o2, Either Side ^{(21, 23, 25)}

Notes : 21. R/W is high for read cycles.

22. Device is continuously enabled, CS = VIL.

23. Addresses valid prior to or coincident with CS transition low.

24. OE = V

.

IL

25. To access RAM, CS = V

.

IL

MATRA MHS

Rev. D (19 Fev. 97)

7

L67132/L67142

AC Parameters

L67132–45

L67142–45

L67132–55

L67142–55

L67132–70

L67142–70

WRITE CYCLE

PARAMETER

UNIT

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SYMBOL SYMBOL

(30)

(31)

PRELIMINARY

TAVAVW

TELWH

TAVWH

TAVWL

TWLWH

TWHAX

TDVWH

TGHQZ

TWHDX

TWLQZ

TWHQX

t

Write cycle time

45

35

0

–

55

40

0

–

70

45

0

–

ns

WC

t

Chip select to end of write (28)

Address valid to end of write

Address Set–up Time

SW

AW

t

–

t

–

AS

WP

WR

DW

t

Write Pulse Width

35

0

–

40

0

–

45

0

–

t

Write Recovery Time

–

t

Data Valid to end of write

Output high Z time (26, 27)

Data hold time (29)

25

–

25

–

30

–

t

20

–

30

–

40

–

HZ

DH

WZ

OW

t

0

t

Write enable to output in high Z (26, 27)

Output active from end of write (26, 27, 29)

–

20

–

30

–

40

–

t

0

Notes : 26. Transition is measured ± 500 mV from low or high impedance voltage with load (figures 1 and 2).

27. This parameter is guaranteed but not tested.

28. To access RAM CS = VIL.

This condition must be valid for entire t time.

SW

29. The specification for t must be met by the device supplying write data to the RAM under all operating conditions.

DH

Although t and t

values vary over voltage and temperature, the actual t will always be smaller than the actual t

.

DH

OW

DH

OW

30. STD symbol.

31. ALT symbol.

8

MATRA MHS

Rev. D (19 Fev. 97)

L67132/L67142

Timing Waveform of Write Cycle n^o1, R/W Controlled Timing ^{(32, 33, 34, 38)}

Timing Waveform of Write Cycle n^o2, CS Controlled Timing ^{(32, 33, 34, 36)}

Notes : 32. R/W must be high during all address transitions.

33. A write occurs during the overlap (t or t ) of a low CS and a low R/W.

SW

WP

34.

t

is measured from the earlier of CS or R/W going high to the end of write cycle.

WR

35. During this period, the I/O pins are in the output state, and input signals must not be applied.

36. If the CS low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high

impedance state.

37. Transition is measured ± 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled

and not 100 % tested.

38. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of t or (t

+ t

DW

)

WP

WZ

to allow the I/O drivers to turn off and data to be placed on the bus for the required t . If OE is high during an R/W

DW

controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t

39. To access RAM, CS = VIL.

.

WP

MATRA MHS

Rev. D (19 Fev. 97)

9

L67132/L67142

AC Parameters

L67132–45

L67142–45

L67132–55

L67142–55

L67132–70

L67142–70

SYMBOL

PARAMETER

UNIT

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

BUSY TIMING (For L 67132 only)

t

BUSY Access time to address

BUSY Disable time to address

BUSY Access time to Chip Select

BUSY Disable time to Chip Select

Write Pulse to data delay (40)

Write data valid to read data delay (40)

Arbitration priority set–up time (41)

BUSY disable to valid data

–

35

–

45

–

50

ns

BAA

BDA

–

5

–

35

30

–

5

–

40

35

–

5

–

40

50

t

BAC

BDC

t

25

30

40

t

70

80

90

WDD

t

45

55

70

DDD

t

–

APS

t

Note 42

BDD

BUSY TIMING (For L 67142 only)

t

Write to BUSY input (43)

0

20

–

0

30

–

0

30

–

ns

WB

WH

t

Write hold after BUSY (44)

Write pulse to data delay (45)

Write data valid to read data delay (45)

t

70

45

80

55

90

70

WDD

t

–

DDD

Notes : 40. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with

BUSY (For L67132 only)”.

41. To ensure that the earlier of the two ports wins.

42.

t

is a calculated parameter and is the greater of 0, t

– t (actual) or t

WP

– t

DW

(actual).

BDD

WDD

DDD

43. To ensure that the write cycle is inhibited during contention.

44. To ensure that a write cycle is completed after contention.

45. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read

with Port to port delay (For L67142 only)”.

10

MATRA MHS

Rev. D (19 Fev. 97)

L67132/L67142

Timing Waveform of Read with BUSY ^{(46, 47, 48)}(For L 67132)

Notes : 46. To ensure that the earlier of the two port wins.

47. Write cycle parameters should be adhered to, to ensure proper writing.

48. Device is continuously enabled for both ports.

49. OE at L for the reading port.

Timing Waveform of Write with Port-to-port ^{(50, 51, 52)}(For L 67142 only)

Notes : 50. Assume BUSY = H for the writing port, and OE = L for the reading port.

51. Write cycle parameters should be adhered to, to ensure proper writing.

52. Device is continuously enabled for both ports.

MATRA MHS

11

Rev. D (19 Fev. 97)

L67132/L67142

Timing Waveform of Write with BUSY (For L 67132)

Timing Waveform of Contention Cycle n^o1, CS Arbitration (For L 67132 only)

12

MATRA MHS

Rev. D (19 Fev. 97)

L67132/L67142

Timing Waveform of Contention Cycle n^o2, Address Valid Abritration

(For L 67132 only) ⁽⁵³⁾

Left Address Valid First :

Right Address Valid First :

Note :

53. CS = CS = V

L R IL

16 Bit Master/Slave Dual-port Memory Systems

Note :

54. No arbitration in L 67142 (SLAVE). BUSY-IN inhibits write in L 67142 (SLAVE).

MATRA MHS

13

Rev. D (19 Fev. 97)

L67132/L67142

Ordering Information

TEMPERATURE RANGE PACKAGE

DEVICE SPEED

FLOW

C

L

S3

67132V

55

3.3 V ± 0.3 Volt

blank

/883

P883

SB/SC

= MHS standards

45 ns

55 ns

70 ns

= MIL-STD 883 Class B or S

= MIL-STD 883 + PIND TEST

= SCC 9000 level B/C

1K = 48 pin DIL ceramic 600 mils

CK = 48 pin DIL side-brazed 600 mils

4K = 48 pin LCC

S3 = 52 pin PLCC

3K = 48 pin DIL plastic 600 mils

RD = 64 pin VQFP

SHXXX = Special customer

request

FHXXX = Flight models (space)

MHXXX = Mechanical parts

(space)

67132 = 16K (2K × 8) Master

67142 = 16K (2K × 8) Slave

C = Commercial

I = Industrial

A = Automotive

M = Military

S = Space

0° to +70°C

–40° to +85°C

–40° to +125°C

–55° to +125°C

L

V

EL

EV

= Low power

= Very low power

= Low power and rad tolerant

LHXXX = Life test parts (space)

= Very low power and rad tolerant

The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication

and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.

14

MATRA MHS

Rev. D (19 Fev. 97)


型号：	C4K-L67142L-55
厂家：	TEMIC SEMICONDUCTORS
描述：	Dual-Port SRAM, 2KX8, 55ns, CMOS, LCC-48 静态存储器
文件：	总14页 (文件大小：178K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C4K-L67142L-55 [TEMIC]

相关型号：

C4K-L67142L-70

C4K-L67142V-45

C4KH,AL

C4KH,BK

C4KH,GY

C4MADUB4100AA4J

C4MADUB4100AA4K

C4MADUC4500AA0J

C4MADUD5150AA3J

C4MADUD5150AA3K

C4MAFUB3470AA5K

C4MAFUB4100AA0J