HM165790K-2/883 [TEMIC]
Standard SRAM, 16KX4, 35ns, CMOS, CDIP28,;
| 型号： | HM165790K-2/883 |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Standard SRAM, 16KX4, 35ns, CMOS, CDIP28, CD 静态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MATRA MHS
HM 65790
16 K × 4 High Speed CMOS SRAM Separate I/O
Introduction
The HM 65790 is a high speed CMOS static RAM Easy memory expansion is provided by two active low
organized as 16384 × 4 bits. It is manufactured using chip select (CS1, CS2), an active low output enable (OE)
MHS’s high performance CMOS technology.
and three state drivers.
All inputs and outputs of the HM 65790 are TTL
compatible and operate from single 5 V supply thus
simplifying system design.
Access times as fast as 15 ns are available with maximum
power consumption of only 633 mW.
The HM 65790 features fully static operation requiring no
external clocks or timing strobes. The automatic
power-down feature reduces the power consumption by
85 % when the circuit is deselected.
The HM 65790 is 100 % processed following the test
methods of MIL STD 883 and/or ESA/SCC 9000, making
it ideally suitable for military/space applications that
demand superior levels of performance and reliability.
Features
D Fast access time
D 300 mils width package
D TTL compatible inputs and outputs
D Asynchronous
Commercial : 15/20/25/35/45 ns (max)
Military : 20/25/35/45 ns (max)
D Low power consumption
Active : 267 mW (typ)
D Capable of withstanding greater than 2000 V electrostatic
discharge
Standby : 75 mW (typ)
D Single 5 volt supply
D Wide temperature range :
D Separate inputs/outputs
D Output enable
–55°C to + 125°C
Interface
Block Diagram
I
0
I
I
I
1
2
INPUT BUFFER
3
A
A
A
A
A
A
0
O
O
O
O
0
1
2
1
256 × 256
ARRAY
3
4
5
2
3
A
6
POWER
DOWN
COLUMN DECODER
CE
1
CE
2
A
8
A A
9 10
A
A
A
11 12 13
W
OE
Rev. C (20/12/94)
1
HM 65790
MATRA MHS
Pin Configuration
Plastic 300 mils, 28 pins, DIL
Ceramic 300 mils, 28 pins, DIL
SOIC 300 mils, 28 pins
A5
A6
A7
A8
A9
A10
A11
A12
A13
IO
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
17
17
16
15
VCC
A4
A3
A2
A1
A0
I3
I2
9
O3
O2
O1
O0
W
10
11
12
13
14
I1
CS1
OE
GND
CS2
Pinout DIL 28 pins (top view)
Logic Symbol
Pin Names
VCC
A0–A13: Address inputs
CS1–CS2 : Chip Select
CS1
CS2
OE
W
I0–I3
: Inputs
: Outputs
: Power
OE
: Output enable
: Write enable
: Ground
O0–O3
VCC
W
I0
I1
I2
I3
GND
A0
A1
A2
A3
A4
A5
A6
Truth Table
A7
A8
A9
A10
A11
A12
A13
O0
O1
O2
O3
CS OE
W
X
DATA–IN DATA–OUT
MODE
Deselect
Read
H
L
L
X
L
Z
Z
Z
Valid
Z
H
X
L
Valid
Write
GND
L = Low – H = High, X = H or L, Z = High impedance.
2
Rev. C (20/12/94)
MATRA MHS
HM 65790
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . . –0.5 V to +7.0 V
DC input voltage : . . . . . . . . . . . . . . . . . . . . . . . . . . . –3.0 V to +7.0 V
DC output voltage in high Z state : . . . . . . . . . . . . . . –0.5 V to +7.0 V
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Output current into outputs (low) : . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Electro Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . > 2001 V
(MIL STD 883C METHOD 3015-2)
Operating Range
OPERATING VOLTAGE
OPERATING TEMPERATURE
– 55_C to + 125_C
Military
(– 2)
(– 5)
5 V ± 10 %
5 V ± 10 %
Commercial
0_C to + 70_C
Recommended DC Operating Conditions
PARAMETER
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
Vcc
Supply Voltage
4.5
0.0
5.0
0.0
0.0
–
5.5
0.0
V
V
V
V
Gnd
VIL
VIH
Ground
Input low voltage
Input high voltage
– 3.0
2.2
0.8
VCC
Capacitance
PARAMETER
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
pF
Cin
(1)
(1)
Input capacitance
Output capacitance
–
–
–
–
5
7
Cout
pF
Note :
1. TA = 25°C, f = 1 MHz, Vcc = 5.0 V, these parameters are not 100 % tested.
DC Parameters
PARAMETER
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
µA
µA
mA
V
IIX
(2)
Input leakage current
– 10.0
– 10.0
–
–
–
–
–
–
10.0
10.0
– 350.0
0.4
IOZ
IOS
(3)
Output leakage current
Output short circuit current
Output low voltage
(3)
(4)
(5)
VOL
VOH
–
Output high voltage
2.4
–
V
Note :
2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output disabled.
3. Vcc = max, Vout = Gnd, duration of the short circuit should not exceed 30 seconds.
Not more than 1 output should be shorted at one time.
4. Vcc min, IOL = 8.0 mA.
5. Vcc min, IOH = –4.0 mA.
Rev. C (20/12/94)
3
HM 65790
MATRA MHS
Consumption for Commercial (–5) Specification
65790
E–5
65790
F–5
65790
H–5
65790
K–5
65790
M–5
SYMBOL
PARAMETER
UNIT
VALUE
ICCSB
ICCSB1
ICCOP
(6)
Standby supply current
Standby supply current
Dynamic operating current
20
20
40
20
30
20
30
20
30
20
mA
mA
mA
max
max
max
(7)
(8)
115
100
100
100
100
Consumption for Military (–2) Specification
65790
F–2
65790
H–2
65790
K–2
65790
M–2
SYMBOL
PARAMETER
UNIT
VALUE
ICCSB
ICCSB1
ICCOP
(6)
Standby supply current
Standby supply current
Dynamic operating current
40
20
40
30
20
30
20
mA
mA
mA
max
max
max
(7)
(8)
20
115
100
100
100
Note :
6. CS ≥ VIH min duty cycle = 100 %, a pull-up resistor to Vcc on the CS input is required to keep the device deselected during Vcc
power-up otherwise ICCSB will exceed values above.
7. CS = Vcc – 0.3 V Iout = 0 mA.
8. Vcc max, Output current = 0 mA, f = max, Vin = Vcc or Gnd.
* Preliminary.
AC Parameters
AC Conditions
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V
Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Output loading IOL/IOH (see figure 1a and 1b) : . . . . . . . . . . . +30 pF
AC Test Loads and Waveforms
Figure 1
a
Figure 1 b
Figure 2
4
Rev. C (20/12/94)
MATRA MHS
HM 65790
Write Cycle : Commercial (–5) Specification
65790
65790
F–5
65790
H–5
65790
K–5
65790
SYMBOL
PARAMETER
UNIT
VALUE
E–5
15
0
M–5
40
0
TAVAV
Write cycle time
20
0
20
0
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
min
min
min
min
min
max
min
min
min
min
TAVWL
TAVWH
TDVWH
TELWH
TWLQZ
TWLWH
TWHAX
TWHDX
TWHQX
Address set–up time
Address valid to end of write
Data set–up time
12
10
12
7
15
10
15
7
20
10
20
7
25
15
25
10
20
0
30
15
30
15
20
0
CS low to write end
Write low to high Z
Write pulse width
12
0
15
0
15
0
Address hold from end of write
Data hold time
0
0
0
0
0
(8) Write high to low Z
5
5
5
5
5
Write Cycle : Military (–2) Specification
65790
F–2
65790
H–2
65790
K–2
65790
M–2
SYMBOL
PARAMETER
UNIT
VALUE
TAVAV
Write cycle time
20
0
20
0
25
0
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
min
min
min
min
min
max
min
min
min
min
TAVWL
TAVWH
TDVWH
TELWH
TWLQZ(8)
TWLWH
TWHAX
TWHDX
TWHQ
Address set–up time
Address Valid to end of write
Data set–up time
15
10
15
7
20
10
20
7
25
15
25
10
20
0
30
15
30
15
20
0
CS low to write end
Write low to high Z
Write pulse width
15
0
15
0
Address hold from end of write
Data hold time
0
0
0
0
(8) Write high to low Z
5
5
5
5
Note :
8. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Rev. C (20/12/94)
5
HM 65790
MATRA MHS
Write Cycle 1 W Controlled
Write Cycle 2 CS controlled
6
Rev. C (20/12/94)
MATRA MHS
HM 65790
Read Cycle : Commercial (–5) Specification
65790
65790
F–5
65790
H–5
65790
K–5
65790
SYMBOL
PARAMETER
UNIT
VALUE
E–5
15
15
3
M–5
45
45
3
TAVAV
Read cycle time
20
20
3
25
25
3
35
35
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
min
max
min
max
min
max
min
max
max
min
max
TAVQV
TAVQX
TELQV
TELQX
TEHQZ
TELIC
Address access time
Address valid to low Z
Chip–select access time
CS low to low Z
15
5
20
5
25
5
35
5
45
5
CS high to high Z
8
8
10
0
12
0
15
0
CS low to power up
CS high to power down
Output enable access time
OE low to low Z
0
0
TEHICL
TGLQV
TGLQX
TGHQZ
15
10
3
20
10
3
20
12
3
20
15
3
25
20
3
OE high to high Z
15
15
15
15
15
Read Cycle : Military (–2) Specification
65790
F–2
65790
H–2
65790
K–2
65790
M–2
SYMBOL
PARAMETER
UNIT
VALUE
TAVAV
Read cycle time
20
20
3
25
25
3
35
35
3
45
45
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
min
max
min
max
min
max
min
max
max
min
min
TAVQV
TAVQX
TELQV
TELQX
TEHQZ
TELIC
Address access time
Address valid to low Z
Chip–select access time
CS low to low Z
20
5
25
5
35
5
45
5
CS high to high Z
8
10
0
12
0
15
0
CS low to power up
CS high to power down
Output enable access time
OE low to low Z
0
TEHICL
TGLQV
TGLQX
TGHQZ
20
10
3
20
12
3
20
15
3
25
20
3
OE high to high Z
15
15
15
15
Rev. C (20/12/94)
7
HM 65790
MATRA MHS
Read Cycle nb 1 (notes 9, 10)
Read Cycle nb 2 (notes 9, 11)
Notes : 9. W is high for read cycle.
10. Device is continuously selected, CS , CS = VIL.
1
2
11. Address valid prior to or coincider with CS , CS transition low.
1
2
8
Rev. C (20/12/94)
MATRA MHS
HM 65790
Ordering Information
PACKAGE
DEVICE TYPE
65790
GRADE
LEVEL
-5 : R
HM
3
H
16 K × 4 high speed
static RAM
with separate I/O
–2 : Military
–5 : Commercial
–6 : 100% 25°C Probe
0 –Chip form
1 –Ceramic 28 pins
3 –Plastic 28 pins
T–SOIC 28 pins
/883 : MIL STD 883 Class B or S
DB : Dice Military program
R
: Tape & Reel option
RD : Tape & Reel/Dry pack option
: Dry pack option
E = 15 ns
F = 20 ns
H = 25 ns
K = 35 ns
M = 45 ns
D
The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication
and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
Rev. C (20/12/94)
9
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