HMU65797M-2:D [TEMIC]
SRAM,;型号: | HMU65797M-2:D |
厂家: | TEMIC SEMICONDUCTORS |
描述: | SRAM, 静态存储器 |
文件: | 总7页 (文件大小:102K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HM 65797
256 K x 1 High Speed CMOS SRAM
Introduction
The HM 65797 is a high speed CMOS static RAM Easy memory expansion is provided by an active low chip
organized as 262, 144 × 1 bit. It is manufactured using select (CS) and three state drivers.
MHS high performance CMOS technology.
All inputs and outputs of the HM 65797 are TTL
Access times as fast 20ns are available with maximum compatible and operate from single 5 V supply thus
power consumption of only 770 mW.
simplifying system design.
The HM 65797 features fully static operation requiring no The HM 65797 is 100 % processed following the test
external clocks or timing strobes. The automatic methods of MIL STD 883 and/or ESA/SCC 9000 making
power-down feature reduces the power consumption by it ideally suitable for military/space applications that
67 % when the circuit is deselected.
demand superior levels of performance and reliability.
Features
D Fast access time
D Wide temperature range :
Commercial/industrial : 20/25/35/45/55 ns (max)
Military : 25/35/45/55 ns (max)
D Low power consumption
Active : 770 mW
–55°C to + 125°C
D 300 mils width package
D TTL compatible inputs and outputs asynchronous
D Capable of withstanding greater than 2000V electrostatic
discharge single 5 volt supply
Standby : 220 mW
Interface
Block Diagram
MATRA MHS
1
Rev. D (16 April.97)
Preliminary Information
HM 65797
Pin Configuration
Plastic 300 mils, 24 pins, DIL
Ceramic 300 mils, 24 pins, DIL
Pinout DIL/SO 24 pins (top view)
Pin Names
Truth Table
A0–A13: Address inputs
W
: Write enable
: Power
CS
H
W
X
INPUT
OUTPUT
MODE
Deselect
Read
Din
Dout
CS
: Input
Vcc
Z
Z
Z
Valid
Z
: Output
GND : Ground
L
H
: Chip Select
L
L
Valid
Write
L = Low – H = High, X = H or L, Z = High impedance.
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . . –0.5 V to +7.0 V
DC input voltage : . . . . . . . . . . . . . . . . . . . . . . . . . . . –3.0 V to +7.0 V
DC output voltage in high Z state : . . . . . . . . . . . . . . –0.5 V to +7.0 V
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Output current into outputs (low) : . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Electro Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . > 2000 V
(MIL STD 883C METHOD 3015-5)
Operating Range
OPERATING VOLTAGE
OPERATING TEMPERATURE
– 55_C to + 125_C
Military
(– 2)
(– 9)
(– 5)
5 V ± 10 %
5 V ± 10 %
5 V ± 10 %
Industrial
Commercial
– 40_C to + 85_C
– 0_C to + 70_C
Recommended DC Operating Conditions
PARAMETER
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
Vcc
Supply Voltage
4.5
0.0
5.0
0.0
0.0
–
5.5
0.0
V
V
V
V
Gnd
VIL
VIH
Ground
Input low voltage
Input high voltage
– 3.0
2.2
0.8
VCC
2
MATRA MHS
Rev. D (16 April.97)
Preliminary Information
HM 65797
Capacitance
PARAMETER
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
pF
Cin
(1)
(1)
Input capacitance
Output capacitance
–
–
–
–
5
7
Cout
pF
Note :
1. TA = 25°C, f = 1 MHz, Vcc = 5.0 V, these parameters are not tested.
AC Test Loads and Waveforms
Figure 1
a
Figure 1 b
Figure 2
Equivalent to : THEVENIN EQUIVALENT
Commercial
Military
DC Parameters
PARAMETER
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
µA
µA
mA
V
IIX
IOZ
(2)
Input leakage current
Output leakage current
Output short circuit current
Output low voltage
– 10.0
– 10.0
–
–
–
–
–
–
10.0
10.0
– 350.0
0.4
(2)
IOS
(3)
(4)
(5)
VOL
VOH
Note :
–
Output high voltage
2.4
–
V
2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output disabled.
3. Vcc = max, Vout = Gnd, duration of the short circuit should not exceed 30 seconds.
Not more than 1 output should be shorted at one time.
4. Vcc min, IOL = 8.0 mA (military), IOL = 12.0 mA (commercial).
5. Vcc min, IOH = –4.0 mA.
MATRA MHS
3
Rev. D (16 April.97)
Preliminary Information
HM 65797
Consumption for Commercial (–5) Specification
65797
F–5
65797
H–5
65797
K–5
65797
M–5
65797
N–5
SYMBOL
PARAMETER
UNIT
VALUE
ICCSB
ICCSB1
ICCOP
(6)
Standby supply current
Standby supply current
Dynamic operating current
40
20
35
20
35
20
35
20
35
20
mA
mA
mA
max
max
max
(8)
(7)
140
100
100
100
100
Consumption for Industrial (–9) and Military (–2) Specification
65797
F–9
65797
H–9/–2
65797
K–9/–2
65797
M–9/–2
65797
N–9/–2
SYMBOL
PARAMETER
UNIT
VALUE
ICCSB
ICCSB1
ICCOP
(6)
Standby supply current
Standby supply current
Dynamic operating current
40
20
35
20
35
20
35
20
35
20
mA
mA
mA
max
max
max
(8)
(7)
150
110
110
110
110
Note :
6. CS ≥ VIH, a pull-up resistor to Vcc on the CS is required to keep the device unselected during the Vcc power-up. Otherwise
IccSB will exceed the above values. Min duty cycle = 100 %.
7. Vcc max, Output current = 0 mA, f = max, Vin = Vcc or Gnd.
8. CS ≥ Vcc – 0.3 V Iout = 0 mA.
AC Parameters
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V
Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output loading IOL/IOH (see figure 1a and 1b) : . . . . . . . . . . . +30 pF
Write Cycle Specification : Commercial, Industrial and Military
65797
65797
65797
65797
65797
F–5/–9
SYMBOL
PARAMETER
H–5/–9 K–5/–9 M–5/–9 N–5/–9
UNIT
VALUE
/–2
25
0
/–2
35
0
/–2
45
0
/–2
55
0
TAVAV
Write cycle time
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
min
min
min
min
min
max
min
min
min
min
TAVWL
Address set–up time
Address valid to end to write
Data set–up time
TAVWH
TDVWH
TELWH
TWLQZ(9)
TWLWH
TWHAX
TWHDX
TWHQX
15
10
15
10
15
0
20
15
20
13
20
0
30
17
30
15
25
0
40
20
40
20
30
0
50
25
50
25
35
0
CS low to write end
Write low to high Z
Write pulse width
Address hold from write end
Data hold time
0
0
0
0
0
(9) Write high to low Z
3
3
3
3
3
Note :
9. The data input set-up and hold timing should be referenced to rising edge of the signal that terminates the write.
4
MATRA MHS
Rev. D (16 April.97)
Preliminary Information
HM 65797
Write Cycle 1 : W Controlled (note 10)
Write Cycle 2 : CS controlled (note 10)
Note : 10. The internal write of the memory is defined by the overlap of CS LOW and W LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to rising edge of the signal that
terminates the write.
MATRA MHS
5
Rev. D (16 April.97)
Preliminary Information
HM 65797
Read Cycle Specification : Commercial, Industrial and Military
65797
65797
65797
65797
65797
F–5/–9
SYMBOL
PARAMETER
H–5/–9 K–5/–9 M–5/–9 N–5/–9
UNIT
VALUE
/–2
25
25
3
/–2
35
35
3
/–2
45
45
3
/–2
55
55
3
TAVAV
READ cycle time
20
20
3
ns
ns
ns
ns
ns
ns
ns
ns
min
max
min
max
min
max
min
max
TAVQV
TAVQX
TELQV
TELQX
TEHQZ
TELIC
Address access time
Address valid to low Z
Chip–select access time
CS low to low Z
20
3
25
3
35
3
45
3
55
3
CS high to high Z
10
0
13
0
15
0
20
0
20
0
CS low to power up
CS high to power up
TEHICL
20
20
25
30
35
Read Cycle 1 : (note 11, 12, 13)
Read Cycle 2 : (note 11, 13)
Notes : 11. W is high for read cycle.
12. Device is continuously selected, CS = VIL.
13. Address valid prior or coincident with CS transition low.
6
MATRA MHS
Rev. D (16 April.97)
Preliminary Information
HM 65797
Ordering Information
PACKAGE
DEVICE TYPE
65797
GRADE
H
LEVEL
-5 : R
HM
3
256 K × 1 high speed
–2 : Military
–5 : Commercial
static RAM
–6 : 100% 25°C Probe
–9 : Industrial
/883 : MIL STD 883 Class B or S
DB : Dice Military program
0 –Chip form
1 –Ceramic 24 pins 300 mils
3 –Plastic 24 pins 300 mils
T–SOIC 24 pins 300 mils
U –SOJ 24 pins
F = 20 ns
H = 25 ns
K = 35 ns
M = 45 ns
N = 55 ns
R
: Tape & Reel option
RD : Tape & Reel/Dry pack option
: Dry pack option
D
Temp. range
Packages
Access Time (ns)
Std process 65797
SMD NUMBER
25
(H)
35
(K)
45
(M)
55
(N)
Mil flows
(including
SMD5962–88725)
5962–88725
M
1
4
0
1
1
X
1
1
X
1
1
X
1
1
1
1
1
1
The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication
and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
MATRA MHS
7
Rev. D (16 April.97)
Preliminary Information
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