M1K-L67140L-45/883 [TEMIC]
Dual-Port SRAM, 1KX8, 45ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48;
| 型号： | M1K-L67140L-45/883 |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Dual-Port SRAM, 1KX8, 45ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48 CD 静态存储器 |
| 文件： | 总16页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L67130/L67140
1 K × 8 CMOS Dual Port RAM 3.3 Volt
Introduction
The L67130/67140 are very low power CMOS dual port Using an array of eight transistors (8T) memory cell and
static RAMs organized as 1024 × 8. They are designed to fabricated with the state of the art 1.0 µm lithography
be used as a stand-alone 8 bits dual port RAM or as a named SCMOS, the M67130/140 combine an extremely
combination MASTER/SLAVE dual port for 16 bits or low standby supply current (typ = 1.0 µA) with a fast
more width systems. The MHS MASTER/SLAVE dual access time at 45 ns over the full temperature range. All
port approach in memory system applications results in versions offer battery backup data retention capability
full speed, error free operation without the need for with a typical power consumption at less than 5 µW.
additional discrete logic.
For military/space applications that demand superior
Master and slave devices provide two independent ports
with separate control, address and I/O pins that permit
independent, asynchronous access for reads and writes to
any location in the memory. An automatic power down
feature controlled by CS permits the onchip circuitry of
each port in order to enter a very low stand by power
mode.
levels of performance and reliability the L67130/67140
is processed according to the methods of the latest
revision of the MIL STD 883 (class B or S) and/or ESA
SCC 9000.
Features
D Single 3.3 V ± 0.3 volt power supply
D Fast access time
D On chip arbitration logic
D BUSY output flag on master
45 ns(*) to 70 ns
D BUSY input flag on slave
D 67130L/67140L low power
D INT flag for port to port communication
D Fully asynchronous operation from either port
D Battery backup operation : 2 V data retention
67130V/67140V very low power
D Expandable data bus to 16 bits or more using master/slave
devices when using more than one device.
(*) Preliminary
MATRA MHS
1
Rev. D (19 Fev. 97)
L67130/L67140
Interface
Pin Configuration
52 PIN PLCC (top view)
48 PIN PLCC (top view)
48 PIN DIL (top view), ceramic,
plastic 600 mils
64 PIN VQFP
(top view)
Block Diagram
Notes : 1. L 67130 (MASTER) : BUSY is open drain output and requires pullup resistor
L 67140 (SLAVE) : BUSY in input
2. Open drain output requires pull-up resistor.
2
MATRA MHS
Rev. D (19 Fev. 97)
L67130/L67140
Pin Names
LEFT PORT
RIGHT PORT
NAMES
CS
L
CS
R
Chip select
R/W
R/W
Write Enable
Output Enable
Address
L
R
OE
OE
R
L
A
A
0R – 9R
0L – 9L
I/O
I/O
Data Input/Output
Busy Flag
0L – 7L
0R – 7R
BUSY
BUSY
R
L
INT
INT
Interrupt Flag
Power
L
R
VCC
GND
Ground
Functional Description
The L 67130/L 67140 has two ports with separate control,
address and I/0 pins that permit independent read/write
access to any memory location. These devices have an
automatic power-down feature controlled by CS. CS
controls on-chip power-down circuitry which causes the
port concerned to go into stand-by mode when not
selected (CS high). When a port is selected access to the
full memory array is permitted. Each port has its own
Output Enable control (OE). In read mode, the port’s OE
turns the Output drivers on when set LOW.
Arbitration Logic
The arbitration logic will resolve an address match or a
chip select match down to a minimum of 5 ns and
determine which port has access. In all cases, an active
BUSY flag will be set for the inhibited port.
The BUSY flags are required when both ports attempt to
access the same location simultaneously.Should this
conflict arise, on-chip arbitration logic will determine
which port has access and set the BUSY flag for the
inhibited port. BUSY is set at speeds that allow the
processor to hold the operation with its associated address
and data. It should be noted that the operation is invalid
for the port for which BUSY is set LOW. The inhibited
port will be given access when BUSY goes inactive.
Non-conflicting
READ/WRITE
conditions
are
illustrated in table 1.
Interrupt Logic
The interrupt flag (INT) allows communication between
ports or systems. If the user chooses to use the interrupt
function, a memory location (mail box or message center)
A conflict will occur when both left and right ports are
active and the two addresses coincide. The on-chip
arbitration determines access in these circumstances.
Two modes of arbitration are provided : (1) if the
addresses match and are valid before CS on-chip control
is assigned to each port. The left port interrupt flag (INT )
L
is set when the right port writes to memory location 3FE
(HEX). The left port clears the interrupt by reading
address location 3FE. Similarly, the right port interrupt
logic arbitrates between CS and CS for access ; or (2)
L
R
if the CSs are low before an address match, on-chip
control logic arbitrates between the left and right
addresses for access (refer to table 2). The inhibited port’s
BUSY flag is set and will reset when the port granted
access completes its operation in both arbitration modes.
flag (INT ) is set when the left port writes to memory
R
location 3FF (hex), and the right port must read memory
location 3FF in order to clear the interrupt flag (INT ).
R
The 8 bit message at 3FE or 3FF is user-defined. If the
interrupt function is not used, address locations 3FE and
3FF are not reserved for mail boxes but become part of the
RAM. See table 3 for the interrupt function.
MATRA MHS
3
Rev. D (19 Fev. 97)
L67130/L67140
Data Bus Width Expansion
Master/Slave Description
Expanding the data bus width to 16 or more bits in a When dual-port RAMs are expanded in width, the
dual-port RAM system means that several chips may be SLAVE RAMs must be prevented from writing until the
active simultaneously. If every chip has a hardware BUSY input has been settled. Otherwise, the SLAVE chip
arbitrator, and the addresses for each chip arrive at the may begin a write cycle during a conflict situation. On the
same time one chip may activate its L BUSY signal while opposite, the write pulse must extend a hold time beyond
another activates its R BUSY signal. Both sides are now BUSY to ensure that a write cycle occurs once the conflict
busy and the CPUs will wait indefinitely for their port to is resolved. This timing is inherent in all dual-port
become free.
memory systems where more than one chip is active at the
same time.
To overcome this “Busy Lock-Out” problem, MHS has
developed a MASTER/SLAVE system which uses a
single hardware arbitrator located on the MASTER. The
SLAVE has BUSY inputs which allow direct interface to
the MASTER with no external components, giving a
speed advantage over other systems.
The write pulse to the SLAVE must be inhibited by the
MASTER’s maximum arbitration time. If a conflict then
occurs, the write to the SLAVE will be inhibited because
of the MASTER’s BUSY signal.
Truth Table
(4)
Table 1 : Non Contention Read/Write Control
LEFT OR RIGHT PORT(1)
FUNCTION
R/W
X
CS
H
OE
X
D0–7
Z
Port Disabled and in Power Down Mode. ICCSB or ICCSB1
(2)
L
L
X
DATA
Data on Port Written into memory
IN
(3)
H
L
L
DATA
Z
Data in Memory Output on Port
OUT
H
L
H
High Impedance Outputs
Notes : 1. A – A
≠ A – A
.
0L
10L
0R
10R
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
and t
DDD
timing.
WDD
4. H = HIGH, L = LOW, X = DON’T CARE, Z = HIGH IMPEDANCE.
4
MATRA MHS
Rev. D (19 Fev. 97)
L67130/L67140
(5)
Table 2 : Arbitration
LEFT PORT
RIGHT PORT
FLAGS
FUNCTION
CSL
H
A0L – A9L
CSR
A0L – A9R
BUSYL
BUSYR
X
Any
X
H
H
L
L
X
X
H
H
H
H
H
H
H
H
No Contention
L
No Contention
No Contention
No Contention
H
Any
L
≠ A – A
≠ A – A
0L 9L
0R
9R
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
L
L
L
LV5R
RV5L
Same
Same
L
L
L
L
LV5R
RV5L
Same
Same
H
L
H
L
L
H
L
L–Port Wins
R–Port Wins
Arbitration Resolved
Arbitration Resolved
H
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS
LL5R
RL5L
LW5R
LW5R
= A – A
LL5R
RL5L
LW5R
LW5R
= A – A
9L
H
L
H
L
L
H
L
L–Port Wins
0R
9R
9R
0L
= A – A
= A
A
R–Port Wins
0R
0L – 9L
= A
A
= A – A
Arbitration Resolved
Arbitration Resolved
0R – 9R
0L
9L
= A – A
= A – A
H
0R
9R
0L
9L
Notes : 5. INT Flags Don’t Care.
6. X = DON’T CARE, L = LOW, H = HIGH.
LV5R = Left Address Valid ≥ 5 ns before right address.
RV5L = Right address Valid ≥ 5 ns before left address.
Same = Left and Right Addresses match within 5 ns of each other.
LL5R = Left CS = LOW ≥ 5 ns before Right CS.
RL5L = Right CS = LOW ≥ 5 ns before left CS.
LW5R = Left and Right CS = LOW within 5 ns of each other.
(7, 10)
Table 3 : Interrupt Flag
LEFT PORT
RIGHT PORT
FUNCTION
R/WL CSL
OEL
X
AOL–A9L
INTL R/WR CSR
OER
X
AOR–A9R
INTR
(8)
L
X
X
X
L
X
X
L
3FF
X
X
X
X
X
L
X
L
L
X
X
L
Set Right INT Flag
R
(9)
X
L
3FF
3FE
X
H
Reset Right INT Flag
R
(9)
X
X
L
X
X
X
Set Left INT Flag
L
(8)
L
3FE
H
X
X
Reset Left INT Flag
L
Notes : 7. Assumes BUSY = BUSY = H.
L
R
8. If BUSY = L, then NC.
L
9. If BUSY = L, then NC.
R
10. H = HIGH, L = LOW, X = DON’T CARE, NC = NO CHANGE.
MATRA MHS
Rev. D (19 Fev. 97)
5
L67130/L67140
Electrical Characteristics
* Notice
Absolute Maximum Ratings
Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extented periods may affect reliability.
Supply voltage (VCC–GND) : . . . . . . . . . . . . . . . . . . –0.3 V to 7.0 V
Input or output voltage applied : . . . (GND –0.3 V) to (VCC + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
OPERATING RANGE
Military
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
o
o
V
V
V
V
= 3.3 V ± 0.3 V
= 3.3 V ± 0.3 V
= 3.3 V ± 0.3 V
= 3.3 V ± 0.3 V
– 55 C to + 125 C
CC
CC
CC
CC
o
o
Automotive
– 40 C to + 125 C
o
o
Industrial
– 40 C to + 85 C
o
o
Commercial
0 C to + 70 C
DC Parameters
L 67130/ 140–45 L 67130/ 140–55 L 67130/ 140–70
IND
IND
COM MIL
AUTO
IND
COM MIL
AUTO
MIL
AUTO
COM
Parameter
Description
Version
Unit
Value
Preliminary
I
Standby supply current (Both
ports TTL level inputs)
V
L
1
5
1
10
1
5
1
10
1
5
1
10
mA
mA
Max
Max
CCSB (11)
I
Standby supply current (Both
ports CMOS level inputs)
V
L
10
100
20
200
10
100
20
200
10
100
20
200
µΑ
µΑ
Max
Max
CCSB1 (12)
I
Operating supply current (Both
ports active)
V
L
80
80
90
100
70
70
80
90
60
60
70
80
mA
mA
Max
Max
CCOP (13)
I
Operating supply current (One
port active – One port standby)
V
L
50
60
55
65
40
50
45
55
35
45
40
50
mA
mA
Max
Max
CCOP 1 (14)
Notes : 11. CS = CS ≥ 2.2 V.
L
R
12. CS = CS ≥ VXX – 0.2 V.
L
R
13. Both ports active – Maximum frequency – Outputs open – OE = VIH.
14. One port active (f = MAX) – Output open – One port stand-by TTL or CMOS Level inputs – CS = CS ≥ 2.2 V.
L
R
L 67130–45/55/70
L 67140–45/55/70
PARAMETER
DESCRIPTION
UNIT
VALUE
II/O
VIL
Input/Output leakage current
Input low voltage
± 10
0.7
µA
V
Max
Max
Min
Max
(15)
(16)
VIH
Input high voltage
1.8
V
(16)
VOL
VOL
Output low voltage (I/O –I/O )
0.5
V
(17)
0
7
Open drain output low voltage
0.5
V
Max
(BUSY, INT) I = 16 mA
OL
VOH
Output high voltage
Input capacitance
Output capacitance
1.5
5
V
Min
Max
Max
(17)
C IN
pF
pF
(21)
C OUT
7
(21)
Notes : 15. V = 5.5 V, Vin = Gnd to V , CS = VIH, Vout = 0 to V .
CC
CC
CC
16. VIH max = V + 0.3 V, VIL min – 0.3 V or –1 V pulse width 50 ns.
CC
17. V min, IOL = 4 mA, IOH = –4 mA.
CC
6
MATRA MHS
Rev. D (19 Fev. 97)
L67130/L67140
Data-Retention Mode
MHS CMOS RAMs are designed with battery backup in 2 – CS must be kept between V – 0.2 V and 70 % of Vcc
CC
mind. Data retention voltage and supply current are during the power up and power down transitions.
guaranteed over temperature. The following rules insure
data retention :
3 – The RAM can begin operation > tRC after Vcc
reaches the minimum operating voltage (3 volts).
1 – Chip select (CS) must be held high during data
retention ; within Vcc to VCC
.
DR
Timing
MAX
MIL
IND
PARAMETER
TEST CONDITIONS (18)
UNIT
COM
AUTO
ICC
@ VCC = 2 V
10
20
µA
DR1
DR
Notes : 18. CS = Vcc, Vin = Gnd to Vcc.
19. = Read cycle time.
t
RC
AC Test Conditions
Input Pulse Levels : GND to 3.0 V
Input Rise/Fall Times : 5 ns
Output Reference Levels : 1.5 V
Output Load : see figures 1, 2
Input Timing Reference Levels : 1.5 V
Figure 1. Output Load.
Figure 2. Output load.
(For t , t , t , and t
)
HZ LZ WZ
OW
MATRA MHS
7
Rev. D (19 Fev. 97)
L67130/L67140
AC Parameters
L67130–45
L67140–45
L67130–55
L67140–55
L67130–70
L67140–70
READ CYCLE
PARAMETER
UNIT
MIN.
MAX.
MIN.
MAX. MIN. MAX.
SYMBOL
(23)
SYMBOL
(24)
PRELIMINARY
TAVAVR
TAVQV
TELQV
TGLQV
TAVQX
TELQZ
TEHQZ
TPU
t
t
t
t
t
t
t
t
t
Read cycle time
45
–
–
45
45
30
–
55
–
–
55
55
35
–
70
–
–
70
70
40
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address access time
AA
ACS
AOE
OH
LZ
Chip Select access time (22)
Output enable access time
–
–
–
–
–
–
Output hold from address change
Output low Z time (20, 21)
Output high Z time (20, 21)
Chip Select to power up time (21)
Chip disable to power down time (21)
0
0
0
5
–
5
–
5
–
–
20
–
–
30
–
–
35
–
HZ
0
0
0
PU
TPD
–
50
–
50
–
50
PD
Notes : 20. Transition is measured ± 500 mV from low or high impedance voltage with load (figures 1 and 2).
21. This parameter is guaranteed but not tested.
22. To access RAM CS = VIL.
23. STD symbol.
24. ALT symbol.
Timing Waveform of Read Cycle no 1, Either Side (25, 26, 28)
Timing Waveform of Read Cycle no 2, Either Side (25, 27, 29)
Notes : 25. R/W is high for read cycles.
26. Device is continuously enabled, CS = VIL.
27. Addresses valid prior to or coincident with CS transition low.
28. OE = VIL.
29. To access RAM, CS = VIL.
8
MATRA MHS
Rev. D (19 Fev. 97)
L67130/L67140
AC Parameters
L67130–45
L67140–45
L67130–55
L67140–55
L67130–70
L67140–70
WRITE CYCLE
PARAMETER
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
SYMBOL SYMBOL
(34)
(35)
PRELIMINARY
TAVAVW
TELWH
TAVWH
TAVWL
TWLWH
TWHAX
TDVWH
TGHQZ
TWHDX
TWLQZ
TWHQX
t
Write cycle time
45
35
35
0
–
–
55
40
40
0
–
–
70
45
45
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
t
Chip select to end of write (32)
Address valid to end of write
Address Set–up Time
SW
AW
t
–
–
–
t
–
–
–
AS
WP
WR
DW
t
Write Pulse Width
35
0
–
40
0
–
45
0
–
t
Write Recovery Time
–
–
–
t
Data Valid to end of write
Output high Z time (30, 31)
Data hold time (33)
25
–
–
25
–
–
30
–
–
t
20
–
30
–
40
–
HZ
DH
WZ
OW
t
0
0
0
t
Write enable to output in high Z (30, 31)
Output active from end of write (30, 31, 33)
–
20
–
–
30
–
–
40
–
t
0
0
0
Notes : 30. Transition is measured ± 500 mV from low or high impedance voltage with load (figures 1 and 2).
31. This parameter is guaranteed but not tested.
32. To access RAM CS = VIL.
This condition must be valid for entire t time.
SW
33. The specification for t must be met by the device supplying write data to the RAM under all operating conditions.
DH
Although t and t
values vary over voltage and temperature, the actual t will always be smaller than the actual t
.
DH
OW
DH
OW
34. STD symbol.
35. ALT symbol.
MATRA MHS
Rev. D (19 Fev. 97)
9
L67130/L67140
Timing Waveform of Write Cycle no 1, R/W Controlled Timing (36, 37, 38, 42)
Timing Waveform of Write Cycle no 2, CS Controlled Timing (36, 37, 38, 40)
Notes : 36. R/W must be high during all address transitions.
37. A write occurs during the overlap (t or t ) of a low CS and a low R/W.
SW
WP
38.
t
is measured from the earlier of CS or R/W going high to the end of write cycle.
WR
39. During this period, the I/O pins are in the output state, and input signals must not be applied.
40. If the CS low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high
impedance state.
41. Transition is measured ± 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled
and not 100 % tested.
42. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of t or (t
+ t
DW
)
WP
WZ
to allow the I/O drivers to turn off and data to be placed on the bus for the required t . If OE is high during an R/W
DW
controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
43. To access RAM, CS = VIL.
.
WP
10
MATRA MHS
Rev. D (19 Fev. 97)
L67130/L67140
AC Parameters
L67130–45
L67140–45
L67130–55
L67140–55
L67130–70
L67140–70
SYMBOL
PARAMETER
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
BUSY TIMING (For L 67130 only)
t
t
BUSY Access time to address
BUSY Disable time to address
BUSY Access time to Chip Select
BUSY Disable time to Chip Select
Write Pulse to data delay (44)
Write data valid to read data delay (44)
Arbitration priority set–up time (45)
BUSY disable to valid data
–
35
–
45
–
50
ns
ns
ns
ns
ns
ns
ns
ns
BAA
BDA
–
–
–
–
–
5
–
35
30
–
–
–
–
–
5
–
40
35
–
–
–
–
–
5
–
40
50
t
BAC
BDC
t
25
30
40
t
70
80
90
WDD
t
45
55
70
DDD
t
–
–
–
APS
t
Note 46
Note 46
Note 46
BDD
BUSY TIMING (For L 67140 only)
t
Write to BUSY input (47)
0
30
–
–
–
0
30
–
–
–
0
30
–
–
–
ns
ns
ns
ns
WB
WH
t
Write hold after BUSY (48)
Write pulse to data delay (49)
Write data valid to read data delay (49)
t
70
45
80
55
90
70
WDD
t
–
–
–
DDD
Notes : 44. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with
BUSY (For L67130 only)”.
45. To ensure that the earlier of the two ports wins.
46.
t
is a calculated parameter and is the greater of 0, t
– t (actual) or t
WP
– t
DW
(actual).
BDD
WDD
DDD
47. To ensure that the write cycle is inhibited during contention.
48. To ensure that a write cycle is completed after contention.
49. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read
with Port to port delay (For L67140 only)”.
MATRA MHS
Rev. D (19 Fev. 97)
11
L67130/L67140
Timing Waveform of Read with BUSY (50, 51, 52) (For L 67130)
Notes : 50. To ensure that the earlier of the two port wins.
51. Write cycle parameters should be adhered to, to ensure proper writing.
52. Device is continuously enabled for both ports.
53. OE at L for the reading port.
Timing Waveform of Write with Port-to-port (54, 55, 56) (For L 67140 only)
Notes : 54. Assume BUSY = H for the writing port, and OE = L for the reading port.
55. Write cycle parameters should be adhered to, to ensure proper writing.
56. Device is continuously enabled for both ports.
12
MATRA MHS
Rev. D (19 Fev. 97)
L67130/L67140
Timing Waveform of Write with BUSY (For L 67140)
Timing Waveform of Contention Cycle no 1, CS Arbitration (For L 67130 only)
MATRA MHS
13
Rev. D (19 Fev. 97)
L67130/L67140
Timing Waveform of Contention Cycle no 2, Address Valid Abritration
(For L 67130 only) (57)
Left Address Valid First :
Right Address Valid First :
Note :
57. CS = CS = V
L R IL
16 Bit Master/Slave Dual-port Memory Systems
Note :
58. No arbitration in L 67140 (SLAVE). BUSY IN inhibits write in L 67140 (SLAVE).
14
MATRA MHS
Rev. D (19 Fev. 97)
L67130/L67140
Waveform of Interrupt Timing (59)
Notes : 59. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
60. See interrupt truth table.
61. Timing depends on which enable signal is asserted last.
52. Timing depends on which enable signal is de-asserted first.
AC Electrical Characteristics over the Full
Operating Temperature and Supply Voltage Range
INTERRUPT
TIMING
L 67130/140–45
L 6 7130/140–55
L 6 7130/140–70
PARAMETER
UNIT
SYMBOL
MIN.
MAX.
—
MIN.
MAX.
—
MIN.
MAX.
—
t
AS
Address set–up time
0
0
0
0
0
0
ns
ns
ns
ns
t
Write recovery time
Interrupt set time
Interrupt reset time
—
—
—
WR
INS
INR
t
—
—
40
—
—
45
—
—
60
t
40
45
60
MATRA MHS
Rev. D (19 Fev. 97)
15
L67130/L67140
Ordering Information
TEMPERATURE RANGE PACKAGE
DEVICE SPEED
FLOW
C
L
S3
67130V
55
3.3 V ± 0.3 Volt
blank
/883
P883
SB/SC
= MHS standards
45 ns
55 ns
70 ns
= MIL-STD 883 Class B or S
= MIL-STD 883 + PIND TEST
= SCC9000 level B/C
1K = 48 pin DIL ceramic 600 mils
CK = 48 pin DIL side-brazed 600 mils
4K = 48 pin LCC
S3 = 52 pin PLCC
3K = 48 pin DIL plastic 600 mils
RD = 64 pin VQFP
SHXXX = Special customer
request
FHXXX = Flight models (space)
MHXXX = Mechanical parts
(space)
67130 = 8K (1K × 8) Master
67140 = 8K (1K × 8) Slave
C = Commercial
I = Industrial
A = Automotive
M = Military
S = Space
0° to +70°C
–40° to +85°C
–40° to +125°C
–55° to +125°C
–55° to +125°C
L
V
EL
EV
= Low power
= Very low power
LHXXX = Life test parts (space)
= Low power and rad tolerant
= Very low power and rad tolerant
The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication
and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
16
MATRA MHS
Rev. D (19 Fev. 97)
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