M44C892-H [TEMIC]
Microcontroller, 4-Bit, MROM, MARC4 CPU, 1MHz, CMOS, PDSO20,;
| 型号： | M44C892-H |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Microcontroller, 4-Bit, MROM, MARC4 CPU, 1MHz, CMOS, PDSO20, 微控制器 光电二极管 |
| 文件： | 总84页 (文件大小：644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M44C092–H
M44C892–H
Low-Current Microcontrollers for Wireless Communication
The M44C092–H and M44C892–H are members of Atmel Wireless & Microcontrollers’ family of 4-bit single-chip
microcontrollers. They offer highest integration for IR and RF data communication, remote-control and phase-control
applications. The M44C092–H and M44C892–Hare suitable for the transmitter side as well as the receiver side. It
contains ROM, RAM, parallel I/O ports, two 8-bit programmable multifunction timer/counters with modulator and
demodulator function, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock gen-
eration with external clock input, integrated RC-, 32-kHz crystal- and 4-MHz crystal-oscillators. The M44C892–H has
an additional EEPROM as a second chip in one package.
Features / Benefits
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different clock sources
ꢀ Wide supply voltage range (1.8 to 6.5 V)
ꢀ Very low sleep current (< 1 µA)
ꢀ 32 x 16-bit EEPROM (M44C892–H only)
ꢀ 4-Kbyte ROM, 256 x 4-bit RAM
ꢀ 16 bidirectional I/Os
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–
–
IR remote control carrier generator
Biphase-, Manchester- and pulse-width modulator
and demodulator
ꢀ Watchdog, POR and brown-out function
ꢀ Voltage monitoring incl. Lo_BAT detect
ꢀ Flash controller T48C893 available (SSO20)
–
Phase control function
V
V
OSC1 OSC2
SS DD
UTCM
Brown-out protect.
RESET
Voltage monitor
External input
External
oscillators clock input
RC
oscillators
Crystal
Timer 1
interval- and
watchdog timer
Clock management
T2I
VMI
Timer 2
8/12-bit timer
with modulator
T2O
BP10
BP13
ROM
4 K x 8 bit
RAM
256 x 4 bit
Port 1
SD
SC
SSI
Serial interface
MARC4
BP20/NTE
Timer 3
8-bit
timer / counter
with modulator
and demodulator
T3O
T3I
4-bit CPU core
BP21
BP22
BP23
I/O bus
Data direction +
alternate function
Data direction +
interrupt control
Data dir. +
alt. function
Port 4
Port 6
Port 5
BP63
T3I
BP50
INT6
BP52
INT1
BP60
T3O
BP40
INT3
BP41
BP42
T2O
BP43
INT3
SD
BP53
INT1
BP51
INT6
SC
VMI
T2I
13361
Figure 1. Block diagram M44C092–H / M44C892–H
Rev. A1, 08-Aug-01
1 (84)
M44C092–H
M44C892–H
1
2
VSS
VDD
20
19 BP43/INT3/SD
18 BP42/T2O
BP40/INT3/SC
3
BP53/INT1
BP52/INT1
BP51/INT6
4
17
BP41/VMI/T2I
5
16
15
BP23
BP22
M44C092–H
M44C892–H
6
BP50/INT6
OSC1
7
14 BP21
8
13
12
OSC2
BP20/NTE
BP63/T3I
9
BP60/T3O
BP10
10
11 BP13
Figure 2. Pinning SSO20 package
Table 1 Pin description
Name Type
Function
Alternate Function
Pin-No. Reset State
V
V
Supply voltage
Circuit ground
–––
–––
–––
–––
1
NA
NA
DD
SS
20
10
11
13
14
15
16
2
BP10
BP13
BP20
BP21
BP22
BP23
BP40
I/O Bidirectional I/O line of Port 1.0
I/O Bidirectional I/O line of Port 1.3
I/O Bidirectional I/O line of Port 2.0 NTE–test mode enable
I/O Bidirectional I/O line of Port 2.1
I/O Bidirectional I/O line of Port 2.2
I/O Bidirectional I/O line of Port 2.3
I/O Bidirectional I/O line of Port 4.0 SC-serial clock or INT3 external
interrupt input
Input
Input
Input
Input
Input
Input
Input
–––
–––
–––
BP41
I/O Bidirectional I/O line of Port 4.1 VMI voltage monitor input or T2I
external clock input Timer 2
17
Input
BP42
BP43
I/O Bidirectional I/O line of Port 4.2 T2O Timer 2 output
I/O Bidirectional I/O line of Port 4.3 SD serial data I/O or INT3–exter-
18
19
Input
Input
nal interrupt input
BP50
BP51
BP52
BP53
BP60
BP63
OSC1
I/O Bidirectional I/O line of Port 5.0 INT6 external interrupt input
I/O Bidirectional I/O line of Port 5.1 INT6 external interrupt input
I/O Bidirectional I/O line of Port 5.2 INT1 external interrupt input
I/O Bidirectional I/O line of Port 5.3 INT1 external interrupt input
I/O Bidirectional I/O line of Port 6.0 T3O Timer 3 output
I/O Bidirectional I/O line of Port 6.3 T3I Timer 3 input
6
5
4
3
9
Input
Input
Input
Input
Input
Input
Input
12
7
I
Oscillator input
4-MHz crystal input or 32-kHz
crystal input or external clock in-
put or external trimming resistor
input
OSC2
O
Oscillator output
4-MHz crystal output or 32-kHz
crystal output
8
NA
2 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
2
MARC4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
2.2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Components of MARC4 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
7
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7
8
10
10
10
10
12
12
12
13
14
14
14
15
16
16
17
17
17
17
17
18
18
18
19
19
20
20
22
22
23
23
23
24
26
27
28
29
2.3
Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
2.3.2
2.3.3
Power-on Reset and Brown-out Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
2.5
Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Voltage Monitor Control / Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
2.5.2
Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Circuits and External Clock Input Stage . . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 1 Fully Integrated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 2 with External Trimming Resistor . . . . . . . . . . . . . . . . . . . . . . . . .
4-MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Management Register (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Configuration Register (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3
2.6
Power-down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
3.2
Addressing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bidirectional Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
3.2.2
Bidirectional Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bidirectional Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 Data Register (P2DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 Control Register (P2CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bidirectional Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bidirectional Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bidirectional Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3
3.2.4
3.2.5
3.3
Universal Timer/Counter / Communication Module (UTCM) . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. A1, 08-Aug-01
3 (84)
M44C092–H
M44C892–H
Table of Contents (continued)
Timer 1 Control Register 1 (T1C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
30
31
31
32
33
34
37
37
38
39
40
40
40
40
41
42
44
47
Timer 1 Control Register 2 (T1C2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Control Register (WDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Control Register (T2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Mode Register 1 (T2M1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Mode Register 2 (T2M2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Compare and Compare Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Compare Mode Register (T2CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 COmpare Register 1 (T2CO1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 COmpare Register 2 (T2CO2) Byte Write . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer / Counter Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 Modulator / Demodulator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 Modulator for Carrier Frequency Burst Modulation . . . . . . . . . . . . . . . .
3.3.2
3.3.3
Timer 3 Demodulator for Biphase, Manchester and Pulse-Width Modulated Signals 47
Timer 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 Mode Register (T3M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 Control Register 1 (T3C) Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 Status Register 1 (T3ST) Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 Clock Select Register (T3CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 Compare- and Compare Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 Compare Mode Register 1 (T3CM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 Compare Mode Register 2 (T3CM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 COmpare Register 1 (T3CO1) Byte Write . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 COmpare Register 2 (T3CO2) Byte Write . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 Capture register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 3 CaPture Register (T3CP) Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSI Peripheral Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General SSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-bit Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-bit Shift Mode (I2C compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-bit Pseudo I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modulation and Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal 2-Wire Multi-Chip Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
48
48
49
49
49
50
50
51
51
51
51
52
52
53
54
55
56
56
58
58
58
59
3.3.4
4 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Table of Contents (continued)
Serial Interface Control Register 1 (SIC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Control Register 2 (SIC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Status and Control Register (SISC) . . . . . . . . . . . . . . . . . . . . . . .
Serial Transmit Buffer (STB) – Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Receive Buffer (SRB) – Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combination Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combination Mode Timer 2 and SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combination Mode Timer 3 and SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combination Mode Timer 2 and Timer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combination Mode Timer 2, Timer 3 and SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
59
60
60
61
61
61
64
67
69
71
71
72
72
73
73
73
74
74
75
75
75
77
82
83
3.3.5
4
M44C892 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 U505M EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM – Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization after a Reset Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2
5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
5.2
5.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. A1, 08-Aug-01
5 (84)
M44C092–H
M44C892–H
counters, voltage supervisor, interval timer with
watchdog function and a sophisticated on-chip clock gen-
eration with integrated RC-, 32-kHz crystal- and 4-MHz
crystal-oscillators.
1 Introduction
The M44C092–H / M44C892–Hare members of Atmel
Wireless & Microcontrollers’ family of 4-bit single-chip
microcontrollers. They contain ROM, RAM, parallel I/O
ports, two 8-bit programmable multifunction timer/ Table 2 provides an overview of the available variants.
Table 2 Available variants of M4xCx9x
Version
Type
T48C893
M44C092–H
M44C892–H
ROM
E2PROM peripheral
Packages
SSO20
SSO20
SSO20
Flash device
Production
Production
4 Kbyte EEPROM
4 Kbyte mask ROM
4 Kbyte mask ROM
64 byte
–––
64 byte
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
communication to the on-chip peripheral circuitry. The
extremely powerful integrated interrupt controller with
2 MARC4 Architecture
2.1 General Description
The MARC4 microcontroller consists of an advanced associated eight prioritized interrupt levels supports fast
stack-based, 4-bit CPU core and on-chip peripherals. The and efficient processing of hardware events. The MARC4
CPU is based on the HARVARD architecture with is designed for the high-level programming language
physically separate program memory (ROM) and data qFORTH. The core includes both, an expression and a
memory (RAM). Three independent buses, the return stack. This architecture enables high-level
instruction bus, the memory bus and the I/O bus, are used language programming without any loss of efficiency or
for parallel communication between ROM, RAM and code density.
MARC4 CORE
X
Y
SP
RP
Reset
Program
memory
RAM
PC
256 x 4-bit
Reset
Instruction
bus
Clock
Memory bus
CCR
Instruction
decoder
TOS
ALU
System
clock
Interrupt
controller
Sleep
I/O bus
On–chip peripheral modules
94 8973
Figure 3. MARC4 core
6 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
2.2 Components of MARC4 Core
1F8h
1F0h
1E8h
1E0h
FFFh
1E0h
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
ROM
1C0h
180h
140h
100h
0C0h
080h
040h
(4 K x 8 bit)
Zero
page
7FFh
020h
018h
010h
008h
000h
1FFh
Zero page
$RESET
008h
000h
000h
$AUTOSLEEP
13362
Figure 4. ROM map of M44C092–H
The core contains ROM, RAM, ALU, program counter, the expression stack, the return stack and data memory for
RAM address registers, instruction decoder and interrupt variables and arrays. The RAM is addressed by any of the
controller. The following sections describe each four 8-bit wide RAM address registers SP, RP, X and Y.
functional block in more detail:
Expression Stack
2.2.1
ROM
The 4-bit wide expression stack is addressed with the
expression stack pointer (SP). All arithmetic, I/O and
memory reference operations take their operands from,
and return their results to the expression stack. The
MARC4 performs the operations with the top of stack
items (TOS and TOS–1). The TOS register contains the
top element of the expression stack and works in the same
way as an accumulator. This stack is also used for passing
parameters between subroutines and as a scratch pad area
for temporary storage of data.
The program memory (ROM) is mask programmed with
the customer application program during the fabrication
of the microcontroller. The ROM is addressed by a 12–bit
wide program counter, thus predefining a maximum
program bank size of 4 Kbytes. An additional 1 Kbyte of
ROM exists which is reserved for quality control self–test
software The lowest user ROM address segment is taken
up by a 512 byte zero page which contains predefined
start addresses for interrupt service routines and special
subroutines accessible with single byte instructions
(SCALL).
Return Stack
The 12-bit wide return stack is addressed by the return
stack pointer (RP). It is used for storing return addresses
of subroutines, interrupt routines and for keeping loop
index counts. The return stack can also be used as a
temporary storage area.
The corresponding memory map is shown in figure 4.
Look-up tables of constants can also be held in ROM and
are accessed via the MARC4’s built-in TABLE
instruction.
The MARC4 instruction set supports the exchange of data
between the top elements of the expression stack and the
2.2.2
RAM
The M44C092–H and M44C892–H contain 256 x 4-bit return stack. The two stacks within the RAM have a user
wide static random access memory (RAM). It is used for definable location and maximum depth.
Rev. A1, 08-Aug-01
7 (84)
M44C092–H
M44C892–H
RAM
(256 x 4-bit)
Autosleep
Expression stack
3
0
FFh
TOS
FCh
TOS–1
TOS–2
SP
Global
variables
X
Y
4-bit
Expression
stack
Return stack
11
TOS–1
0
SP
RP
Return
stack
RP
Global
04h
00h
v
ariables
07h
03h
12-bit
94 8975
Figure 5. RAM map
from the ROM. Instructions currently being executed are
decoded in the instruction decoder to determine the
internal micro-operations. For linear code (no calls or
branches) the program counter is incremented with every
instruction cycle. If a branch-, call-, return-instruction or
an interrupt is executed, the program counter is loaded
with a new address. The program counter is also used with
2.2.3
Registers
The MARC4 controller has seven programmable
registers and one condition code register. They are shown
in the following programming model.
Program Counter (PC)
The program counter (PC) is a 12-bit register which the TABLE instruction to fetch 8-bit wide ROM
contains the address of the next instruction to be fetched constants.
11
0
PC
Program counter
0
0
0
7
7
0
RP
SP
Return stack pointer
Expression stack pointer
0
7
7
X
Y
RAM address register(X)
RAM address register(Y)
Top of stack register
0
0
3
TOS
CCR
3
0
B
C
––
I
Condition code register
Interrupt enable
Branch
Reserved
Carry / borrow
Figure 6. Programming model
8 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
RAM Address Registers
Top Of Stack (TOS)
The top of stack register is the accumulator of the
MARC4. All arithmetic/logic, memory reference and I/O
operations use this register. The TOS register receives
data from the ALU, ROM, RAM or I/O bus.
The RAM is addressed with the four 8-bit wide RAM
address registers: SP, RP, X and Y. These registers allow
access to any of the 256 RAM nibbles.
Expression Stack Pointer (SP)
Condition Code Register (CCR)
The stack pointer (SP) contains the address of the next-to-
top 4-bit item (TOS–1) of the expression stack. The
pointer is automatically pre-incremented if a nibble is
moved onto the stack or post-decremented if a nibble is
removed from the stack. Every post-decrement operation
moves the item (TOS–1) to the TOS register before the SP
is decremented. After a reset the stack pointer has to be
initialized with ” >SP S0 ” to allocate the start address of
the expression stack area.
The 4-bit wide condition code register contains the
branch, the carry and the interrupt enable flag. These bits
indicate the current state of the CPU. The CCR flags are
set or reset by ALU operations. The instructions
SET_BCF, TOG_BF, CCR! and DI allow direct
manipulation of the condition code register.
Carry/Borrow (C)
The carry/borrow flag indicates that the borrowing or
carrying out of arithmetic logic unit ( ALU ) occurred
during the last arithmetic operation. During shift and
rotate operations, this bit is used as a fifth bit. Boolean
operations have no affect on the C-flag.
Return Stack Pointer (RP)
The return stack pointer points to the top element of the
12-bit wide return stack. The pointer automatically pre-
increments if an element is moved onto the stack, or it
post-decrements if an element is removed from the stack.
The return stack pointer increments and decrements in
steps of 4. This means that every time a 12-bit element
is stacked, a 4-bit RAM location is left unwritten. This
location is used by the qFORTH compiler to allocate 4-bit
variables. After a reset the return stack pointer has to be
initialized via ”>RP FCh ”.
Branch (B)
The branch flag controls the conditional program
branching. Should the branch flag have been set by a
previous instruction a conditional branch will cause a
jump. This flag is affected by arithmetic, logic, shift, and
rotate operations.
Interrupt Enable (I)
The interrupt enable flag globally enables or disables the
triggering of all interrupt routines with the exception of
RAM Address Registers (X and Y)
The X and Y registers are used to address any 4-bit item the non-maskable reset. After a reset or on executing the
in the RAM. A fetch operation moves the addressed DI instruction, the interrupt enable flag is reset thus
nibble onto the TOS. A store operation moves the TOS to disabling all interrupts. The core will not accept any
the addressed RAM location. By using either the further interrupt requests until the interrupt enable flag
pre–increment or post–decrement addressing mode has been set again by either executing an EI, RTI or
arrays in the RAM can be compared, filled or moved.
SLEEP instruction.
Rev. A1, 08-Aug-01
9 (84)
M44C092–H
M44C892–H
2.2.4
ALU
RAM
TOS–1
TOS–2
TOS–3
TOS–4
SP
TOS
ALU
CCR
94 8977
Figure 7. ALU zero-address operations
The 4-bit ALU performs all the arithmetic, logical, shift The MARC4 is a zero address machine, the instructions
and rotate operations with the top two elements of the containing only the operation to be performed and no
expression stack (TOS and TOS–1) and returns the result source or destination address fields. The operations are
to the TOS. The ALU operations affect the carry/borrow implicitly performed on the data placed on the stack.
and branch flag in the condition code register (CCR).
There are one and two byte instructions which are
executed within 1 to 4 machine cycles. A MARC4
machine cycle is made up of two system clock
cycles (SYSCL). Most of the instructions are only one
byte long and are executed in a single machine cycle. For
more information refer to the ”MARC4 Programmer’s
Guide”.
2.2.5
I/O Bus
The I/O ports and the registers of the peripheral modules
are I/O mapped. All communication between the core and
the on-chip peripherals takes place via the I/O bus and the
associated I/O control. With the MARC4 IN and OUT
instructions the I/O bus allows a direct read or write
access to one of the 16 primary I/O addresses. More about
the I/O access to the on-chip peripherals is described in
the section ”Peripheral Modules”. The I/O bus is internal
and is not accessible by the customer on the final micro-
controller device, but it is used as the interface for the
MARC4 emulation (see also the section ”Emulation”).
2.2.7
Interrupt Structure
The MARC4 can handle interrupts with eight different
priority levels. They can be generated from the internal
and external interrupt sources or by a software interrupt
from the CPU itself. Each interrupt level has a hard-wired
priority and an associated vector for the service routine in
the ROM (see table 2). The programmer can postpone the
2.2.6
Instruction Set
The MARC4 instruction set is optimized for the high level processing of interrupts by resetting the interrupt enable
programming language qFORTH. Many MARC4 flag (I) in the CCR. An interrupt occurrence will still be
instructions are qFORTH words. This enables the registered, but the interrupt routine only started after the
compiler to generate a fast and compact program code. I flag is set. All interrupts can be masked, and the priority
The CPU has an instruction pipeline allowing the individually software configured by programming the
controller to prefetch an instruction from ROM at the appropriate control register of the interrupting module.
same time as the present instruction is being executed. (see section ”Peripheral Modules”).
10 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
INT7
INT7 active
7
6
5
4
3
2
1
0
RTI
INT5
INT5 active
RTI
INT3
INT2
INT3 active
RTI
INT2 active
INT2 pending
RTI
SWI0
INT0 pending
INT0 active
RTI
Main /
Autosleep
Main /
Autosleep
Time
94 8978
Figure 8. Interrupt handling
Interrupt Processing
service routines is inhibited but not the logging of the
interrupt requests in the interrupt pending register. The
execution of the interrupt is delayed until the interrupt
enable flag is set again. Note that interrupts are only lost
if an interrupt request occurs while the corresponding bit
in the pending register is still set (i.e., the interrupt service
routine is not yet finished).
For processing the eight interrupt levels, the MARC4
includes an interrupt controller with two 8-bit wide
”interrupt pending” and ”interrupt active” registers. The
interrupt controller samples all interrupt requests during
every non-I/O instruction cycle and latches these in the
interrupt pending register. If no higher priority interrupt It should also be noted that automatic stacking of the RBR
is present in the interrupt active register, it signals the
CPU to interrupt the current program execution. If the
interrupt enable bit is set, the processor enters an interrupt
acknowledge cycle. During this cycle a short call
(SCALL) instruction to the service routine is executed
and the current PC is saved on the return stack. An
interrupt service routine is completed with the RTI
instruction. This instruction sets the interrupt enable flag,
is not carried out by the hardware and so if ROM banking
is used, the RBR must be stacked on the expression stack
by the application program and restored before the RTI.
After a master reset (power-on, brown-out or watchdog
reset), the interrupt enable flag and the interrupt pending
and interrupt active register are all reset.
Interrupt Latency
resets the corresponding bits in the interrupt The interrupt latency is the time from the occurrence of
pending/active register and fetches the return address the interrupt to the interrupt service routine being
from the return stack to the program counter. When the activated. In MARC4 this is extremely short (taking
interrupt enable flag is reset (triggering of interrupt between 3 to 5 machine cycles depending on the state of
routines are disabled), the execution of new interrupt the core).
Rev. A1, 08-Aug-01
11 (84)
M44C092–H
M44C892–H
Table 3 Interrupt priority table
Interrupt Priority ROM Address
Interrupt Opcode
C8h (SCALL 040h)
D0h (SCALL 080h)
Function
Software interrupt (SWI0)
External hardware interrupt, any edge at BP52
or BP53
INT0
INT1
lowest
|
040h
080h
INT2
INT3
|
|
0C0h
100h
D8h (SCALL 0C0h)
E8h (SCALL 100h)
Timer 1 interrupt
SSI interrupt or external hardware interrupt at
BP40 or BP43
INT4
INT5
INT6
|
|
↓
140h
180h
1C0h
E8h (SCALL 140h)
F0h (SCALL 180h)
F8h (SCALL 1C0h)
Timer 2 interrupt
Timer 3 interrupt
External hardware interrupt, at any edge at
BP50 or BP51
INT7
highest
1E0h
FCh (SCALL 1E0h)
Voltage monitor (VM) interrupt
Table 4 Hardware interrupts
Interrupt
Interrupt Mask
Register Bit
Interrupt Source
INT1
P5CR
P52M1, P52M2
P53M1, P53M2
Any edge at BP52
any edge at BP53
INT2
INT3
INT4
INT5
T1M
SISC
T2CM
T3CM1
T3CM2
T3C
T1IM
SIM
T2IM
T3IM1
T3IM2
T3EIM
Timer 1
SSI buffer full / empty or BP40/BP43 interrupt
Timer 2 compare match / overflow
Timer 3 compare register 1 match
Timer 3 compare register 2 match
Timer 3 edge event occurs (T3I)
INT6
INT7
P5CR
P50M1, P50M2
P51M1, P51M2
Any edge at BP50,
any edge at BP51
External / internal voltage monitoring
VCM
VIM
Software Interrupts
2.3 Master Reset
The master reset forces the CPU into a well-defined
condition. It is unmaskable and is activated independent
of the current program state. It can be triggered by either
initial supply power-up, a short collapse of the power sup-
ply, brown-out detection circuitry, watchdog time-out, or
an external input clock supervisor stage (see figure 9). A
master reset activation will reset the interrupt enable flag,
the interrupt pending register and the interrupt active
register. During the power-on reset phase the I/O bus con-
trol signals are set to ’reset mode’ thereby initializing all
on-chip peripherals. All bidirectional ports are set to input
mode. Attention: During any reset phase, the BP20/NTE
The programmer can generate interrupts by using the
software interrupt instruction (SWI) which is supported
in qFORTH by predefined macros named SWI0...SWI7.
The software triggered interrupt operates exactly like any
hardware triggered interrupt. The SWI instruction takes
the top two elements from the expression stack and writes
the corresponding bits via the I/O bus to the interrupt
pending register. Therefore, by using the SWI instruction,
interrupts can be re-prioritized or lower priority processes
scheduled for later execution.
Hardware Interrupts
input is driven towards V by a strong pull-up transistor.
DD
In the M44C092–H , there are eleven hardware interrupt Releasing the reset results in a short call instruction
sources with seven different levels. Each source can be (opcode C1h) to the ROM address 008h. This activates
masked individually by mask bits in the corresponding the initialization routine $RESET which in turn has to
control registers. An overview of the possible hardware initialize all necessary RAM variables, stack pointers and
configurations is shown in table 4.
peripheral configuration registers (see table 7).
12 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
V
DD
Pull-up
CL
Reset
timer
Internal
reset
NRST
res
CL=SYSCL/4
V
DD
Power–on
reset
V
SS
V
DD
Brown–out
detection
V
SS
Watch–
dog
CWD
res
Ext. clock
supervisor
ExIn
13752
Figure 9. Reset configuration
reached. A reset condition will also be generated should
the supply voltage drop momentarily below the minimum
operating level except when a power down mode is
activated (the core is in SLEEP mode and the peripheral
clock is stopped). In this power-down mode the brown-
out detection is disabled.
2.3.1
Power-on Reset and Brown-out
Detection
The M44C092–H / M44C892–H has a fully integrated
power-on reset and brown-out detection circuitry. For re-
set generation no external components are needed .
These circuits ensure that the core is held in the reset state Two values for the brown-out voltage threshold are
until the minimum operating supply voltage has been programmable via the BOT-bit in the SC-register.
V
DD
2.0 V
1.7 V
t
t
d
CPU
Reset
BOT = ’1’
BOT = ’0’
t
t
d
d
CPU
Reset
13753
t = 1.5 ms (typically)
d
BOT = 1, low brown-out voltage threshold. (1.7 V) is reset value.
BOT = 0, high brown-out voltage threshold (2.0 V).
Figure 10. Brown-out detection
Rev. A1, 08-Aug-01
13 (84)
M44C092–H
M44C892–H
A power-on reset pulse is generated by a V rise across
the default BOT voltage level (1.7 V). A brown-out reset
DD
2.4 Voltage Monitor
The voltage monitor consists of a comparator with
internal voltage reference. It is used to supervise the
supply voltage or an external voltage at the VMI-pin. The
comparator for the supply voltage has three internal
programmable thresholds one lower threshold (2.2 V),
one middle threshold (2.6 V). and one higher threshold
(3.0 V). For external voltages at the VMI-pin, the
pulse is generated when V falls below the brown-out
DD
voltage threshold. Two values for the brown-out voltage
threshold are programmable via the BOT-bit in the
SC-register. When the controller runs in the upper supply
voltage range with a high system clock frequency, the
high threshold must be used. When it runs with a lower
system clock frequency, the low threshold and a wider
supply voltage range may be chosen. For further details,
see the electrical specification and the SC-register
description for BOT programming.
comparator threshold is set to V = 1.3 V. The VMS-bit
BG
indicates if the supervised voltage is below (VMS = 0) or
above (VMS = 1) this threshold. An interrupt can be
generated when the VMS-bit is set or reset to detect a
rising or falling slope. A voltage monitor interrupt (INT7)
is enabled when the interrupt mask bit (VIM) is reset in
the VMC-register.
2.3.2
Watchdog Reset
The watchdog’s function can be enabled at the WDC-reg-
ister and triggers a reset with every watchdog counter
overflow. To supress the watchdog reset, the watchdog
counter must be regularly reset by reading the watchdog
register address (CWD).
V
DD
Voltage monitor
INT7
OUT
BP41/
VMI
IN
The CPU reacts in exactly the same manner as a reset
stimulus from any of the above sources.
2.3.3
External Clock Supervisor
The external input clock supervisor function can be
enabled if the external input clock is selected within the
CM- and SC-registers of the clock module.
VMC :
VM2 VM1 VM0 VIM
VMST :
Figure 11. Voltage monitor
VMS
–
–
res
13754
The CPU reacts in exactly the same manner as a reset
stimulus from any of the above sources.
14 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
2.4.1
Voltage Monitor Control / Status Register
Primary register address: ’F’hex
Bit 3
Bit 2
Bit 1
Bit 0
VMC: Write
VMST: Read
VM2
VM1
VM0
VIM
Reset value: 1111b
Reset value: xx11b
–––
–––
reserved
VMS
VM2: Voltage monitor Mode bit 2
VM1: Voltage monitor Mode bit 1
VM0: Voltage monitor Mode bit 0
VM2 VM1 VM0
Function
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Disable voltage monitor
External (VIM-input), internal reference threshold (1.3 V), interrupt with negative slope
Not allowed
External (VMI-input), internal reference threshold (1.3 V), interrupt with positive slope
Internal (supply voltage), high threshold (3.0 V), interrupt with negative slope
Internal (supply voltage), middle threshold (2.6 V), interrupt with negative slope
Internal (supply voltage), low threshold (2.2 V), interrupt with negative slope
Not allowed
VIM Voltage Interrupt Mask bit
VIM = 0, voltage monitor interrupt is enabled
VIM = 1, voltage monitor interrupt is disabled
VMS Voltage Monitor Status bit
VMS = 0, the voltage at the comparator input is below Vref
VMS = 1, the voltage at the comparator input is above Vref
Low threshold
VMS = 1
DD
Middle threshold
High threshold
V
3.0 V
2.6 V
2.2 V
Low threshold
Middle threshold
High threshold
VMS = 0
13755
Figure 12. Internal supply voltage supervisor
Internal reference level
Interrupt positive slope
VMI
Negative slope
VMS = 1
VMS = 1
VMS = 0
1.3 V
VMS = 0
Positive slope
t
13756
Interrupt negative slope
Figure 13. External input voltage supervisor
Rev. A1, 08-Aug-01
15 (84)
M44C092–H
M44C892–H
configuration, the RC-oscillator 2 frequency can be
maintained stable to within a tolerance of 15% over the
full operating temperature and voltage range.
2.5 Clock Generation
2.5.1
Clock Module
The clock module is programmable via software with the
clock management register (CM) and the system
configuration register (SC). The required oscillator
configuration can be selected with the OS1-bit and the
OS0-bit in the SC-register. A programmable 4-bit divider
stage allows the adjustment of the system clock speed. A
special feature of the clock management is that an
external oscillator may be used and switched on and off
via a port pin for the power-down mode. Before the
external clock is switched off, the internal RC-oscillator
1 must be selected with the CCS-bit and then the SLEEP
mode may be activated. In this state an interrupt can wake
up the controller with the RC-oscillator, and the external
The M44C092–H / M44C892–H contains a clock module
with different internal oscillator types: two
4
RC-oscillators, one 4-MHz crystal oscillator and one
32-kHz crystal oscillator. The pins OSC1 and OSC2 are
the interface to connect a crystal either to the 4-MHz, or
to the 32-kHz crystal oscillator. OSC1 can be used as
input for external clocks or to connect an external
trimming resistor for the RC-oscillator 2. All necessary
circuitry except the crystal and the trimming resistor is
integrated on-chip. One of these oscillator types or an
external input clock can be selected to generate the
system clock (SYSCL).
In applications that do not require exact timing, it is oscillator can be activated and selected by software. A
possible to use the fully integrated RC-oscillator 1 synchronization stage avoids too short clock periods if the
without any external components. The RC-oscillator 1 clock source or the clock speed is changed. If an external
center frequency tolerance is better than 50%. The input clock is selected, a supervisor circuit monitors the
RC-oscillator 2 is a trimmable oscillator whereby the external input and generates a hardware reset if the
oscillator frequency can be trimmed with an external external clock source fails or drops below 500 kHz for
resistor attached between OSC1 and V . In this more than 1 msec.
DD
RC
oscillator 1
Ext. clock
ExIn
OSC1
SYSCL
Oscin
ExOut
Stop
*
IN1
IN2
RCOut1
Stop Control
RC oscillator2
RTrim
Cin
RCOut2
Stop
/2
/2
/2
/2
4–MHz oscillator
Oscin
Oscout
Divider
4Out
Stop
32–kHz oscillator
Oscin
OSC2
Oscout
Oscout
32Out
Sleep
WDL
*
*
Osc–Stop
Cin/16
32 kHz
SUBCL
13757
CM: NSTOP CCS
CSS1 CSS0
mask option
SC:
BOT
– – –
OS1
OS0
Figure 14. Clock module
Table 5 Clock modes
Mode
Clock Source for SYSCL
CCS = 1 CCS = 0
Clock Source for SUBCL
OS1 OS0
1
2
1
0
1
1
RC-oscillator 1 (intern)
RC-oscillator 1 (intern)
External input clock
RC-oscillator 2 with
C
C
/ 16
/ 16
in
in
external trimming resistor
3
4
1
0
0
0
RC-oscillator 1 (intern)
RC-oscillator 1 (intern)
4-MHz oscillator
32-kHz oscillator
C
/ 16
in
32 kHz
16 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
The clock module generates two output clocks. One is the
system clock (SYSCL) and the other the periphery
(SUBCL). The SYSCL can supply the core and the
peripherals and the SUBCL can supply only the
peripherals with clocks. The modes for clock sources are
programmable with the OS1-bit and OS0-bit in the SC-
register and the CCS-bit in the CM-register.
Ext. input clock
RcOut1
ExOut
OSC1
OSC2
Ext.
Clock
ExIn
Osc–Stop
Stop
CCS
Res
Clock monitor
2.5.2
Oscillator Circuits and External
Clock Input Stage
13759
Figure 16. External input clock
The M44C092–H / M44C892–H series consists of four
different internal oscillators: two RC-oscillators, one
4-MHz crystal oscillator, one 32-kHz crystal oscillator
and one external clock input stage.
OS1 OS0 CCS
Supervisor Reset Output
(Res)
enable
disable
disable
1
1
x
1
1
0
0
1
x
RC-Oscillator 1 Fully Integrated
For timing insensitive applications, it is possible to use
the fully integrated RC oscillator 1. It operates without
any external components and saves additional costs. The
RC–oscillator 1 center frequency tolerance is better than
50% over the full temperature and voltage range. The
basic center frequency of the RC-oscillator 1 is
RC-Oscillator 2 with External Trimming
Resistor
The RC-oscillator 2 is a high resolution trimmable
oscillator whereby the oscillator frequency can be
trimmed with an external resistor between OSC1 and
f [3.8 MHz The RC oscillator 1 is selected by default
O
V . In this configuration, the RC-oscillator 2 frequency
DD
after power–on reset.
can be maintained stable to within a tolerance of 10%
over the full operating temperature and a voltage range
V
DD
from 2.5 V to 6.0 V.
For example: An output frequency at the RC-oscillator 2
of 2 MHz, can be obtained by connecting a resistor
RC
oscillator 1
R
= 360 kΩ (see figures 17).
ext
RcOut1
RcOut1
Osc–Stop
V
DD
Stop
RC
oscillator 2
R
ext
Control
RcOut2
RcOut2
OSC1
13758
R
Trim
Osc–Stop
Stop
Figure 15. RC-oscillator 1
OSC2
External Input Clock
13760
The OSC1 can be driven by an external clock source
provided it meets the specified duty cycle, rise and fall
times and input levels. Additionally the external clock
stage contains a supervisory circuit for the input clock.
Figure 17. RC-oscillator 2
4-MHz Oscillator
The supervisor function is controlled via the OS1, The M44C092–H / M44C892–H 4-MHz oscillator
OS0-bit in the SC–register and the CCS–bit in the CM- options need a crystal or ceramic resonator connected to
register. If the external input clock is missing for more the OSC1 and OSC2 pins to establish oscillation. All the
than 1 ms and CCS = 0 is set in the CM-register, the necessary oscillator circuitry, with the exception of the
supervisory circuit generates a hardware reset..
actual crystal, resonator, C3 and C4 are integrated on-
chip.
Rev. A1, 08-Aug-01
17 (84)
M44C092–H
M44C892–H
32-kHz Oscillator
OSC1
Oscin
4Out
Some applications require long-term time keeping or low
resolution timing. In this case, an on–chip, low power
32-kHz crystal oscillator can be used to generate both the
SUBCL and the SYSCL. In this mode, power
consumption is greatly reduced. The 32-kHz crystal
oscillator can not be stopped while the power-down mode
is in operation.
4Out
4–MHz
oscillator
Stop
*
XTAL
4 MHz
C1
Osc–Stop
Oscout
OSC2
*
*
C2
OSC1
13761
mask option
Oscin
32Out
32Out
*
XTAL
32 kHz
Figure 18. 4-MHz crystal oscillator
32–kHz
oscillator
C1
Oscout
OSC2
C3
C4
*
OSC1
Oscin
*
4Out
4Out
4–MHz
oscillator
Stop
*
C2
Cer.
Res
13763
mask option
C1
Osc–Stop
Figure 20. 32-kHz crystal oscillator
Oscout
OSC2
*
*
2.5.3
Clock Management
C2
13762
mask option
The clock management register controls the system clock
divider and synchronization stage. Writing to this register
triggers the synchronization cycle.
Figure 19. Ceramic resonator
Clock Management Register (CM)
Auxiliary register address: ’3’hex
Bit 3
Bit 2
Bit 1
Bit 0
CM:
NSTOP
CCS
CSS1
CSS0
Reset value: 1111b
NSTOP
Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode
NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode
CCS
Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the
internal RC-oscillator 2 with the external resistor at OSC1 generates SYSCL dependent on
the setting of OS0 and OS1 in the system configuration register
CSS1
CSS0
Core Speed Select 1
Core Speed Select 0
CSS1
CSS0
Divider
Note
0
1
1
0
0
1
0
1
16
8
4
Reset value
2
18 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
System Configuration Register (SC)
Primary register address: ’3’hex
Bit 3
Bit 2
Bit 1
Bit 0
SC: write
BOT
BOT
–––
OS1
OS0
Reset value: 1x11b
Brown-Out Threshold
BOT = 1, low brown-out voltage threshold (1.7 V)
BOT = 0, high brown-out voltage threshold (2.0 V)
OS1
OS0
Oscillator Select 1
Oscillator Select 0
Mode
OS1
OS0
Input for SUBCL
C / 16
Selected Oscillators
RC–oscillator 1 and external input clock
RC-oscillator 1 and RC-oscillator 2
RC-oscillator 1 and 4-MHz crystal oscillator
RC-oscillator 1 and 32-kHz crystal oscillator
1
2
3
4
1
0
1
0
1
1
0
0
in
C
C
/ 16
/ 16
in
in
32 kHz
If the bit CCS = 0 in the CM-register the RC-oscillator 1 always stops.
instruction cycles (for example NOP NOP NOP) between
the IN or OUT command and the SLEEP command.
2.6 Power-down Modes
The total power consumption is directly proportional to
the active time of the µC. For a rough estimation of the
expected average system current consumption, the fol-
lowing formula should be used:
The sleep mode is a shut-down condition which is used to
reduce the average system power consumption in applica-
tions where the µC is not fully utilized. In this mode, the
system clock is stopped. The sleep mode is entered via the
SLEEP instruction. This instruction sets the interrupt en-
able bit (I) in the condition code register to enable all
interrupts and stops the core. During the sleep mode the
peripheral modules remain active and are able to generate
interrupts. The µC exits the sleep mode by carrying out
any interrupt or a reset.
I
(V ,f
) = I
+ (I t
/ t
)
total
DD syscl
Sleep
DD
active total
I
depends on V and f
.
DD
DD
syscl
The M44C092–H / M44C892–H has various power-
down modes. During the sleep mode the clock for the
MARC4 core is stopped. With the NSTOP-bit in the clock
management register (CM) it is programmable if the
The sleep mode can only be kept when none of the inter- clock for the on–chip peripherals is active or stopped dur-
rupt pending or active register bits are set. The application ing the sleep mode. If the clock for the core and the
of the $AUTOSLEEP routine ensures the correct function peripherals is stopped the selected oscillator is switched
of the sleep mode. For standard applications use the $AU- off. An exception is the 32-kHz oscillator, if it is selected
TOSLEEP routine to enter the power-down mode. Using it runs continously independent of the NSTOP-bit. If the
the SLEEP instruction instead of the $AUTOSLEEP fol- oscillator is stopped or the 32 kHz oscillator is selected,
lowing an I/O instruction requires to insert 3 non I/O power consumption is extremely low.
Table 6 Power-down modes
Mode
CPU Core Osc-Stop* Brown-out
Function
RC-Oscillator 1
RC-Oscillator 2
4-MHz Oscillator
32-kHz
Oscillator
External Input
Clock
Active
Power-down
SLEEP
RUN
SLEEP
SLEEP
NO
NO
YES
Active
Active
STOP
RUN
RUN
STOP
RUN
RUN
RUN
YES
YES
STOP
* Osc-Stop = SLEEP & NSTOP & WDL
Rev. A1, 08-Aug-01
19 (84)
M44C092–H
M44C892–H
primary register. Accessing the auxiliary register is per-
formed with the same instruction preceded by writing the
module address into the auxiliary switching module. Byte
wide registers are accessed by multiple IN- (or OUT-)
3 Peripheral Modules
3.1 Addressing Peripherals
Accessing the peripheral modules takes place via the I/O instructions. For more complex peripheral modules, with
bus (see figure 21). The IN or OUT instructions allow di- a larger number of registers, extended addressing is used.
rect addressing of up to 16 I/O modules. A dual register In this case a bank of up to 16 subport registers are indi-
addressing scheme has been adopted to enable direct ad- rectly addressed with the subport address. The first
dressing of the ”primary register”. To address the OUT-instruction writes the subport address to the sub-
”auxiliary register”, the access must be switched with an address register, the second IN- or OUT-instruction reads
”auxiliary switching module”. Thus a single IN (or OUT) data from or writes data to the addressed subport.
to the module address will read (or write) into the module
Module M1
Module ASW
Module M2
Module M3
(Address Pointer)
Bank of
Primary Regs.
Aux. Reg.
Subaddress Reg.
Subport Fh
Subport Eh
Auxiliary Switch
Module
5
1
Subport 1
Primary Reg.
6
Primary Reg.
Primary Reg.
3
Subport 0
2
4
I/O bus
to other modules
Dual Register
Access
Indirect Subport
Access
Single Register
Access
(Primary Register Write)
(Subport Register Write)
(Primary Register Write)
3
Prim._Data Address(M2) OUT
6
1
2
Prim._Data Address(M3) OUT
Addr.(SPort) Addr.(M1) OUT
SPort_Data Addr.(M1) OUT
( Auxiliary Register Write )
(Primary Register Read)
Address(M3) IN
4
5
(Subport Register Read)
Address(M2) Address(ASW) OUT
6
Aux._Data
Address(M2) OUT
1
2
Addr.(SPort) Addr.(M1) OUT
Addr.(M1) IN
Example of
qFORTH
Program
Code
(Primary Register Read)
Address(M2) IN
3
(Subport Register Write Byte)
1
2
2
Addr.(SPort) Addr.(M1) OUT
SPort_Data(lo) Addr.(M1) OUT
SPort_Data(hi) Addr.(M1) OUT
(Auxiliary Register Read)
Address(M2) Address(ASW) OUT
Address(M2) IN
4
5
(Auxiliary Register Write Byte)
(Subport Register Read Byte)
Addr.(SPort) Addr.(M1) OUT
4
5
5
1
2
2
Address(M2) Address(ASW) OUT
Aux._Data(lo) Address(M2) OUT
Aux._Data(hi) Address(M2) OUT
(hi)
Addr.(M1) IN
Addr.(M1) IN
(lo)
Auxiliary Switch Module Address
Addr.(ASW) =
Aux._Data (hi) = data to be written into Auxiliary Register(high nibble)
data to be written into SubPort (low nibble)
Addr.(Mx) = Module Mx Address
Addr.(SPort) = Subport Address
SPort_Data(lo) =
SPort_Data(hi) = data to be written into Subport (high nibble)
(lo) = SPort_Data (low nibble)
(hi) = SPort_Data (high nibble)
data to be written into Primary Register.
Prim._Data =
Aux._Data = data to be written into Auxiliary Register
13357
_
(
)
y
g
(
)
Aux. Data lo = data to be written into Auxiliar Re ister low nibble
Figure 21. Example of I/O addressing
20 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Table 7 Peripheral addresses
Port Address
Name
Write
/Read
Reset Value
Register Function
Module
Type
See
Page
1
P1DAT
W/R
W/R
W
1xx1b
1111b
Port 1 – data register / input data
Port 2 – data register / pin data
Port 2 – control register
M3
M2
22
23
23
19
29
18
26
26
25
25
27
27
20
2
P2DAT
P2CR
SC
Aux.
3
1111b
W
1x11b
Port 3 – system configuration register
Watchdog reset
M3
M3
M2
M2
CWD
CM
R
xxxxb
Aux.
W/R
W/R
W
1111b
Port 3 – clock management register
Port 4 – data register / pin data
Port 4 – control register (byte)
Port 5 – data register / pin data
Port 5 – control register (byte)
Port 6 – data register / pin data
Port 6 – control register (byte)
Data to Timer 1/2 subport
4
P4DAT
P4CR
P5DAT
P5CR
P6DAT
P6CR
T12SUB
1111b
Aux.
5
1111 1111b
1111b
W/R
W
M2
M2
M1
Aux.
6
1111 1111b
1xx1b
W/R
W
Aux
7
1111b
W
––––
Subport address
0
1
T2C
W
W
0000b
1111b
1111b
0000b
1111b
1111 1111b
––––
Timer 2 control register
Timer 2 mode register 1
Timer 2 mode register 2
Timer 2 compare mode register
Timer 2 compare register 1
Timer 2 compare register 2 (byte)
Reserved
M1
M1
M1
M1
M1
M1
37
38
39
40
40
40
T2M1
T2M2
T2CM
T2CO1
T2CO2
––––
2
W
3
W
4
W
5
W
6
––––
––––
W
7
––––
––––
Reserved
8
T1C1
T1C2
WDC
1111b
x111b
1111b
Timer 1 control register 1
Timer 1 control register 2
Watchdog control register
Reserved
M1
M1
M1
30
30
31
9
W
A
B-F
W
8
9
ASW
STB
W
W
1111b
xxxx xxxxb
xxxx xxxxb
1111b
Auxiliary / switch register
Serial transmit buffer (byte)
Serial receive buffer (byte)
Serial interface control register 1
Serial interface status / control register
Serial interface control register 2
Data to / from Timer 3 subport
ASW
M2
20
60
61
59
60
59
20
SRB
R
Aux.
Aux.
SIC1
SISC
SIC2
T3SUB
W
A
B
W/R
W
1x11b
M2
M1
1111b
W/R
––––
Subport address
0
1
T3M
W
W
W
W
W
R
1111b
1111b
Timer 3 mode register
M1
M1
M1
M1
M1
M1
M1
48
49
50
50
51
51
51
T3CS
Timer 3 clock select register
Timer 3 compare mode register 1
Timer 3 compare mode register 2
Timer 3 compare register 1 (byte)
Timer 3 capture register (byte)
Timer 3 compare register 2 (byte)
Reserved
2
T3CM1
T3CM2
T3CO1
T3CP
0000b
3
0000b
4
1111 1111b
xxxx xxxxb
1111 1111b
––––
4
5
T3CO2
W
6–F
C
T3C
W
R
0000b
Timer 3 control register
Timer 3 status register
M3
M3
48
49
T3ST
–––
x000b
D
E
F
––––
Reserved
–––
––––
Reserved
VMC
VMST
W
R
1111b
Voltage monitor control register
Voltage monitor status register
M3
M3
15
15
xx11b
Rev. A1, 08-Aug-01
21 (84)
M44C092–H
M44C892–H
3.2.1
Bidirectional Port 1
3.2 Bidirectional Ports
In Port 1 the data direction register is not independently
software programmable, the direction of the complete
port being switched automatically when an I/O
instruction occurs (see figure 22). The port is switched to
output mode via an OUT instruction and to input via an
IN instruction. The data written to a port will be stored
into the output data latches and appears immediately at
the port pin following the OUT instruction. After RESET
all output latches are set to ’1’ and the port is switched to
input mode. An IN instruction reads the condition of the
associated pins.
With the exception of Port 1 and Port 6, all other ports (2,
4 and 5) are 4 bits wide. Port 1 and Port 6 have a data width
of 2 bits (bit 0 and bit 3). All ports may be used for data
input or output. All ports are equipped with Schmitt trig-
ger inputs and a variety of mask options for open drain,
open source, full complementary outputs, pull up and pull
down transistors. All Port Data Registers (PxDAT) are I/O
mapped to the primary address register of the respective
port address and the Port Control Register (PxCR), to the
corresponding auxiliary register.
Note:
There are five different directional ports available:
Care must be taken when switching the bidirectional port
from output to input. The capacitive pin loading at this
port in conjunction with the high resistance pull-ups may
cause the CPU to read the contents of the output data
register rather than the external input state. To avoid this,
one should use either of the following programming
techniques:
Port 1 2-bit wide bidirectional ports with automatic full
bus width direction switching.
Port 2 4-bit wide bitwise-programmable I/O port.
Port 5 4-bit wide bitwise-programmable bidirectional
port with optional strong pull-ups and program-
mable interrupt logic.
Use two IN-instructions and DROP the first data
nibble. The first IN switches the port from output
to input and the DROP removes the first invalid
nibble. The second IN reads the valid pin state.
Port 4 4-bit wide bitwise-programmable bidirectional
port also provides the I/O interface to Timer 2,
SSI, voltage monitor input and external interrupt
input.
Use an OUT-instruction followed by an IN–
instruction. Via the OUT-instruction, the
capacitive load is charged or discharged depend-
Port 6 2-bit wide bitwise-programmable bidirectional
port also provides the I/O interface to Timer 3
and external interrupt input.
ing on the optional pull-up / pull-down
configuration. Write a ”1” for pins with pull-up
resistors and a ”0” for pins with pull-down
resistors.
V
DD
I/O Bus
*
Static
pull-up
(Data out)
Pull-up
*
Q
D
BP1y
P1DATy
R
*
V
DD
Reset
(Direction)
*
OUT
S
Q
Static
pull-down
*) Mask options
Pull-down
IN
R
NQ
14021
Master reset
Figure 22. Bidirectional Port 1
22 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
condition when in output mode. This is a useful feature
for self testing and for serial bus applications.
3.2.2
Bidirectional Port 2
This, and all other bidirectional ports include a bitwise
programmable Control Register (P2CR), which enables Port 2 however, has an increased drive capability and an
the individual programming of each port bit as input or additional low resistance pull-up/-down transistor mask
output. It also opens up the possibility of reading the pin option.
V
DD
I/O Bus
Pull-up
*
Static
Pull-up
*
(Data out)
*
*
I/O Bus
D
Q
P2DATy
S
BP2y
V
DD
Master reset
I/O Bus
Static
Pull-down
*
S
*
Q
D
P2CRy
Pull-down
13388
* Mask options
Figure 23. Bidirectional Port 2
(Direction)
Port 2 Data Register (P2DAT)
Primary register address: ’2’hex
Bit 3 *
Bit 2
Bit 1
Bit 0
P2DAT
P2DAT3 P2DAT2 P2DAT1 P2DAT0
Reset value: 1111b
* Bit 3 –> MSB, Bit 0 –> LSB
Port 2 Control Register (P2CR)
Auxiliary register address: ’2’hex
Bit 3
Bit 2
Bit 1
Bit 0
P2CR
P2CR3
P2CR2
P2CR1
P2CR0
Reset value: 1111b
Value: 1111b means all pins in input mode
Code
Function
3 2 1 0
x x x 1
x x x 0
x x 1 x
x x 0 x
x 1 x x
x 0 x x
1 x x x
0 x x x
BP20 in input mode
BP20 in output mode
BP21 in input mode
BP21 in output mode
BP22 in input mode
BP22 in output mode
BP23 in input mode
BP23 in output mode
Rev. A1, 08-Aug-01
23 (84)
M44C092–H
M44C892–H
ther edge. The interrupt configuration and port direction
is controlled by the Port 5 Control Register (P5CR). An
additional low resistance pull–up/–down transistor mask
option provides an internal bus pull–up for serial bus ap-
plications.
3.2.3
Bidirectional Port 5
This, and all other bidirectional ports include a bitwise
programmable Control Register (P5CR), which allows
the individual programming of each port bit as input or
output. It also opens up the possibility of reading the pin
condition when in output mode. This is a useful feature
for self testing and for serial bus applications.
The Port 5 Data Register (P5DAT) is I/O mapped to the
primary address register of address ’5’h and the Port 5
Control Register (P5CR) to the corresponding auxiliary
The port pins can also be used as external interrupt inputs register. The P5CR is a byte-wide register and is config-
(see figures 24 & 25). The interrupts (INT1 and INT6) can ured by writing first the low nibble then the high nibble
be masked or independently configured to trigger on ei- (see section 2.1 ”Addressing peripherals”).
V
V
DD
DD
*
I/O Bus
Pull-up
*
Static
Pull-up
V
DD
(Data out)
*
*
I/O Bus
D
Q
P5DATy
BP5y
V
S
DD
Master reset
IN enable
Static
Pull-down
*
*
Pull-down
* Mask options
Figure 24. Bidirectional Port 5
13359
INT1
INT6
Data in
Data in
BP52
BP51
Bidir. Port
Bidir. Port
IN_Enable
IN_Enable
I/O–bus
I/O–bus
Data in
Bidir. Port
IN_Enable
Data in
BP53
BP50
Bidir. Port
IN_Enable
Decoder
Decoder
Decoder
Decoder
P5CR: P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1
Figure 25. Port 5 external interrupts
13764
24 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Port 5 Data Register (P5DAT)
Primary register address: ’5’hex
Bit 3
Bit 2
Bit 1
Bit 0
P5DAT
P5DAT3
P5DAT2
P5DAT1
P5DAT0
Reset value: 1111b
Port 5 Control Register (P5CR) Byte Write
Auxiliary register address: ’5’hex
Bit 3
Bit 2
P51M1
Bit 6
Bit 1
P50M2
Bit 5
Bit 0
P5CR
First write cycle
P51M2
Bit 7
P50M1
Bit 4
Reset value: 1111b
Reset value: 1111b
Second write cycle
P53M2
P53M1
P52M2
P52M1
P5xM2, P5xM1 – Port 5x Interrupt mode/direction code
Auxiliary Address: ’5’hex First Write Cycle
Function
Second Write Cycle
Function
Code
Code
3 2 1 0
3 2 1 0
x x 1 1 BP50 in input mode – interrupt disabled
x x 0 1 BP50 in input mode – rising edge interrupt
x x 1 0 BP50 in input mode – falling edge interrupt
x x 0 0 BP50 in output mode – interrupt disabled
1 1 x x BP51 in input mode – interrupt disabled
0 1 x x BP51 in input mode – rising edge interrupt
1 0 x x BP51 in input mode – falling edge interrupt
0 0 x x BP51 in output mode – interrupt disabled
x x 1 1 BP52 in input mode – interrupt disabled
x x 0 1 BP52 in input mode – rising edge interrupt
x x 1 0 BP52 in input mode – falling edge interrupt
x x 0 0 BP52 in output mode – interrupt disabled
1 1 x x BP53 in input mode – interrupt disabled
0 1 x x BP53 in input mode – rising edge interrupt
1 0 x x BP53 in input mode – falling edge interrupt
0 0 x x BP53 in output mode – interrupt disabled
Rev. A1, 08-Aug-01
25 (84)
M44C092–H
M44C892–H
3.2.4
Bidirectional Port 4
The bidirectional Port 4 is both a bitwise configurable I/O and SD line have an additional mode to generate an SSI–
port and provides the external pins for the Timer 2, SSI interrupt.
and the voltage monitor input (VMI). As a normal port,
All four Port 4 pins can be individually switched by the
it performs in exactly the same way as bidirectional Port 2
P4CR–register . Figure 26 shows the internal interfaces to
(see figure 26). Two additional multiplexes allow data
bidirectional Port 4.
and port direction control to be passed over to other inter-
nal modules (Timer 2, VM or SSI). The I/O-pins for SC
V
I/O Bus
Intx
DD
*
Static
Pull-up
*
PxMRy
PIn
V
DD
POut
Pull-up
*
*
I/O Bus
D
Q
BPxy
PxDATy
S
V
DD
Master reset
I/O Bus
(Direction)
Static
Pull-down
*
*
S
D
Q
PxCRy
Pull-down
PDir
* Mask options
13360
Figure 26. Bidirectional Port 4 and Port 6
Port 4 Data Register (P4DAT)
Primary register address: ’4’hex
Bit 3
Bit 2
Bit 1
Bit 0
P4DAT
P4DAT3
P4DAT2
P4DAT1
P4DAT0
Reset value: 1111b
Port 4 Control Register (P4CR) Byte Write
Auxiliary register address: ’4’hex
Bit 3
Bit 2
P41M1
Bit 6
Bit 1
P40M2
Bit 5
Bit 0
P4CR
First write cycle
P41M2
Bit 7
P40M1
Bit 4
Reset value: 1111b
Reset value: 1111b
Second write cycle
P43M2
P43M1
P42M2
P42M1
P4xM2, P4xM1 – Port 4x Interrupt mode/direction code
26 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Auxiliary Address: ’4’hex
First Write Cycle
Second Write Cycle
Function
Code
Function
Code
3 2 1 0
3 2 1 0
x x 1 1 BP40 in input mode
x x 1 0 BP40 in output mode
x x 1 1 BP42 in input mode
x x 1 0 BP42 in output mode
x x 0 1 BP40 enable alternate function (SC for SSI)
x x 0 x BP42 enable alternate function (T2O for
Timer 2)
x x 0 0 BP40 enable alternate function (falling
edge interrupt input for INT3)
1 1 x x BP43 in input mode
1 1 x x BP41 in intput mode
1 0 x x BP41 in output mode
1 0 x x BP43 in output mode
0 1 x x BP43 enable alternate function (SD for SSI)
0 1 x x BP41 enable alternate function (VMI for
voltage monitor input)
0 0 x x BP43 enable alternate function (falling
edge interrupt input for INT3)
0 0 x x BP41 enable alternate function (T2I exter-
nal clock input for Timer 2)
–––
–––
over to other internal module (Timer 3). The I/O-pin for
T3I line has an additional mode to generate a Timer 3–in-
terrupt.
3.2.5
Bidirectional Port 6
The bidirectional Port 6 is both a bitwise configurable I/O
port and provides the external pins for the Timer 3. As a
normal port, it performs in exactly the same way as All two Port 6 pins can be individually switched by the
bidirectional Port 6 (see figure 26). Two additional multi- P6CR-register . Figure 26 shows the internal interfaces to
plexes allow data and port direction control to be passed bidirectional Port 6.
Port 6 Data Register (P6DAT)
Primary register address: ’6’hex
Bit 3
Bit 2
Bit 1
Bit 0
P6DAT
P6DAT3
– – –
– – –
P6DAT0
Reset value: 1xx1b
Port 6 Control Register (P6CR)
Auxiliary register address: ’6’hex
Bit 3
Bit 2
Bit 1
Bit 0
P6CR
P63M2
P63M1
P60M2
P60M0
Reset value: 1111b
P6xM2, P6xM1 – Port 6x Interrupt mode/direction code
Auxiliary Address: ’6’hex
Function Code
Write Cycle
Code
Function
3 2 1 0
3 2 1 0
x x 1 1 BP60 in input mode
x x 1 0 BP60 in output mode
1 1 x x BP63 in intput mode
1 0 x x BP63 in output mode
x x 0 x BP60 enable alternate port function (T3O for
Timer 3)
0 x x x BP63 enable alternate port function (T3I for
Timer 3)
Rev. A1, 08-Aug-01
27 (84)
M44C092–H
M44C892–H
3.3 Universal Timer/Counter / Communication Module (UTCM)
The Universal Timer/counter/Communication Module ꢀ Timer 3 is an 8-bit timer/counter with its own input
(UTCM) consists of three timers (Timer 1 ,Timer 2,
(T3I) and output (T3O).
Timer 3) and a Synchronous Serial Interface (SSI).
ꢀ The SSI operates as two wire serial interface or as shift
register for modulation and demodulation. The
modulator and demodulator units work together with
the timers and shift the data bits into or out of the shift
register.
ꢀ Timer 1 is an interval timer that can be used to
generate periodical interrupts and as prescaler for
Timer 2, Timer 3, the serial interface and the watch-
dog function.
There is a multitude of modes in which the timers and the
ꢀ Timer 2 is an 8/12-bit timer with an external clock in- serial interface can work together.
put (T2I) and an output (T2O).
SYSCL
from clock module
SUBCL
Timer 1
NRST
INT2
Watchdog
MUX
MUX
MUX
Interval / Prescaler
Timer 3
T1OUT
Control
Capture 3
Demodu–
lator 3
T3I
8–bit Counter 3
Compare 3/1
Compare 3/2
Modu–
lator 3
T3O
T2O
INT5
Timer 2
TOG3
4–bit Counter 2/1
Modu–
lator 2
Compare 2/1
Control
I/O bus
POUT
T2I
8–bit Counter 2/2
MUX DCG
INT4
Compare 2/2
SSI
TOG2
SCL
Receive–Buffer
8–bit Shift–Register
Transmit–Buffer
SC
SD
MUX
Control
INT3
13765
Figure 27. UTCM block diagram
28 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
power-on reset ! If the watchdog function is not activated,
the timer can be restarted by writing into the T1C1
register with T1RM=1.
3.3.1
Timer 1
The Timer 1 is an interval timer which can be used to gen-
erate periodical interrupts and as prescaler for Timer 2,
Timer 3, the serial interface and the watchdog function.
Timer 1 can also be used as a watchdog timer to prevent
a system from stalling. The watchdog timer is a 3-bit
counter that is supplied by a separate output of Timer 1.
It generates a system reset when the 3-bit counter
overflows. To avoid this, the 3-bit counter must be reset
before it overflows. The application software has to
accomplish this by reading the CWD register.
The Timer 1 consists of a programmable 14-stage divider
that is driven by either SUBCL or SYSCL. The timer
output signal can be used as prescaler clock or as SUBCL
and as source for the Timer 1 interrupt. Because of other
system requirements the Timer 1 output T1OUT is
synchronized with SYSCL. Therefore in the power-down
mode SLEEP (CPU core –> sleep and OSC-Stop –> yes)
the output T1OUT is stopped (T1OUT=0). Nevertheless
the Timer 1 can be active in SLEEP and generate Timer 1
interrupts. The interrupt is maskable via the T1IM bit and
the SUBCL can be bypassed via the T1BP bit of the T1C2
register. The time interval for the timer output can be
programmed via the Timer 1 control register T1C1.
After power-on reset the watchdog must be activated by
software in the $RESET initialization routine. There are
two watchdog modes, in one mode the watchdog can be
switched on and off by software, in the other mode the
watchdog is active and locked. This mode can only be
stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval
for the watchdog reset can be programmed via the
This timer starts running automatically after any watchdog control register (WDC).
SYSCL
SUBCL
WDCL
NRST
INT2
CL1
Prescaler
14 bit
Watchdog
4 bit
MUX
T1CS
T1BP
T1IM
T1OUT
T1MUX
13766
Figure 28. Timer 1 module
T1C1 T1RM T1C2 T1C1 T1C0
3
T1C2 T1BP T1IM
T1MUX
T1IM=0
T1IM=1
Write of the
T1C1 register
INT2
Decoder
MUX for interval timer
T1OUT
Q1 Q2 Q3 Q4 Q5
Q8
Q8
Q11
Q11
Q14
SUBCL
RES
CL1
CL
Q6
Q14
Watchdog
Divider / 8
Decoder
MUX for watchdog timer
RESET
(NRST)
Divider
RESET
2
WDCL
RES
WDC WDL WDR WDT1 WDT0
Read of the
CWD register
Watchdog
mode control
13767
Figure 29. Timer 1 and watchdog
Rev. A1, 08-Aug-01
29 (84)
M44C092–H
M44C892–H
Timer 1 Control Register 1 (T1C1)
Address: ’7’hex – Subaddress: ’8’hex
Bit 3 *
Bit 2
Bit 1
Bit 0
T1C1
T1RM
T1C2
T1C1
T1C0
Reset value: 1111b
* Bit 3 –> MSB, Bit 0 –> LSB
T1RM
Timer 1 Restart Mode
T1RM = 0, write access without Timer 1 restart
T1RM = 1, write access with Timer 1 restart
Note: if WDL = 0, Timer 1 restart is impossible
T1C2
T1C1
T1C0
Timer 1 Control bit 2
Timer 1 Control bit 1
Timer 1 Control bit 0
The three bits T1C[2:0] select the divider for timer 1. The clock management. If the clock management generates
resulting time interval depends on this divider and the the SUBCL, the selected input clock from the RC oscilla-
timer 1 input clock source. The timer input can be sup- tor, 4MHz oscillator or an external clock is divided by 16.
plied by the system clock, the 32kHz oscillator or via the
T1C2 T1C1 T1C0 Divider Time Interval with SUBCL
Time Interval with
SUBCL = 32 kHz
Time Interval with
SYSCL = 2/1 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
SUBCL / 2
SUBCL / 4
61 µs
122 µs
244 µs
1 µs / 2 µs
2 µs / 4 µs
4 µs / 8 µs
8
SUBCL / 8
16
SUBCL / 16
SUBCL / 32
SUBCL / 256
SUBCL / 2048
SUBCL / 16384
488 µs
8 µs / 16 µs
32
0.977 ms
7.812 ms
62.5 ms
500 ms
16 µs / 32 µs
128 µs / 256 µs
1024 µs / 2048 µs
8192 µs / 16384 µs
256
2048
16384
Timer 1 Control Register 2 (T1C2)
Address: ’7’hex – Subaddress: ’9’hex
Bit 3 *
Bit 2
Bit 1
Bit 0
T1C2
– – –
T1BP
T1CS
T1IM
Reset value: x111b
* Bit 3 –> MSB, Bit 0 –> LSB
T1BP
T1CS
T1IM
Timer 1 SUBCL ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
Timer 1 input Clock Select
T1CS = 1, CL1 = SUBCL (see figure 28)
T1CS = 0, CL1 = SYSCL (see figure 28)
Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
30 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Watchdog Control Register (WDC)
Address: ’7’hex – Subaddress: ’A’hex
Bit 3 *
Bit 2
Bit 1
Bit 0
WDC
WDL
WDR
WDT1
WDT0
Reset value: 1111b
* Bit 3 –> MSB, Bit 0 –> LSB
WDL
WDR
WatchDog Lock mode
WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit
WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no effect. After the
WDL-bit is cleared, the watchdog is active until a system reset or power-on reset occurs.
WatchDog Run and stop mode
WDR = 1, the watchdog is stopped / disabled
WDR = 0, the watchdog is active / enabled
WDT1
WDT0
WatchDog Time 1
WatchDog Time 0
Both these bits control the time interval for the watchdog reset
WDT1 WDT0 Divider
Delay Time to Reset with
SUBCL = 32 kHz
Delay Time to Reset with
SYSCL = 2 / 1 MHz
0
0
1
1
0
1
0
1
512
2048
16384
131072
15.625 ms
62.5 ms
0.5 s
0.256 ms / 0.512 ms
1.024 ms / 2.048 ms
8.2 ms / 16.4 ms
4 s
65.5 ms / 131 ms
interface. The external input clock T2I is not synchro-
nized with SYSCL. Therefore it is possible to use Timer 2
with a higher clock speed than SYSCL. Furthermore with
that input clock the Timer 2 operates in the power-down
mode SLEEP (CPU core –> sleep and OSC–Stop –> yes)
as well as in the POWER-DOWN (CPU core –> sleep and
OSC–Stop –> no). All other clock sources supplied no
clock signal in SLEEP. The 4-bit counter stages of Timer
2 have an additional clock output (POUT).
3.3.2
Timer 2
Features: 8/12 bit timer for
ꢀ
I
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d
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generation
ꢀ
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a
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-
r
a
t
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r
a
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o
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ꢀ Manchester and Biphase modulation together with the
SSI
Its output has a modulator stage that allows the generation
of pulses as well as the generation and modulation of
carrier frequencies. The Timer 2 output can modulate
with the shift register data output to generate Biphase- or
Manchester-code.
ꢀ Carrier frequency generation and modulation
together with the SSI
Timer 2 can be used as interval timer for interrupt
generation, as signal generator or as baud-rate generator
and modulator for the serial interface. It consists of a 4-bit
and an 8-bit up counter stage which both have compare
registers. The 4-bit counter stages of Timer 2 are
cascadable as 12-bit timer or as 8-bit timer with 4-bit
prescaler. The timer can also be configured as 8-bit timer
and separate 4-bit prescaler.
If the serial interface is used to modulate a bitstream, the
4-bit stage of Timer 2 has a special task. The shift register
can only handle bitstream lengths divisible by 8. For other
lengths, the 4-bit counter stage can be used to stop the
modulator after the right bitcount is shifted out.
If the timer is used for carrier frequency modulation, the
The Timer 2 input can be supplied via the system clock, 4-bit stage works together with an additional 2-bit duty
the external input clock (T2I), the Timer 1 output clock, cycle generator like a 6-bit prescaler to generate carrier
the Timer 3 output clock or the shift clock of the serial frequency and duty cycle. The 8-bit counter is used to en-
Rev. A1, 08-Aug-01
31 (84)
M44C092–H
M44C892–H
able and disable the modulator output for a programmable Timer 2 compare data values
count of pulses.
The Timer 2 has a 4-bit compare register (T2CO1) and an
For programming the time interval, the timer has a 4-bit
and an 8-bit compare register. For programming the timer
function, it has four mode and control registers. The
comparator output of stage 2 is controlled by a special
compare mode register (T2CM). This register contains
mask bits for the actions (counter reset, output toggle,
timer interrupt) which can be triggered by a compare
8-bit compare register (T2CO2). Both these compare
registers are cascadable as a 12-bit compare register, or
8-bit compare register and 4-bit compare register.
For 12-bit compare data value: m = x +1 0 ≤ x ≤ 4095
For 8-bit compare data value: n = y +1 0 ≤ y ≤ 255
match event or the counter overflow. This architecture en- For 4-bit compare data value: l = z +1 0 ≤ z ≤ 15
ables the timer function for various modes.
I/O–bus
P4CR
T2M1
T2M2
T2I
DCGO
8–bit Counter 2/2
SYSCL
T1OUT
TOG3
SCL
T2O
CL2/1
CL2/2
4–bit Counter 2/1
DCG
OUTPUT
RES
OVF1
POUT
RES
OVF2
TOG2
M2
to
T2C
Compare 2/1
Control
Compare 2/2
Modulator 3
MOUT
Biphase–,
INT4
CM1
Manchester–
modulator
Timer 2
modulator
output–stage
T2CO1
T2CM
T2CO2
SSI POUT
I/O–bus
SO
Control
SSI
SSI
13776
Figure 30. Timer 2
Timer 2 Modes
Mode 1: 12-bit compare counter
POUT (CL2/1 /16)
CL2/1
OVF2
4-bit counter
4-bit compare
4-bit register
DCG
8-bit counter
TOG2
INT4
RES
RES
CM2
8-bit compare
CM1
Timer 2
output mode
and T2OTM–bit
8-bit register
T2D1, 0
T2RM
T2OTM
T2IM
T2CTM
13778
Figure 31. 12-bit compare counter
The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A compare match signal of the 4-bit and
the 8-bit stage generates the signal for the counter reset, toggle flip-flop or interrupt. The compare action is program-
mable via the compare mode register (T2CM). The 4-bit counter overflow (OVF1) supplies the clock output (POUT)
with clocks. The duty cycle generator (DCG) has to be bypassed in this mode.
32 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Mode 2: 8-bit compare counter with 4-bit programmable prescaler
DCGO
POUT
CL2/1
OVF2
CM2
4-bit counter
4-bit compare
4-bit register
DCG
8-bit counter
8-bit compare
8-bit register
TOG2
INT4
RES
RES
CM1
Timer 2
output mode
and T2OTM–bit
T2D1, 0
T2RM
T2OTM
T2IM
T2CTM
13778
Figure 32. 8-bit compare counter
The 4-bit stage is used as programmable prescaler for the 8-bit counter stage. In this mode, a duty cycle stage is also
available. This stage can be used as an additional 2-bit prescaler or for generating duty cycles of 25%, 33% and 50%.
The 4-bit compare output (CM1) supplies the clock output (POUT) with clocks.
Mode 3/4: 8-bit compare counter and 4-bit programmable prescaler
DCGO
T2I
CL2/2
OVF2
CM2
DCG
8-bit counter
TOG2
INT4
SYSCL
RES
8-bit compare
8-bit register
Timer 2
output mode
and T2OTM–bit
P4CR P41M2, 1
T2D1, 0
T2RM
T2OTM
T2IM
T2CTM
TOG3
T1OUT
CL2/1
MUX
4-bit counter
SYSCL
SCL
RES
POUT
13779
CM1
4-bit compare
4-bit register
T2CS1, 0
Figure 33. 4-/8-bit compare counter
In these modes the 4-bit and the 8-bit counter stages work or to generate the stop signal for modulator 2 and
independently as a 4-bit prescaler and an 8-bit timer with modulator 3.
an 2-bit prescaler or as a duty cycle generator. Only in the
mode 3 and mode 4, can the 8-bit counter be supplied via
Timer 2 Output Modes
the external clock input (T2I) which is selected via the The signal at the timer output is generated via
P4CR register. The 4-bit prescaler is started via activating modulator 2. In the toggle mode, the compare match
of mode 3 and stopped and reset in mode 4. Changing event toggles the output T2O. For high resolution duty
mode 3 and 4 has no effect for the 8-bit timer stage. The cycle modulation 8 bits or 12 bits can be used to toggle the
4-bit stage can be used as prescaler for Timer 3, the SSI output. In the duty cycle burst modulator modes the DCG
Rev. A1, 08-Aug-01
33 (84)
M44C092–H
M44C892–H
output is connected to T2O and switched on and off either is started with the start of the shift register (SIR = 0) and
by the toggle flipflop output or the serial data line of the stopped either by carrying out a shift register stop
SSI. Modulator 2 also has 2 modes to output the content (SIR = 1) or compare match event of stage 1 (CM1) of
of the serial interface as Biphase or Manchester code.
Timer 2. For this task, Timer 2 mode 3 must be used and
the prescaler has to be supplied with the internal shift
clock (SCL).
The modulator output stage can be configured by the
output control bits in the T2M2 register. The modulator
DCGO
SO
TOG2
T2O
RE
Biphase/
S3
M2
Manchester
Toggle
S2
S1
modulator
FE
SSI
CONTROL
RES/SET
Modulator3
OMSK
M2
T2M2 T2OS2, 1, 0 T2TOP
13780
Figure 34. Timer 2 modulator output stage
Timer 2 Output Signals
Timer 2 output mode 1:
Toggle mode A: a Timer 2 compare match toggles the output flip-flop (M2) –> T2O
Input
Counter 2
T2R
0
0
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
Counter 2
CMx
INT4
T2O
13781
Figure 35. Interrupt timer / square wave generator – the output toggles with each edge compare match event
34 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Timer 2 output mode 1:
Toggle mode B: a Timer 2 compare match toggles the output flip-flop (M2) –> T2O
Input
Counter 2
T2R
4095/
255
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
Counter 2
CMx
INT4
T2O
Toggle
by start
13782
T2O
Figure 36. Pulse generator – the timer output toggles with the timer start if the T2TS-bit is set
Timer 2 output mode 1:
Toggle mode C:
a Timer 2 compare match toggles the output flip-flop (M2) –> T2O
Input
Counter 2
T2R
4095/
0
0
0
1
2
3
4
5
6
7
255
0
1
2
3
4
5
6
Counter 2
CMx
OVF2
INT4
T2O
13783
Figure 37. Pulse generator – the timer toggles with timer overflow and compare match
Timer 2 output mode 2:
Duty cycle burst generator 1:
the DCG output signal (DCGO) is given to the output, and gated by the output
flip-flop (M2)
DCGO
1
2 0 1 2 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5
Counter 2
TOG2
M2
T2O
Counter = compare register (=2)
13784
Figure 38. Carrier frequency burst modulation with Timer 2 toggle flip-flop output
Rev. A1, 08-Aug-01
35 (84)
M44C092–H
M44C892–H
Timer 2 output mode 3:
Duty cycle burst generator 2:
the DCG output signal (DCGO) is given to the output, and gated by the SSI internal
data output (SO)
DCGO
1
2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1
Counter = compare register (=2)
Counter 2
TOG2
SO
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13
T2O
13785
Figure 39. Carrier frequency burst modulation with the SSI data output
Timer 2 output mode 4:
Biphase modulator:
Timer 2 modulates the SSI internal data output (SO) to Biphase code.
TOG2
SC
8-bit SR-Data
0
0
0
1
1
0
1
0
0
1
SO
Bit 7
Bit 0
1
0
1
1
0
1
13786
T2O
Data: 00110101
Figure 40. Biphase modulation
Timer 2 output mode 5:
Manchester modulator: Timer 2 modulates the SSI internal data output (SO) to Manchester code
TOG2
SC
8-bit SR-Data
0
0
1
1
0
1
0
1
SO
Bit 7
Bit 0
0
0
1
1
0
1
0
1
T2O
13787
Bit 7
Bit 0
Data: 00110101
Figure 41. Manchester modulation
36 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Timer 2 output mode 7: PWM mode: Pulse–width modulation output on Timer 2 output pin (T2O)
In this mode the timer overflow defines the period and the compare register defines the duty cycle. During one period
only the first compare match occurence is used to toggle the timer output flip-flop, until the overflow all further
compare match are ignored. This avoids the situation that changing the compare register causes the occurence of sev-
eral compare match during one period. The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all
other Timer 2 modes are 8-bit.
Input clock
Counter 2/2
T2R
0
0
50
255
0
100
255 0
150 255
0
50
255
0
100
Counter 2/2
CM2
OVF2
INT4
load the next
T2CO2=150
load
load
T
compare value
T2O
T1
T2
T3
T1
T2
T
T
T
T
13788
Figure 42. PWM modulation
Timer 2 Registers
Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function.
All registers are indirectly addressed using extended addressing as described in section ”Addressing peripherals”. The
alternate functions of the Ports BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of the
Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42.
Timer 2 Control Register (T2C)
Address: ’7’hex – Subaddress: ’0’hex
Bit 3
Bit 2
Bit 1
Bit 0
T2C
T2CS1
T2CS0
T2TS
T2R
Reset value: 0000b
T2CS1
T2CS0
Timer 2 Clock Select bit 1
Timer 2 Clock Select bit 0
T2CS1 T2CS0
Input Clock (CL 2/1) of
Counter Stage 2/1
System clock (SYSCL)
Output signal of Timer 1 (T1OUT)
Internal shift clock of SSI (SCL)
Output signal of Timer 3 (TOG3)
0
0
1
1
0
1
0
1
T2TS
T2R
Timer 2 Toggle with Start
T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start
T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with T2R
Timer 2 Run
T2R = 0, Timer 2 stop and reset
T2R = 1, Timer 2 run
Rev. A1, 08-Aug-01
37 (84)
M44C092–H
M44C892–H
Timer 2 Mode Register 1 (T2M1)
Address: ’7’hex – Subaddress: ’1’hex
Bit 3
Bit 2
Bit 1
Bit 0
T2M1
T2D1
T2D0
T2MS1
T2MS0
Reset value: 1111b
T2D1
T2D0
Timer 2 Duty cycle bit 1
Timer 2 Duty cycle bit 0
T2D1
T2D0
Function of Duty Cycle Generator (DCG)
Bypassed (DCGO0)
Duty cycle 1/1 (DCGO1)
Duty cycle 1/2 (DCGO2)
Duty cycle 1/3 (DCGO3)
Additional Divider Effect
1
1
0
0
1
0
1
0
/ 1
/ 2
/ 3
/ 4
T2MS1
T2MS0
Timer 2 Mode Select bit 1
Timer 2 Mode Select bit 0
Mode T2MS1 T2MS0
Clock Output (POUT)
Timer 2 Modes
1
1
1
4-bit counter overflow (OVF1)
12-bit compare counter; the DCG
has to be bypassed in this mode
2
1
0
4-bit compare output (CM1)
4-bit compare output (CM1)
8-bit compare counter with 4-bit
programmable prescaler and duty
cycle generator
8-bit compare counter clocked by
SYSCL or the external clock input
T2I, 4-bit prescaler run, the
counter 2/1 starts after writing
mode 3
3
4
0
0
1
0
4-bit compare output (CM1)
8-bit compare counter clocked by
SYSCL or the external clock input
T2I, 4-bit prescaler stop and resets
Duty Cycle Generator
The duty cycle generator generates duty cycles from 25%, 33% or 50%. The frequency at the duty cycle generator
output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-stage can also be used as additional
programmable prescaler for Timer 2.
DCGIN
DCGO0
DCGO1
DCGO2
DCGO3
13807
Figure 43. DCG output signals
38 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Timer 2 Mode Register 2 (T2M2)
Address: ’7’hex – Subaddress: ’2’hex
Bit 3
Bit 2
Bit 1
Bit 0
T2M2
T2TOP
T2OS2
T2OS1
T2OS0
Reset value: 1111b
T2TOP
Timer 2 Toggle Output Preset
This bit allows the programmer to preset the Timer 2 output T2O.
T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0)
T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1)
Note: If T2R = 1, no output preset is possible
T2OS2
T2OS1
T2OS0
Timer 2 Output Select bit 2
Timer 2 Output Select bit 1
Timer 2 Output Select bit 0
Output T2OS2 T2OS1 T2OS0
Mode
Clock Output (POUT)
1
1
1
1
Toggle mode: a Timer 2 compare match toggles the
output flip-flop (M2) –> T2O
2
1
1
0
Duty cycle burst generator 1: the DCG output signal
(DCG0) is given to the output and gated by the output
flip-flop (M2)
3
1
0
1
Duty cycle burst generator 2: the DCG output signal
(DCGO) is given to the output and gated by the SSI in-
ternal data output (SO)
4
5
6
1
0
0
0
1
1
0
1
0
Biphase modulator: Timer 2 modulates the SSI internal
data output (SO) to Biphase code
Manchester modulator: Timer 2 modulates the SSI inter-
nal data output (SO) to Manchester code
SSI output: T2O is used directly as SSI internal data
output (SO)
7
8
0
0
0
0
1
0
PWM mode: an 8/12-bit PWM mode
Not allowed
If one of these output modes is used the T2O alternate function of Port 4 must also be activated.
Rev. A1, 08-Aug-01
39 (84)
M44C092–H
M44C892–H
Timer 2 Compare and Compare Mode Registers
Timer 2 has two separate compare registers, T2CO1 for stage.
the 4-bit stage and T2CO2 for the 8-bit stage of Timer 2. In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and
The timer compares the contents of the compare register T2CO2 bits 4 to 11 of the 12-bit compare value. In all
current counter value and if it matches it generates an other modes, the two compare registers work
output signal. Dependent on the timer mode, this signal independently as a 4- and 8-bit compare register.
is used to generate a timer interrupt, to toggle the output When asigned to the compare register a compare event
flip-flop as SSI clock or as a clock for the next counter will be supressed.
Timer 2 Compare Mode Register (T2CM)
Address: ’7’hex – Subaddress: ’3’hex
Bit 3
Bit 2
Bit 1
Bit 0
T2CM
T2OTM T2CTM
T2RM
T2IM
Reset value: 0000b
T2OTM
Timer 2 Overflow Toggle Mask bit
T2OTM = 0, disable overflow toggle
T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output flip-flop (TOG2).
If the T2OTM-bit is set, only a counter overflow can generate an interrupt except on
the Timer 2 output mode 7.
T2CTM
Timer 2 Compare Toggle Mask bit
T2CTM = 0, disable compare toggle
T2CTM = 1, enable compare toggle, a match of the counter with the compare register toggles out-
put flip-flop (TOG2). In Timer 2 output mode 7 and when the T2CTM-bit is set, only
a match of the counter with the compare register can generate an interrupt.
T2RM
T2IM
Timer 2 Reset Mask bit
T2RM = 0, disable counter reset
T2RM = 1, enable counter reset, a match of the counter with the compare register resets the
counter
Timer 2 Interrupt Mask bit
T2IM = 0, disable Timer 2 interrupt
T2IM = 1, enable Timer 2 interrupt
Timer 2 Output Mode
1, 2, 3, 4, 5 and 6
1, 2, 3, 4, 5 and 6
7
T2OTM
T2CTM
Timer 2 Interrupt Source
Compare match (CM2)
Overflow (OVF2)
0
1
x
x
x
1
Compare match (CM2)
Timer 2 COmpare Register 1 (T2CO1)
Address: ’7’hex – Subaddress: ’4’hex
Bit 0 Reset value: 1111b
T2CO1
Write cycle
Bit 3
Bit 2
Bit 1
In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.
Timer 2 COmpare Register 2 (T2CO2) Byte Write
Address: ’7’hex – Subaddress: ’5’hex
T2CO2
First write cycle
Bit 3
Bit 7
Bit 2
Bit 6
Bit 1
Bit 5
Bit 0
Bit 4
Reset value: 1111b
Reset value: 1111b
Second write cycle
40 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
3.3.3
Timer 3
Features
ꢀ 2 Compare Registers
ꢀ Automatically modulation and demodulation modes
ꢀ FSK modulation
ꢀ Capture Register
ꢀ Pulse width modulation (PWM)
ꢀ Edge sensitive input with zero cross detection capa-
bility
ꢀ Manchester demodulation together with SSI
ꢀ Biphase demodulation together with SSI
ꢀ Pulse-width demodulation together with SSI
ꢀ Trigger and single action modes
ꢀ Output control modes
I/O–bus
T3CS
T3M
T3I
T3EX
T3I
SCI
SI
Demodu–
lator 3
CM31
RES
CP3
T3CP
T3EX
INT5
CL3
SYSCL
T1OUT
POUT
8–bit Counter 3
T3C
T3ST
TOG3
RES
Compare 3/1
SO
Control
T3O
Modulator 3
Compare 3/2
Control
M2
TOG2
T3CO1
T3CO2
T3CM1
T3CM2
I/O–bus
Timer 2
SSI
SSI
13808
Figure 44. Timer 3
Timer 3 consists of an 8-bit up-counter with two compare A special feature of this timer is the trigger- and single-ac-
registers and one capture register. The timer can be used tion mode. In trigger mode, the counter starts counting
as event counter, timer and signal generator. Its output can triggered by the external signal at its input. In single-ac-
be programmed as modulator and demodulator for the tion mode, the counter counts only one time up to the
serial interface. The two compare registers enable various programmed compare match event. These modes are very
modes of signal generation, modulation and useful for modulation, demodulation, signal generation,
demodulation. The counter can be driven by internal and signal measurement and phase controlling. For phase
external clock sources. For external clock sources, it has controlling, the timer input is protected against negative
a programmable edge-sensitive input which can be used voltages and has zero-cross detection capability.
as counter input, capture signal input or trigger input. This
Timer 3 has a modulator output stage and input functions
timer input is synchronized with SYSCL. Therefore in the
for demodulation. As modulator it works together with
power-down mode SLEEP (CPU core –> sleep and OSC–
Timer 2 or the serial interface. When the shift register is
Stop –> yes) this timer input is stopped too. The counter
used for modulation the data shifted out of the register is
is readable via its capture register while it is running. In
encoded bitwise. In all demodulation modes, the decoded
capture mode, the counter value can be captured by a
data bits are shifted automatically into the shift register.
programmable capture event from the Timer 3 input or
Timer 2 output.
Rev. A1, 08-Aug-01
41 (84)
M44C092–H
M44C892–H
TOG2 T3I
T3EIM
INT5
Control
Capture register
8-bit counter
D
: T3M1
T3SM1
T3RM1
T3IM1
T3TM1
NQ
CL3
RES
CM31
CM32
TOG3
C31
C32
8-bit comparator
Compare register 1
Compare register 2
Control
NQ
: T3M2
D
T3SM2
T3RM2
T3IM2
T3TM2
13809
Figure 45. Counter 3 stage
If single-action mode is set for one compare register, the
comparison is always carried out after the first cycle via
the other compare register.
Timer / Counter Modes
Timer 3 has 6 timer modes and 6 modulator/demodulator
modes. The mode is set via the Timer 3 Mode Register
T3M.
The counter can be started and stopped via the control
register T3C. This register also controls the initial level
of the output before start. T3C contains the interrupt mask
for a T3I input interrupt.
In all these modes, the compare register and the compare-
mode register belonging to it define the counter value for
a compare match and the action of a compare match. A
match of the current counter value with the content of one
compare register triggers a counter reset, a Timer 3
interrupt or the toggling of the output flip-flop. The
compare mode registers T3M1 and T3M2 contain the
mask bits for enabling or disabling these actions.
Via the Timer 3 clock-select register, the internal or
external clock source can be selected. This register selects
also the active edge of the external input. An edge at the
external input T3I can generate also an interrupt if the
T3EIM-bit is set and the Timer 3 is stopped (T3R = 0) in
the T3C-register.
The counter can also be enabled to execute single actions
with one or both compare registers. If this mode is set the
corresponding compare match event is generated only
once after the counter start.
The status of the timer as well as the occurrence of a
compare match or an edge detect of the input signal is
indicated by the status register T2ST. This allows
identification of the interrupt source because all these
events share only one timer interrupt.
Most of the timer modes use its compare registers
alternately. After the start has been activated, the first
comparison is carried out via the compare register 1,
the second is carried out via the compare register 2, the
third is carried out again via the compare register 1
and so on. This makes it easy to generate signals with
Timer 3 compare data values
The Timer 3 has two 8-bit compare registers (T3CO1,
T3CO2). The compare data value can be ‘m’ for each of
the Timer 3 compare registers.
constant periods and variable duty cycle or to generate The compare data value for the compare registers is:
signals with variable pulse and space widths.
m = x +1
0 ≤ x ≤ 255
42 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Timer 3 – Mode 1: Timer / Counter
The selected clock from an internal or external source increments the 8-bit counter. In this mode, the timer can be used
as event counter for external clocks at T3I or as timer for generating interrupts and pulses at T3O. The counter value
can be read by the software via the capture register.
T3R
0
0
0
1
2
3
0
1
2
3
4
5
0
1
2
3
0
1
2
3
Counter 3
CM31
CM32
INT5
T3O
13810
Figure 46. Counter reset with each compare match
CL3
T3R
0
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
Counter 3
CM31
CM32
INT5
T3O
Toggle
by start
T3O
13811
Figure 47. Counter reset with compare register 2 and toggle with start
T3R
Counter 3
CM31
CM32
T3O
0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1
Toggle by start
13812
Figure 48. Single action of compare register 1
Rev. A1, 08-Aug-01
43 (84)
M44C092–H
M44C892–H
Timer 3 – Mode 2: Timer/Counter, Ext. Trigger Restart & Ext. Capture (with T3I Input)
The counter is driven by an internal clock source. After starting with T3R, the first edge from the external input T3I
starts the counter. The following edges at T3I load the current counter value into the capture register, reset the counter
and restart it. The edge can be selected by the programmable edge decoder of the timer input stage. If single-action
mode is activated for one or both compare registers the trigger signal restarts the single action.
T3R
0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 X X X 0 1 2 3 4 5 6 7 8 9 10 0 1 2 X X X X
Counter 3
T3EX
CM31
CM32
13813
T3O
Figure 49. Externally triggered counter reset and start combined with single-action mode
Timer 3 – Mode 3: Timer/Counter, Int. Trigger Restart & Int. Capture (with TOG2)
The counter is driven by an internal or external (T3I) clock source. The output toggle signal of Timer 2 resets the
counter. The counter value before the reset is saved in the capture register. If single-action mode is activated for one
ore both compare registers, the trigger signal restarts the single actions. This mode can be used for frequency measure-
ments or as event counter with time gate (see combination mode 10).
T3R
T3I
0 0 1 2 3 4 5 6 7 8 9 10
11
0 1
2
4
0 1 2
3
Counter 3
TOG2
Capture
T3CP–
Capture value = 0
Capture value = 11
value = 4
Register
13814
Figure 50. Event counter with time gate
Timer 3 – Mode 4: Timer/Counter
The timer runs as timer/counter in mode 1, but its output T3O is used as output for the Timer 2 output signal.
Timer 3 – Mode 5: Timer/Counter, Ext. Trigger Restart & Ext. Capture (with T3I Input)
The Timer 3 runs as timer/counter in mode 2, but its output T3O is used as output for the Timer 2 output signal.
Timer 3 Modulator / Demodulator Modes
Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle Flip-Flop (M2)
The Timer 3 counter is driven by an internal or external clock source. Its compare– and compare mode registers must
be programmed to generate the carrier frequency via the output toggle flip-flop. The output toggle flip-flop of Timer 2
is used to enable or disable the Timer 3 output. Timer 2 can be driven by the toggle output signal of Timer 3 or any
other clock source. (see combination mode 11)
44 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO)
The Timer 3 counter is driven by an internal or external clock source. Its compare– and compare mode registers must
be programmed to generate the carrier frequency via the output toggle flip-flop. The output (SO) of the SSI is used
to enable or disable the Timer 3 output. The SSI should be supplied with the toggle signal of Timer 2 (see combination
mode 12).
Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO)
The two compare registers are used for generating two different time intervals. The SSI internal data output (SO) selects
which compare register is used for the output frequency generation. A ’0’ level at the SSI data output enables the
compare register 1. An ’1’ level enables compare register 2. The both compare- and compare mode registers must be
programmed to generate the two frequencies via the output toggle flip-flop. The SSi can be supplied with the toggle
signal of Timer 2. The Timer 3 counter is driven by an internal or external clock source. The Timer 2 counter is driven
by the Counter 3 (TOG3) (see also combination mode 13).
T3R
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 4 0 1
Counter 3
CM31
CM32
0
1
0
SO
T3O
13815
Figure 51. FSK modulation
Timer 3 – Mode 9: Pulse-Width Modulation with the Shift Register
The two compare registers are used for generating two different time intervals. The SSI internal data output (SO) selects
which compare register is used for the output pulse generation. In this mode both compare- and compare mode registers
must be programmed for generating the two pulse widths. It is also useful to enable the single-action mode for extreme
duty cycles. Timer 2 is used as baudrate generator and for the trigger restart of Timer 3. The SSI must be supplied with
a toggle signal of Timer 2. The counter is driven by an internal or external clock source (see combination mode 7).
TOG2
SIR
0
1
0
1
SO
SCO
T3R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 1011121314150 1 2 3 4 5 6 7 8 9 1011121314150 1 2 3 4
Counter 3
CM31
CM32
T3O
13816
Figure 52. Pulse-width modulation
Rev. A1, 08-Aug-01
45 (84)
M44C092–H
M44C892–H
Timer 3 – Mode 10: Manchester demodulation / pulse-width demodulation
For Manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. These
edges are evaluated by the demodulator stage. The timer stage is used to generate the shift clock for the SSI. The
compare register 1 match event defines the correct moment for shifting the state from the input T3I as the decoded bit
into shift register – after that the demodulator waits for the next edge to synchronize the timer by a reset for the next
bit. The compare register 2 can also be used to detect a time-out error and handle it with an interrupt routine (see also
combination mode 8).
Timer 3
mode
Synchronize
1
Manchester demodulation mode
0
1
1
1
0
0
1
1
0
T3I
T3EX
SI
CM31=SCI
SR–DATA
1
1
1
0
0
1
1
0
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 6
BIT 5
13817
Figure 53. Manchester demodulation
Timer 3 – Mode 11: Biphase demodulation
In the Biphase demodulation mode, the timer operates like in Manchester demodulation mode. The difference is that
the bits are decoded via a toggle flip-flop. This flip-flop samples the edge in the middle of the bitframe and the compare
register 1 match event shifts the toggle flip-flop output into shift register (see also combined mode 9).
Timer 3
mode
Synchronize
0
Biphase demodulation mode
0
1
1
0
1
0
1
0
T3I
T3EX
Q1=SI
CM31=SCI
Reset
Counter 3
0
1
1
0
1
0
1
0
SR–DATA
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
13818
Figure 54. Biphase demodulation
46 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Timer 3 – Mode 12: Timer / counter with external capture mode (T3I)
The counter is driven by an internal clock source and an edge at the external input T3I loads the counter value into the
capture register. The edge can be selected with the programmable edge detector of the timer input stage. This mode
can be used for signal and pulse measurements.
T3R
T3I
0 0 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132333435363738394041
Counter 3
Capture
value = 35
T3CP–
Register
Capture value = 17
Capture value = X
13819
Figure 55. External capture mode
Timer 3 Modulator for Carrier Frequency Burst Modulation
If the output stage operates as pulse-width modulator for the shift register the output can be stopped with stage 1 of
Timer 2. For this task, the timer mode 3 must be used and the prescaler must be supplied by the internal shift clock
of the shift register.
The modulator can be started with the start of the shift register (SIR=0) and stopped either by a shift register stop
(SIR=1) or compare match event of stage 1 of Timer 2. For this task, the Timer 2 must be used in mode 3 and the pre-
scaler stage must be supplied by the internal shift clock of the shift register.
0
T3
Set
M3
TOG3
1
Res
T3TOP
Timer 3 Mode T3O
T3O
2
MUX
6
MUX 1
SO
M2
7
9
MUX 2
MUX 3
MUX 0
3
other
SSI/
Control
OMSK
T3M
13820
Figure 56. Modulator 3
Timer 3 Demodulator for Biphase, Manchester and Pulse-Width-Modulated Signals
The demodulator stage of Timer 3 can be used to decode Biphase, Manchester and pulse-width-coded signals
T3M
SCI
T3I
Demodulator 3
SI
T3EX
Res
Counter 3
Reset
CM31
Counter 3
Control
13821
Figure 57. Timer 3 demodulator 3
Rev. A1, 08-Aug-01
47 (84)
M44C092–H
M44C892–H
Timer 3 Registers
Timer 3 Mode Register (T3M)
Address: ’B’hex – Subaddress: ’0’hex
Bit 3
T3M3
Bit 2
T3M2
Bit 1
T3M1
Bit 0
T3M0
T3M
Reset value: 1111b
T3M3
T3M2
T3M1
T3M0
Timer 3 Mode select bit 3
Timer 3 Mode select bit 2
Timer 3 Mode select bit 1
Timer 3 Mode select bit 0
Mode T3M3 T3M2 T3M1 T3M0
Timer 3 Modes
1
2
1
1
1
1
1
1
1
0
Timer / counter with a read access
Timer / counter, external capture & external trigger restart
mode (T3I)
3
1
1
0
1
Timer / counter, internal capture & internal trigger restart
mode (TOG2)
4
5
6
7
8
9
1
1
1
1
1
0
1
0
0
0
0
1
0
1
1
0
0
1
0
1
0
1
0
1
Timer / counter mode 1 without output
Timer / counter mode 2 without output
Burst modulation with Timer 2 (M2)
Burst modulation with shift register (SO)
FSK modulation with shift register (SO)
(T2O –> T3O)
(T2O –> T3O)
Pulse-width modulation with shift register (SO) & Timer 2
(TOG2), internal trigger restart (SCO) –> counter reset
10
0
1
1
0
Manchester demodulation / pulse-width demodulation *
(T2O –> T3O)
11
12
13
14
15
16
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
Biphase demodulation *
(T2O –> T3O)
Timer / counter with external capture mode (T3I)
Not allowed
Not allowed
Not allowed
Not allowed
* In this mode, the SSI can be used only as demodulator (8-bit NRZ rising edge). All other SSI modes are not allowed.
Timer 3 Control Register 1 (T3C) Write
Primary register address: ’C’hex – Write
Bit 3
Bit 2
Bit 1
Bit 0
T3C
Write
T3EIM
T3TOP
T3TS
T3R
Reset value: 0000b
T3EIM
Timer 3 Edge Interrupt Mask
T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I)
T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I)
T3TOP
Timer 3 Toggle Output Preset
T3TOP = 0, sets toggle output (M3) to ’0’
T3TOP = 1, sets toggle output (M3) to ’1’
Note: If T3R = 1, no output preset is possible
T3TS
T3R
Timer 3 Toggle with Start
T3TS = 0, Timer 3 output is not toggled during the start
T3TS = 1, Timer 3 output is toggled if it is started with T3R
Timer 3 Run
T3R = 0, Timer 3 stop and reset
T3R = 1, Timer 3 run
48 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Timer 3 Status Register 1 (T3ST) Read
Primary register address: ’C’hex – Read
Bit 3
Bit 2
Bit 1
Bit 0
T3ST
Read
– – –
T3ED
T3C2
T3C1
Reset value: x000b
T3ED
T3C2
T3C1
Timer 3 Edge Detect
This bit will be set by the edge-detect logic of Timer 3 input (T3I)
Timer 3 Compare 2
This bit will be set when a match occurs between Counter 3 and T3CO2
Timer 3 Compare 1
This bit will be set when a match occurs between Counter 3 and T3CO1
Note: The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST.
Timer 3 Clock Select Register (T3CS)
Address: ’B’hex – Subaddress: ’1’hex
Bit 3
Bit 2
Bit 1
Bit 0
T3CS
T3E1
T3E0
T3CS1
T3CS0
Reset value: 1111b
T3E1
T3E0
Timer 3 Edge select bit 1
Timer 3 Edge select bit 0
T3E1
T3E0
Timer 3 Input Edge Select (T3I)
– – –
Positive edge at T3I pin
Negative edge at T3I pin
Each edge at T3I pin
1
1
0
0
1
0
1
0
T3CS1
T3CS0
Timer 3 Clock Source select bit 1
Timer 3 Clock Source select bit 0
T3CS1
TCS0
Counter 3 Input Signal (CL3)
System clock (SYSCL)
Output signal of Timer 2 (POUT)
Output signal of Timer 1 (T1OUT)
External input signal from T3I edge
detect
1
1
0
0
1
0
1
0
Timer 3 Compare- and Compare Mode Register
Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of Timer 3. The timer compares the
content of the compare register with the current counter value. If both match, it generates a signal. This signal can be
used for the counter reset, to generate a timer interrupt, for toggling the output flip-flop, as SSI clock or as clock for
the next counter stage. For each compare register an compare-mode register exists. This registers contain mask bits
to enable or disable the generation of an interrupt, a counter reset, or an output toggling with the occurrence of a
compare match of the corresponding compare register. The mask bits for activating the single-action mode can also
be located in the compare mode registers. When assigned to the compare register a compare event will be supressed.
Rev. A1, 08-Aug-01
49 (84)
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M44C892–H
Timer 3 Compare Mode Register 1 (T3CM1)
Address: ’B’hex – Subaddress: ’2’hex
Bit 3
Bit 2
Bit 1
Bit 0
T3CM1
T3SM1
T3SM1
T3TM1
T3RM1
T3IM1
Reset value: 0000b
Timer 3 Single action Mask bit 1
T3SM1 = 0, disables single-action compare mode
T3SM1 = 1, enables single-compare mode. After this bit is set, the compare register (T3CO1) is
used until the next compare match.
T3TM1
T3RM1
T3IM1
Timer 3 compare Toggle action Mask bit 1
T3TM1 = 0, disables compare toggle
T3TM1 = 1, enables compare toggle. A match of Counter 3 with the compare register
(T3CO1) toggles the output flip-flop (TOG3).
Timer 3 Reset Mask bit 1
T3RM1 = 0, disables counter reset
T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare register (T3CO1)
resets the Counter 3.
Timer 3 Interrupt Mask bit 1
T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register.
T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register.
T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1
Timer 3 Compare Mode Register 2 (T3CM2)
Address: ’B’hex – Subaddress: ’3’hex
Bit 3
Bit 2
Bit 1
Bit 0
T3CM2
T3SM2
T3SM2
T3TM2
T3RM2
T3IM2
Reset value: 0000b
Timer 3 Single action Mask bit 2
T3SM2 = 0, disables single-action compare mode
T3SM2 = 1, enables single-compare mode. After this bit is set, the compare register (T3CO2) is
used until the next compare match.
T3TM2
T3RM2
T3IM2
Timer 3 compare Toggle action Mask bit 2
T3TM2 = 0, disables compare toggle
T3TM2 = 1, enables compare toggle. A match of Counter 3 with the compare register
(T3CO2) toggles the output flip-flop (TOG3).
Timer 3 Reset Mask bit 2
T3RM2 = 0, disables counter reset
T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare register (T3CO2)
resets the Counter 3.
Timer 3 Interrupt Mask bit 2
T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register.
T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register.
T3CM2 contains the mask bits for the match event of Counter 3 compare register 2
The compare registers and corresponding counter reset masks can be used to program the counter time intervals and
the toggle masks can be used to program output signal. The single-action mask can also be used in this mode. It starts
operating after the timer started with T3R.
50 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Timer 3 COmpare Register 1 (T3CO1) Byte Write
Address: ’B’hex – Subaddress: ’4’hex
High nibble
Bit 6 Bit 5
T3CO1
Second write cycle
First write cycle
Bit 7
Bit 3
Bit 4
Bit 0
Reset value: 1111b
Reset value: 1111b
Low nibble
Bit 2 Bit 1
Timer 3 COmpare Register 2 (T3CO2) Byte Write
Address: ’B’hex – Subaddress: ’5’hex
High nibble
T3CO2
Second write cycle
First write cycle
Bit 7
Bit 3
Bit 6
Bit 5
Bit 4
Bit 0
Reset value: 1111b
Reset value: 1111b
Low nibble
Bit 2
Bit 1
Timer 3 Capture register
The counter content can be read via the capture register. There are two ways to use the capture register. In modes 1
and 4, it is possible to read the current counter value directly out of the capture register. In the capture modes 2, 3, 5
and 12, a capture event like an edge at the Timer 3 input or a signal from Timer 2 stores the current counter value into
the capture register. This counter value can be read from the capture register.
Timer 3 CaPture Register (T3CP) Byte Read
Address: ’B’hex – Subaddress: ’4’hex
High nibble
T3CP
First read cycle
Bit 7
Bit 3
Bit 6
Bit 5
Bit 4
Bit 0
Reset value: xxxxb
Reset value: xxxxb
Low nibble
Second read cycle
Bit 2
Bit 1
Rev. A1, 08-Aug-01
51 (84)
M44C092–H
M44C892–H
3.3.4
Synchronous Serial Interface (SSI)
SSI Features:
register. The SSI can be configured in any one of the
following ways:
2- and 3-wire NRZ
a)
2-wire external interface for bidirectional data
2
2-wire mode (I C compatible)
communication with one data terminal and one shift
clock. The SSI uses the Port BP43 as a bidirectional serial
data line (SD) and BP40 as shift clock line (SC).
(additional internal 2-wire link for multi-chip
packaging solutions)
b)
3-wire external interface for simultaneous input
ꢀ With Timer 2:
and output of serial data, with a serial input data terminal
(SI), a serial output data terminal (SO) and a shift clock
(SC). The SSI uses BP40 as shift clock (SC), while the
serial data input (SI) is applied to BP43 (configured in
P4CR as input!). Serial output data (SO) in this case is
passed through to BP42 (configured in P4CR to T2O) via
the Timer 2 output stage (T2M2 configured in mode 6).
Biphase modulation
Manchester modulation
Pulse-width demodulation
Burst modulation
ꢀ With Timer 3:
c)
Timer/SSI combined modes – the SSI used
Pulse-width modulation (PWM)
FSK modulation
together with Timer 2 or Timer 3 is capable of performing
a variety of data modulation and demodulation functions
(see Timer Section). The modulating data is converted by
the SSI into a continuous serial stream of data which is in
turn modulated in one of the timer functional blocks.
Serial demodulated data can be serially captured in the
SSI and read by the controller. In the Timer 3 modes 10
and 11 (demodulation modes) the SSI can only be used as
demodulator.
Biphase demodulation
Manchester demodulation
Pulse-width demodulation
Pulse position Demodulation
SSI Peripheral Configuration
d)
Multi-chip link (MCL) – the SSI can also be used
The synchronous serial interface (SSI) can be used either as an interchip data interface for use in single package
for serial communication with external devices such as multi–chip modules or hybrids. For such applications, the
EEPROMs, shift registers, display drivers, other SSI is provided with two dedicated pads (MCL_SD and
microcontrollers, or as a means for generating and MCL_SC) which act as a two-wire chip-to-chip link. The
capturing on-chip serial streams of data. External data MCL can be activated by the MCL control bit. Should
communication takes place via the Port 4 (BP4) these MCL pads be used by the SSI, the standard SD and
multi-functional port which can be software configured SC pins are not required and the corresponding Port 4
by writing the appropriate control word into the P4CR ports are available as conventional data ports.
52 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
I/O-bus
Timer 2 / Timer 3
SIC1
SIC2
SISC
SI SCI
SO
INT3
Control
SC
SC
SSI-Control
MCL_SC
Output
TOG2
POUT
SO
MCL_SD
SD
SI
/2
T1OUT
SYSCL
8-bit Shift Register
MSB
LSB
Shift_CL
STB
SRB
Transmit
Buffer
Receive
Buffer
13822
I/O–bus
Figure 58. Block diagram of the synchronous serial interface
mode, an additional acknowledge bit is appended to the
end of the telegram for handshaking purposes (see I C
General SSI Operation
2
The SSI is comprised essentially of an 8-bit shift register
with two associated 8-bit buffers – the receive buffer
(SRB) for capturing the incoming serial data and a trans-
mit buffer (STB) for intermediate storage of data to be
serially output. Both buffers are directly accessable by
software. Transferring the parallel buffer data into and out
of the shift register is controlled automatically by the SSI
control, so that both single byte transfers or continuous bit
streams can be supported.
protocol).
At the beginning of every telegram, the SSI control loads
the transmit buffer into the shift register and proceeds
immediately to shift data serially out. At the same time,
incoming data is shifted into the shift register input. This
incoming data is automatically loaded into the receive
buffer when the complete telegram has been received.
Data can, if required thus be simultaneously received and
transmitted.
The SSI can generate the shift clock (SC) either from one
of several on-chip clock sources or accept an external
clock. The external shift clock is output on, or applied to
the Port BP40. Selection of an external clock source is
performed by the Serial Clock Direction control bit
(SCD). In the combinational modes, the required clock is
selected by the corresponding timer mode.
Before data can be transferred, the SSI must first be
activated. This is performed by means of the SSI reset
control (SIR) bit. All further operation then depends on
the data directional mode (TX/RX) and the present status
of the SSI buffer registers shown by the Serial Interface
Ready Status Flag (SRDY). This SRDY flag indicates the
(empty/full) status of either the transmit buffer (in TX
mode), or the receive buffer (in RX mode). The control
logic ensures that data shifting is temporarily halted at
any time, if the appropriate receive/transmit buffer is not
ready (SRDY = 0). The SRDY status will then
automatically be set back to ‘1’ and data shifting resumed
as soon as the application software loads the new data into
the transmit register (in TX mode) or frees the shift
register by reading it into the receive buffer (in RX mode).
The SSI can operate in three data transfer modes –
2
synchronous 8-bit shift mode, I C compatible 9-bit shift
2
modes or 8-bit pseudo I C protocol (without acknowl-
edge-bit).
External SSI clocking is not supported in these modes.
The SSI should thus generate and has full control over the
2
shift clock so that it can always be regarded as an I C Bus
Master device.
All directional control of the external data port used by
the SSI is handled automatically and is dependent on the
transmission direction set by the Serial Data Direction
(SDD) control bit. This control bit defines whether the
SSI is currently operating in Transmit (TX) mode or
Receive (RX) mode.
A further activity status (ACT) bit indicates the present
status of the serial communication. The ACT bit remains
high for the duration of the serial telegram or if I C stop
or start conditions are currently being generated. Both the
current SRDY and ACT status can be read in the SSI
2
Serial data is organized in 8-bit telegrams which are status register. To deactivate the SSI, the SIR bit must be
2
shifted with the most significant bit first. In the 9-bit I C set high.
Rev. A1, 08-Aug-01
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M44C892–H
8-bit Synchronous Mode
SC
(rising edge)
SC
(falling edge)
0
0
0
1
1
1
1
0
0
1
1
0
0
1
DATA
Bit 7
Bit 0
0
1
SD/TO2
Bit 7
Bit 0
Data: 00110101
13823
Figure 59. 8-bit synchronous mode
In the 8-bit synchronous mode, the SSI can operate as generated. The SSI then continues shifting in the
either a 2- or 3-wire interface (see SSI peripheral following 8-bit telegram. If, during this time the first
configuration). The serial data (SD) is received or telegram has been read by the controller, the second
transmitted in NRZ format, synchronised to either the telegram will also be transferred in the same way into the
rising or falling edge of the shift clock (SC). The choice receive buffer and the SSI will continue clocking in the
of clock edge is defined by the Serial Mode Control bits next telegram. Should, however, the first telegram not
(SM0,SM1). It should be noted that the transmission edge have been read (SRDY=1), then the SSI will stop,
refers to the SC clock edge with which the SD changes. temporarily holding the second telegram in the shift
To avoid clock skew problems, the incoming serial input register until a certain point of time when the controller
data is shifted in with the opposite edge.
is able to service the receive buffer. In this way no data is
lost or overwritten.
When used together with one of the timer modulator or
demodulator stages, the SSI must be set in the 8-bit
synchronous mode 1.
Deactivating the SSI (SIR=1) in mid–telegram will
immediately stop the shift clock and latch the present
contents of the shift register into the receive buffer. This
In RX mode, as soon as the SSI is activated (SIR= 0), 8 can be used for clocking in a data telegram of less than 8
shift clocks are generated and the incoming serial data is bits in length. Care should be taken to read out the final
shifted into the shift register. This first telegram is complete 8-bit data telegram of a multiple word message
automatically transferred into the receive buffer and the before deactivating the SSI (SIR=1) and terminating the
SRDY set to 0 indicating that the receive buffer contains reception. After termination, the shift register contents
valid data. At the same time an interrupt (if enabled) is will overwrite the receive buffer.
SC
msb
lsb
1
msb
lsb msb
lsb
1
7
6
5
4
3
2
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
0
SD
SIR
tx data 1
tx data 2
tx data 3
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
Write STB
(tx data 1)
Write STB Write STB
(tx data 2) (tx data 3)
13824
Figure 60. Example of 8-bit synchronous transmit operation
54 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
SC
SD
msb
lsb msb
lsb
msb
lsb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4
rx data 3
rx data 1
rx data 2
SIR
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
Read SRB
(rx data 1)
Read SRB
(rx data 2)
Read SRB
(rx data 3)
13825
Figure 61. Example of 8-bit synchronous receive operation
9-bit Shift Mode (I2C compatible)
corresponding acknowledge bit can be shifted out or read
in. In transmit mode, the acknowledge bit received from
the slave device is captured in the SSI Status Register
(TACK ) where it can be read by the controller. and in
receive mode, the state of the acknowledge bit to be
returned to the slave device is predetermined by the SSI
Status Register (RACK ).
2
In the 9-bit shift mode, the SSI is able to handle the I C
protocol (described below). It always operates as an I C
2
master device, i.e., SC is always generated and output by
2
the SSI. Both the I C start and stop conditions are auto-
matically generated whenever the SSI is activated or
deactivated by the SIR–bit. In accordance with the I C
protocol, the output data is always changed in the clock
low phase and shifted in on the high phase.
2
Changing the directional mode (TX/RX) should not be
2
performed during the transfer of an I C telegram. One
should wait until the end of the telegram which can be
detected using the SSI interrupt (IFN =1) or by
interrogating the ACT status.
Before activating the SSI (SIR=0) and commencing an
I C dialog, the appropriate data direction for the first
word must be set using the SDD control bit. The state of
2
this bit controls the direction of the data port (BP43 or A 9-bit telegram, once started will always run to
MCL_SD). Once started, the 8 data bits are, depending on completion and will not be prematurely terminated by the
the selected direction, either clocked into or out of the SIR bit. So, if the SIR–bit is set to ‘1’ in mit telegram, the
shift register. During the 9th clock period, the port SSI will complete the current transfer and terminate the
2
direction is automatically switched over so that the dialog with an I C stop condition.
Rev. A1, 08-Aug-01
55 (84)
M44C092–H
M44C892–H
Start
Stop
SC
msb
lsb
msb
lsb
SD
7 6 5 4 3 2 1 0 A
7 6 5 4 3 2 1 0 A
tx data 2
tx data 1
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
SIR
SDD
Write STB
(tx data 1)
Write STB
(tx data 2)
13826
Figure 62. Example of I2C transmit dialog
Start
Stop
SC
SD
msb
lsb
msb
lsb
A
7 6 5 4 3 2 1 0 A
tx data 1
7 6 5 4 3 2 1 0
rx data 2
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
SIR
SDD
Write STB
(tx data 1)
Read SRB
(rx data 2)
13827
Figure 63. Example of I2C receive dialog
8-bit Pseudo I2C Mode
I2C Bus Protocol
2
The I C protocol constitutes a simple 2-wire bidirectional
In this mode, the SSI exhibits all the typical I C opera- communication highway via which devices can
2
tional features except for the acknowledge-bit which is communicate control and data information. Although the
2
never expected or transmitted.
I C protocol can support multi–master bus
56 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
2
2
configurations, the SSI, in I C mode is intended for use device connected onto the I C bus. Each slave receives
purely as a master controller on a single master bus this address and compares it with it’s own unique address.
system. So all reference to multiple bus control and bus The addressed slave device, if ready to receive data will
contention will be omitted at this point.
respond by pulling the SD line low during the 9th clock
pulse. This represents a so-called I C acknowledge. The
2
All data is packaged into 8-bit telegrams plus a trailing controller on detecting this affirmative acknowledge then
handshaking or acknowledge-bit. Normally the opens a connection to the required slave. Data can then be
communication channel is opened with a so-called start passed back and forth by the master controller, each 8-bit
condition, which initializes all devices connected to the telegram being acknowledged by the respective recipient.
bus. This is then followed by a data telegram, transmitted The communication is finally closed by the master device
by the master controller device. This telegram usually and the slave device put back into standby by applying a
contains an 8-bit address code to activate a single slave stop condition onto the bus.
(1)
(2)
(4)
(4)
(3)
(1)
SC
SD
Start
Data
valid
Data
Data
valid
Stop
condition
change
condition
13832
Figure 64. I2C bus protocol 1
Data valid (4)
Bus not busy (1)
Both data and clock lines remain HIGH.
The state of the data line represents valid data
when, after START condition, the data line is
stable for the duration of the HIGH period of the
clock signal.
Start data transfer (2)
A HIGH to LOW transition of the SD line while
the clock (SC) is HIGH defines a START
condition.
Acknowledge
All address and data words are serially transmitted
to and from device in eight–bit words. The
receiving device returns a zero on the data line
during the ninth clock cycle to acknowledge word
receipt.
Stop data transfer (3)
A LOW to HIGH transition of the SD line while
the clock (SC) is HIGH defines a STOP condition.
SC
1
n
8
9
SD
Start
1st Bit
8th Bit
ACK
Stop
13833
Figure 65. I2C bus protocol 2
Rev. A1, 08-Aug-01
57 (84)
M44C092–H
M44C892–H
of any length. The OMSK signal is derived indirectly
from the 4-bit prescaler of the Timer 2 and masks out a
programmable number of unrequired trailing data bits
during the shifting out of the final data word in the bit
stream. The number of non-masked data bits is defined by
the value pre-programmed in the prescaler compare
register. To use output masking, the modulator stop mode
bit (MSM) must be set to ’0’ before programming the
final data word into the SSI transmit buffer. This in turn,
enables shift clocks to the prescaler when this final word
is shifted out. On reaching the compare value, the
prescaler triggers the OMSK signal and all following data
bits are blanked.
SSI Interrupt
The SSI interrupt INT3 can be generated either by an SSI
buffer register status (i.e., transmit buffer empty or
receive buffer full) end of SSI data telegram or on the
falling edge of the SC/SD pins on Port 4 (see P4CR). SSI
interrupt selection is performed by the Interrupt FunctioN
control bit (IFN). The SSI interrupt is usually used to
synchronize the software control of the SSI and inform
the controller of the present SSI status. The Port 4
interrupts can be used together with the SSI or, if the SSI
itself is not required, as additional external interrupt
sources. In either case this interrupt is capable of waking
the controller out of sleep mode.
Internal 2-Wire Multi-Chip Link
To enable and select the SSI relevant interrupts use the
SSI interrupt mask (SIM) and the Interrupt Function
(IFN) while the Port 4 interrupts are enabled by setting
appropriate control bits in P4CR register.
Two additional on-chip pads (MCL_SC and MCL_SD)
for the SC and the SD line can be used as chip-to-chip link
for multi-chip applications. These pads can be activated
by setting the MCL-bit in the SISC-register.
Modulation and Demodulation
If the shift register is used together with Timer 2 or
Timer 3 for modulation or demodulation purposes, the
8-bit synchronous mode must be used. In this case, the
unused Port 4 pins can be used as conventional
bidirectional ports.
U505M
SCL
SDA
Multi chip link
MCL_SD
MCL_SC
The modulation and demodulation stages, if enabled,
operate as soon as the SSI is activated (SIR=0) and cease
when deactivated (SIR=1).
VDD
VSS
BP40/SC
BP43/SD
M44C092–H
BP10
BP13
Due to the byte-orientated data control, the SSI when
running normally generates serial bit streams which are
submultiples of 8 bits. An SSI output masking (OMSK)
function permits, however, the generation of bit streams
13835
Figure 66. Multi-chip link
Timer 2
CL2/1
4-bit counter 2/1
SCL
Compare 2/1
CM1
OMSK
Control
SO
SC
SSI-control
Output
SO
TOG2
POUT
SI
/2
8-bit shift register
T1OUT
SYSCL
MSB
LSB
Shift_CL
13834
Figure 67. SSI output masking function
58 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Serial Interface Registers
Serial Interface Control Register 1 (SIC1)
Auxiliary register address: ’9’hex
Bit 3
Bit 2
Bit 1
Bit 0
SIC1
SIR
SIR
SCD
SCS1
SCS0
Reset value: 1111b
Serial Interface Reset
SIR = 1, SSI inactive
SIR = 0, SSI active
SCD
Serial Clock Direction
SCD = 1, SC line used as output
SCD = 0, SC line used as input
Note: This bit has to be set to ’1’ during the I C mode and the Timer 3 mode 10 or 11
2
SCS1
SCS0
Serial Clock source Select bit 1
Serial Clock source Select bit 0
SCS1
SCS0
Internal Clock for SSI
SYSCL / 2
T1OUT / 2
POUT / 2
TOG2 / 2
1
1
0
0
1
0
1
0
Note: with SCD = ’0’ the bits SCS1
and SCS0 are insignificant
•
In Transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1).
Setting SIR-bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only).
•
•
2
In I C modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop condition.
Serial Interface Control Register 2 (SIC2)
Auxiliary register address: ’A’hex
Bit 3
Bit 2
Bit 1
Bit 0
SIC2
MSM
SM1
SM0
SDD
Reset value: 1111b
MSM
Modular Stop Mode
MSM = 1, modulator stop mode disabled (output masking off)
MSM = 0, modulator stop mode enabled (output masking on) – used in modulation modes for
generating bit streams which are not sub-multiples of 8 bit.
Mode SM1 SM0
SSI Mode
SM1
SM0
Serial Mode control bit 1
Serial Mode control bit 0
1
2
3
4
1
1
0
0
1
0
1
0
8-bit NRZ-Data changes with the rising edge of SC
8-bit NRZ-Data changes with the falling edge of SC
2
9-bit two-wire I C compatible
2
8-bit two-wire pseudo I C compatible (no
acknowledge)
SDD
Serial Data Direction
SDD = 1, transmit mode – SD line used as output (transmit data). SRDY is set by a transmit buffer
write access.
SDD = 0, receive mode – SD line used as input (receive data). SRDY is set by a receive buffer
read access
Note: SDD controls port directional control and defines the reset function for the SRDY–flag
Rev. A1, 08-Aug-01
59 (84)
M44C092–H
M44C892–H
Serial Interface Status and Control Register (SISC)
Primary register address: ’A’hex
Bit 3
Bit 2
Bit 1
Bit 0
SISC
SISC
MCL
write
read
MCL
RACK
SIM
IFN
Reset value: 1111b
Reset value: xxxxb
– – –
TACK
ACT
SRDY
Multi-Chip Link activation
MCL = 1,
multi-chip link disabled. This bit has to be set to ’0’ during transactions to/from
EEPROM of the M44C892–H
MCL = 0,
connnects SC and SD additional to the internal multi-chip link pads
2
RACK
TACK
SIM
Receive ACKnowledge status/control bit for I C mode
RACK = 0, transmit acknowledge in next receive telegram
RACK = 1, transmit no acknowledge in last receive telegram
2
Transmit ACKnowledge status/control bit for I C mode
TACK = 0, acknowledge received in last transmit telegram
TACK = 1, no acknowledge received in last transmit telegram
Serial Interrupt Mask
SIM = 1,
SIM = 0,
disable interrupts
enable serial interrupt. An interrupt is generated.
IFN
Interrupt FuNction
IFN = 1,
IFN = 0,
the serial interrupt is generated at the end of telegram
the serial interrupt is generated when the SRDY goes low (i.e., buffer becomes
empty/full in transmit/receive mode)
SRDY
ACT
Serial interface buffer ReaDY status flag
SRDY = 1, in receive mode: receive buffer empty
in transmit mode: transmit buffer full
SRDY = 0, in receive mode: receive buffer full
in transmit mode: transmit buffer empty
Transmission ACTive status flag
ACT = 1,
transmission is active, i.e., serial data transfer. Stop or start conditions are currently in
progress.
ACT = 0,
transmission is inactive
Serial Transmit Buffer (STB) – Byte Write
Primary register address: ’9’hex
STB
First write cycle
Bit 3
Bit 7
Bit 2
Bit 6
Bit 1
Bit 5
Bit 0
Bit 4
Reset value: xxxxb
Reset value: xxxxb
Second write cycle
The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and starts shifting
with the most significant bit.
60 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Serial Receive Buffer (SRB) – Byte Read
Primary register address: ’9’hex
SRB
First read cycle
Bit 7
Bit 3
Bit 6
Bit 2
Bit 5
Bit 1
Bit 4
Bit 0
Reset value: xxxxb
Reset value: xxxxb
Second read cycle
The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and loads
content into the receive buffer when complete telegram has been received.
3.3.5
Combination Modes
The UTCM consists of two timers (Timer 2 and Timer 3) and a serial interface. There is a multitude of modes in which
the timers and serial interface can work together.
The 8-bit wide serial interface operates as shift register for modulation and demodulation. The modulator and demodu-
lator units work together with the timers and shift the data bits into or out of the shift register.
Combination Mode Timer 2 and SSI
I/O–bus
P4CR
T2M1
T2M2
T2I
DCGO
8-bit Counter 2/2
SYSCL
T1OUT
TOG3
SCL
T2O
CL2/1
CL2/2
4-bit Counter 2/1
RES OVF1
DCG
OUTPUT
POUT
RES
OVF2
TOG2
T2C
Compare 2/1
Timer 2 – control
Compare 2/2
MOUT
INT4
POUT
TOG2
CM1
Biphase–,
Manchester–
modulator
Timer 2
T2CO1
T2CM
T2CO2
SISC
modulator
output–stage
SO
Control
I/O–bus
SIC1
SIC2
Control
INT3
SO
TOG2
SC
SD
SCLI
SCL
POUT
T1OUT
SYSCL
SSI–control
MCL_SC
MCL_SD
Output
SO
SI
8-bit shift register
MSB
LSB
Shift_CL
STB
SRB
Transmit
buffer
Receive
buffer
13836
I/O–bus
Figure 68. Combination Timer 2 and SSI
Rev. A1, 08-Aug-01
61 (84)
M44C092–H
M44C892–H
Combination mode 1: Burst modulation
SSI mode 1:
8-bit NRZ and internal data SO output to the Timer 2 modulator stage
Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler and DCG
Timer 2 output mode 3:
Duty cycle burst generator
DCGO
1
2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1
Counter = compare register (=2)
Counter 2
TOG2
SO
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13
T2O
13785
Figure 69. Carrier frequency burst modulation with the SSI internal data output
Combination mode 2: Biphase modulation 1
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2 modulator stage
Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler
Timer 2 output mode 4:
The modulator 2 of Timer 2 modulates the SSI internal data output to Biphase code
TOG2
SC
8-bit SR-data
0
0
0
1
1
0
1
0
0
1
SO
Bit 7
Bit 0
1
0
1
1
0
1
13786
T2O
Data: 00110101
Figure 70. Biphase modulation 1
Combination mode 3: Manchester modulation 1
SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage
Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler
Timer 2 output mode 5:
The modulator 2 of Timer 2 modulates the SSI internal data output to Manchester code
TOG2
SC
8-bit SR-data
0
0
1
1
0
1
0
1
SO
Bit 7
Bit 0
0
0
1
1
0
1
0
1
T2O
13787
Bit 7
Bit 0
Data: 00110101
Figure 71. Manchester modulation 1
62 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Combination mode 4: Manchester modulation 2
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2 modulator stage
Timer 2 mode 3:
8-bit compare counter and 4-bit prescaler
Timer 2 output mode 5:
The modulator 2 of Timer 2 modulates the SSI data output to Manchester code
The 4 bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has a special
mode to supply the prescaler with the shiftclock. The control output signal (OMSK) of the SSI is used as stop signal
for the modulator. This is an example for a 12-bit Manchester telegram:
SCLI
Buffer full
SIR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
SC
MSM
Timer 2
Mode 3
SCL
Counter 2/1 = Compare Register 2/1 (= 4)
3
0
0
0
0
0
0
0
0
0
1
2
3
4
0
1
2
Counter
2/1
OMSK
T2O
13837
Figure 72. Manchester modulation 2
Combination mode 5: Biphase modulation 2
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2 modulator stage
Timer 2 mode 3:
8-bit compare counter and 4-bit prescaler
Timer 2 output mode 4:
The modulator 2 of Timer 2 modulates the SSI data output to Biphase code
The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has a special
mode to supply the prescaler via the shift-clock. The control output signal (OMSK) of the SSI is used as stop signal
for the modulator. This is an example for a 13-bit Biphase telegram:
SCLI
Buffer full
SIR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
SC
MSM
Timer 2
Mode 3
SCL
Counter 2/1 = Compare Register 2/1 (= 5)
0
1
2
0
0
0
0
0
0
0
0
0
1
2
3
4
5
2/1
Counter
OMSK
T2O
13838
Figure 73. Biphase modulation
Rev. A1, 08-Aug-01
63 (84)
M44C092–H
M44C892–H
Combination Mode Timer 3 and SSI
I/O–bus
T3CS
T3M
T3EX
T3I
SC
SI
T3I
Demodu–
lator 3
CM31
RES
CP3
T3CP
T3EX
INT5
CL3
RES
Compare 3/1
SYSCL
T1OUT
POUT
8–bit Counter 3
T3C
T3ST
TOG3
SO
Control
T3O
Modulator 3
Compare 3/2
Timer 3 – control
T3CM1
M2
T3CO1
T3CO2
T3CM2
SISC
SI
SC
SIC1
SIC2
Control
INT3
SC
SI
TOG2
SCLI
POUT
T1OUT
SYSCL
SSI–control
MCL_SC
MCL_SD
Output
SO
SI
8–bit shift register
MSB
LSB
Shift_CL
STB
SRB
Transmit buffer
Receive buffer
I/O–bus
13877
Figure 74. Combination Timer 3 and SSI
Combination mode 6: FSK modulation
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 3
FSK modulation with shift register data (SO)
Timer 3 mode 8:
The two compare registers are used to generarte two varied time intervals. The SSI data output selects which compare
register is used for the output frequency generation. A ’0’-level at the SSI data output enables the compare register 1
and a ’1’-level enables the compare register 2. The both compare and compare mode registers must be programmed
to generate the two frequencies via the output toggle flip-flop. The SSI can be supplied with the toggle signal of Timer 2
or any other clock source. The Timer 3 counter is driven by an internal or external clock source.
T3R
0 1 2 3 4 0 1 2 3 4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 4 0 1 2 3 4 0
Counter 3
CM31
CM32
0
1
0
SO
T3O
13893
Figure 75. FSK modulation
64 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Combination mode 7: Pulse width modulation (PWM)
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 3
Pulse width modulation with the shift register data (SO)
Timer 3 mode 9:
The two compare registers are used to generarte two varied time intervals. The SSI data output selects which compare
register is used for the output pulse generation. In this mode both compare and compare mode registers must be pro-
grammed to generate the two pulse width. It is also useful to enable the single action mode for extreme duty cycles.
Timer 2 is used as baudrate generator and for the triggered restart of Timer 3. The SSI must be supplied with the toggle
signal of Timer 2. The counter is driven by an internal or external clock source.
TOG2
SIR
0
1
0
1
SO
SCO
T3R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 1011121314150 1 2 3 4 5 6 7 8 9 1011121314150 1 2 3 4
Counter 3
CM31
CM32
T3O
13816
Figure 76. Pulse-width modulation
Combination mode 8: Manchester demodulation / pulse width demodulation
SSI mode 1:
8-bit shift register internal data input (SI) and the internal shift clock (SCI) from the Timer 3
Timer 3 mode 10: Manchester demodulation / pulse width demodulation with Timer 3
For Manchester demodulation the edge detection stage must be programmed to detect each edge at the input. These
edges are evaluated by the demodulator stage. The timer stage is used to generate the shift clock for the SSI. A compare
register 1 match event defines the correct moment for shifting the state from the input T3I as the decoded bit into shift
register. After that the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The
compare register 2 can be used to detect a time error and handle it with an interrupt routine.
Before activating the demodulator mode the timer and the demodulator stage must be synchronized with the bitstream.
The Manchester code timing consists of parts with the half bitlength and the complete bitlength. A synchronization
routine must start the demodulator after an interval with the complete bitlength.
The counter can be driven by any internal clock source. The output T3O can be used by Timer 2 in this mode. The
Manchester decoder can also be used for pulse-width demodulation. The input must programmed to detect the positive
edge. The demodulator and timer must be synchronized with the leading edge of the pulse. After that a counter match
with the compare register 1 shifts the state at the input T3I into the shift register. The next positive edge at the input
restarts the timer.
Rev. A1, 08-Aug-01
65 (84)
M44C092–H
M44C892–H
Timer 3
mode
Synchronize
Manchester demodulation mode
1
0
1
1
1
0
0
1
1
0
T3I
T3EX
SI
CM31=SCI
SR–DATA
1
1
1
0
0
1
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
13817
Figure 77. Manchester demodulation
Combination mode 9: Biphase demodulation
SSI mode 1: 8-bit shift register internal data input (SI) and the internal shift clock (SCI) from the Timer 3
Timer 3 mode 11: Biphase demodulation with Timer 3
In the Biphase demodulation mode the timer works like in the Manchester demodulation mode. The diffenence is that
the bits are decoded with the toggle flip-flop. This flip-flop samples the edge in the middle of the bitframe and the
compare register 1 match event shifts the toggle flip-flop output into shift register. Before activating the demodulation
the timer and the demodulation stage must be synchronized with the bitstream. The Biphase code timing consists of
parts with the half bitlength and the complete bitlength. The synchronization routine must start the demodulator after
an interval with the complete bitlength.
The counter can be driven by any internal clock source and the output T3O can be used by Timer 2 in this mode.
Timer 3
mode
Synchronize
0
Biphase demodulation mode
0
1
1
0
1
0
1
0
T3I
T3EX
Q1=SI
CM31=SCI
Reset
Counter 3
0
1
1
0
1
0
1
0
SR–DATA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
13818
Figure 78. Biphase demodulation
66 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Combination Mode Timer 2 and Timer 3
I/O-bus
T3CS
T3M
T3I
T3EX
T3I
SCI
SI
Demodu–
lator 3
CM31
RES
CP3
T3CP
T3EX
INT5
CL3
SYSCL
T1OUT
POUT
8-bit Counter 3
T3C
T3ST
TOG3
RES
Compare 3/1
SO
T3O
Control
Modulator 3
Compare 3/2
Timer 3 – control
TOG2
M2
T3CO1
T3CO2
T3CM1
T3CM2
I/O-bus
SSI
P4CR
T2M1
T2M2
T2I
DCGO
T2O
TOG3
SYSCL
T1OUT
SCL
CL2/1
CL2/2
POUT
OUTPUT
MOUT
DCG
4-bit Counter 2/1
RES OVF1
8-bit Counter 2/2
RES OVF2
TOG2
M2
T2C
Compare 2/1
Timer 2 – control
Compare 2/2
Biphase–,
Manchester–
modulator
INT4
CM1
POUT
Timer 2
modulator 2
output-stage
T2CO1
T2CM
T2CO2
SO
SSI
I/O-bus
Control
(RE, FE, SCO, OMSK)
SSI
13878
Figure 79. Combination Timer 3 and Timer 2
Rev. A1, 08-Aug-01
67 (84)
M44C092–H
M44C892–H
Combination mode 10: Frequency measurement or event counter with time gate
Timer 2 mode 1/2:
12-bit compare counter / 8-bit compare counter and 4-bit prescaler
Timer 2 output mode 1/6: Timer 2 compare match toggles (TOG2) to the Timer 3
Timer 3 mode 3:
Timer / Counter; int. trigger restart & int. capture (with Timer 2 TOG2–signal)
The counter is driven by an external (T3I) clock source. The output signal (TOG2) of Timer 2 resets the counter. The
counter value before reset is saved in the capture register. If single-action mode is activated for one or both compare
registers, the trigger signal restarts also the single actions. This mode can be used for frequency measurements or as
event counter with time gate.
T3R
T3I
0 0 1 2 3 4 5 6 7 8 9 1011121314151617 0 1 2 3 4 5 6 7 8 9 101112131415161718 0 1 2 3 4 5
Counter 3
TOG2
Capture
value = 18
T3CP–
Capture value = 0
Capture value = 17
13879
Register
Figure 80. Frequency measurements
T3R
T3I
0 0 1 2 3 4 5 6 7 8 9 10
11
0 1
2
4
0 1 2
3
Counter 3
TOG2
Capture
T3CP–
Capture value = 0
Capture value = 11
13814
value = 4
Register
Figure 81. Event counter with time gate
Combination mode 11: Burst modulation 1
Timer 2 mode 1/2: 12-bit compare counter / 8-bit compare counter and 4-bit prescaler
Timer 2 output mode 1/6: Timer 2 compare match toggles the output flip-flop (M2) to the Timer 3
Timer 3 mode 6: Carrier frequency burst modulation controlled by Timer 2 output (M2)
The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare mode registers must
be programmed to generate the carrier frequency with the output toggle flip-flop. The output toggle flip-flop (M2) of
Timer 2 is used to enable and disable the Timer 3 output. The Timer 2 can be driven by the toggle output signal of
Timer 3 (TOG3) or any other clock source.
CL3
0 1 01 2 34 5 01 0 12 3 45 0 10 1 23 4 50 1 01
5 0 1 01
50 1 01
5 01 01
5 01 01
5 0 1 01
5 01 01
50 1 01
5 01 01
5 01 01
Counter 3
CM1
CM2
TOG3
M3
3
0
1
2
3
3
0
1
2
3
Counter 2/2
TOG2
M2
T3O
13880
Figure 82. Burst modulation 1
68 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Combination Mode Timer 2, Timer 3 and SSI
I/O–bus
T3CS
T3M
T3I
T3EX
T3I
SCI
SI
Demodu–
lator 3
CM31
RES
CP3
T3CP
T3EX
CL3
INT5
TOG3
SYSCL
8–bit Counter 3
T3C
T3ST
T1OUT
POUT
RES
Compare 3/1
T3O
SO
Modulator 3
Control
Compare 3/2
Timer 3 – control
M2
TOG2
T3CO1
T3CO2
T3CM1
T3CM2
SSI
I/O–bus
P4CR
T2M1
T2M2
T2I
DCGO
8–bit Counter 2/2
RES OVF2
T2O
TOG3
SYSCL
T1OUT
CL2/1
CL2/2
POUT
OUTPUT
MOUT
4–bit Counter 2/1
RES OVF1
DCG
SCL
TOG2
M2
T2C
Compare 2/1
Compare 2/2
Timer 2 – control
Biphase–,
Manchester–
modulator
INT4
CM1
POUT
T2CO1
T2CM
T2CO2
SO
Control
Timer 2
modulator 2
I/O–bus
Control
output–stage
(RE, FE,
SIC1
SIC2
SISC
SCO, OMSK)
INT3
TOG2
SC
SI
SCLI
POUT
T1OUT
SYSCL
SSI–control
MCL_SC
Output
SO
MCL_SD
SI
SCL
MSB 8-bit shift register
LSB
Shift_CL
STB
SRB
Receive buffer
Transmit buffer
I/O–bus
13881
Figure 83. Combination Timer 2, Timer 3 and SSI
Rev. A1, 08-Aug-01
69 (84)
M44C092–H
M44C892–H
Combination mode 12: Burst modulation 2
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 3
8-bit compare counter and 4-bit prescaler
Timer 2 output mode 2:
Timer 2 output mode 1/6: Timer 2 compare match toggles (TOG2) to the SSI
Timer 3 mode 7:
Carrier frequency burst modulation controlled by the internal output (SO) of SSI
The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare mode registers must
be programmed to generate the carrier frequency with the output toggle flip-flop (M3). The internal data output (SO)
of the SSI is used to enable and disable the Timer 3 output. The SSI can by supplied with the toggle signal of Timer 2.
CL3
0 1 01 2 34 5 01 0 12 3 45 0 10 1 23 4 50 1 01
50 1 01
5 0 1 01
5 0 1 01
5 0 1 01
5 0 1 01
5 0 1 01
5 01 0 1
5 01 01
5 0 1 01
Counter 3
CM31
CM32
TOG3
M3
3
0
1
2
3
3
0
1
2
3
Counter 2/2
TOG2
SO
T3O
13882
Figure 84. Burst modulation 2
Combination mode 13: FSK modulation
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 3
Timer 2 output mode 3:
8-bit compare counter and 4-bit prescaler
Timer 2 output mode 1/6: Timer 2 4-bit compare match signal (POUT) to the SSI
Timer 3 mode 8: FSK modulation with shift register data output (SO)
The two compare registers are used to generate two different time intervals. The SSI data output selects which compare
register is used for the output frequency generation. A ’0’ level at the SSI data output enables the compare register 1
and an ’1’ level enables the compare register 2. The both compare- and compare mode registers must be programmed
to generate the two frequencies via the output toggle flip-flop. The SSI can be supplied with the toggle signal of Timer 2
or any other clock source. The Timer 3 counter is driven by an internal or external clock source.
T3R
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 4 0 1
Counter 3
CM31
CM32
0
1
0
SO
T3O
13815
Figure 85. FSK modulation
70 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
U505M
4 M44C892–H
SCL
SDA
Multi chip link
MCL_SD
The M44C892–H is a multi-chip product which offers a
combination of a MARC4-based microcontroller and a
serial E2PROM data memory in a single package. As
microcontroller the M44C092–H is used and as serial
E2PROM the U505M. Two internal lines can be used as
chip-to-chip link in a single package. The maximum
internal data communication frequency between the
M44C092–H and the U505M over the chip link
MCL_SC
VDD
VSS
BP40/SC
BP43/SD
M44C092–H
BP10
BP13
13835
(MCL_SC and MCL_SD) is f
= 500 kHZ.
SC_MCL
Figure 86. Link between M44C092–H and U505M
The microcontroller and the EEPROM portions of this
multi-chip device are equivalent to their respective
individual component chips, except for the electrical
specification.
4.1 U505M EEPROM
The U505M is a 512-bit EEPROM internally organized
32 x 16 bit. The programming voltage as well as the write-
Internal 2-wire multi-chip link
Two additional on-chip pads (MCL_SC and MCL_SD) cycle timing is generated on-chip. The U505M features
for the SC and the SD line can be used as chip-to-chip link a serial interface allowing operation on a simple two-wire
2
for multi-chip applications. These pads can be activated bus with an I C-compatible protocol. Its low power con-
by setting the MCL-bit in the SISC-register.
sumption makes it well suited for battery applications.
Timing control
HV–generator
VDD
VSS
Address
control
EEPROM
32 x 16
Mode
control
16–bit read/write buffer
SCL
SDA
8–bit data register
I/O
control
13883
Figure 87. Block diagram EEPROM
Rev. A1, 08-Aug-01
71 (84)
M44C092–H
M44C892–H
4.1.1
Serial Interface
2
The U505M has an I C-like two-wire serial interface to ꢀ A START condition is defined as high to low transi-
the microcontroller for read and write accesses to the
EEPROM. The U505M is considered to be a slave in all
these applications. That means, the controller has to be
the master that initiates the data transfer and provides the
clock for transmit and receive operations.
tion on the SDA-line while the SCL-line is high.
ꢀ
A
S
T
O
P
c
o
n
d
i
t
i
o
n
i
s
d
e
f
i
n
e
d
a
s
l
o
w
t
o
h
i
g
h
t
r
a
n
s
i
t
i
o
n
on the SDA-line while the SCL-line is high.
ꢀ Each data transfer must be initialized with a START
condition and terminated with a STOP condition. The
START condition wakes the device from standby
mode and the STOP condition returns the device to
standby mode.
The serial interface is controlled by the M44C892–H
microcontroller which generates the serial clock and
controls the access via the SCL-line and SDA-line. SCL
is used to clock the data into and out of the device. SDA
is a bidirectional line that is used to transfer data into and
out of the device. The following protocol is used for the
data transfers.
ꢀ A receiving device generates an acknowledge (A)
after the reception of each byte. This requires an
additional clock pulse, generated by the master. If the
reception was successful the receiving master or slave
device pulls down the SDA-line during that clock
cycle. If an acknowledge is not detected (N) by the
interface in transmit mode, it will terminate further
data transmissions and go into receive mode. A master
device must finish its read operation by a non-ac-
knowledge and then send a stop condition to bring the
device into a known state.
Serial Protocol
ꢀ Data states on the SDA-line changing only while SCL
is low.
ꢀ Changes on the SDA-line while SCL is high are
interpreted as START or STOP condition.
SCL
SDA
Stand Start
by condition
Data
valid
Data
change
Data/
acknowledge
valid
Stop Stand-
condition by
13884
Figure 88. I2C protocol
ꢀ Before the START condition and after the STOP
condition the device is in stand-by mode and the SDA
line is switched as input with pull-up resistor.
termines the following operation. It consists of the
5-bit row address, 2 mode control bits and the READ
/ NWRITE bit that is used to control the direction of
the following transfer. A ”0” defines a write access
and a ”1” a read access.
ꢀ The control byte that follows the START condition de-
ꢀ Control byte format:
Mode control
bits
Read/
NWrite
EEPROM address
Start
A4
A3
A2
A1
A0
C1
C0
R/NW
Ackn
ꢀ Control byte format:
Start Control byte
Ackn
Data byte
Ackn
Data byte
Ackn
Stop
72 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
Two special control bytes enable the complete
initialization of EEPROM with ”0” or with ”1.
4.1.2
EEPROM
The EEPROM has a size of 512 bits and is organized as
32 x 16-bit matrix. To read and write data to and from the
EEPROM the serial interface must be used. The interface
supports one and two byte write accesses and one to
n-byte read accesses to the EEPROM.
Write Operations
The EEPROM permits 8-bit and 16-bit write operations.
A write access starts with the START condition followed
by a write control byte and one or two data bytes from the
master. It is completed via the STOP condition from the
master after the acknowledge cycle.
EEPROM – Operating Modes
The operating modes of the EEPROM are defined via the
control byte. The control byte contains the row address,
the mode control bits and the read/not-write bit that is
used to control the direction of the following transfer. A
”0” defines a write access and a ”1” a read access. The
The programming cycle consists of an erase cycle (write
”zeros”) and the write cycle (write ”ones”). Both cycles
together take about 10 ms.
Acknowledge Polling
five address bits select one of the 32 rows of the EEPROM If the EEPROM is busy with an internal write cycle, all
memory to be accessed. For all accesses the complete inputs are disabled and the EEPROM will not
16-bit word of the selected row is loaded into a buffer. The acknowledge until the write cycle is finished. This can be
buffer must be read or overwritten via the serial interface. used to detect the end of the write cycle. The master must
The two mode control bits C1 and C2 define in which or- perform acknowledge polling by sending a start condition
der the accesses to the buffer are performed: High byte – followed by the control byte. If the device is still busy
low byte or low byte – high byte. The EEPROM also sup- with the write cycle, it will not return an acknowledge and
ports autoincrement and autodecrement read operations. the master has to generate a stop condition or perform fur-
After sending the start address with the corresponding ther acknowledge polling sequences. If the cycle is
mode, consecutive memory cells can be read row by row complete, it returns an acknowledge and the master can
without transmission of the row addresses.
proceed with the next read or write cycle.
Write One Data Byte
Start
Write Two Data Bytes
Start Control byte
Write Control Byte Only
Start Control byte
Control byte
A
A
Data byte 1
Data byte 1
A
A
Stop
Data byte 2
A
Stop
A
Stop
Write Control Bytes
Write low byte first
MSB
LSB
R/NW
0
A4
A3
A2
A1
A0
C1
0
C0
1
Row address
Byte order
LB(R)
MSB
HB(R)
LSB
R/NW
0
Write high byte first
Byte order
A4
A3
A2
A1
A0
C1
1
C0
0
Row address
HB(R)
LB(R)
A –> acknowledge; HB: high byte; LB: low byte; R: row address
Rev. A1, 08-Aug-01
73 (84)
M44C092–H
M44C892–H
if it wants to proceed the read operation. If two bytes are
read out from the buffer the device increments respec-
Read Operations
The EEPROM allows byte-, word- and current address tively decrements the word address automatically and
read operations. The read operations are initiated in the loads the buffer with the next word. The read mode bits
same way as write operations. Every read access is initi- determines if the low or high byte is read first from the
ated by sending the START condition followed by the buffer and if the word address is incremented or decre-
control byte which contains the address and the read mented for the next read access. If the memory address
mode. After the device receives a read command it re- limit is reached, the data word address will ”roll over” and
turns an acknowledge, loads the addressed word into the the sequential read will continue. The master can termi-
read\write buffer and sends the selected data byte to the nate the read operation after every byte by not responding
master. The master has to acknowledge the received byte with an acknowledge (N) and by issuing a stop condition.
Read One Data Byte
Start
Control byte
A
A
A
Data byte 1
Data byte 1
Data byte 1
N
A
Stop
Read Two Data Bytes
Start Control byte
Data byte 2
Data byte 2
N
A
Stop
Read n Data Bytes
Start
Control byte
A
– – – –
Data byte n
N
Stop
Read Control Bytes
MSB
LSB
R/NW
1
Read low byte first, address increment
A4
A3
A2
A1
A0
C1
0
C0
1
Row address
Byte order
LB(R)
HB(R)
LB(R+1) HB(R+1)
– – –
LB(R+n) HB(R+n)
MSB
LSB
R/NW
1
Read high byte first, addr. decrement
A4
A3
A2
A1
A0
C1
1
C0
0
Row address
Byte order
HB(R)
LB(R)
HB(R–1) LB(R–1)
– – –
HB(R–n) LB(R–n)
A –> acknowledge, N –> no acknowledge; HB: high byte; LB: low byte, R: row address
Initialization after a Reset Condition
The EEPROM with the serial interface has its own reset circuitry. In systems with microcontrollers that have their own
reset circuitry for power on reset, watchdog reset or brown-out reset, it may be necessary to bring the U505M into a
known state independent of its internal reset. This is performed by writing:
Start
Control byte
A
Data byte 1
N
Stop
to the serial interface. If the U505M acknowledges this sequence it is in a defined state. Maybe it is necessary to perform
this sequence twice.
74 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
5 Electrical Characteristics
5.1 Absolute Maximum Ratings
Voltages are given relative to V
SS
Parameters
Symbol
V
DD
Value
–0.3 to + 6.5
VSS –0.3 ꢀVIN ꢀVDD +0.3
indefinite
Unit
V
V
Supply voltage
Input voltage (on any pin)
Output short circuit duration
Operating temperature range
Storage temperature range
Thermal resistance (SSO20)
Soldering temperature (t ≤ 10 s)
V
IN
t
s
short
T
amb
–40 to +105
–40 to +130
140
°C
°C
K/W
°C
T
stg
R
thJA
T
sld
260
Stresses greater than those listed under absolute reliability. All inputs and outputs are protected against
maximum ratings may cause permanent damage to the high electrostatic voltages or electric fields. However,
device. This is a stress rating only and functional precautions to minimize the build-up of electrostatic
operation of the device at any condition above those charges during handling are recommended. Reliability of
indicated in the operational section of this specification operation is enhanced if unused inputs are connected to
is not implied. Exposure to absolute maximum rating an appropriate logic voltage level (e.g. V ).
DD
condition for an extended period may affect device
5.2 DC Operating Characteristics
V
SS
= 0 V, T
= –40 to 105°C unless otherwise specified.
amb
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Power supply
Operating voltage at V
V
I
V
POR
6.5
V
DD
DD
Active current
CPU active
f
= 1 MHz
SYSCL
V
V
V
= 1.8 V
= 3.0 V
= 6.5 V
200
300
700
µA
µA
µA
DD
DD
DD
DD
450
180
Power down current
(CPU sleep,
RC oscillator active,
f
= 1 MHz
SYSCL
V
V
V
= 1.8 V
= 3.0 V
= 6.5 V
I
40
70
200
µA
µA
µA
DD
DD
DD
PD
4-MHz quartz-osc. active)
Sleep current
(CPU sleep,
32-kHz quartz-osc. active
4-MHz quartz-osc. inactive)
V
V
V
= 1.8 V
= 3.0 V
= 6.5 V
I
I
0.4
0.6
0.8
µA
µA
µA
DD
DD
DD
Sleep
1.3
1.8
Sleep current
(CPU sleep,
32-kHz quartz-osc. inactive
4-MHz quartz-osc. inactive)
V
DD
V
DD
V
DD
= 1.8 V
= 3.0 V
= 6.5 V for
M44C092–H
= 6.5 V for
0.1
0.3
µA
µA
Sleep
0.5
0.8
1.0
0.5
0.6
µA
µA
V
DD
M44C892–H
Rev. A1, 08-Aug-01
75 (84)
M44C092–H
M44C892–H
V
SS
= 0 V, T
= –40 to 105°C unless otherwise specified.
amb
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Power-on reset threshold voltage
POR threshold voltage
POR threshold voltage
POR hysteresis
BOT = 1
BOT = 0
V
POR
V
POR
V
POR
1.6
1.7
2.0
50
1.8
V
V
1.85
2.15
mV
Voltage monitor threshold voltage
VM high threshold voltage
VM high threshold voltage
VM middle thresh. voltage
VM middle thresh. voltage
VM low threshold voltage
VM low threshold voltage
External input voltage
VMI
V
V
V
V
V
V
> VM, VMS = 1
< VM, VMS = 0
> VM, VMS = 1
< VM, VMS = 0
> VM, VMS = 1
< VM, VMS = 0
V
V
3.0
3.0
2.6
2.6
2.2
2.2
3.25
2.8
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
MThh
MThh
MThm
MThm
2.8
2.4
2.0
V
V
V
2.4
MThl
V
MThl
V
V
= 3 V, VMS = 1
= 3 V, VMS = 0
V
V
1.3
1.3
1.4
V
V
DD
VMI
VMI
1.2
DD
VMI
All Bidirectional Ports
V
SS
= 0 V, T
= –40 to 105°C unless otherwise specified.
amb
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
V
Input voltage LOW
Input voltage HIGH
V
V
= 1.8 to 6.5 V
= 1.8 to 6.5 V
= 2.0 V,
V
IL
V
SS
0.2*V
DD
DD
DD
0.8* VDD
V
IH
V
DD
V
Input LOW current
(dyn. pull-up)
V
V
V
I
–2
–10
–50
–4
–20
–100
–12
–40
–200
µA
µA
µA
DD
DD
DD
IL
= 3.0 V, V = V
IL
SS
= 6.5 V
Input HIGH current
(dyn. pull-down)
V
DD
V
DD
V
DD
= 2.0 V,
= 3.0 V, V = V
= 6.5 V
I
2
10
50
4
20
100
12
40
200
µA
µA
µA
IH
IH
DD
Input LOW current
(strong pull-up)
V
V
V
= 2.0 V
= 3.0 V, V = V
= 6.5 V
I
I
–20
–80
–300
–50
–160
–600
–100
–320
–1200
µA
µA
µA
µA
µA
µA
DD
DD
DD
IL
IL
SS
Input LOW current
(strong pull-down)
V
DD
V
DD
V
DD
= 2.0 V
= 3.0 V, V = V
= 6.5 V
20
80
300
50
160
600
100
320
1200
IH
IH
DD
Input leakage current
Input leakage current
Output LOW current
V = V
I
100
100
nA
nA
IL
SS
IL
V = V
IH
I
DD
IH
V
= 0.2 V
DD
OL
V
DD
V
DD
V
DD
= 2.0 V
= 3.0 V,
= 6.5 V
I
0.6
3
8
1.2
5
15
2.5
8
22
mA
mA
mA
OL
Output HIGH current
V = 0.8 V
OH DD
V
DD
V
DD
V
DD
= 2.0 V
= 3.0 V,
= 6.5 V
I
–0.6
–3
–8
–1.2
–5
–16
–2.5
–8
–24
mA
mA
mA
OH
Note: The Pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller
76 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
5.3 AC Characteristics
Supply voltage V = 1.8 to 6.5 V, V = 0 V, T = 25°C unless otherwise specified.
amb
DD
SS
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
System clock cycle
V
T
= 1.8 to 6.5 V
= –40 to 105°C
= 2.4 to 6.5 V
= –40 to 105°C
t
t
t
500
4000
ns
DD
SYSCL
SYSCL
SYSCL
amb
V
DD
250
500
4000
2000
ns
ns
T
amb
V
DD
= 2.4 to 6.5 V
T
amb
= –40 to 85°C
Timer 2 input timing Pin T2I
5
Timer 2 input clock
f
MHz
ns
T2I
Timer 2 input LOW time
Timer 2 input HIGH time
Rise / fall time < 10 ns
Rise / fall time < 10 ns
t
100
100
T2IL
T2IH
t
ns
Timer 3 input timing Pin T3I
SYSCL/2
Timer 3 input clock
f
MHz
ns
T3I
T3IL
T3IH
2 tSYSCL
2 tSYSCL
Timer 3 input LOW time
Timer 3 input HIGH time
Rise / fall time < 10 ns
Rise / fall time < 10 ns
t
t
ns
Interrupt request input timing
Int. request LOW time
Int. request HIGH time
External system clock
Rise / fall time < 10 ns
t
100
100
ns
ns
IRL
Rise / fall time < 10 ns
t
IRH
EXSCL at OSC1, ECM =
EN
Rise / fall time < 10 ns
f
f
0.5
4
4
MHz
EXSCL
EXSCL
EXSCL at OSC1, ECM = DI
Input HIGH time
Reset timing
Rise / fall time < 10 ns
Rise / fall time < 10 ns
0.02
0.1
MHz
t
µs
IH
Power-on reset time
RC oscillator 1
Frequency
V
V
t
POR
1.5
3.8
5
ms
DD
POR
u
f
f
MHz
%
RcOut1
Stability
V
T
= 2.0 to 6.5 V
= –40 to 105°C
∆f/f
"50
DD
amb
RC oscillator 2 – external resistor
Frequency
Stability
R
= 170 kΩ
= 2.0 to 6.5 V
= –40 to 85°C
4
MHz
%
ext
RcOut2
V
T
∆f/f
"15
DD
amb
Stabilization time
t
10
µs
S
4-MHz crystal oscillator (operating range V = 2.2 V to 6.5 V)
DD
Frequency
Start-up time
Stability
f
4
5
MHz
ms
X
t
SQ
∆f/f
C
IN
–10
10
20
ppm
pF
Integrated input / output
capacitances
C
/ C
programmable
0
IN
OUT
in steps of 2 pF
(mask programmable)
C
0
20
pF
OUT
Rev. A1, 08-Aug-01
77 (84)
M44C092–H
M44C892–H
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
32-kHz crystal oscillator (operating range V = 2.0 V to 6.5 V)
DD
Frequency
Start-up time
Stability
f
32.768
0.5
kHz
s
X
t
SQ
∆f/f
C
IN
–10
10
20
ppm
pF
Integrated input / output
capacitances
C
/ C
programmable
0
IN
OUT
in steps of 2 pF
(mask programmable)
C
0
20
pF
OUT
External 32-kHz crystal parameters
Crystal frequency
f
32.768
30
kHz
kΩ
pF
X
Serial resistance
RS
C0
C1
50
Static capacitance
1.5
3
Dynamic capacitance
External 4-MHz crystal parameters
Crystal frequency
fF
f
4.0
40
1.4
3
MHz
Ω
X
Serial resistance
RS
C0
C1
150
3
Static capacitance
pF
Dynamic capacitance
fF
Crystal Characteristics
C1
C0
L
RS
Equivalent
circuit
OSCIN
SCLIN
OSCOUT
SCLOUT
96 11553
Figure 89. Crystal equivalent circuit
Supply voltage V = 1.8 to 6.5 V, V = 0 V, T = 25°C unless otherwise specified.
amb
DD
SS
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
EEPROM
Operating current during
erase/write cycle
I
600
1,000,000
9
1300
µA
WR
Endurance
Erase- / write-cycles
n
n
500,000
50,000
Cycles
Cycles
EW
EW
@105ꢁ C
Data erase/write cycle time for 16-bit access
Data retension time
t
12
ms
DEW
t
t
10
1
years
years
DR
DR
@105ꢁ C
Power-up to read operation
t
0.2
0.2
ms
ms
PUR
Power-up to write opera-
tion
t
PUW
Serial interface
SCL clock frequency
f
100
500
kHz
SC_MCL
78 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
2.5
2.0
1.5
1.0
0.5
0.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
f
= 1 MHz
SYSCLK
T
= 25ꢁC
amb
V
DD
= 6.5 V
5 V
Tamb = 125ꢁC
25ꢁC
–40ꢁC
3 V
2 V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
( MHz )
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
( V )
f
V
DD
SYSCLK
Figure 93. Active supply current vs. VDD
Figure 90. Active supply current vs. frequency
120
100
80
60
40
20
0
400
350
300
250
200
150
100
50
V = 6.5 V
DD
T
= 25ꢁC, f
= 500 kHz
T
= 25ꢁC
amb
SYSCLK
amb
5 V
4 V
3 V
2 V
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
( V )
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
( MHz )
V
DD
f
SYSCLK
Figure 94. Power-down supply current vs. VDD
Figure 91. Power-down supply current vs. frequency
1.0
0.9
1.0
0.9
0.8
0.7
0.6
0.5
V
DD
= 6.5 V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
5 V
3 V
V
DD
= 6.5 V
0.4
0.3
0.2
0.1
0.0
5 V
3 V
–40 –20
0
20 40 60 80 100 120
( ꢁC )
–40 –20
0
20 40 60 80 100 120
( ꢁC )
T
amb
T
amb
Figure 92. Sleep current vs. Tamb
Figure 95. Sleep current vs. Tamb
M44C092–H
M44C892–H
Rev. A1, 08-Aug-01
79 (84)
M44C092–H
M44C892–H
5.0
4.5
4.0
3.5
3.0
2.5
2.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
Tamb = –40ꢁC
25ꢁC
V
DD
= 6.5 V
3 V
105ꢁC
2 V
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
( V )
–40 –20
0
20 40 60 80 100 120
( ꢁC )
V
DD
T
amb
Figure 96. Internal RC frequency vs. VDD
Figure 99. Internal RC frequency vs. Tamb
4.6
4.4
4.2
4.0
3.8
3.6
3.4
4.6
4.4
4.2
4.0
3.8
3.6
3.4
R
ext
= 170 kOhm
R
ext
= 170 kOhm
Tamb = –40ꢁC
105ꢁC
V
DD
= 6.5 V
25ꢁC
3 V
2 V
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
( V )
–40 –20
0
20 40 60 80 100 120
( ꢁC )
V
DD
T
amb
Figure 97. External RC frequency vs. VDD
SYSCLKmax
Figure 100. External RC frequency vs. Tamb
10.00
1.00
0.10
0.01
7.5
6.5
5.5
4.5
3.5
2.5
1.5
T
V
=
25ꢁC,
amb
DD
= 3 V
SYSCLKmin
max.
typ.
min.
100
150
200
250
300
350
400
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
( V )
R
( kOhm )
V
DD
ext
Figure 98. System clock vs. VDD
Figure 101. External RC frequency vs. Rext
80 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
1000.00
100.00
10.00
1000.00
100.00
10.00
V
= V
SS
IL
V
= V
DD
IH
Tamb = 105ꢁC
Tamb = 105ꢁC
25ꢁC
25ꢁC
–40ꢁC
–40ꢁC
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
( V )
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
( V )
V
DD
V
DD
Figure 102. Pull-up resistor vs. VDD
Figure 105. Pull-down resistor vs. VDD
100.00
100.00
V
IL
= V
SS
V
IH
= V
DD
Tamb = 105ꢁC
–40ꢁC
Tamb = 105ꢁC
25ꢁC
25ꢁC
–40ꢁC
10.00
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
( V )
10.00
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
( V )
V
DD
V
DD
Figure 103. Strong pull-up resistor vs. VDD
Figure 106. Strong pull-down resistor vs. VDD
30
0
–5
V
DD
= 2.0 V
3.0 V
T
= 25ꢁC
V
DD
= 6.5 V
amb
25
20
15
10
5
–10
–15
–20
–25
–30
–35
–40
5.0 V
4.0 V
4.0 V
5.0 V
3.0 V
2.0 V
T
= 25ꢁC
amb
6.5 V
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
– V ( V )
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
( V )
V
DD
V
OL
OH
Figure 104. Output high current vs. VDD – output high volt-
Figure 107. Output low current vs. output low voltage
age
Rev. A1, 08-Aug-01
81 (84)
M44C092–H
M44C892–H
0
25
20
15
10
5
–5
min.
max.
typ.
–10
–15
–20
–25
typ.
max.
min.
0
–40 –20
0
20 40 60 80 100 120
( ꢁC )
–40 –20
0
20 40 60 80 100 120
T
amb
T
( ꢁC )
amb
Figure 108. Output high current vs. VDD = 6.5 V,
OH = 0.8 VDD
Figure 109. Output low current vs. Tamb
V
VDD = 6.5 V, VOL = 0.2 VDD
Package Information
Package SSO20
Dimensions in mm
5.7
5.3
6.75
6.50
4.5
4.3
1.30
0.15
0.15
0.05
0.25
0.65
6.6
6.3
5.85
20
11
technical drawings
according to DIN
specifications
13007
1
10
82 (84)
Rev. A1, 08-Aug-01
M44C092–H
M44C892–H
6 Ordering Information
Please select the option setting from the list below and insert ROM CRC.
Port 1
BP10
Port 5
BP50
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
BP51
BP52
BP53
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
BP13
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
Port 2
BP20
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
BP21
BP22
BP23
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
Port 6
BP60
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
BP63
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
OSC1
OSC2
Port 4
ꢂ
ꢂ
No integrated capacitance
Internal capacitance ( ___ pF)
BP40
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
ꢂ
ꢂ
No integrated capacitance
Internal capacitance ( ___ pF)
BP41
BP42
BP43
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
Clock used
ꢂ
ꢂ
ꢂ
ꢂ
External resistor
External clock
32-kHz crystal
4-MHz crystal
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
ECM(External clock monitor)
ꢂ
ꢂ
ꢂ
CMOS
Open drain [N]
Open drain [P]
ꢂ
ꢂ
ꢂ
ꢂ
Pull-up
Pull-down
Pull-up strong
Pull-down strong
ꢂ
ꢂ
Enable
Disable
File:____________. HEX
CRC: _____________ HEX
Signature: _______________
Approval
Date: ____–____–____
Rev. A1, 08-Aug-01
83 (84)
M44C092–H
M44C892–H
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid
their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these
substances.
Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed
in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances
and do not contain such substances.
12.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended
or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims,
costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death
associated with such unintended or unauthorized use.
Data sheets can also be retrieved from the Internet:
http://www.atmel–wm.com
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
84 (84)
Rev. A1, 08-Aug-01
相关型号：
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