MMDP-65697V-55/883 [TEMIC]
Standard SRAM, 256KX1, 55ns, CMOS, CQFP28,;
| 型号： | MMDP-65697V-55/883 |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Standard SRAM, 256KX1, 55ns, CMOS, CQFP28, ATM 异步传输模式 静态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MATRA MHS
M 65697
256 K × 1 Ultimate CMOS SRAM
Introduction
The M 65697 is a very low power CMOS static RAM supply current (Typical value = 0.1 µA) with a fast access
organized as 262144 × 1 bit. It is manufactured using the time at 40 ns. The high stability of the 6T cell provides
MHS high performance CMOS technology named excellent protection against soft errors due to noise.
SCMOS.
Extra protection against heavy ions is given by the use of
With this process, MHS is the first to bring the solution for
applications where fast computing is as mandatory as low
consumption, such as aerospace electronics, portable
instruments or embarked systems.
an epitaxial layer of a P substrate.
The M 67697 is 100 % processed following the test
methods of MIL STD 883 and/or ESA/SCC 9000, making
it ideally suitable for military/space applications that
demand superior levels of performance and reliability.
Utilizing an array of six transistors (6T) memory cells, the
M
65697 combines an extremely low standby
Features
D Access time
D 300 mils width package
D TTL compatible inputs and outputs
D Asynchronous
commercial : 35(*), 40, 45, 55 ns
industrial and military : 40(*), 45, 55 ns
D Very low power consumption
active : 50 mW (typ)
D Single 5 volt supply
D Equal cycle and access time
standby : 0.5 µW (typ)
D Gated inputs :
no pull-up/down
resistors are required
data retention : 0.4 µW (typ)
D Wide temperature range : –55 to + 125 °C
* Preliminary. Consult sales.
Interface
Block Diagram
Rev. C (12/12/94)
1
M 65697
MATRA MHS
Pin Configuration
Side Brazed 300 mils 24 pins
SOIC 300 mils 28 pins
Multilayer Flat Pack 28 pins
(Top View)
(Top View)
Pin Description
Truth Table
A -A
:
:
:
:
:
Address inputs
Input
CS
W
:
:
Chip-Select
DATA DATA
0
17
CS
W
MODE
IN
OUT
Din
Write Enable
Deselect/
POWER-DOWN
H
X
Z
Z
Output
V
V
Power
CC
SS
L
L
H
L
Z
Valid
Z
Read
Write
Ground
Valid
L = low, H = high, X = H or L, Z = high impedance
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . –0.5 V to + 7.0 V
Input or Output voltage applied : . . . . . (Gnd – 0.3 V) to (Vcc + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . –65 °C to + 150 °C
Electro static discharge voltage . . . . . . . . . . > 1250 V (MIL STD 883,
METHOD 3015)
Operating Range
OPERATING VOLTAGE
OPERATING TEMPERATURE
– 55 _C to + 125 _C
Military
V
V
V
= 5 V ± 10 %
= 5 V ± 10 %
= 5 V ± 10 %
CC
CC
CC
Industrial
Commercial
– 40 _C to 85 _C
0 _C to + 70 _C
DC Operating Conditions
PARAMETER
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
Vcc
Supply voltage
Ground
4.5
0.0
5.0
0.0
0.0
–
5.5
0.0
V
V
V
V
Gnd
VIL
(1)
Input low voltage
Input high voltage
– 0.3
2.2
0.8
VIH(1)
Vcc + 0.3
Note :
1. VIH max = Vcc + 0.3 V, VIL min = –0.3 V or –1.0 pulse 50 ns.
2
Rev. C (12/12/94)
MATRA MHS
M 65697
Capacitance
PARAMETER
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
pF
Cin
Cout
(2)
(2)
Input capacitance
Output capacitance
–
–
–
–
8
8
pF
Note :
2. TA = 25°C, f = 1 MHz, Vcc = 5.0 V, these parameters are not tested.
DC Parameter
PARAMETER
DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNIT
µA
µA
V
IIX
(3)
Input leakage current
– 1.0
– 1.0
–
–
–
–
–
1.0
1.0
0.4
–
IOZ(3)
Output leakage current
Output low voltage
Output high voltage
VOL (4)
VOH (4)
2.4
V
Notes : 3. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output disabled.
4. Vcc min, IOL = 8 mA, IOH = –4 mA.
Consumption for Commercial Specification
M 65697 M 65697 M 65697 M 65697 M 65697 M 65697 M 65697 M 65697
L-35(*) V-35(*) L - 40 V - 40 L - 45 V - 45 L - 55 V - 55
SYMBOL PARAMETER
UNIT VALUE
ICCSB
(5)
Standby supply
current
10
75
90
5
5
10
75
90
5
5
10
75
90
5
5
10
75
90
5
5
mA
µA
max
max
max
ICCSB1
(6)
Standby supply
current
ICCOP
(7)
Operating supply
current
70
70
70
70
mA
Consumption for Industrial Specification
M 65697 M 65697 M 65697 M 65697 M 65697 M 65697
SYMBOL PARAMETER
UNIT
VALUE
max
L - 40(*) V - 40(*)
L - 45
V - 45
L - 55
V - 55
ICCSB
(5)
Standby supply
current
10
100
90
5
10
5
10
5
mA
µA
ICCSB1
(6)
Standby supply
current
10
70
100
90
10
70
100
90
10
70
max
ICCOP
(7)
Operating supply
current
mA
max
Consumption for Military Specification
M 65697 M 65697 M 65697 M 65697 M 65697 M 65697
SYMBOL PARAMETER
UNIT
VALUE
L - 40(*) V - 40(*)
L - 45
V - 45
L - 55
V - 55
ICCSB
(5)
Standby supply
current
10
500
90
5
10
5
10
5
mA
max
ICCSB1
(6)
Standby supply
current
100
70
500
90
100
70
500
90
100
70
µA
max
max
ICCOP
(7)
Operating supply
current
mA
Notes : 5. CS ≥ VIH, Vin ≥ VIH or Vin ≤ VIL.
6. CS ≥ Vcc – 0.3 V, Iout = 0 mA. Vin ≥ Vcc – 0.3 V or Vin ≤ 0.3 V.
7. Vcc max, Iout = 0 mA, Vin = Gnd/Vcc. Duty cycle 100 %, F = 5 MHz, derating = 10 mA/MHz.
(*) Preliminary. Please consult sales.
Rev. C (12/12/94)
3
M 65697
MATRA MHS
Data Retention Mode
MHS CMOS RAM’s are designed with battery backup in 2. CS must be kept between Vcc – 0.3 V and 70 % of
mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure
data retention :
Vcc during the power up and power down transitions.
4. The RAM can begin operation > 45 ns after Vcc
reaches the minimum operating voltage (4.5 V).
1. Chip select (CS) must be held high during data
retention ; within Vcc to Vcc – 0.2 V.
Timing
Data Retention Characteristics
PARAMETER
VCCDR
DESCRIPTION
MINIMUM TYPICAL (8)
MAXIMUM
UNIT
V
V
for data retention
2.0
0.0
–
–
–
–
CC
TCDR
Chip deselect to data retention
time
ns
TR
Operation recovery time
Data retention current
TAVAV (9)
–
–
ns
ICCDR1 (10)
COM
IND
MIL
@ 2.0 V : M-65697 V
M-65697 L
–
–
0.1
0.1
3
60
8
80
80
300
µA
µA
ICCDR2 (10)
Data retention current
@ 3.0 V : M-65697 V
M-65697 L
–
–
0.3
0.3
4
70
9
90
90
400
µA
µA
Notes : 8. TA = 25°C.
9. TAVAV = Read cycle time.
10. CS = V , Vin = Gnd/V , this parameter is only tested at V = 2 V.
CC
CC
CC
4
Rev. C (12/12/94)
MATRA MHS
M 65697
AC Parameters
AC Conditions :
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V
Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output load : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See fig. 1a, 1b
Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Write Cycle : Commercial Specification (note 12)
M 65697 M 65697 M 65697 M 65697
SYMBOL
PARAMETER
UNIT
VALUE
L/V - 35(*) L/V - 40
L/V - 45
L/V - 55
TAVAV
Write cycle time
35
0
40
0
45
0
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
min
min
min
min
min
max
min
min
min
min
TAVWL
Address set-up time
Address valid to end of write
Data set-up time
TAVWH
30
20
30
15
30
0
30
22
30
15
30
0
40
25
40
15
40
0
50
25
50
20
50
0
TDVWH
TELWH
CS low to write end
Write low to high Z
Write pulse width
TWLQZ (11)
TWLWH
TWHAX
TWHDX
TWHQX (11)
Address hold to end of write
Data hold time
0
0
0
0
Write high to low Z
0
0
0
0
Write Cycle : Industrial and Military Specification (note 12)
M 65697
L/V - 40(*)
M 65697
L/V - 45
M 65697
L/V - 55
SYMBOL
PARAMETER
UNIT
VALUE
TAVAV
Read cycle time
40
0
45
0
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
min
min
min
min
min
min
min
min
min
min
TAVWL
Address set-up time
Address valid to end of write
Data set-up time
TAVWH
30
22
30
15
30
0
40
25
40
15
40
0
50
25
50
20
50
0
TDVWH
TELWH
CS low to write end
Write low to high Z
Write pulse width
TWLQZ (11)
TWLWH
TWHAX
TWHDX
TWHQX (11)
Address hold to end of write
Data hold time
0
0
0
Write high to low Z
0
0
0
Notes : 11. Specified with C = 5 pF (see figure 1b). Guaranteed. Not tested.
L
(*) Preliminary. Consult sales.
Rev. C (12/12/94)
5
M 65697
MATRA MHS
Write Cycle 1 : W Controlled (note 12)
Write Cycle 2 : CS Controlled (note 12)
Note : 12. The internal write time of the memory is defined by the overlap of CS LOW and W LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the
rising edge of the signal that terminates the write.
AC Test Loads and Waveforms
Figure 1
a
Figure 1 b
Figure 2
6
Rev. C (12/12/94)
MATRA MHS
M 65697
Read Cycle : Commercial Specification
M 65697 M 65697 M 65697 M 65697
SYMBOL
PARAMETER
UNIT
VALUE
L/V - 35(*) L/V - 40
L/V - 45
L/V - 55
TAVAV
Write cycle time
35
35
5
40
40
5
45
45
5
55
55
5
ns
ns
ns
ns
ns
ns
min
max
min
max
min
max
TAVQV
Address access time
Address valid to low Z
Chip-select access time
CS low to low Z
TAVQX
TELQV
35
5
40
5
45
5
55
5
TELQX (13)
TEHQZ (13)
CS high to high Z
20
20
20
20
Read Cycle : Industrial and Military Specification
M 65697
L/V - 40(*)
M 65697
L/V - 45
M 65697
L/V - 55
SYMBOL
PARAMETER
UNIT
VALUE
TAVAV
Read cycle time
40
40
5
45
45
5
55
55
5
ns
ns
ns
ns
ns
ns
min
max
min
max
min
max
TAVQV
Address access time
Address valid to low Z
Chip-select access time
CS low to low Z
TAVQX
TELQV
40
5
45
5
55
5
TELQX (13)
TEHQZ (13)
CS high to high Z
20
20
20
Notes : 13. Specified with CL = 5 pF (see figure 1b). Guaranteed but not tested.
(*) Preliminary. Consult sales.
Rev. C (12/12/94)
7
M 65697
MATRA MHS
Read Cycle nb 1 (notes 14, 15)
Read Cycle nb 2 (notes 14, 16)
Notes : 14. W is high for read cycle.
15. Device is continuously selected CS = VIL.
16. Address valid prior to or coincident with CS transition low.
8
Rev. C (12/12/94)
MATRA MHS
M 65697
Ordering Information
TEMPERATURE RANGE
PACKAGE
DEVICE
GRADE
SPEED
FLOW
C
M
TI
- 65697
V
- 45
35 ns
40 ns
45 ns
55 ns
C = Commercial
I = Industrial
M = Military
S = Space
0° to +70°C
–40° to +85°C
–55° to +125°C
–55° to +125°C
256K × 1
STATIC RAM
V = Very low power
L = Low power
blank
/883
CB
= MHS Standards
CZ = 24 pins DIL SIDE-BRAZED 300 mils
DP = 28 pins Multilayer Flat Pack
TI = 28 pins SOIC 300 mils
= MIL STD 883 Class B or S
= Compliant CECC 90000
Level B
SHXXX = Special customer request
FHXXX = Flight models (space)
EHXXX = Engineering models (space)
MHXXX = Mechanical parts (space)
LHXXX = Life test parts (space)
The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication
and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
Rev. C (12/12/94)
9
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